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Config: Keep track of uncached and cached ports separately.

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This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
This commit is contained in:
Gabe Black
2011-02-03 20:23:00 -08:00
parent 869a046e41
commit 00f24ae92c
28 changed files with 55 additions and 50 deletions
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4
configs/common/CacheConfig.py
View File

@@ -52,8 +52,8 @@ def config_cache(options, system):
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
if options.l2cache:
system.cpu[i].connectMemPorts(system.tol2bus)
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else:
system.cpu[i].connectMemPorts(system.membus)
system.cpu[i].connectAllPorts(system.membus)
return system

2
configs/example/fs.py
View File

@@ -178,7 +178,7 @@ if len(bm) == 2:
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
drive_sys.cpu.connectAllPorts(drive_sys.membus)
if options.fastmem:
drive_sys.cpu.physmem_port = drive_sys.physmem.port
if options.kernel is not None:

2
configs/splash2/run.py
View File

@@ -218,7 +218,7 @@ for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
L1(size = options.l1size, assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2bus)
cpu.connectAllPorts(system.toL2bus, system.membus)
# ----------------------