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MEM: Fix master/slave ports in Ruby and non-regression scripts

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This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.
This commit is contained in:
Andreas Hansson
2012-02-14 03:41:53 -05:00
parent 0d46708dc2
commit 00978170f3
13 changed files with 29 additions and 29 deletions
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8
configs/ruby/MI_example.py
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@@ -95,7 +95,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@@ -153,10 +153,10 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl.dma_sequencer.port = dma_device.dma
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl.dma_sequencer.slave = dma_device.dma
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1