From 00008b725c7c4d1755b0b7432a906b281fde95d8 Mon Sep 17 00:00:00 2001 From: Matt Sinclair Date: Sun, 19 Jun 2022 01:33:50 -0500 Subject: [PATCH] arch-vega: some Vega instructions don't use dest reg Some of the Vega scalar instructions (S_SETPC_B64, S_RFE_B64, S_CBRANCH_JOIN, and S_SET_GPR_IDX_IDX) do not use the SDST scalar destination register. However, Vega's operand encoding function for the SOP1 instruction type's class assumed all instructions used the destination register, which results in an assert failure for these instructions. To resolve this, this commit updates the Vega SOP1 operand encoder to ignore the destination register for these specific instructions. Change-Id: I2f0d830f6264fc7f47c0694a2fd5da5d33d2ea0b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60649 Maintainer: Matt Sinclair Tested-by: kokoro Maintainer: Matthew Poremba Reviewed-by: Matthew Poremba --- src/arch/amdgpu/vega/insts/op_encodings.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/arch/amdgpu/vega/insts/op_encodings.cc b/src/arch/amdgpu/vega/insts/op_encodings.cc index 6f78b6962e..4abea2e112 100644 --- a/src/arch/amdgpu/vega/insts/op_encodings.cc +++ b/src/arch/amdgpu/vega/insts/op_encodings.cc @@ -254,9 +254,18 @@ namespace VegaISA opNum++; } - reg = instData.SDST; - dstOps.emplace_back(reg, getOperandSize(opNum), false, + /* + S_SETPC_B64, S_RFE_B64, S_CBRANCH_JOIN, and S_SET_GPR_IDX_IDX do not + use SDST, so don't put anything on dstOps for them. + */ + if ((instData.OP != 0x1D) /* S_SETPC_B64 (29 base 10) */ && + (instData.OP != 0x1F) /* S_RFE_B64 (31 base 10) */ && + (instData.OP != 0x2E) /* S_CBRANCH_JOIN (46 base 10) */ && + (instData.OP != 0x32)) /* S_SET_GPR_IDX_IDX (50 base 10) */ { + reg = instData.SDST; + dstOps.emplace_back(reg, getOperandSize(opNum), false, isScalarReg(instData.SDST), false, false); + } assert(srcOps.size() == numSrcRegOperands()); assert(dstOps.size() == numDstRegOperands());