
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.813572                       # Number of seconds simulated
sim_ticks                                2813572242000                       # Number of ticks simulated
final_tick                               2813572242000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1893151                       # Simulator instruction rate (inst/s)
host_op_rate                                  1893151                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2651343461                       # Simulator tick rate (ticks/s)
host_mem_usage                                 227888                       # Number of bytes of host memory used
host_seconds                                  1061.19                       # Real time elapsed on the host
sim_insts                                  2008987605                       # Number of instructions simulated
sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            152128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          94417856                       # Number of bytes read from this memory
system.physmem.bytes_read::total             94569984                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       152128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          152128                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4281472                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4281472                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2377                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1475279                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1477656                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66898                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66898                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                54069                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             33558000                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                33612069                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           54069                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              54069                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1521721                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1521721                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1521721                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               54069                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            33558000                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               35133790                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    511070026                       # DTB read hits
system.cpu.dtb.read_misses                     418884                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                511488910                       # DTB read accesses
system.cpu.dtb.write_hits                   210794896                       # DTB write hits
system.cpu.dtb.write_misses                     14581                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               210809477                       # DTB write accesses
system.cpu.dtb.data_hits                    721864922                       # DTB hits
system.cpu.dtb.data_misses                     433465                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                722298387                       # DTB accesses
system.cpu.itb.fetch_hits                  2009421071                       # ITB hits
system.cpu.itb.fetch_misses                       105                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses              2009421176                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   39                       # Number of system calls
system.cpu.numCycles                       5627144484                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  2008987605                       # Number of instructions committed
system.cpu.committedOps                    2008987605                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    172959296                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   1779374816                       # number of integer instructions
system.cpu.num_fp_insts                      71831671                       # number of float instructions
system.cpu.num_int_register_reads          2314712013                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1332688300                       # number of times the integer registers were written
system.cpu.num_fp_register_reads             77066699                       # number of times the floating registers were read
system.cpu.num_fp_register_writes            52280770                       # number of times the floating registers were written
system.cpu.num_mem_refs                     722298387                       # number of memory refs
system.cpu.num_load_insts                   511488910                       # Number of load instructions
system.cpu.num_store_insts                  210809477                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 5627144484                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                   9046                       # number of replacements
system.cpu.icache.tagsinuse               1478.417406                       # Cycle average of tags in use
system.cpu.icache.total_refs               2009410475                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               189638.587675                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1478.417406                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.721883                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.721883                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst   2009410475                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      2009410475                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    2009410475                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       2009410475                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   2009410475                       # number of overall hits
system.cpu.icache.overall_hits::total      2009410475                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        10596                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         10596                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        10596                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          10596                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        10596                       # number of overall misses
system.cpu.icache.overall_misses::total         10596                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    248319000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    248319000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    248319000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    248319000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    248319000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    248319000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   2009421071                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   2009421071                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   2009421071                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   2009421071                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   2009421071                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   2009421071                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000005                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000005                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000005                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23435.164213                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23435.164213                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23435.164213                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23435.164213                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23435.164213                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23435.164213                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10596                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        10596                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        10596                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        10596                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        10596                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        10596                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216531000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    216531000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216531000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    216531000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216531000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    216531000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000005                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000005                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20435.164213                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20435.164213                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20435.164213                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20435.164213                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20435.164213                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20435.164213                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1526048                       # number of replacements
system.cpu.dcache.tagsinuse               4095.192384                       # Cycle average of tags in use
system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             1063975000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4095.192384                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999803                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999803                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    509611834                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       509611834                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    210722944                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      210722944                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     720334778                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        720334778                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    720334778                       # number of overall hits
system.cpu.dcache.overall_hits::total       720334778                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1458192                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1458192                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        71952                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        71952                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1530144                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1530144                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1530144                       # number of overall misses
system.cpu.dcache.overall_misses::total       1530144                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  79567803000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  79567803000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   3816006000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   3816006000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  83383809000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  83383809000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  83383809000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  83383809000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    511070026                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    511070026                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    721864922                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    721864922                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    721864922                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    721864922                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002853                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002853                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000341                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000341                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002120                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002120                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002120                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002120                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.067431                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.067431                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.440294                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.440294                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.092713                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54494.092713                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.092713                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54494.092713                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       109771                       # number of writebacks
system.cpu.dcache.writebacks::total            109771                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1458192                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1458192                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71952                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        71952                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1530144                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1530144                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1530144                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1530144                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75193227000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  75193227000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3600150000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3600150000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78793377000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  78793377000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78793377000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  78793377000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002853                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002853                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000341                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000341                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002120                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002120                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.067431                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.067431                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.440294                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.440294                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.092713                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.092713                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.092713                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.092713                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements               1479705                       # number of replacements
system.cpu.l2cache.tagsinuse             32703.875584                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   65761                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs               1512436                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.043480                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks  3255.326122                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     33.503711                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  29415.045751                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.099345                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.001022                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.897676                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.998043                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         8219                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        49786                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          58005                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       109771                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       109771                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         5079                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         5079                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         8219                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        54865                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           63084                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         8219                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        54865                       # number of overall hits
system.cpu.l2cache.overall_hits::total          63084                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2377                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1408406                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1410783                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66873                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66873                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2377                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1475279                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1477656                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2377                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1475279                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1477656                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    123604000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  73237112000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  73360716000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3477396000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   3477396000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    123604000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  76714508000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  76838112000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    123604000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  76714508000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  76838112000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        10596                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1458192                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1468788                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       109771                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       109771                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        71952                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        71952                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        10596                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1530144                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1540740                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        10596                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1530144                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1540740                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.224330                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.965858                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.960508                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.929411                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.929411                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.224330                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.964144                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.959056                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.224330                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.964144                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.959056                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
system.cpu.l2cache.writebacks::total            66898                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2377                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1408406                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1410783                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66873                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66873                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2377                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1475279                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1477656                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2377                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1475279                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1477656                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     95080000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56336240000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56431320000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2674920000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2674920000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     95080000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59011160000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  59106240000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     95080000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59011160000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  59106240000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.965858                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.960508                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.929411                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.929411                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964144                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.959056                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964144                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.959056                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
