
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.642008                       # Number of seconds simulated
sim_ticks                                2642007987000                       # Number of ticks simulated
final_tick                               2642007987000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1913242                       # Simulator instruction rate (inst/s)
host_op_rate                                  1913242                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2777698581                       # Simulator tick rate (ticks/s)
host_mem_usage                                 217920                       # Number of bytes of host memory used
host_seconds                                   951.15                       # Real time elapsed on the host
sim_insts                                  1819780127                       # Number of instructions simulated
sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             51328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         137580288                       # Number of bytes read from this memory
system.physmem.bytes_read::total            137631616                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        51328                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           51328                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     67105600                       # Number of bytes written to this memory
system.physmem.bytes_written::total          67105600                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                802                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            2149692                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2150494                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1048525                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1048525                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                19428                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             52074138                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                52093565                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           19428                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              19428                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          25399469                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               25399469                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          25399469                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               19428                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            52074138                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               77493034                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    444595663                       # DTB read hits
system.cpu.dtb.read_misses                    4897078                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                449492741                       # DTB read accesses
system.cpu.dtb.write_hits                   160728502                       # DTB write hits
system.cpu.dtb.write_misses                   1701304                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               162429806                       # DTB write accesses
system.cpu.dtb.data_hits                    605324165                       # DTB hits
system.cpu.dtb.data_misses                    6598382                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                611922547                       # DTB accesses
system.cpu.itb.fetch_hits                  1826378510                       # ITB hits
system.cpu.itb.fetch_misses                        18                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses              1826378528                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   29                       # Number of system calls
system.cpu.numCycles                       5284015974                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  1819780127                       # Number of instructions committed
system.cpu.committedOps                    1819780127                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            1725565901                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 805526                       # Number of float alu accesses
system.cpu.num_func_calls                    33534877                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    164021647                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   1725565901                       # number of integer instructions
system.cpu.num_fp_insts                        805526                       # number of float instructions
system.cpu.num_int_register_reads          2347934659                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1376202618                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                  357                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                 345                       # number of times the floating registers were written
system.cpu.num_mem_refs                     611922547                       # number of memory refs
system.cpu.num_load_insts                   449492741                       # Number of load instructions
system.cpu.num_store_insts                  162429806                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 5284015974                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                      1                       # number of replacements
system.cpu.icache.tagsinuse                612.519467                       # Cycle average of tags in use
system.cpu.icache.total_refs               1826377708                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               2277278.937656                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     612.519467                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.299082                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.299082                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst   1826377708                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      1826377708                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    1826377708                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       1826377708                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   1826377708                       # number of overall hits
system.cpu.icache.overall_hits::total      1826377708                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          802                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           802                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          802                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
system.cpu.icache.overall_misses::total           802                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     45149000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     45149000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     45149000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     45149000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     45149000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     45149000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   1826378510                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   1826378510                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   1826378510                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   1826378510                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   1826378510                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   1826378510                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56295.511222                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56295.511222                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56295.511222                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56295.511222                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56295.511222                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56295.511222                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          802                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42743000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     42743000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42743000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     42743000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42743000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     42743000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53295.511222                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53295.511222                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53295.511222                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                9107638                       # number of replacements
system.cpu.dcache.tagsinuse               4079.366966                       # Cycle average of tags in use
system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle            40989979000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4079.366966                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.995939                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.995939                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    437373249                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       437373249                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    158839182                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      158839182                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     596212431                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        596212431                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    596212431                       # number of overall hits
system.cpu.dcache.overall_hits::total       596212431                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7222414                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7222414                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1889320                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1889320                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      9111734                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9111734                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9111734                       # number of overall misses
system.cpu.dcache.overall_misses::total       9111734                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 158759423000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 158759423000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  59584620000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  59584620000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 218344043000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 218344043000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 218344043000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 218344043000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    605324165                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    605324165                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    605324165                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    605324165                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016245                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.016245                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.011755                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.011755                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.015053                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.015053                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.015053                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.015053                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21981.490261                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21981.490261                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31537.600830                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31537.600830                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23962.951838                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23962.951838                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23962.951838                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23962.951838                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3389919                       # number of writebacks
system.cpu.dcache.writebacks::total           3389919                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222414                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7222414                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889320                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1889320                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9111734                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9111734                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9111734                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9111734                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137092181000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 137092181000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53916660000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  53916660000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191008841000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 191008841000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191008841000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 191008841000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011755                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011755                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015053                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.015053                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015053                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.015053                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18981.490261                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18981.490261                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28537.600830                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28537.600830                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20962.951838                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20962.951838                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20962.951838                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20962.951838                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements               2133721                       # number of replacements
system.cpu.l2cache.tagsinuse             30166.534681                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 8449191                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs               2163414                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  3.905490                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          498438853000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14372.614424                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     37.649566                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  15756.270691                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.438617                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.001149                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.480843                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.920610                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data      5861531                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        5861531                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3389919                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3389919                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1100511                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1100511                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data      6962042                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         6962042                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      6962042                       # number of overall hits
system.cpu.l2cache.overall_hits::total        6962042                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          802                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1360883                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1361685                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       788809                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       788809                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          802                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      2149692                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2150494                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          802                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      2149692                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2150494                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     41704000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  70765916000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  70807620000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41018068000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  41018068000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     41704000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 111783984000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 111825688000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     41704000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 111783984000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 111825688000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          802                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7222414                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7223216                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3389919                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3389919                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889320                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1889320                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          802                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9111734                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9112536                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          802                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9111734                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9112536                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.188425                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.188515                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.417509                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.417509                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.235926                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.235993                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.235926                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.235993                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1048525                       # number of writebacks
system.cpu.l2cache.writebacks::total          1048525                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1360883                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1361685                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       788809                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       788809                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      2149692                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2150494                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      2149692                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2150494                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     32080000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  54435320000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  54467400000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31552360000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31552360000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     32080000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  85987680000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  86019760000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     32080000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  85987680000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  86019760000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.188425                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.188515                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.417509                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.417509                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.235926                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.235993                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.235926                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.235993                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
