
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.720346                       # Number of seconds simulated
sim_ticks                                720345914000                       # Number of ticks simulated
final_tick                               720345914000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 808443                       # Simulator instruction rate (inst/s)
host_op_rate                                   910979                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1153216038                       # Simulator tick rate (ticks/s)
host_mem_usage                                 236932                       # Number of bytes of host memory used
host_seconds                                   624.64                       # Real time elapsed on the host
sim_insts                                   504986853                       # Number of instructions simulated
sim_ops                                     569034839                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            178368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9663872                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9842240                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       178368                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          178368                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6574720                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6574720                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2787                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             150998                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                153785                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          102730                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               102730                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               247614                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             13415599                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                13663213                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          247614                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             247614                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           9127171                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                9127171                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           9127171                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              247614                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            13415599                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               22790384                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                       1440691828                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   504986853                       # Number of instructions committed
system.cpu.committedOps                     569034839                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             470727695                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
system.cpu.num_func_calls                    19311615                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     94894804                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    470727695                       # number of integer instructions
system.cpu.num_fp_insts                            16                       # number of float instructions
system.cpu.num_int_register_reads          2844375179                       # number of times the integer registers were read
system.cpu.num_int_register_writes          646169352                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                     182890034                       # number of memory refs
system.cpu.num_load_insts                   126029555                       # Number of load instructions
system.cpu.num_store_insts                   56860479                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 1440691828                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                   9788                       # number of replacements
system.cpu.icache.tagsinuse                983.378720                       # Cycle average of tags in use
system.cpu.icache.total_refs                516599855                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               44839.845066                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     983.378720                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.480165                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.480165                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    516599855                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       516599855                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     516599855                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        516599855                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    516599855                       # number of overall hits
system.cpu.icache.overall_hits::total       516599855                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        11521                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         11521                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        11521                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          11521                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        11521                       # number of overall misses
system.cpu.icache.overall_misses::total         11521                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    279753000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    279753000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    279753000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    279753000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    279753000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    279753000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    516611376                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    516611376                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    516611376                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    516611376                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    516611376                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    516611376                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24282.006770                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 24282.006770                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24282.006770                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 24282.006770                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24282.006770                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24282.006770                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11521                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        11521                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        11521                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        11521                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        11521                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        11521                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    245190000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    245190000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    245190000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    245190000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    245190000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    245190000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21282.006770                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21282.006770                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21282.006770                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21282.006770                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21282.006770                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21282.006770                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1134822                       # number of replacements
system.cpu.dcache.tagsinuse               4065.381389                       # Cycle average of tags in use
system.cpu.dcache.total_refs                179817786                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1138918                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 157.884752                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle            11899663000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4065.381389                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.992525                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.992525                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    122957658                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       122957658                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53883046                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     176840704                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        176840704                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    176840704                       # number of overall hits
system.cpu.dcache.overall_hits::total       176840704                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       782658                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        782658                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       356260                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       356260                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1138918                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1138918                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  13181704000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  13181704000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9327564000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9327564000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  22509268000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  22509268000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  22509268000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  22509268000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    123740316                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    123740316                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    177979622                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    177979622                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    177979622                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    177979622                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006325                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.006325                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006568                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006568                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.006399                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.006399                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.006399                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.006399                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16842.227384                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16842.227384                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26181.900859                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26181.900859                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19763.730137                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19763.730137                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19763.730137                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19763.730137                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1061444                       # number of writebacks
system.cpu.dcache.writebacks::total           1061444                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782658                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       782658                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356260                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356260                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1138918                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1138918                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10833730000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  10833730000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8258784000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8258784000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19092514000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  19092514000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19092514000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  19092514000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006325                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006325                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006568                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006399                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006399                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006399                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006399                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13842.227384                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13842.227384                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23181.900859                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23181.900859                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16763.730137                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16763.730137                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16763.730137                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16763.730137                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                122482                       # number of replacements
system.cpu.l2cache.tagsinuse             26939.836590                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1623186                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                153644                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 10.564591                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          344531371000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 23226.765026                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    246.719769                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   3466.351794                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.708825                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.007529                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.105785                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.822139                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         8734                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       734961                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         743695                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1061444                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1061444                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       252959                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       252959                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         8734                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       987920                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          996654                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         8734                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       987920                       # number of overall hits
system.cpu.l2cache.overall_hits::total         996654                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2787                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        47697                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        50484                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       103301                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       103301                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2787                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       150998                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        153785                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2787                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       150998                       # number of overall misses
system.cpu.l2cache.overall_misses::total       153785                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    144924000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2480244000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2625168000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5371652000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5371652000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    144924000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7851896000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   7996820000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    144924000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7851896000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   7996820000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        11521                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       782658                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       794179                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1061444                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1061444                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356260                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356260                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        11521                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1138918                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1150439                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        11521                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1138918                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1150439                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.241906                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.060942                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.063568                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.289960                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.289960                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.241906                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.132580                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.133675                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.241906                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.132580                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.133675                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102730                       # number of writebacks
system.cpu.l2cache.writebacks::total           102730                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2787                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        47697                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        50484                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       103301                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       103301                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2787                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       150998                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       153785                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2787                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       150998                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       153785                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    111480000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1907880000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2019360000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4132040000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4132040000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    111480000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6039920000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6151400000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    111480000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6039920000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6151400000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.241906                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.060942                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.063568                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.289960                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.289960                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.241906                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.132580                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.133675                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.241906                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.132580                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.133675                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
