
---------- Begin Simulation Statistics ----------
sim_seconds                                  5.901049                       # Number of seconds simulated
sim_ticks                                5901048883000                       # Number of ticks simulated
final_tick                               5901048883000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 582820                       # Simulator instruction rate (inst/s)
host_op_rate                                   908086                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1143336514                       # Simulator tick rate (ticks/s)
host_mem_usage                                 274832                       # Number of bytes of host memory used
host_seconds                                  5161.25                       # Real time elapsed on the host
sim_insts                                  3008081022                       # Number of instructions simulated
sim_ops                                    4686862594                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         139043584                       # Number of bytes read from this memory
system.physmem.bytes_read::total            139086784                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        43200                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           43200                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     67393856                       # Number of bytes written to this memory
system.physmem.bytes_written::total          67393856                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                675                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            2172556                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2173231                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1053029                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1053029                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                 7321                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             23562520                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                23569841                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst            7321                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total               7321                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          11420657                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               11420657                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          11420657                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst                7321                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            23562520                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               34990498                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                      11802097766                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  3008081022                       # Number of instructions committed
system.cpu.committedOps                    4686862594                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            4686862523                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    182173300                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   4686862523                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads         11915474418                       # number of times the integer registers were read
system.cpu.num_int_register_writes         5355771935                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                    1677713082                       # number of memory refs
system.cpu.num_load_insts                  1239184745                       # Number of load instructions
system.cpu.num_store_insts                  438528337                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                11802097766                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                     10                       # number of replacements
system.cpu.icache.tagsinuse                555.745887                       # Cycle average of tags in use
system.cpu.icache.total_refs               4013232208                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    675                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               5945529.197037                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     555.745887                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.271360                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.271360                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst   4013232208                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      4013232208                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    4013232208                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       4013232208                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   4013232208                       # number of overall hits
system.cpu.icache.overall_hits::total      4013232208                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           675                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            675                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          675                       # number of overall misses
system.cpu.icache.overall_misses::total           675                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     37868000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     37868000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     37868000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     37868000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     37868000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     37868000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   4013232883                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   4013232883                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   4013232883                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   4013232883                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   4013232883                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   4013232883                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56100.740741                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56100.740741                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          675                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          675                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          675                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35843000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     35843000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35843000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     35843000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35843000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     35843000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                9108581                       # number of replacements
system.cpu.dcache.tagsinuse               4084.618108                       # Cycle average of tags in use
system.cpu.dcache.total_refs               1668600405                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                9112677                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 183.107599                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle            58864195000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4084.618108                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.997221                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.997221                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data   1231961895                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total      1231961895                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    436638510                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      436638510                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data    1668600405                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total       1668600405                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data   1668600405                       # number of overall hits
system.cpu.dcache.overall_hits::total      1668600405                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7222850                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7222850                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1889827                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1889827                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      9112677                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9112677                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9112677                       # number of overall misses
system.cpu.dcache.overall_misses::total       9112677                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 159195313000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  59631053000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  59631053000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 218826366000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 218826366000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 218826366000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 218826366000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data   1239184745                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total   1239184745                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    438528337                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    438528337                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data   1677713082                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total   1677713082                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data   1677713082                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total   1677713082                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005829                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.005829                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004309                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.004309                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.005432                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.005432                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.005432                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24013.400892                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24013.400892                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3375759                       # number of writebacks
system.cpu.dcache.writebacks::total           3375759                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222850                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7222850                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889827                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1889827                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9112677                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9112677                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9112677                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53961572000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  53961572000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 191488335000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 191488335000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.005829                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.004309                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005432                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005432                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements               2158210                       # number of replacements
system.cpu.l2cache.tagsinuse             30851.471482                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 8410861                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs               2187939                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  3.844194                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          1317386123000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14661.795129                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     21.581563                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  16168.094790                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.447442                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.000659                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.493411                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.941512                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data      5840135                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        5840135                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3375759                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3375759                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1099986                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1099986                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data      6940121                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         6940121                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data      6940121                       # number of overall hits
system.cpu.l2cache.overall_hits::total        6940121                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1382715                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1383390                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       789841                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       789841                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      2172556                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2173231                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          675                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      2172556                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2173231                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     35100000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  71901180000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  71936280000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41071732000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  41071732000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     35100000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 112972912000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 113008012000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     35100000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 112972912000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 113008012000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          675                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7222850                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7223525                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3375759                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3375759                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889827                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1889827                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          675                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9112677                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9113352                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          675                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9112677                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9113352                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.191436                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.191512                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.417944                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.417944                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.238410                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.238467                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.238410                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.238467                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1053029                       # number of writebacks
system.cpu.l2cache.writebacks::total          1053029                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1382715                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1383390                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       789841                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       789841                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      2172556                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2173231                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      2172556                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2173231                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     27000000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  55308600000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  55335600000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31593640000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31593640000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     27000000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  86902240000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  86929240000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     27000000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  86902240000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  86929240000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.191436                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.191512                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.417944                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.417944                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.238410                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.238467                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.238410                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.238467                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
