
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.134581                       # Number of seconds simulated
sim_ticks                                134581343000                       # Number of ticks simulated
final_tick                               134581343000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1566292                       # Simulator instruction rate (inst/s)
host_op_rate                                  1566291                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2386143258                       # Simulator tick rate (ticks/s)
host_mem_usage                                 226128                       # Number of bytes of host memory used
host_seconds                                    56.40                       # Real time elapsed on the host
sim_insts                                    88340673                       # Number of instructions simulated
sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            485312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10270528                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10755840                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       485312                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          485312                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7421120                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7421120                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               7583                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             160477                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                168060                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          115955                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               115955                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              3606087                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             76314649                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                79920736                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         3606087                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            3606087                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          55142264                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               55142264                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          55142264                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             3606087                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            76314649                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              135063001                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     20276638                       # DTB read hits
system.cpu.dtb.read_misses                      90148                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                 20366786                       # DTB read accesses
system.cpu.dtb.write_hits                    14613377                       # DTB write hits
system.cpu.dtb.write_misses                      7252                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                14620629                       # DTB write accesses
system.cpu.dtb.data_hits                     34890015                       # DTB hits
system.cpu.dtb.data_misses                      97400                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
system.cpu.itb.fetch_hits                    88438074                       # ITB hits
system.cpu.itb.fetch_misses                      3934                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                88442008                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                 4583                       # Number of system calls
system.cpu.numCycles                        269162686                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    88340673                       # Number of instructions committed
system.cpu.committedOps                      88340673                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      8920848                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     78039444                       # number of integer instructions
system.cpu.num_fp_insts                        267757                       # number of float instructions
system.cpu.num_int_register_reads           105931758                       # number of times the integer registers were read
system.cpu.num_int_register_writes           52319251                       # number of times the integer registers were written
system.cpu.num_fp_register_reads               229023                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              227630                       # number of times the floating registers were written
system.cpu.num_mem_refs                      34987415                       # number of memory refs
system.cpu.num_load_insts                    20366786                       # Number of load instructions
system.cpu.num_store_insts                   14620629                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                  269162686                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                  74391                       # number of replacements
system.cpu.icache.tagsinuse               1871.699205                       # Cycle average of tags in use
system.cpu.icache.total_refs                 88361638                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  76436                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                1156.021220                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1871.699205                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.913916                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.913916                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     88361638                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        88361638                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      88361638                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         88361638                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     88361638                       # number of overall hits
system.cpu.icache.overall_hits::total        88361638                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        76436                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         76436                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        76436                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          76436                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        76436                       # number of overall misses
system.cpu.icache.overall_misses::total         76436                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1390813000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1390813000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1390813000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1390813000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1390813000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1390813000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     88438074                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     88438074                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     88438074                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     88438074                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     88438074                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     88438074                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000864                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000864                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000864                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000864                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000864                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000864                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18195.784709                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18195.784709                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18195.784709                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18195.784709                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18195.784709                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18195.784709                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        76436                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        76436                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        76436                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        76436                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        76436                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        76436                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1161505000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1161505000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1161505000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1161505000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1161505000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1161505000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000864                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000864                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000864                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15195.784709                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15195.784709                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15195.784709                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15195.784709                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15195.784709                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15195.784709                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 200248                       # number of replacements
system.cpu.dcache.tagsinuse               4078.801621                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 34685671                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 169.741568                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              947396000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4078.801621                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.995801                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.995801                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     20215872                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        20215872                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     14469799                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       14469799                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      34685671                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         34685671                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     34685671                       # number of overall hits
system.cpu.dcache.overall_hits::total        34685671                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        60766                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         60766                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       143578                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       143578                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       204344                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         204344                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       204344                       # number of overall misses
system.cpu.dcache.overall_misses::total        204344                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   2092728000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   2092728000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   7513894000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   7513894000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   9606622000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   9606622000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   9606622000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   9606622000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     34890015                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     34890015                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     34890015                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     34890015                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002997                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002997                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009825                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.009825                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.005857                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.005857                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.005857                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.005857                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34439.127143                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34439.127143                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52333.184750                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52333.184750                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47012.009161                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 47012.009161                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47012.009161                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 47012.009161                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       165828                       # number of writebacks
system.cpu.dcache.writebacks::total            165828                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60766                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        60766                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143578                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       143578                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       204344                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       204344                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       204344                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       204344                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1910430000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   1910430000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7083160000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   7083160000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8993590000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   8993590000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8993590000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   8993590000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002997                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009825                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.005857                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.005857                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31439.127143                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31439.127143                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49333.184750                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49333.184750                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44012.009161                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44012.009161                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44012.009161                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44012.009161                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                135625                       # number of replacements
system.cpu.l2cache.tagsinuse             29002.571879                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  136279                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                166491                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.818537                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 25772.303239                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   1646.708734                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   1583.559905                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.786508                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.050254                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.048326                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.885088                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        68853                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        31317                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         100170                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       165828                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       165828                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data        12550                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total        12550                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        68853                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        43867                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          112720                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        68853                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        43867                       # number of overall hits
system.cpu.l2cache.overall_hits::total         112720                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         7583                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        29449                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        37032                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       131028                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       131028                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         7583                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       160477                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        168060                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         7583                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       160477                       # number of overall misses
system.cpu.l2cache.overall_misses::total       168060                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    394316000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1531348000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1925664000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6813456000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6813456000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    394316000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   8344804000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8739120000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    394316000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   8344804000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8739120000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        76436                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        60766                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       137202                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       165828                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       165828                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       143578                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       143578                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        76436                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       204344                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       280780                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        76436                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       204344                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       280780                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.099207                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.484630                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.269909                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912591                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.912591                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.099207                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.785328                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.598547                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.099207                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.785328                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.598547                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       115955                       # number of writebacks
system.cpu.l2cache.writebacks::total           115955                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7583                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        29449                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        37032                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131028                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       131028                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         7583                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       160477                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       168060                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         7583                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       160477                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       168060                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    303320000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1177960000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1481280000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5241120000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5241120000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    303320000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6419080000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6722400000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    303320000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6419080000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6722400000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.099207                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.484630                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.269909                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912591                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912591                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.099207                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.785328                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.598547                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.099207                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.785328                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.598547                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
