
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.270629                       # Number of seconds simulated
sim_ticks                                270628667000                       # Number of ticks simulated
final_tick                               270628667000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1532509                       # Simulator instruction rate (inst/s)
host_op_rate                                  1532510                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2143977461                       # Simulator tick rate (ticks/s)
host_mem_usage                                 235212                       # Number of bytes of host memory used
host_seconds                                   126.23                       # Real time elapsed on the host
sim_insts                                   193444518                       # Number of instructions simulated
sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            230208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            100864                       # Number of bytes read from this memory
system.physmem.bytes_read::total               331072                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       230208                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          230208                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3597                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1576                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5173                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst               850642                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               372703                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1223344                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          850642                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             850642                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              850642                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              372703                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                1223344                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                  401                       # Number of system calls
system.cpu.numCycles                        541257334                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   193444518                       # Number of instructions committed
system.cpu.committedOps                     193444756                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             167974806                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      8665106                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    167974806                       # number of integer instructions
system.cpu.num_fp_insts                       1970372                       # number of float instructions
system.cpu.num_int_register_reads           352617941                       # number of times the integer registers were read
system.cpu.num_int_register_writes          163060123                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
system.cpu.num_mem_refs                      76733958                       # number of memory refs
system.cpu.num_load_insts                    57735091                       # Number of load instructions
system.cpu.num_store_insts                   18998867                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                  541257334                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                  10362                       # number of replacements
system.cpu.icache.tagsinuse               1591.550018                       # Cycle average of tags in use
system.cpu.icache.total_refs                193433248                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  12288                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               15741.638021                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1591.550018                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.777124                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.777124                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    193433248                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       193433248                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     193433248                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        193433248                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    193433248                       # number of overall hits
system.cpu.icache.overall_hits::total       193433248                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        12288                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         12288                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        12288                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          12288                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        12288                       # number of overall misses
system.cpu.icache.overall_misses::total         12288                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    323106000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    323106000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    323106000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    323106000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    323106000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    323106000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    193445536                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    193445536                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    193445536                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    193445536                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    193445536                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    193445536                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000064                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000064                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000064                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000064                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000064                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000064                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 26294.433594                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 26294.433594                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 26294.433594                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12288                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        12288                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        12288                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        12288                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        12288                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        12288                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    286242000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    286242000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    286242000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    286242000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    286242000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    286242000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000064                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000064                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000064                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      2                       # number of replacements
system.cpu.dcache.tagsinuse               1237.179149                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 76732337                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   1576                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               48688.031091                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1237.179149                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.302046                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.302046                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     57734570                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        57734570                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18975362                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18975362                       # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data        22405                       # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total           22405                       # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data      76709932                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         76709932                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     76709932                       # number of overall hits
system.cpu.dcache.overall_hits::total        76709932                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          498                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           498                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1077                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1077                       # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data            1                       # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total             1                       # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data         1575                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           1575                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         1575                       # number of overall misses
system.cpu.dcache.overall_misses::total          1575                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     27888000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     27888000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     60312000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     60312000                       # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data        56000                       # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total        56000                       # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     88200000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     88200000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     88200000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     88200000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     57735068                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     57735068                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     18976439                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     18976439                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data        22406                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total        22406                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     76711507                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     76711507                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     76711507                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     76711507                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000009                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000009                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000057                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000057                       # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.000045                       # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total     0.000045                       # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000021                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000021                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000021                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000021                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        56000                       # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total        56000                       # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks            2                       # number of writebacks
system.cpu.dcache.writebacks::total                 2                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          498                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          498                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1077                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1077                       # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data            1                       # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total            1                       # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         1575                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         1575                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         1575                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         1575                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     26394000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     26394000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57081000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     57081000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        53000                       # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total        53000                       # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     83475000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     83475000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     83475000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     83475000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000057                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000057                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000021                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000021                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        53000                       # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        53000                       # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              2678.289604                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    8691                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  4097                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  2.121308                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks     0.000456                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   2275.240623                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    403.048526                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.069435                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.012300                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.081735                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         8691                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           8691                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks            2                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total            2                       # number of Writeback hits
system.cpu.l2cache.demand_hits::cpu.inst         8691                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            8691                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         8691                       # number of overall hits
system.cpu.l2cache.overall_hits::total           8691                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3597                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          498                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4095                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1078                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1078                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3597                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1576                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          5173                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3597                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1576                       # number of overall misses
system.cpu.l2cache.overall_misses::total         5173                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    187044000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     25896000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    212940000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56056000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     56056000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    187044000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     81952000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    268996000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    187044000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     81952000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    268996000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        12288                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          498                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        12786                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks            2                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total            2                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1078                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1078                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        12288                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1576                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        13864                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        12288                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1576                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        13864                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.292725                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.320272                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.292725                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.373125                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.292725                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.373125                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3597                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          498                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4095                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1078                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1078                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3597                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1576                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         5173                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3597                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1576                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         5173                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    143880000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     19920000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    163800000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     43120000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     43120000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    143880000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     63040000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    206920000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    143880000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     63040000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    206920000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.320272                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.373125                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.373125                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
