
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.250981                       # Number of seconds simulated
sim_ticks                                250980994000                       # Number of ticks simulated
final_tick                               250980994000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 540200                       # Simulator instruction rate (inst/s)
host_op_rate                                   905422                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1026566177                       # Simulator tick rate (ticks/s)
host_mem_usage                                 281300                       # Number of bytes of host memory used
host_seconds                                   244.49                       # Real time elapsed on the host
sim_insts                                   132071193                       # Number of instructions simulated
sim_ops                                     221362961                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            181760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            121280                       # Number of bytes read from this memory
system.physmem.bytes_read::total               303040                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       181760                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          181760                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               2840                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1895                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  4735                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst               724198                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               483224                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1207422                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          724198                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             724198                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              724198                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              483224                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                1207422                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        501961988                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   132071193                       # Number of instructions committed
system.cpu.committedOps                     221362961                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             220339550                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      8268466                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    220339550                       # number of integer instructions
system.cpu.num_fp_insts                       2162459                       # number of float instructions
system.cpu.num_int_register_reads           616958548                       # number of times the integer registers were read
system.cpu.num_int_register_writes          257597200                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
system.cpu.num_mem_refs                      77165302                       # number of memory refs
system.cpu.num_load_insts                    56649586                       # Number of load instructions
system.cpu.num_store_insts                   20515716                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                  501961988                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                   2836                       # number of replacements
system.cpu.icache.tagsinuse               1455.271959                       # Cycle average of tags in use
system.cpu.icache.total_refs                173489674                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   4694                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               36959.879421                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1455.271959                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.710582                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.710582                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    173489674                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       173489674                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     173489674                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        173489674                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    173489674                       # number of overall hits
system.cpu.icache.overall_hits::total       173489674                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         4694                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          4694                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         4694                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           4694                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         4694                       # number of overall misses
system.cpu.icache.overall_misses::total          4694                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    185042500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    185042500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    185042500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    185042500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    185042500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    185042500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    173494368                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    173494368                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    173494368                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    173494368                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    173494368                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    173494368                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000027                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000027                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000027                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000027                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39421.069450                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 39421.069450                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39421.069450                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 39421.069450                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39421.069450                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 39421.069450                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4694                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         4694                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         4694                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         4694                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         4694                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         4694                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    170929000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    170929000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    170929000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    170929000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    170929000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    170929000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000027                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.358756                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.358756                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.358756                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.358756                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                     41                       # number of replacements
system.cpu.dcache.tagsinuse               1363.439047                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 77195829                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   1905                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               40522.744882                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1363.439047                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.332871                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.332871                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     56681677                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        56681677                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     20514152                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       20514152                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      77195829                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         77195829                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     77195829                       # number of overall hits
system.cpu.dcache.overall_hits::total        77195829                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          327                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           327                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1578                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1578                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         1905                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           1905                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         1905                       # number of overall misses
system.cpu.dcache.overall_misses::total          1905                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     18020000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     18020000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     88243000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     88243000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    106263000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    106263000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    106263000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    106263000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     56682004                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     56682004                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     20515730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     77197734                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     77197734                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     77197734                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     77197734                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000006                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000006                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000077                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000077                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55107.033639                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.785805                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.785805                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55781.102362                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 55781.102362                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55781.102362                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55781.102362                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks            7                       # number of writebacks
system.cpu.dcache.writebacks::total                 7                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          327                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          327                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1578                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1578                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         1905                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         1905                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         1905                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         1905                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17038500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     17038500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     83509000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     83509000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    100547500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    100547500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    100547500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    100547500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000006                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000077                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000077                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.785805                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.785805                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.839895                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.839895                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              2058.146468                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    1862                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  3164                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.588496                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks     0.021788                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   1829.948778                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    228.175901                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000001                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.055846                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.006963                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.062810                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         1854                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data            7                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           1861                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks            7                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total            7                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            3                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total            3                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         1854                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           10                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            1864                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         1854                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           10                       # number of overall hits
system.cpu.l2cache.overall_hits::total           1864                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2840                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          320                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         3160                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1575                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1575                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2840                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1895                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          4735                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2840                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1895                       # number of overall misses
system.cpu.l2cache.overall_misses::total         4735                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    147694000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16641500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    164335500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     81900000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     81900000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    147694000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     98541500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    246235500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    147694000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     98541500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    246235500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         4694                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          327                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         5021                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks            7                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total            7                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1578                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1578                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         4694                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1905                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         6599                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         4694                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1905                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         6599                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.605028                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.978593                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.629357                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.998099                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.998099                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.605028                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.994751                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.717533                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.605028                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.994751                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.717533                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.905063                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52003.273495                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52003.273495                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2840                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          320                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         3160                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1575                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1575                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2840                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1895                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         4735                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2840                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1895                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         4735                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    113600000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12800000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    126400000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     63000000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     63000000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    113600000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     75800000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    189400000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    113600000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     75800000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    189400000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.978593                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.629357                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.998099                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.998099                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.994751                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.717533                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.994751                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.717533                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
