
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.232090                       # Number of seconds simulated
sim_ticks                                232089948000                       # Number of ticks simulated
final_tick                               232089948000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1678684                       # Simulator instruction rate (inst/s)
host_op_rate                                  1838338                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2267224735                       # Simulator tick rate (ticks/s)
host_mem_usage                                 235976                       # Number of bytes of host memory used
host_seconds                                   102.37                       # Real time elapsed on the host
sim_insts                                   171842483                       # Number of instructions simulated
sim_ops                                     188185920                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            110336                       # Number of bytes read from this memory
system.physmem.bytes_read::total               220992                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       110656                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          110656                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               1729                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1724                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  3453                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst               476781                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               475402                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  952183                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          476781                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             476781                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              476781                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              475402                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                 952183                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        464179896                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   171842483                       # Number of instructions committed
system.cpu.committedOps                     188185920                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             150106218                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
system.cpu.num_func_calls                     3545028                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     32493890                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    150106218                       # number of integer instructions
system.cpu.num_fp_insts                       1752310                       # number of float instructions
system.cpu.num_int_register_reads           898652246                       # number of times the integer registers were read
system.cpu.num_int_register_writes          294073517                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
system.cpu.num_mem_refs                      42494119                       # number of memory refs
system.cpu.num_load_insts                    29849484                       # Number of load instructions
system.cpu.num_store_insts                   12644635                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                  464179896                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                   1506                       # number of replacements
system.cpu.icache.tagsinuse               1147.971530                       # Cycle average of tags in use
system.cpu.icache.total_refs                189857001                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               62227.794494                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1147.971530                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.560533                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.560533                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    189857001                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       189857001                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     189857001                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        189857001                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    189857001                       # number of overall hits
system.cpu.icache.overall_hits::total       189857001                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         3051                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          3051                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         3051                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           3051                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         3051                       # number of overall misses
system.cpu.icache.overall_misses::total          3051                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    115332000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    115332000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    115332000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    115332000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    115332000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    115332000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    189860052                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    189860052                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    189860052                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    189860052                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    189860052                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    189860052                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000016                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000016                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000016                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 37801.376598                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 37801.376598                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 37801.376598                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3051                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         3051                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         3051                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         3051                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         3051                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         3051                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    106179000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    106179000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    106179000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    106179000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    106179000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    106179000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                     40                       # number of replacements
system.cpu.dcache.tagsinuse               1363.590777                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 42007358                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   1789                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               23480.915595                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1363.590777                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.332908                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.332908                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     29599357                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        29599357                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12363187                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41962544                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41962544                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41962544                       # number of overall hits
system.cpu.dcache.overall_hits::total        41962544                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          689                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           689                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1100                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1100                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         1789                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           1789                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     36195000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     36195000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     61264000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     61264000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     97459000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     97459000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     97459000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     97459000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     29600046                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     29600046                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41964333                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41964333                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     41964333                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     41964333                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000023                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000023                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000089                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52532.656023                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 52532.656023                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54476.802683                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54476.802683                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54476.802683                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54476.802683                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
system.cpu.dcache.writebacks::total                16                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          689                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          689                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1100                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1100                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         1789                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         1789                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34128000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     34128000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57964000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     57964000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92092000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     92092000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92092000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     92092000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000043                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000043                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49532.656023                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49532.656023                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51476.802683                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51476.802683                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51476.802683                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51476.802683                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              1675.633213                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    1380                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.582524                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks     3.038052                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   1169.018140                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    503.577021                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000093                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.035676                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.051136                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         1322                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           57                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           1379                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         1322                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           65                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            1387                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         1322                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           65                       # number of overall hits
system.cpu.l2cache.overall_hits::total           1387                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         1729                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          632                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         2361                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1092                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1092                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1729                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         1724                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          3453                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1729                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         1724                       # number of overall misses
system.cpu.l2cache.overall_misses::total         3453                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     89908000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32864000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    122772000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56784000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     56784000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     89908000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     89648000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    179556000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     89908000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     89648000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    179556000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         3051                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          689                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         3740                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1100                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1100                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         3051                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         1789                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         4840                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         3051                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         1789                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         4840                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.566699                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.917271                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.631283                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992727                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.992727                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.566699                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.963667                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.713430                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.566699                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.963667                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.713430                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1729                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          632                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         2361                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1092                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1092                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1729                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         1724                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         3453                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1729                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         1724                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         3453                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     69160000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     25280000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     94440000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     43680000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     43680000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     69160000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     68960000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    138120000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     69160000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     68960000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    138120000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.917271                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.631283                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992727                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992727                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.713430                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.713430                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
