
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000018                       # Number of seconds simulated
sim_ticks                                    17541000                       # Number of ticks simulated
final_tick                                   17541000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 207586                       # Simulator instruction rate (inst/s)
host_op_rate                                   207300                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1409208031                       # Simulator tick rate (ticks/s)
host_mem_usage                                 216876                       # Number of bytes of host memory used
host_seconds                                     0.01                       # Real time elapsed on the host
sim_insts                                        2577                       # Number of instructions simulated
sim_ops                                          2577                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             10432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              5248                       # Number of bytes read from this memory
system.physmem.bytes_read::total                15680                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        10432                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           10432                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                163                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                 82                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   245                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            594720940                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            299184767                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               893905707                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       594720940                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          594720940                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           594720940                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           299184767                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              893905707                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                          415                       # DTB read hits
system.cpu.dtb.read_misses                          4                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                      419                       # DTB read accesses
system.cpu.dtb.write_hits                         294                       # DTB write hits
system.cpu.dtb.write_misses                         4                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                     298                       # DTB write accesses
system.cpu.dtb.data_hits                          709                       # DTB hits
system.cpu.dtb.data_misses                          8                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                      717                       # DTB accesses
system.cpu.itb.fetch_hits                        2586                       # ITB hits
system.cpu.itb.fetch_misses                        11                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                    2597                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                    4                       # Number of system calls
system.cpu.numCycles                            35082                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        2577                       # Number of instructions committed
system.cpu.committedOps                          2577                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
system.cpu.num_func_calls                         140                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
system.cpu.num_int_insts                         2375                       # number of integer instructions
system.cpu.num_fp_insts                             6                       # number of float instructions
system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                           717                       # number of memory refs
system.cpu.num_load_insts                         419                       # Number of load instructions
system.cpu.num_store_insts                        298                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                      35082                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.tagsinuse                 80.027768                       # Cycle average of tags in use
system.cpu.icache.total_refs                     2423                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    163                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  14.865031                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst      80.027768                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.039076                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.039076                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst         2423                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            2423                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          2423                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             2423                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         2423                       # number of overall hits
system.cpu.icache.overall_hits::total            2423                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           163                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          163                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            163                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          163                       # number of overall misses
system.cpu.icache.overall_misses::total           163                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst      9128000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total      9128000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst      9128000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total      9128000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst      9128000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total      9128000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         2586                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         2586                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         2586                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         2586                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         2586                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         2586                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.063032                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.063032                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.063032                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.063032                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.063032                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.063032                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          163                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          163                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          163                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          163                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          163                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      8639000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total      8639000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst      8639000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total      8639000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst      8639000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total      8639000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.063032                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.063032                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.063032                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.tagsinuse                 47.439715                       # Cycle average of tags in use
system.cpu.dcache.total_refs                      627                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                     82                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                   7.646341                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data      47.439715                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.011582                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.011582                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data          360                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total             360                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          267                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            267                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data           627                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total              627                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data          627                       # number of overall hits
system.cpu.dcache.overall_hits::total             627                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            55                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           27                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           27                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data           82                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total             82                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data           82                       # number of overall misses
system.cpu.dcache.overall_misses::total            82                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      3080000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      3080000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      1512000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      1512000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data      4592000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total      4592000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data      4592000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total      4592000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data          415                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total          415                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data          709                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total          709                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data          709                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total          709                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.132530                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.132530                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.091837                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.091837                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.115656                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.115656                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.115656                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.115656                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           27                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           27                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data           82                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total           82                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data           82                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total           82                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2915000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      2915000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1431000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      1431000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4346000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      4346000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4346000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      4346000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.132530                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.132530                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.115656                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.115656                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.115656                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.115656                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse               107.121835                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                   218                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst     80.139278                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data     26.982557                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst     0.002446                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.000823                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.003269                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          218                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           27                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           27                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          163                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data           82                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           245                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          163                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data           82                       # number of overall misses
system.cpu.l2cache.overall_misses::total          245                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      8476000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2860000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     11336000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1404000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      1404000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst      8476000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      4264000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     12740000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst      8476000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      4264000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     12740000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          163                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          218                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          163                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data           82                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          245                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          163                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data           82                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          245                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          163                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          218                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           27                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          163                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data           82                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          245                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          163                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data           82                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          245                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      6520000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2200000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total      8720000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1080000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1080000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      6520000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3280000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total      9800000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      6520000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3280000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total      9800000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
