
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.204097                       # Number of seconds simulated
sim_ticks                                204097178000                       # Number of ticks simulated
final_tick                               204097178000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1441199                       # Simulator instruction rate (inst/s)
host_op_rate                                  1459859                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2188591939                       # Simulator tick rate (ticks/s)
host_mem_usage                                 238748                       # Number of bytes of host memory used
host_seconds                                    93.26                       # Real time elapsed on the host
sim_insts                                   134398962                       # Number of instructions simulated
sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            665664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7906112                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8571776                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       665664                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          665664                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5301376                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5301376                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              10401                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             123533                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                133934                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           82834                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                82834                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              3261505                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             38736998                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                41998503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         3261505                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            3261505                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          25974764                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               25974764                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          25974764                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             3261505                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            38736998                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               67973267                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                        408194356                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   134398962                       # Number of instructions committed
system.cpu.committedOps                     136139190                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             115187746                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      8898969                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    115187746                       # number of integer instructions
system.cpu.num_fp_insts                       2326977                       # number of float instructions
system.cpu.num_int_register_reads           263032361                       # number of times the integer registers were read
system.cpu.num_int_register_writes          113147733                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
system.cpu.num_mem_refs                      58160248                       # number of memory refs
system.cpu.num_load_insts                    37275867                       # Number of load instructions
system.cpu.num_store_insts                   20884381                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                  408194356                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                 184976                       # number of replacements
system.cpu.icache.tagsinuse               2004.409949                       # Cycle average of tags in use
system.cpu.icache.total_refs                134366547                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                 718.445478                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle           145330286000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    2004.409949                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.978716                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.978716                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    134366547                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       134366547                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     134366547                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        134366547                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    134366547                       # number of overall hits
system.cpu.icache.overall_hits::total       134366547                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       187024                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        187024                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       187024                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         187024                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       187024                       # number of overall misses
system.cpu.icache.overall_misses::total        187024                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   3060544000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   3060544000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   3060544000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   3060544000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   3060544000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   3060544000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    134553571                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    134553571                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    134553571                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    134553571                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    134553571                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    134553571                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001390                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001390                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001390                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001390                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001390                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001390                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16364.445205                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16364.445205                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16364.445205                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16364.445205                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16364.445205                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16364.445205                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       187024                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       187024                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       187024                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       187024                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       187024                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       187024                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2499472000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   2499472000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2499472000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   2499472000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2499472000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   2499472000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001390                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001390                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001390                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13364.445205                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13364.445205                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13364.445205                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13364.445205                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 146582                       # number of replacements
system.cpu.dcache.tagsinuse               4087.413116                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 57960842                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 384.666919                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              812030000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4087.413116                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.997904                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.997904                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     37185801                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        37185801                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       20759140                       # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data        15901                       # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total           15901                       # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data      57944941                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         57944941                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     57944941                       # number of overall hits
system.cpu.dcache.overall_hits::total        57944941                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        45499                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         45499                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       105164                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       105164                       # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data           15                       # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total            15                       # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data       150663                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         150663                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       150663                       # number of overall misses
system.cpu.dcache.overall_misses::total        150663                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1571682000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1571682000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   5728295000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   5728295000                       # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data       430000                       # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total       430000                       # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   7299977000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   7299977000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   7299977000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   7299977000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     37231300                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     37231300                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     20864304                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data        15916                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total        15916                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     58095604                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     58095604                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     58095604                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     58095604                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001222                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.001222                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005040                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.005040                       # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.000942                       # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total     0.000942                       # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002593                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002593                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002593                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002593                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34543.220730                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34543.220730                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54470.113347                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54470.113347                       # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28666.666667                       # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 28666.666667                       # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48452.353929                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 48452.353929                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48452.353929                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 48452.353929                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       122378                       # number of writebacks
system.cpu.dcache.writebacks::total            122378                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        45499                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        45499                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       105164                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       105164                       # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data           15                       # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total           15                       # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       150663                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       150663                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       150663                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       150663                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1435185000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   1435185000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5412803000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5412803000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       385000                       # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total       385000                       # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6847988000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   6847988000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6847988000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   6847988000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001222                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001222                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005040                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005040                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.000942                       # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total     0.000942                       # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002593                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002593                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31543.220730                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31543.220730                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51470.113347                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51470.113347                       # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25666.666667                       # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25666.666667                       # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45452.353929                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45452.353929                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                101560                       # number of replacements
system.cpu.l2cache.tagsinuse             29278.942435                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  222505                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                132357                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  1.681097                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 24760.228137                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3263.271559                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   1255.442739                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.755622                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.099587                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.038313                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.893522                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst       176623                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        23301                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         199924                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       122378                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       122378                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         3844                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         3844                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       176623                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        27145                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          203768                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       176623                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        27145                       # number of overall hits
system.cpu.l2cache.overall_hits::total         203768                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        10401                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        22198                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        32599                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       101335                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       101335                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        10401                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       123533                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        133934                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        10401                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       123533                       # number of overall misses
system.cpu.l2cache.overall_misses::total       133934                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    540852000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1154296000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1695148000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5269420000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5269420000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    540852000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   6423716000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   6964568000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    540852000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   6423716000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   6964568000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       187024                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        45499                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       232523                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       122378                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       122378                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       105179                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       105179                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       187024                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       150678                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       337702                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       187024                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       150678                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       337702                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.055613                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.487879                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.140197                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.963453                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.963453                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.055613                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.819848                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.396604                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.055613                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.819848                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.396604                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        82834                       # number of writebacks
system.cpu.l2cache.writebacks::total            82834                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10401                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        22198                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        32599                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101335                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       101335                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10401                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       123533                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       133934                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10401                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       123533                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       133934                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    416040000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    887920000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1303960000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4053400000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4053400000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    416040000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4941320000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   5357360000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    416040000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4941320000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   5357360000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.055613                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.487879                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.140197                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.963453                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.963453                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.055613                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.819848                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.396604                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.055613                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.819848                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.396604                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
