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# Authors: Steve Reinhardt

import m5
from m5.objects import *

class MyCache(BaseCache):
    assoc = 2
    block_size = 64
    latency = '1ns'
    mshrs = 10
    tgts_per_mshr = 5

class MyL1Cache(MyCache):
    is_top_level = True

cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
                              MyL1Cache(size = '256kB'),
                              MyCache(size = '2MB', latency='10ns'))
system = System(cpu = cpu,
                physmem = SimpleMemory(),
                membus = CoherentBus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'

root = Root(full_system=False, system = system)
