
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.764109                       # Number of seconds simulated
sim_ticks                                764109115000                       # Number of ticks simulated
final_tick                               764109115000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                2465110                       # Simulator instruction rate (inst/s)
host_op_rate                                  2465110                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3129668646                       # Simulator tick rate (ticks/s)
host_mem_usage                                 218984                       # Number of bytes of host memory used
host_seconds                                   244.15                       # Real time elapsed on the host
sim_insts                                   601856964                       # Number of instructions simulated
sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             50112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           1620160                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1670272                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        50112                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           50112                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks        56512                       # Number of bytes written to this memory
system.physmem.bytes_written::total             56512                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                783                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              25315                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 26098                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks             883                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                  883                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                65582                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2120325                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2185908                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           65582                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              65582                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks             73958                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                  73958                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks             73958                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               65582                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2120325                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2259866                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    114514042                       # DTB read hits
system.cpu.dtb.read_misses                       2631                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                114516673                       # DTB read accesses
system.cpu.dtb.write_hits                    39451321                       # DTB write hits
system.cpu.dtb.write_misses                      2302                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                39453623                       # DTB write accesses
system.cpu.dtb.data_hits                    153965363                       # DTB hits
system.cpu.dtb.data_misses                       4933                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                153970296                       # DTB accesses
system.cpu.itb.fetch_hits                   601861898                       # ITB hits
system.cpu.itb.fetch_misses                        20                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               601861918                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   17                       # Number of system calls
system.cpu.numCycles                       1528218230                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   601856964                       # Number of instructions committed
system.cpu.committedOps                     601856964                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     58554292                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    563959696                       # number of integer instructions
system.cpu.num_fp_insts                          1520                       # number of float instructions
system.cpu.num_int_register_reads           801088993                       # number of times the integer registers were read
system.cpu.num_int_register_writes          463854847                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                  169                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                  42                       # number of times the floating registers were written
system.cpu.num_mem_refs                     153970296                       # number of memory refs
system.cpu.num_load_insts                   114516673                       # Number of load instructions
system.cpu.num_store_insts                   39453623                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 1528218230                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                     24                       # number of replacements
system.cpu.icache.tagsinuse                673.286058                       # Cycle average of tags in use
system.cpu.icache.total_refs                601861103                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    795                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               757057.991195                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     673.286058                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.328753                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.328753                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    601861103                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       601861103                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     601861103                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        601861103                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    601861103                       # number of overall hits
system.cpu.icache.overall_hits::total       601861103                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          795                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           795                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          795                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            795                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          795                       # number of overall misses
system.cpu.icache.overall_misses::total           795                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     44165000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     44165000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     44165000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     44165000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     44165000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     44165000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    601861898                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    601861898                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    601861898                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    601861898                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    601861898                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    601861898                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000001                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000001                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000001                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55553.459119                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55553.459119                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          795                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          795                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          795                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          795                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          795                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          795                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     41780000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     41780000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     41780000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     41780000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     41780000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     41780000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000001                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000001                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 451299                       # number of replacements
system.cpu.dcache.tagsinuse               4094.128141                       # Cycle average of tags in use
system.cpu.dcache.total_refs                153509968                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 337.091905                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              590218000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4094.128141                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999543                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999543                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    114312810                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114312810                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     39197158                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       39197158                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     153509968                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        153509968                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    153509968                       # number of overall hits
system.cpu.dcache.overall_hits::total       153509968                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       201232                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        201232                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       254163                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       254163                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       455395                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         455395                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       455395                       # number of overall misses
system.cpu.dcache.overall_misses::total        455395                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   2991812000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   2991812000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   4452609000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   4452609000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   7444421000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   7444421000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   7444421000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   7444421000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    114514042                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    114514042                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     39451321                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    153965363                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    153965363                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    153965363                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    153965363                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001757                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.001757                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006442                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006442                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002958                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002958                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002958                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002958                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16347.173333                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16347.173333                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       436902                       # number of writebacks
system.cpu.dcache.writebacks::total            436902                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       201232                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       201232                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254163                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       254163                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       455395                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       455395                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       455395                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       455395                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2388116000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2388116000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3690120000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3690120000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6078236000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   6078236000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6078236000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   6078236000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001757                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001757                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006442                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006442                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002958                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002958                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                   903                       # number of replacements
system.cpu.l2cache.tagsinuse             22839.375690                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  538870                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                 23085                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 23.342863                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21645.673483                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    668.235332                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    525.466875                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.660574                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.020393                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.016036                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.697002                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst           12                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       197110                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         197122                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       436902                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       436902                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       232970                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       232970                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           12                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       430080                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          430092                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           12                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       430080                       # number of overall hits
system.cpu.l2cache.overall_hits::total         430092                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          783                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         4122                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4905                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        21193                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        21193                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          783                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        25315                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         26098                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          783                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        25315                       # number of overall misses
system.cpu.l2cache.overall_misses::total        26098                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     40716000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    214344000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    255060000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1102036000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1102036000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     40716000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   1316380000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   1357096000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     40716000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   1316380000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   1357096000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          795                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       201232                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       202027                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       436902                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       436902                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       254163                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       254163                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          795                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       455395                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       456190                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          795                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       455395                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       456190                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.984906                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.020484                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.024279                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083383                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.083383                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.984906                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.055589                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.057209                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.984906                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.055589                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.057209                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks          883                       # number of writebacks
system.cpu.l2cache.writebacks::total              883                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          783                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4122                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4905                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21193                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        21193                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          783                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        25315                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        26098                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          783                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        25315                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        26098                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     31320000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    164880000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    196200000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    847720000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    847720000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31320000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1012600000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   1043920000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31320000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1012600000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   1043920000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.984906                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.020484                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.024279                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083383                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083383                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.984906                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.055589                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.057209                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.984906                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.055589                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.057209                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
