
---------- Begin Simulation Statistics ----------
sim_seconds                                  1.801980                       # Number of seconds simulated
sim_ticks                                1801979679000                       # Number of ticks simulated
final_tick                               1801979679000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 528145                       # Simulator instruction rate (inst/s)
host_op_rate                                   973136                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1081454463                       # Simulator tick rate (ticks/s)
host_mem_usage                                 274856                       # Number of bytes of host memory used
host_seconds                                  1666.26                       # Real time elapsed on the host
sim_insts                                   880025278                       # Number of instructions simulated
sim_ops                                    1621493926                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             46208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           1682368                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1728576                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        46208                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           46208                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks       160640                       # Number of bytes written to this memory
system.physmem.bytes_written::total            160640                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                722                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              26287                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 27009                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            2510                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                 2510                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                25643                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               933622                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  959265                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           25643                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              25643                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks             89146                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                  89146                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks             89146                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               25643                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              933622                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                1048411                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                   48                       # Number of system calls
system.cpu.numCycles                       3603959358                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   880025278                       # Number of instructions committed
system.cpu.committedOps                    1621493926                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            1621354436                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     99478856                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   1621354436                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads          4204103507                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1886895257                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                     607228178                       # number of memory refs
system.cpu.num_load_insts                   419042121                       # Number of load instructions
system.cpu.num_store_insts                  188186057                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 3603959358                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                      4                       # number of replacements
system.cpu.icache.tagsinuse                660.169550                       # Cycle average of tags in use
system.cpu.icache.total_refs               1186515974                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               1643373.925208                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     660.169550                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.322348                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.322348                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst   1186515974                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      1186515974                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    1186515974                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       1186515974                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   1186515974                       # number of overall hits
system.cpu.icache.overall_hits::total      1186515974                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          722                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           722                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          722                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            722                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          722                       # number of overall misses
system.cpu.icache.overall_misses::total           722                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     40521000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     40521000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     40521000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     40521000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     40521000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     40521000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   1186516696                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   1186516696                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   1186516696                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   1186516696                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   1186516696                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   1186516696                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000001                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000001                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000001                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56123.268698                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56123.268698                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56123.268698                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56123.268698                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56123.268698                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56123.268698                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          722                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          722                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          722                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          722                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          722                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          722                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     38355000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     38355000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     38355000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     38355000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     38355000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     38355000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000001                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000001                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53123.268698                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53123.268698                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53123.268698                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53123.268698                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 437952                       # number of replacements
system.cpu.dcache.tagsinuse               4094.884130                       # Cycle average of tags in use
system.cpu.dcache.total_refs                606786130                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 442048                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                1372.670230                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              788810000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4094.884130                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999728                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999728                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    418844795                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       418844795                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    187941335                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      187941335                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     606786130                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        606786130                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    606786130                       # number of overall hits
system.cpu.dcache.overall_hits::total       606786130                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       197326                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        197326                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       244722                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       244722                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       442048                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         442048                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       442048                       # number of overall misses
system.cpu.dcache.overall_misses::total        442048                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   2948308000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   2948308000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   4362877000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   4362877000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   7311185000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   7311185000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   7311185000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   7311185000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    419042121                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    419042121                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    188186057                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    188186057                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    607228178                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    607228178                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    607228178                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    607228178                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000471                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000471                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001300                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001300                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000728                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000728                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000728                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000728                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.305251                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.305251                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17827.890423                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17827.890423                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16539.346406                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16539.346406                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16539.346406                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16539.346406                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       422980                       # number of writebacks
system.cpu.dcache.writebacks::total            422980                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       197326                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       197326                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       244722                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       244722                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       442048                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       442048                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       442048                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       442048                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2356330000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2356330000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3628711000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3628711000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5985041000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   5985041000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5985041000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   5985041000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000471                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000471                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001300                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.001300                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000728                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000728                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000728                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000728                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11941.305251                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11941.305251                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14827.890423                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14827.890423                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13539.346406                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13539.346406                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                  2581                       # number of replacements
system.cpu.l2cache.tagsinuse             22161.850174                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  506758                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                 23832                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 21.263763                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21018.400685                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    596.832055                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    546.617434                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.641431                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.018214                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.016681                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.676326                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data       193009                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         193009                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       422980                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       422980                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       222752                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       222752                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data       415761                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          415761                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data       415761                       # number of overall hits
system.cpu.l2cache.overall_hits::total         415761                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          722                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         4317                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         5039                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        21970                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        21970                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          722                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        26287                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         27009                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          722                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        26287                       # number of overall misses
system.cpu.l2cache.overall_misses::total        27009                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     37544000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    224484000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    262028000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1142440000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1142440000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     37544000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   1366924000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   1404468000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     37544000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   1366924000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   1404468000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          722                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       197326                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       198048                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       422980                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       422980                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       244722                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       244722                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          722                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       442048                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       442770                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          722                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       442048                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       442770                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021878                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.025443                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089775                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.089775                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.059466                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.061000                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.059466                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.061000                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks         2510                       # number of writebacks
system.cpu.l2cache.writebacks::total             2510                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          722                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4317                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         5039                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21970                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        21970                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          722                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        26287                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        27009                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          722                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        26287                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        27009                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     28880000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    172680000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    201560000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    878800000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    878800000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     28880000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1051480000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   1080360000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     28880000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1051480000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   1080360000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021878                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.025443                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089775                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089775                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.059466                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.061000                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.059466                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.061000                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
