
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.118780                       # Number of seconds simulated
sim_ticks                                118779533000                       # Number of ticks simulated
final_tick                               118779533000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1503058                       # Simulator instruction rate (inst/s)
host_op_rate                                  1503057                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1942616372                       # Simulator tick rate (ticks/s)
host_mem_usage                                 222720                       # Number of bytes of host memory used
host_seconds                                    61.14                       # Real time elapsed on the host
sim_insts                                    91903056                       # Number of instructions simulated
sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            167744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            137216                       # Number of bytes read from this memory
system.physmem.bytes_read::total               304960                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       167744                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          167744                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               2621                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               2144                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  4765                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1412230                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1155216                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2567446                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1412230                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1412230                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1412230                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1155216                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2567446                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     19996198                       # DTB read hits
system.cpu.dtb.read_misses                         10                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                 19996208                       # DTB read accesses
system.cpu.dtb.write_hits                     6501103                       # DTB write hits
system.cpu.dtb.write_misses                        23                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                 6501126                       # DTB write accesses
system.cpu.dtb.data_hits                     26497301                       # DTB hits
system.cpu.dtb.data_misses                         33                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
system.cpu.itb.fetch_hits                    91903090                       # ITB hits
system.cpu.itb.fetch_misses                        47                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                91903137                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                  389                       # Number of system calls
system.cpu.numCycles                        237559066                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    91903056                       # Number of instructions committed
system.cpu.committedOps                      91903056                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      7465012                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     79581109                       # number of integer instructions
system.cpu.num_fp_insts                       6862064                       # number of float instructions
system.cpu.num_int_register_reads           115028592                       # number of times the integer registers were read
system.cpu.num_int_register_writes           62575473                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              6071661                       # number of times the floating registers were read
system.cpu.num_fp_register_writes             5851888                       # number of times the floating registers were written
system.cpu.num_mem_refs                      26497334                       # number of memory refs
system.cpu.num_load_insts                    19996208                       # Number of load instructions
system.cpu.num_store_insts                    6501126                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                  237559066                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                   6681                       # number of replacements
system.cpu.icache.tagsinuse               1417.992791                       # Cycle average of tags in use
system.cpu.icache.total_refs                 91894580                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               10798.423032                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1417.992791                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.692379                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.692379                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     91894580                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        91894580                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      91894580                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         91894580                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     91894580                       # number of overall hits
system.cpu.icache.overall_hits::total        91894580                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         8510                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          8510                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         8510                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           8510                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         8510                       # number of overall misses
system.cpu.icache.overall_misses::total          8510                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    229226000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    229226000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    229226000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    229226000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    229226000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    229226000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     91903090                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     91903090                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     91903090                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     91903090                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     91903090                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     91903090                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000093                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000093                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000093                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000093                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000093                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000093                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26936.075206                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 26936.075206                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26936.075206                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 26936.075206                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26936.075206                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 26936.075206                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         8510                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         8510                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         8510                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         8510                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         8510                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         8510                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    203696000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    203696000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    203696000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    203696000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    203696000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    203696000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000093                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000093                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000093                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23936.075206                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23936.075206                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23936.075206                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23936.075206                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23936.075206                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23936.075206                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                    157                       # number of replacements
system.cpu.dcache.tagsinuse               1441.982871                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    1441.982871                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.352047                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.352047                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     19995723                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        19995723                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      6499355                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        6499355                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      26495078                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         26495078                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     26495078                       # number of overall hits
system.cpu.dcache.overall_hits::total        26495078                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          475                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           475                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         1748                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         1748                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         2223                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           2223                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         2223                       # number of overall misses
system.cpu.dcache.overall_misses::total          2223                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     24380000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     24380000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     96796000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     96796000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    121176000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    121176000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    121176000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    121176000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     19996198                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     19996198                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     26497301                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     26497301                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     26497301                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     26497301                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000269                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000269                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000084                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000084                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000084                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000084                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51326.315789                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51326.315789                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54510.121457                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54510.121457                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54510.121457                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54510.121457                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
system.cpu.dcache.writebacks::total               107                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          475                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          475                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1748                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         1748                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         2223                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     22955000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     22955000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     91552000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     91552000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    114507000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    114507000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    114507000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    114507000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000269                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48326.315789                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48326.315789                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51510.121457                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51510.121457                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51510.121457                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51510.121457                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              2073.981313                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                    5956                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  3109                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  1.915729                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks    17.795350                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   1704.943449                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    351.242515                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.052031                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.010719                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.063293                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         5889                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           5942                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         5889                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           79                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            5968                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         5889                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
system.cpu.l2cache.overall_hits::total           5968                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2621                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          422                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         3043                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         1722                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         1722                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2621                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         2144                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          4765                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2621                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         2144                       # number of overall misses
system.cpu.l2cache.overall_misses::total         4765                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    136292000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21944000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    158236000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     89544000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     89544000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    136292000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    111488000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    247780000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    136292000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    111488000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    247780000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         8510                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          475                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         8985                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         1748                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         1748                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         8510                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         2223                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        10733                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         8510                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         2223                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        10733                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.307991                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.888421                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.338676                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985126                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.985126                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.307991                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.964462                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.443958                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.307991                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.964462                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.443958                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2621                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          422                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         3043                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1722                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1722                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2621                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         2144                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         4765                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2621                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         4765                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    104840000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     16880000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    121720000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     68880000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     68880000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    104840000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     85760000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    190600000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    104840000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     85760000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    190600000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.338676                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985126                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985126                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.443958                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.443958                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
