
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.369932                       # Number of seconds simulated
sim_ticks                                2369931974000                       # Number of ticks simulated
final_tick                               2369931974000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1141587                       # Simulator instruction rate (inst/s)
host_op_rate                                  1548644                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1958218374                       # Simulator tick rate (ticks/s)
host_mem_usage                                 241676                       # Number of bytes of host memory used
host_seconds                                  1210.25                       # Real time elapsed on the host
sim_insts                                  1381604339                       # Number of instructions simulated
sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            144448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          94437440                       # Number of bytes read from this memory
system.physmem.bytes_read::total             94581888                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       144448                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          144448                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230336                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230336                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2257                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1475585                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1477842                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66099                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66099                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                60950                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             39848165                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                39909115                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           60950                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              60950                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1785003                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1785003                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1785003                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               60950                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            39848165                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               41694118                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1411                       # Number of system calls
system.cpu.numCycles                       4739863948                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  1381604339                       # Number of instructions committed
system.cpu.committedOps                    1874244941                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            1653698868                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
system.cpu.num_func_calls                    80372855                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    223735905                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   1653698868                       # number of integer instructions
system.cpu.num_fp_insts                      52289415                       # number of float instructions
system.cpu.num_int_register_reads         10466679913                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1874331393                       # number of times the integer registers were written
system.cpu.num_fp_register_reads             60540850                       # number of times the floating registers were read
system.cpu.num_fp_register_writes            46777010                       # number of times the floating registers were written
system.cpu.num_mem_refs                     908382479                       # number of memory refs
system.cpu.num_load_insts                   631387181                       # Number of load instructions
system.cpu.num_store_insts                  276995298                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 4739863948                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                  18364                       # number of replacements
system.cpu.icache.tagsinuse               1392.322496                       # Cycle average of tags in use
system.cpu.icache.total_refs               1390251699                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               70204.095289                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1392.322496                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.679845                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.679845                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst   1390251699                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      1390251699                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    1390251699                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       1390251699                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   1390251699                       # number of overall hits
system.cpu.icache.overall_hits::total      1390251699                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        19803                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         19803                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        19803                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          19803                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        19803                       # number of overall misses
system.cpu.icache.overall_misses::total         19803                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    372133000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    372133000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    372133000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    372133000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    372133000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    372133000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   1390271502                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   1390271502                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   1390271502                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   1390271502                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   1390271502                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   1390271502                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000014                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000014                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000014                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000014                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000014                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000014                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18791.748725                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18791.748725                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18791.748725                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18791.748725                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18791.748725                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18791.748725                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19803                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        19803                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        19803                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        19803                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        19803                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        19803                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312724000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    312724000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312724000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    312724000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312724000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    312724000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000014                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000014                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000014                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15791.748725                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15791.748725                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15791.748725                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1529557                       # number of replacements
system.cpu.dcache.tagsinuse               4094.950469                       # Cycle average of tags in use
system.cpu.dcache.total_refs                895757408                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 584.067848                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             1004561000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4094.950469                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999744                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999744                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    618874540                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       618874540                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    276862898                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      276862898                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         9985                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         9985                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     895737438                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        895737438                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    895737438                       # number of overall hits
system.cpu.dcache.overall_hits::total       895737438                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1460873                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1460873                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        72780                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        72780                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1533653                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1533653                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1533653                       # number of overall misses
system.cpu.dcache.overall_misses::total       1533653                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  79650958000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  79650958000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   3794840000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   3794840000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  83445798000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  83445798000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  83445798000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  83445798000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    620335413                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    620335413                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         9985                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         9985                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    897271091                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    897271091                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    897271091                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    897271091                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002355                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002355                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000263                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000263                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.001709                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.001709                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.001709                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.001709                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.849009                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.849009                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.247595                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.247595                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.829342                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54409.829342                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.829342                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54409.829342                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       109047                       # number of writebacks
system.cpu.dcache.writebacks::total            109047                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460873                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1460873                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        72780                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        72780                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1533653                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1533653                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1533653                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1533653                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75268339000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  75268339000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3576500000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3576500000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78844839000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  78844839000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78844839000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  78844839000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002355                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002355                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000263                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000263                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001709                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001709                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.849009                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.849009                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.247595                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.247595                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.829342                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.829342                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.829342                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.829342                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements               1478696                       # number of replacements
system.cpu.l2cache.tagsinuse             32689.689328                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   77413                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs               1511439                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.051218                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks  3194.581985                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     32.931287                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  29462.176056                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.097491                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.001005                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.899114                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.997610                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        17546                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        51381                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          68927                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       109047                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       109047                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         6687                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         6687                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        17546                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        58068                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           75614                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        17546                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        58068                       # number of overall hits
system.cpu.l2cache.overall_hits::total          75614                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2257                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1409492                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1411749                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66093                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66093                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2257                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1475585                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1477842                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2257                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1475585                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1477842                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117364000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  73293584000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  73410948000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3436836000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   3436836000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    117364000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  76730420000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  76847784000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    117364000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  76730420000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  76847784000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        19803                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1460873                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1480676                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       109047                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       109047                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        72780                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        72780                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        19803                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1533653                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1553456                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        19803                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1533653                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1553456                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113973                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.964829                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.953449                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.908120                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.908120                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113973                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.962137                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.951325                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113973                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.962137                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.951325                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
system.cpu.l2cache.writebacks::total            66099                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2257                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1409492                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1411749                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66093                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2257                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1475585                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1477842                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2257                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1475585                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1477842                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     90280000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56379680000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56469960000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2643720000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2643720000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     90280000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59023400000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  59113680000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     90280000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59023400000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  59113680000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.964829                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.953449                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.908120                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.908120                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.962137                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.951325                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.962137                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.951325                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
