
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.795271                       # Number of seconds simulated
sim_ticks                                795270546000                       # Number of ticks simulated
final_tick                               795270546000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 873454                       # Simulator instruction rate (inst/s)
host_op_rate                                   922399                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1221783566                       # Simulator tick rate (ticks/s)
host_mem_usage                                 232680                       # Number of bytes of host memory used
host_seconds                                   650.91                       # Real time elapsed on the host
sim_insts                                   568539335                       # Number of instructions simulated
sim_ops                                     600398272                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             39104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           1735040                       # Number of bytes read from this memory
system.physmem.bytes_read::total              1774144                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        39104                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           39104                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks       194752                       # Number of bytes written to this memory
system.physmem.bytes_written::total            194752                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                611                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              27110                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 27721                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            3043                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                 3043                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                49171                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2181698                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2230868                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           49171                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              49171                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            244888                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                 244888                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            244888                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               49171                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2181698                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2475756                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   48                       # Number of system calls
system.cpu.numCycles                       1590541092                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   568539335                       # Number of instructions committed
system.cpu.committedOps                     600398272                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             533522631                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
system.cpu.num_func_calls                     1995305                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     67017094                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    533522631                       # number of integer instructions
system.cpu.num_fp_insts                            16                       # number of float instructions
system.cpu.num_int_register_reads          3212467067                       # number of times the integer registers were read
system.cpu.num_int_register_writes          614470972                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                     219173606                       # number of memory refs
system.cpu.num_load_insts                   148952593                       # Number of load instructions
system.cpu.num_store_insts                   70221013                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 1590541092                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                     12                       # number of replacements
system.cpu.icache.tagsinuse                577.715333                       # Cycle average of tags in use
system.cpu.icache.total_refs                570073883                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    643                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               886584.576983                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     577.715333                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.282088                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.282088                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    570073883                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       570073883                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     570073883                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        570073883                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    570073883                       # number of overall hits
system.cpu.icache.overall_hits::total       570073883                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          643                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           643                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          643                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            643                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          643                       # number of overall misses
system.cpu.icache.overall_misses::total           643                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     34792000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     34792000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     34792000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     34792000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     34792000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     34792000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    570074526                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    570074526                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    570074526                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    570074526                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    570074526                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    570074526                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000001                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000001                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000001                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54108.864697                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54108.864697                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54108.864697                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54108.864697                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54108.864697                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54108.864697                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          643                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          643                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          643                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          643                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          643                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          643                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32863000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     32863000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32863000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     32863000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32863000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     32863000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000001                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000001                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51108.864697                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51108.864697                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51108.864697                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51108.864697                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51108.864697                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51108.864697                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 433468                       # number of replacements
system.cpu.dcache.tagsinuse               4094.191707                       # Cycle average of tags in use
system.cpu.dcache.total_refs                216774472                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 437564                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 495.412036                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              547974000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4094.191707                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999559                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999559                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    147602035                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       147602035                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     69169783                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       69169783                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         1327                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         1327                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         1327                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         1327                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     216771818                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        216771818                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    216771818                       # number of overall hits
system.cpu.dcache.overall_hits::total       216771818                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       189816                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        189816                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       247748                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       247748                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       437564                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         437564                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       437564                       # number of overall misses
system.cpu.dcache.overall_misses::total        437564                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   2866972000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   2866972000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   4400884000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   4400884000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   7267856000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   7267856000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   7267856000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   7267856000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    147791851                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    147791851                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     69417531                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     69417531                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         1327                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         1327                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         1327                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         1327                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    217209382                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    217209382                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    217209382                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    217209382                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001284                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.001284                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003569                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.003569                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002014                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002014                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002014                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002014                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.953302                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.953302                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17763.550059                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 17763.550059                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16609.812507                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16609.812507                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16609.812507                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16609.812507                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       418219                       # number of writebacks
system.cpu.dcache.writebacks::total            418219                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       189816                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       189816                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       247748                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       247748                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       437564                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       437564                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       437564                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       437564                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2297524000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2297524000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3657640000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3657640000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5955164000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   5955164000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5955164000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   5955164000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001284                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001284                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003569                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.003569                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002014                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002014                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002014                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002014                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.953302                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.953302                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14763.550059                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14763.550059                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13609.812507                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13609.812507                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13609.812507                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13609.812507                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                  3963                       # number of replacements
system.cpu.l2cache.tagsinuse             21579.150724                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                  495400                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                 24559                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 20.171831                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20939.895204                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    130.071130                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    509.184390                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.639035                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.003969                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.015539                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.658543                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst           32                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       184871                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         184903                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       418219                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       418219                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       225583                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       225583                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           32                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       410454                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          410486                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           32                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       410454                       # number of overall hits
system.cpu.l2cache.overall_hits::total         410486                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          611                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         4945                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         5556                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        22165                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        22165                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          611                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        27110                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         27721                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          611                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        27110                       # number of overall misses
system.cpu.l2cache.overall_misses::total        27721                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31772000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    257140000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    288912000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1152580000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1152580000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     31772000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   1409720000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   1441492000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     31772000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   1409720000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   1441492000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          643                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       189816                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       190459                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       418219                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       418219                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       247748                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       247748                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          643                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       437564                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       438207                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          643                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       437564                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       438207                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.950233                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026052                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.029172                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089466                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.089466                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.950233                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.061957                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063260                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.950233                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.061957                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063260                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks         3043                       # number of writebacks
system.cpu.l2cache.writebacks::total             3043                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          611                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4945                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         5556                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        22165                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        22165                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          611                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        27110                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        27721                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          611                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        27110                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        27721                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24440000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    197800000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    222240000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    886600000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    886600000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24440000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1084400000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   1108840000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24440000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1084400000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   1108840000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.950233                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026052                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.029172                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089466                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089466                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.950233                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.061957                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063260                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.950233                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.061957                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063260                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
