
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000003                       # Number of seconds simulated
sim_ticks                                     2870500                       # Number of ticks simulated
final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 136961                       # Simulator instruction rate (inst/s)
host_op_rate                                   170823                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               85547635                       # Simulator tick rate (ticks/s)
host_mem_usage                                 223208                       # Number of bytes of host memory used
host_seconds                                     0.03                       # Real time elapsed on the host
sim_insts                                        4591                       # Number of instructions simulated
sim_ops                                          5729                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             18416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              4491                       # Number of bytes read from this memory
system.physmem.bytes_read::total                22907                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        18416                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           18416                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data           3648                       # Number of bytes written to this memory
system.physmem.bytes_written::total              3648                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4604                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               1157                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  5761                       # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data               924                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                  924                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst           6415607037                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data           1564535795                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              7980142832                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      6415607037                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         6415607037                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data          1270858735                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total             1270858735                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          6415607037                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data          2835394531                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             9251001568                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
system.cpu.checker.dtb.read_misses                  0                       # DTB read misses
system.cpu.checker.dtb.write_hits                   0                       # DTB write hits
system.cpu.checker.dtb.write_misses                 0                       # DTB write misses
system.cpu.checker.dtb.flush_tlb                    0                       # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries                0                       # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses                0                       # DTB read accesses
system.cpu.checker.dtb.write_accesses               0                       # DTB write accesses
system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.dtb.hits                         0                       # DTB hits
system.cpu.checker.dtb.misses                       0                       # DTB misses
system.cpu.checker.dtb.accesses                     0                       # DTB accesses
system.cpu.checker.itb.inst_hits                    0                       # ITB inst hits
system.cpu.checker.itb.inst_misses                  0                       # ITB inst misses
system.cpu.checker.itb.read_hits                    0                       # DTB read hits
system.cpu.checker.itb.read_misses                  0                       # DTB read misses
system.cpu.checker.itb.write_hits                   0                       # DTB write hits
system.cpu.checker.itb.write_misses                 0                       # DTB write misses
system.cpu.checker.itb.flush_tlb                    0                       # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries                0                       # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
system.cpu.checker.itb.inst_accesses                0                       # ITB inst accesses
system.cpu.checker.itb.hits                         0                       # DTB hits
system.cpu.checker.itb.misses                       0                       # DTB misses
system.cpu.checker.itb.accesses                     0                       # DTB accesses
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu.checker.numCycles                        0                       # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.numCycles                             5742                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        4591                       # Number of instructions committed
system.cpu.committedOps                          5729                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                  4976                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
system.cpu.num_func_calls                         203                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          774                       # number of instructions that are conditional controls
system.cpu.num_int_insts                         4976                       # number of integer instructions
system.cpu.num_fp_insts                            16                       # number of float instructions
system.cpu.num_int_register_reads               25195                       # number of times the integer registers were read
system.cpu.num_int_register_writes               5334                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                          2138                       # number of memory refs
system.cpu.num_load_insts                        1200                       # Number of load instructions
system.cpu.num_store_insts                        938                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                       5742                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles

---------- End Simulation Statistics   ----------
