
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.133513                       # Number of seconds simulated
sim_ticks                                133513136000                       # Number of ticks simulated
final_tick                               133513136000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1170283                       # Simulator instruction rate (inst/s)
host_op_rate                                  1659492                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2220265254                       # Simulator tick rate (ticks/s)
host_mem_usage                                 240448                       # Number of bytes of host memory used
host_seconds                                    60.13                       # Real time elapsed on the host
sim_insts                                    70373628                       # Number of instructions simulated
sim_ops                                      99791654                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            273728                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8003456                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8277184                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       273728                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          273728                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5403392                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5403392                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4277                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             125054                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                129331                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           84428                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                84428                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              2050195                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             59945083                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                61995278                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2050195                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2050195                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          40470864                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               40470864                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          40470864                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2050195                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            59945083                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              102466142                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                        267026272                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    70373628                       # Number of instructions committed
system.cpu.committedOps                      99791654                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              91472780                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
system.cpu.num_func_calls                     3311620                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     10711742                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     91472780                       # number of integer instructions
system.cpu.num_fp_insts                            56                       # number of float instructions
system.cpu.num_int_register_reads           533542872                       # number of times the integer registers were read
system.cpu.num_int_register_writes           96252285                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
system.cpu.num_mem_refs                      47862847                       # number of memory refs
system.cpu.num_load_insts                    27307108                       # Number of load instructions
system.cpu.num_store_insts                   20555739                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                  267026272                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                  16890                       # number of replacements
system.cpu.icache.tagsinuse               1735.470121                       # Cycle average of tags in use
system.cpu.icache.total_refs                 78126161                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                4131.910355                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1735.470121                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.847398                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.847398                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     78126161                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        78126161                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      78126161                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         78126161                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     78126161                       # number of overall hits
system.cpu.icache.overall_hits::total        78126161                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        18908                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         18908                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        18908                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          18908                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        18908                       # number of overall misses
system.cpu.icache.overall_misses::total         18908                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    445311000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    445311000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    445311000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    445311000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    445311000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    445311000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     78145069                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     78145069                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     78145069                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     78145069                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     78145069                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     78145069                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000242                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000242                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000242                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000242                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000242                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000242                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23551.459700                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23551.459700                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23551.459700                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23551.459700                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23551.459700                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23551.459700                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18908                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        18908                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        18908                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        18908                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        18908                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        18908                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    388587000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    388587000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    388587000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    388587000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    388587000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    388587000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000242                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000242                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000242                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20551.459700                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20551.459700                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20551.459700                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20551.459700                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20551.459700                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20551.459700                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 155902                       # number of replacements
system.cpu.dcache.tagsinuse               4076.664624                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 46862074                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 159998                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 292.891624                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             1111220000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4076.664624                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.995279                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.995279                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     27087367                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        27087367                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       19742869                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      46830236                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         46830236                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     46830236                       # number of overall hits
system.cpu.dcache.overall_hits::total        46830236                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        52966                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         52966                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       107032                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       107032                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       159998                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         159998                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       159998                       # number of overall misses
system.cpu.dcache.overall_misses::total        159998                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1699159000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1699159000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   5797120000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   5797120000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   7496279000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   7496279000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   7496279000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   7496279000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     27140333                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     27140333                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46990234                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46990234                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46990234                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46990234                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001952                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.001952                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.005392                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.003405                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.003405                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.003405                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.003405                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32080.183514                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32080.183514                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54162.493460                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54162.493460                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46852.329404                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 46852.329404                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46852.329404                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 46852.329404                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       127057                       # number of writebacks
system.cpu.dcache.writebacks::total            127057                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        52966                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        52966                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107032                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107032                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       159998                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       159998                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1540261000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   1540261000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5476024000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5476024000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7016285000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   7016285000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7016285000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   7016285000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001952                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001952                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003405                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003405                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.183514                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29080.183514                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51162.493460                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51162.493460                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43852.329404                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43852.329404                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43852.329404                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43852.329404                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 96735                       # number of replacements
system.cpu.l2cache.tagsinuse             28857.116422                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   71387                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                127516                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.559828                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 26427.849240                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    949.438432                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   1479.828749                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.806514                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.028975                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.045161                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.880649                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        14631                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        30253                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          44884                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       127057                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       127057                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4691                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4691                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        14631                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        34944                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           49575                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        14631                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        34944                       # number of overall hits
system.cpu.l2cache.overall_hits::total          49575                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4277                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        22713                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26990                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102341                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102341                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4277                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       125054                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        129331                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4277                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       125054                       # number of overall misses
system.cpu.l2cache.overall_misses::total       129331                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    222404000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1181076000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1403480000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5321732000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5321732000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    222404000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   6502808000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   6725212000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    222404000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   6502808000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   6725212000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        18908                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        52966                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        71874                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       127057                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       127057                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107032                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107032                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        18908                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       159998                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       178906                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        18908                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       159998                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       178906                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.226201                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.428822                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.375518                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.956172                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.956172                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.226201                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.781597                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.722899                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.226201                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.781597                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.722899                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        84428                       # number of writebacks
system.cpu.l2cache.writebacks::total            84428                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4277                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        22713                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26990                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102341                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102341                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4277                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       125054                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       129331                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4277                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       125054                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       129331                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    171080000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    908520000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1079600000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4093640000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4093640000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171080000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5002160000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   5173240000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171080000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5002160000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   5173240000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.226201                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.428822                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.375518                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.956172                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.956172                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.226201                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.781597                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.722899                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.226201                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.781597                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.722899                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
