
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.086149                       # Number of seconds simulated
sim_ticks                                 86149358000                       # Number of ticks simulated
final_tick                                86149358000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 240669                       # Simulator instruction rate (inst/s)
host_op_rate                                   253706                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              120331720                       # Simulator tick rate (ticks/s)
host_mem_usage                                 272336                       # Number of bytes of host memory used
host_seconds                                   715.93                       # Real time elapsed on the host
sim_insts                                   172303022                       # Number of instructions simulated
sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            652096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            192896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher        71744                       # Number of bytes read from this memory
system.physmem.bytes_read::total               916736                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       652096                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          652096                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst              10189                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               3014                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher         1121                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 14324                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              7569366                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2239088                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher       832786                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                10641240                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         7569366                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            7569366                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             7569366                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2239088                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher       832786                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               10641240                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         14324                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                       14324                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   916736                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    916736                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1375                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 498                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5101                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 808                       # Per bank write bursts
system.physmem.perBankRdBursts::4                2279                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 424                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 384                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 628                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 270                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 231                       # Per bank write bursts
system.physmem.perBankRdBursts::10                354                       # Per bank write bursts
system.physmem.perBankRdBursts::11                348                       # Per bank write bursts
system.physmem.perBankRdBursts::12                320                       # Per bank write bursts
system.physmem.perBankRdBursts::13                267                       # Per bank write bursts
system.physmem.perBankRdBursts::14                240                       # Per bank write bursts
system.physmem.perBankRdBursts::15                797                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     86149299500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   14324                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     12783                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      1071                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       182                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        41                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        36                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         8487                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      107.956168                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      86.535791                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     122.736079                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           5894     69.45%     69.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         2098     24.72%     94.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          256      3.02%     97.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           63      0.74%     97.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           36      0.42%     98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           32      0.38%     98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           19      0.22%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           10      0.12%     99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           79      0.93%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           8487                       # Bytes accessed per row activation
system.physmem.totQLat                     1500750524                       # Total ticks spent queuing
system.physmem.totMemAccLat                1769325524                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     71620000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                      104771.75                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                 123521.75                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          10.64                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       10.64                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.08                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.08                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       5833                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   40.72                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      6014332.55                       # Average gap between requests
system.physmem.pageHitRate                      40.72                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                   51543660                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   27384720                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  82088580                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           5186946960.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             1121176890                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              276161760                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       12273342600                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        8346662400                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy         9294814230                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              36662152740                       # Total energy per rank (pJ)
system.physmem_0.averagePower              425.565010                       # Core power per rank (mW)
system.physmem_0.totalIdleTime            82965211526                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      532687000                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2205840000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF    34315599752                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  21736059604                       # Time in different power states
system.physmem_0.memoryStateTime::ACT       443979474                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  26915192170                       # Time in different power states
system.physmem_1.actEnergy                    9082080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    4823445                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  20184780                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           883852320.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy              198703710                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               50905920                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy        1989700140                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        1383894720                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        18830063895                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              23371485780                       # Total energy per rank (pJ)
system.physmem_1.averagePower              271.290305                       # Core power per rank (mW)
system.physmem_1.totalIdleTime            85580460271                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      101384000                       # Time in different power states
system.physmem_1.memoryStateTime::REF       376118000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF    77613150500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN   3603890386                       # Time in different power states
system.physmem_1.memoryStateTime::ACT        91368979                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN   4363446135                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                85639426                       # Number of BP lookups
system.cpu.branchPred.condPredicted          68185953                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5937258                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             39949340                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                38185565                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.584971                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 3683095                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              81909                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups          681696                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits             653573                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            28123                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        40352                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        172298717                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5689617                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      347266831                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85639426                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           42522233                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     158380748                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                11888463                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 4145                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingQuiesceStallCycles           80                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles         4281                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  78346664                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 18062                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          170023102                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.137102                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.057569                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 18318468     10.77%     10.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 30068726     17.69%     28.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 31619725     18.60%     47.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 90016183     52.94%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            170023102                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.497040                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.015493                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 17554244                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              18101467                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 121824905                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6773054                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                5769432                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             11065775                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                189948                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              305038109                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              27237354                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                5769432                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37539679                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 8956907                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         601126                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 108322423                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               8833535                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              277447852                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              13184486                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3097243                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 842563                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                2612762                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                  40533                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            26849                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           481448776                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1187920227                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        296497585                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           3005089                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                188471847                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              23626                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          23625                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13449474                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             33921609                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            14424624                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           2552614                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1816807                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  263824183                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               45978                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 214443460                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           5190288                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        82234207                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    216932052                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            762                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     170023102                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.261261                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.018489                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            53215331     31.30%     31.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            36043504     21.20%     52.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            65536118     38.55%     91.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            13631246      8.02%     99.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             1550810      0.91%     99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               45816      0.03%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 277      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       170023102                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                35671391     66.13%     66.13% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 153271      0.28%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd              1065      0.00%     66.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp             35712      0.07%     66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt               263      0.00%     66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              556      0.00%     66.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult            40135      0.07%     66.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               13909773     25.79%     92.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3850022      7.14%     99.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead            142020      0.26%     99.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite           136319      0.25%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             167011334     77.88%     77.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               919426      0.43%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd           33015      0.02%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp          165180      0.08%     78.40% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt          245708      0.11%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         460349      0.21%     78.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult         206623      0.10%     78.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt            318      0.00%     78.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             31296412     14.59%     93.49% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            13233182      6.17%     99.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead          576648      0.27%     99.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite         147624      0.07%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              214443460                       # Type of FU issued
system.cpu.iq.rate                           1.244603                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    53940732                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.251538                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          654047721                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         344100630                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    204290427                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             3993321                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            2010682                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      1806323                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              266209914                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 2174278                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1590245                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      6025465                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         7430                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation         7094                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1779990                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        25605                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           790                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                5769432                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 5627104                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                174387                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           263890272                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              33921609                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             14424624                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              23570                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   3854                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                167353                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents           7094                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3148097                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3247402                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              6395499                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             207161825                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              30639651                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           7281635                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         20111                       # number of nop insts executed
system.cpu.iew.exec_refs                     43786600                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 44861358                       # Number of branches executed
system.cpu.iew.exec_stores                   13146949                       # Number of stores executed
system.cpu.iew.exec_rate                     1.202341                       # Inst execution rate
system.cpu.iew.wb_sent                      206406222                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     206096750                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 129381204                       # num instructions producing a value
system.cpu.iew.wb_consumers                 221650091                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.196160                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.583718                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        68697467                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           5762459                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    158721175                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.144462                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.650716                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     74120611     46.70%     46.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     41150811     25.93%     72.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     22560961     14.21%     86.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      9504738      5.99%     92.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3552513      2.24%     95.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      2129219      1.34%     96.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1299436      0.82%     97.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1012456      0.64%     97.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3390430      2.14%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    158721175                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       40540778                       # Number of memory references committed
system.cpu.commit.loads                      27896144                       # Number of loads committed
system.cpu.commit.membars                       22408                       # Number of memory barriers committed
system.cpu.commit.branches                   40300312                       # Number of branches committed
system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 143085667                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        138987813     76.51%     76.51% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          908940      0.50%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd        32754      0.02%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp       154829      0.09%     77.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt       238880      0.13%     77.25% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv        76016      0.04%     77.29% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       437591      0.24%     77.53% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult       200806      0.11%     77.64% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc        71617      0.04%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt          318      0.00%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        27348059     15.06%     92.74% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       12498388      6.88%     99.62% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead       548085      0.30%     99.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite       146246      0.08%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3390430                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    405673353                       # The number of ROB reads
system.cpu.rob.rob_writes                   512011515                       # The number of ROB writes
system.cpu.timesIdled                            9971                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2275615                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.999975                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.999975                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.000025                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.000025                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                218762027                       # number of integer regfile reads
system.cpu.int_regfile_writes               114194444                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   2903946                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2441681                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 708323214                       # number of cc regfile reads
system.cpu.cc_regfile_writes                229513810                       # number of cc regfile writes
system.cpu.misc_regfile_reads                57456345                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements             72586                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.401008                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            41045518                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs             73098                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            561.513557                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         555248500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.401008                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998830                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998830                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          230                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          82389396                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         82389396                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     28659277                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        28659277                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12341322                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12341322                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data          365                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total           365                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22147                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22147                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41000599                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41000599                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     41000964                       # number of overall hits
system.cpu.dcache.overall_hits::total        41000964                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        89290                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         89290                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        22965                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        22965                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          116                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          116                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          260                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          260                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       112255                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         112255                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       112371                       # number of overall misses
system.cpu.dcache.overall_misses::total        112371                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1989594500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1989594500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    244666499                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    244666499                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2316500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      2316500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   2234260999                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   2234260999                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   2234260999                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   2234260999                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     28748567                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     28748567                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data          481                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total          481                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41112854                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41112854                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     41113335                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     41113335                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003106                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.003106                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001857                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001857                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.241164                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.241164                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011604                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011604                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002730                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002730                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002733                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002733                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22282.388845                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22282.388845                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10653.886305                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10653.886305                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8909.615385                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8909.615385                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19903.443045                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19903.443045                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19882.896824                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19882.896824                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          180                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        11152                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             864                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           90                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    12.907407                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks        72586                       # number of writebacks
system.cpu.dcache.writebacks::total             72586                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24872                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        24872                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14398                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        14398                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          260                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          260                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        39270                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        39270                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        39270                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        39270                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64418                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        64418                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8567                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         8567                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          113                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          113                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data        72985                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total        72985                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data        73098                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total        73098                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1060539500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   1060539500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     87795999                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     87795999                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       969000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       969000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   1148335499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   1148335499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   1149304499                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   1149304499                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002241                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002241                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000693                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000693                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.234927                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.234927                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001775                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001775                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001778                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001778                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16463.403086                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16463.403086                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10248.161433                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10248.161433                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8575.221239                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8575.221239                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15733.856258                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15733.856258                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15722.789940                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15722.789940                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             53582                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.578561                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            78288973                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             54094                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           1447.276463                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       85378568500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.578561                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997224                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997224                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           49                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         156747350                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        156747350                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     78288973                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        78288973                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      78288973                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         78288973                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     78288973                       # number of overall hits
system.cpu.icache.overall_hits::total        78288973                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        57655                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         57655                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        57655                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          57655                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        57655                       # number of overall misses
system.cpu.icache.overall_misses::total         57655                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   2247853926                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   2247853926                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   2247853926                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   2247853926                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   2247853926                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   2247853926                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     78346628                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     78346628                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     78346628                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     78346628                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     78346628                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     78346628                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000736                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000736                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000736                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000736                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000736                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000736                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38988.013633                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 38988.013633                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 38988.013633                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 38988.013633                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 38988.013633                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 38988.013633                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        94468                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           55                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              3203                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    29.493600                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    27.500000                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        53582                       # number of writebacks
system.cpu.icache.writebacks::total             53582                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3560                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3560                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3560                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3560                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3560                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3560                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54095                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        54095                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        54095                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        54095                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        54095                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        54095                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2052751452                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   2052751452                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2052751452                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   2052751452                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2052751452                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   2052751452                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000690                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000690                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000690                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000690                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000690                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000690                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37947.156891                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37947.156891                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37947.156891                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 37947.156891                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37947.156891                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 37947.156891                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued         9257                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified         9257                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage         1327                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         1809.107747                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              98955                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             2836                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            34.892454                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1727.095683                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    82.012064                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.105414                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.005006                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.110419                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          131                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         2705                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           19                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           46                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4           66                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          283                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1127                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          198                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          958                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.007996                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.165100                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          4002973                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         4002973                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks        64701                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total        64701                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        50991                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        50991                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         8404                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         8404                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        43901                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        43901                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data        61671                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total        61671                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        43901                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        70075                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          113976                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        43901                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        70075                       # number of overall hits
system.cpu.l2cache.overall_hits::total         113976                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data          230                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          230                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10194                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        10194                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data         2793                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total         2793                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        10194                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         3023                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         13217                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        10194                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         3023                       # number of overall misses
system.cpu.l2cache.overall_misses::total        13217                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     20353000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     20353000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1710678000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1710678000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    556147500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total    556147500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1710678000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    576500500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   2287178500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1710678000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    576500500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   2287178500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks        64701                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total        64701                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        50991                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        50991                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         8634                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         8634                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54095                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        54095                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64464                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total        64464                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        54095                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data        73098                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       127193                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        54095                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data        73098                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       127193                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.026639                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.026639                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.188446                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.188446                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043327                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043327                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.188446                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.041355                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.103913                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.188446                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.041355                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.103913                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88491.304348                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88491.304348                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167812.242496                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167812.242496                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199121.911923                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199121.911923                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167812.242496                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190704.763480                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 173048.233336                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167812.242496                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190704.763480                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 173048.233336                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         2048                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total         2048                       # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          229                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          229                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10189                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10189                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         2785                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total         2785                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10189                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         3014                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        13203                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10189                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         3014                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         2048                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        15251                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     98123639                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     98123639                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     18771000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     18771000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1648684500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1648684500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    538898000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    538898000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1648684500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    557669000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   2206353500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1648684500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    557669000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     98123639                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   2304477139                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.026523                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.026523                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.188354                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.188354                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043202                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043202                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.188354                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.041232                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.103803                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.188354                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.041232                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.119904                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47911.933105                       # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81969.432314                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81969.432314                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161810.236530                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161810.236530                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 193500.179533                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 193500.179533                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161810.236530                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185026.211015                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167110.012876                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161810.236530                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185026.211015                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151103.346600                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests       253361                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       126188                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10476                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          927                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          926                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        118558                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty        64701                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        61467                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq         2398                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         8634                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         8634                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        54095                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq        64464                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       161771                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       218782                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            380553                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6891264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9323776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           16215040                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                        2398                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples       129591                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.088154                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.283547                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             118168     91.19%     91.19% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              11422      8.81%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         129591                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      252848500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      81149483                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     109651491                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests         14324                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests        10483                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  86149358000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp              14094                       # Transaction distribution
system.membus.trans_dist::ReadExReq               229                       # Transaction distribution
system.membus.trans_dist::ReadExResp              229                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         14095                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        28647                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  28647                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       916672                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  916672                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples             14324                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   14324    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               14324                       # Request fanout histogram
system.membus.reqLayer0.occupancy            18004660                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           77243027                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
