
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.038007                       # Number of seconds simulated
sim_ticks                                 38007342000                       # Number of ticks simulated
final_tick                                38007342000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 224949                       # Simulator instruction rate (inst/s)
host_op_rate                                   287684                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              120575368                       # Simulator tick rate (ticks/s)
host_mem_usage                                 283980                       # Number of bytes of host memory used
host_seconds                                   315.22                       # Real time elapsed on the host
sim_insts                                    70907652                       # Number of instructions simulated
sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst           2373952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           5705216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher      6169536                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14248704                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      2373952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         2373952                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6224192                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6224192                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              37093                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              89144                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        96399                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                222636                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97253                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97253                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             62460353                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            150108261                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher    162324848                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               374893461                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        62460353                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           62460353                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         163762886                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              163762886                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         163762886                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            62460353                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           150108261                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher    162324848                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              538656347                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        222637                       # Number of read requests accepted
system.physmem.writeReqs                        97253                       # Number of write requests accepted
system.physmem.readBursts                      222637                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97253                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 14240000                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8704                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6222848                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  14248768                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6224192                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      136                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9656                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9952                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12608                       # Per bank write bursts
system.physmem.perBankRdBursts::3               25349                       # Per bank write bursts
system.physmem.perBankRdBursts::4               17405                       # Per bank write bursts
system.physmem.perBankRdBursts::5               22083                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11752                       # Per bank write bursts
system.physmem.perBankRdBursts::7               14068                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11731                       # Per bank write bursts
system.physmem.perBankRdBursts::9               15466                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11740                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11331                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9464                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9568                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9844                       # Per bank write bursts
system.physmem.perBankRdBursts::15              20483                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5965                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6210                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6157                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6128                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6115                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6243                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6020                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5952                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5952                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6130                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6213                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5918                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6006                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6051                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6145                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6027                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     38007330500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  222637                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97253                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    112108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     59931                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     15573                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     10934                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5238                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4622                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4261                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3516                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        73                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       42                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1086                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1871                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3276                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5989                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7735                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8436                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       132899                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      153.968593                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     102.497917                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     209.528989                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          82983     62.44%     62.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        32243     24.26%     86.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6367      4.79%     91.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2726      2.05%     93.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1184      0.89%     94.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1005      0.76%     95.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          875      0.66%     95.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          807      0.61%     96.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4709      3.54%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         132899                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5883                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        37.820840                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      210.672420                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            5878     99.92%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            4      0.07%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-15871            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5883                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5882                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.528392                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.490234                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.186972                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4697     79.85%     79.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 46      0.78%     80.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                744     12.65%     93.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                191      3.25%     96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 91      1.55%     98.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 73      1.24%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 20      0.34%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 15      0.26%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5882                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8329547257                       # Total ticks spent queuing
system.physmem.totMemAccLat               12501422257                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1112500000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       37436.00                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      4999.98                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  56185.91                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         374.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         163.73                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      374.90                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      163.76                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.21                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.93                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.28                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.37                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.63                       # Average write queue length when enqueuing
system.physmem.readRowHits                     157173                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     29653                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   70.64                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  30.49                       # Row buffer hit rate for writes
system.physmem.avgGap                       118813.75                       # Average gap between requests
system.physmem.pageHitRate                      58.43                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  507596880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  269771370                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 877313220                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                254683800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3009892080.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             2962459860                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy               75632160                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       13054365150                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy         948417120                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy           77983215                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              22038660255                       # Total energy per rank (pJ)
system.physmem_0.averagePower              579.852702                       # Core power per rank (mW)
system.physmem_0.totalIdleTime            31313307761                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE       43781047                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1273526000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF      214718250                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN   2469720434                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      5376727192                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  28628869077                       # Time in different power states
system.physmem_1.actEnergy                  441337680                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  234557565                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 711336780                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                252841140                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           2899256880.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             2760551040                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy               73978560                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       11934955830                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        1428119040                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy          493845795                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              21231004530                       # Total energy per rank (pJ)
system.physmem_1.averagePower              558.602674                       # Core power per rank (mW)
system.physmem_1.totalIdleTime            31760586804                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE       51273339                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1226918000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF     1868150750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN   3718457459                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      4968563857                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  26173978595                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                17074531                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11460402                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            598628                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9274722                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7374340                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             79.510092                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1855435                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             101567                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups          233050                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits             195925                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            37125                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        22231                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON     38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                         76014685                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5565404                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       87125388                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17074531                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9425700                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      66120510                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1223729                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                11256                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            48                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        32224                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  22440736                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 69274                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           72341306                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.522198                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.331033                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 27150688     37.53%     37.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  8169627     11.29%     48.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9114831     12.60%     61.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 27906160     38.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             72341306                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.224621                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.146165                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8942287                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              26299816                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  30976482                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5677371                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 445350                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3133946                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                168438                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              100318297                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               2804928                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 445350                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13582767                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                11480611                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         882043                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  31792045                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14158490                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               98346425                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                855389                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               4229008                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  68182                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                4663621                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                5443965                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           103273055                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             453619684                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        114297516                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               686                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              93629369                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                  9643686                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              18991                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          19021                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12815345                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             24159121                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            21761593                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1442839                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2330212                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   97411129                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               34857                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  94489103                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            595557                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         6763379                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     17995254                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1071                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      72341306                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.306157                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.170975                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            24199109     33.45%     33.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            17470195     24.15%     57.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17034708     23.55%     81.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            11601119     16.04%     97.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2034740      2.81%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                1435      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        72341306                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 6739464     22.68%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     40      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11065982     37.24%     59.92% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              11909373     40.08%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead                33      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite               21      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49308872     52.18%     52.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                86547      0.09%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  32      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp              13      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc             20      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             23960981     25.36%     77.63% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21132544     22.37%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead              62      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite             32      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               94489103                       # Type of FU issued
system.cpu.iq.rate                           1.243037                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    29714913                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.314480                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          291629642                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         104220574                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     93205627                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 340                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                544                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           99                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              124203819                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     197                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1369166                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1292859                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2033                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11913                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1205855                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       148706                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        187344                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 445350                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  625818                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1199933                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            97461708                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              24159121                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             21761593                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              18937                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   1609                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               1195657                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11913                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         250763                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       222991                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               473754                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              93695211                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23697676                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            793892                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         15722                       # number of nop insts executed
system.cpu.iew.exec_refs                     44622526                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14207940                       # Number of branches executed
system.cpu.iew.exec_stores                   20924850                       # Number of stores executed
system.cpu.iew.exec_rate                     1.232594                       # Inst execution rate
system.cpu.iew.wb_sent                       93313259                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      93205726                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  44957522                       # num instructions producing a value
system.cpu.iew.wb_consumers                  76634731                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.226154                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.586647                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts         5905401                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            432114                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     71383083                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.270443                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.106463                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     37916370     53.12%     53.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16693361     23.39%     76.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4299601      6.02%     82.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4172974      5.85%     88.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1943479      2.72%     91.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1233650      1.73%     92.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       737671      1.03%     93.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       579334      0.81%     94.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3806643      5.33%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     71383083                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913204                       # Number of instructions committed
system.cpu.commit.committedOps               90688159                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       43422000                       # Number of memory references committed
system.cpu.commit.loads                      22866262                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741468                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  81528527                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         47186033     52.03%     52.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22866242     25.21%     77.33% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555706     22.67%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead           20      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite           32      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          90688159                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3806643                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    164144701                       # The number of ROB reads
system.cpu.rob.rob_writes                   194146843                       # The number of ROB writes
system.cpu.timesIdled                           54077                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         3673379                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907652                       # Number of Instructions Simulated
system.cpu.committedOps                      90682607                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.072024                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.072024                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.932815                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.932815                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                101986551                       # number of integer regfile reads
system.cpu.int_regfile_writes                56614441                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        62                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       51                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 345121100                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 38758964                       # number of cc regfile writes
system.cpu.misc_regfile_reads                44102244                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            484796                       # number of replacements
system.cpu.dcache.tags.tagsinuse           510.868688                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40338903                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            485308                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             83.120210                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         154723500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   510.868688                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997790                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997790                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          456                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          84466908                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         84466908                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     21416602                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21416602                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18830761                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18830761                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        60264                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         60264                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15306                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15306                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40247363                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40247363                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40307627                       # number of overall hits
system.cpu.dcache.overall_hits::total        40307627                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       563583                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        563583                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1019140                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1019140                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        68608                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        68608                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          617                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          617                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1582723                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1582723                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1651331                       # number of overall misses
system.cpu.dcache.overall_misses::total       1651331                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14467064000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14467064000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  14294982430                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  14294982430                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      6393500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      6393500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  28762046430                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  28762046430                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  28762046430                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  28762046430                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     21980185                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     21980185                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128872                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128872                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15923                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15923                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41830086                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41830086                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     41958958                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     41958958                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025641                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.025641                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051342                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.051342                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532373                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.532373                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.038749                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.038749                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037837                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037837                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.039356                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.039356                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25669.801964                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25669.801964                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14026.514934                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14026.514934                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10362.236629                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10362.236629                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18172.508032                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18172.508032                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17417.493180                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17417.493180                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           29                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      2976739                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          131356                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.800000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    22.661614                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       484796                       # number of writebacks
system.cpu.dcache.writebacks::total            484796                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       264511                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       264511                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870576                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       870576                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          617                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          617                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1135087                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1135087                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1135087                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1135087                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299072                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       299072                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148564                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       148564                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37686                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        37686                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       447636                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       447636                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       485322                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       485322                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   7113004000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   7113004000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2350412971                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2350412971                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2001432500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2001432500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9463416971                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   9463416971                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11464849471                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  11464849471                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013606                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013606                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007484                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007484                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.292430                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.292430                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010701                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010701                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011567                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.011567                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23783.583886                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23783.583886                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.878349                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.878349                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53108.117073                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53108.117073                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21140.875557                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21140.875557                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23623.181045                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23623.181045                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements            325456                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.336563                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            22103277                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            325967                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             67.808327                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        1174665500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.336563                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996751                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996751                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          332                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            8                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          45207041                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         45207041                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     22103280                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        22103280                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      22103280                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         22103280                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     22103280                       # number of overall hits
system.cpu.icache.overall_hits::total        22103280                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       337250                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        337250                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       337250                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         337250                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       337250                       # number of overall misses
system.cpu.icache.overall_misses::total        337250                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   5803062852                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   5803062852                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   5803062852                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   5803062852                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   5803062852                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   5803062852                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     22440530                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     22440530                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     22440530                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     22440530                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     22440530                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     22440530                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015029                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.015029                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.015029                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.015029                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.015029                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.015029                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17207.006233                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17207.006233                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17207.006233                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17207.006233                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17207.006233                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17207.006233                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       559762                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs             25894                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    21.617440                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           47                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks       325456                       # number of writebacks
system.cpu.icache.writebacks::total            325456                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        11268                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        11268                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        11268                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        11268                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        11268                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        11268                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       325982                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       325982                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       325982                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       325982                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       325982                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       325982                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   5371171413                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   5371171413                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   5371171413                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   5371171413                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   5371171413                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   5371171413                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014526                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014526                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014526                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014526                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014526                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014526                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16476.895697                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16476.895697                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16476.895697                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16476.895697                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16476.895697                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16476.895697                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued       822258                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       825535                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         2876                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        78497                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           125579                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        15699.484972                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             681508                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           141902                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.802667                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15625.141607                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    74.343365                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.953683                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.004538                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.958221                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           24                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        16299                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           12                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4            3                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2587                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12184                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          533                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          859                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001465                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994812                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         25493850                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        25493850                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks       260429                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       260429                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       469974                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       469974                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       137044                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       137044                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       288848                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       288848                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       255916                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       255916                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       288848                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       392960                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          681808                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       288848                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       392960                       # number of overall hits
system.cpu.l2cache.overall_hits::total         681808                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           14                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           14                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        11552                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        11552                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        37119                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        37119                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        80796                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        80796                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        37119                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        92348                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        129467                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        37119                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        92348                       # number of overall misses
system.cpu.l2cache.overall_misses::total       129467                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1233354500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1233354500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   3144915500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   3144915500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   6919452000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   6919452000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   3144915500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   8152806500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11297722000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   3144915500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   8152806500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11297722000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       260429                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       260429                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       469974                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       469974                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           14                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           14                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       148596                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       148596                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       325967                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       325967                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336712                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       336712                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       325967                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       485308                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       811275                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       325967                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       485308                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       811275                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.077741                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.077741                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.113873                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.113873                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.239956                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.239956                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113873                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.190287                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.159585                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113873                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.190287                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.159585                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106765.451870                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106765.451870                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.221585                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.221585                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85641.021833                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85641.021833                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.221585                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88283.519946                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87263.333514                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.221585                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88283.519946                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87263.333514                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches              426                       # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks        97253                       # number of writebacks
system.cpu.l2cache.writebacks::total            97253                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3091                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3091                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           25                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           25                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          113                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          113                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         3204                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         3229                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         3204                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         3229                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       114995                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       114995                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           14                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           14                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8461                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         8461                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        37094                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        37094                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        80683                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        80683                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        37094                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        89144                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       126238                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        37094                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        89144                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       114995                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       241233                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10227090401                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10227090401                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       218000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       218000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    733523000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    733523000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2920395500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2920395500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   6427576500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   6427576500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2920395500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7161099500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10081495000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2920395500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7161099500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10227090401                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  20308585401                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056940                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056940                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.113797                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.113797                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.239620                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.239620                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113797                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.183685                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.155604                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113797                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.183685                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.297350                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 88935.087621                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15571.428571                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15571.428571                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86694.598747                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86694.598747                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78729.592387                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78729.592387                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79664.569984                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79664.569984                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78729.592387                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80331.817060                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79861.016493                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78729.592387                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80331.817060                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84186.597194                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      1621556                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       810285                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        80433                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops        18616                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops        18570                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           46                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        662693                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       357682                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       549823                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        28326                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       146207                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           14                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           14                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       148596                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       148596                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       325982                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       336712                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       977404                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1455440                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2432844                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41691008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62086656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          103777664                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      271801                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               6225152                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      1083090                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.091523                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.288499                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             984008     90.85%     90.85% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              99036      9.14%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                 46      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1083090                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     1621030000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          4.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     489099244                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     728047842                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.9                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests        348230                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       205331                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED  38007342000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp             214175                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        97253                       # Transaction distribution
system.membus.trans_dist::CleanEvict            28326                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               14                       # Transaction distribution
system.membus.trans_dist::ReadExReq              8461                       # Transaction distribution
system.membus.trans_dist::ReadExResp             8461                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        214176                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       570866                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 570866                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     20472896                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                20472896                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            222651                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  222651    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              222651                       # Request fanout histogram
system.membus.reqLayer0.occupancy           835869990                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1175713686                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              3.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
