
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.368600                       # Number of seconds simulated
sim_ticks                                368600047500                       # Number of ticks simulated
final_tick                               368600047500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 377886                       # Simulator instruction rate (inst/s)
host_op_rate                                   409300                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              274959159                       # Simulator tick rate (ticks/s)
host_mem_usage                                 276756                       # Number of bytes of host memory used
host_seconds                                  1340.56                       # Real time elapsed on the host
sim_insts                                   506579366                       # Number of instructions simulated
sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            179840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9053376                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9233216                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       179840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          179840                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6241792                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6241792                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2810                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141459                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                144269                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97528                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97528                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               487900                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             24561516                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                25049416                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          487900                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             487900                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          16933780                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               16933780                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          16933780                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              487900                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            24561516                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               41983196                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        144269                       # Number of read requests accepted
system.physmem.writeReqs                        97528                       # Number of write requests accepted
system.physmem.readBursts                      144269                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97528                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9225856                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6240448                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9233216                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6241792                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9372                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8929                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8963                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8667                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9424                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9372                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8974                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8127                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8635                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8697                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8761                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9485                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9346                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9545                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8729                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9128                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6253                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6118                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6042                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5901                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6273                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6263                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6069                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5535                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5819                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5920                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5985                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6510                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6360                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6344                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6013                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6102                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    368600022000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  144269                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97528                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    143801                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       333                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5742                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5743                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5749                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5765                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5752                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5747                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        63970                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      241.763327                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     162.115864                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     241.210402                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          22774     35.60%     35.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18302     28.61%     64.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7461     11.66%     75.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         8049     12.58%     88.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2117      3.31%     91.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1180      1.84%     93.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          776      1.21%     94.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          623      0.97%     95.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         2688      4.20%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          63970                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5740                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.113240                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      375.658190                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5737     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5740                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5740                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.987282                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.957535                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.009458                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2852     49.69%     49.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                159      2.77%     52.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               2701     47.06%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 19      0.33%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                  6      0.10%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5740                       # Writes before turning the bus around for reads
system.physmem.totQLat                     3577410500                       # Total ticks spent queuing
system.physmem.totMemAccLat                6280298000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    720770000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       24816.59                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  43566.59                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          25.03                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          16.93                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       25.05                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       16.93                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        20.06                       # Average write queue length when enqueuing
system.physmem.readRowHits                     110541                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     67141                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.68                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  68.84                       # Row buffer hit rate for writes
system.physmem.avgGap                      1524419.34                       # Average gap between requests
system.physmem.pageHitRate                      73.52                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  229615260                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  122028225                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 512851920                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                252929880                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           7711888080.000002                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             3985232520                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              353635200                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       24742392420                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        8329190880                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy        68838786810                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             115080429525                       # Total energy per rank (pJ)
system.physmem_0.averagePower              312.209478                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           358934929250                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      533175250                       # Time in different power states
system.physmem_0.memoryStateTime::REF      3272498000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   282985158000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  21690772000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      5858998750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  54259445500                       # Time in different power states
system.physmem_1.actEnergy                  227194800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  120737925                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 516407640                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                256056660                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           7588960080.000002                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             3990680010                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              342748800                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       24389261460                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        8128903200                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        69135043560                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             114698287785                       # Total energy per rank (pJ)
system.physmem_1.averagePower              311.172742                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           358951299500                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      511434000                       # Time in different power states
system.physmem_1.memoryStateTime::REF      3220288000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   284296687500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  21168817000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      5916972250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  53485848750                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups               132103819                       # Number of BP lookups
system.cpu.branchPred.condPredicted          98193306                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5910048                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             68601561                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                60590477                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             88.322301                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                10017121                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              18743                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         3891575                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            3883028                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             8547                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        54138                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        737200095                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   506579366                       # Number of instructions committed
system.cpu.committedOps                     548692589                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      12939783                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.455251                       # CPI: cycles per instruction
system.cpu.ipc                               0.687167                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu               375609862     68.46%     68.46% # Class of committed instruction
system.cpu.op_class_0::IntMult                 339219      0.06%     68.52% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatMisc                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                3      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     68.52% # Class of committed instruction
system.cpu.op_class_0::MemRead              115883283     21.12%     89.64% # Class of committed instruction
system.cpu.op_class_0::MemWrite              56860206     10.36%    100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite               16      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                548692589                       # Class of committed instruction
system.cpu.tickCycles                       694074449                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        43125646                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           1141337                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4070.214598                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           171083823                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1145433                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            149.361703                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        5072633500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4070.214598                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993705                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993705                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          543                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3507                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         346338043                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        346338043                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    114566012                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114566012                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     53537935                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       53537935                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2794                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2794                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168103947                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168103947                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168106741                       # number of overall hits
system.cpu.dcache.overall_hits::total       168106741                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       811353                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        811353                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       701114                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       701114                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1512467                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1512467                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1512482                       # number of overall misses
system.cpu.dcache.overall_misses::total       1512482                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  14511839000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  14511839000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  24015670000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  24015670000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  38527509000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  38527509000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  38527509000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  38527509000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    115377365                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    115377365                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2809                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2809                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    169616414                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    169616414                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    169619223                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    169619223                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007032                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007032                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012926                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.012926                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005340                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.005340                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.008917                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.008917                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.008917                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.008917                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25473.289004                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25473.036373                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      1068942                       # number of writebacks
system.cpu.dcache.writebacks::total           1068942                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22320                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        22320                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344726                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       344726                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       367046                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       367046                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       367046                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       367046                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       789033                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       789033                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356388                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       356388                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1145421                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1145421                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1145433                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1145433                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13416892000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  13416892000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12196191500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12196191500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      4297000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      4297000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25613083500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25613083500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  25617380500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  25617380500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006839                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006839                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006571                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006571                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004272                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004272                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006753                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006753                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006753                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006753                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             18178                       # number of replacements
system.cpu.icache.tags.tagsinuse          1186.508929                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           199149019                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             20050                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           9932.619401                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1186.508929                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.579350                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.579350                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          311                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1400                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         398358188                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        398358188                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    199149019                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       199149019                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     199149019                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        199149019                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    199149019                       # number of overall hits
system.cpu.icache.overall_hits::total       199149019                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        20050                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         20050                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        20050                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          20050                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        20050                       # number of overall misses
system.cpu.icache.overall_misses::total         20050                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    544279500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    544279500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    544279500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    544279500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    544279500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    544279500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    199169069                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    199169069                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    199169069                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    199169069                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    199169069                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    199169069                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000101                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000101                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000101                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000101                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000101                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000101                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 27146.109726                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 27146.109726                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        18178                       # number of writebacks
system.cpu.icache.writebacks::total             18178                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20050                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        20050                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        20050                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        20050                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        20050                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        20050                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    524229500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    524229500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    524229500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    524229500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    524229500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    524229500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000101                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000101                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000101                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           112761                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29076.848035                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2174458                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           145529                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            14.941750                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     102118428000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   133.889045                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   307.541066                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.004086                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009385                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.873884                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.887355                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          111                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          981                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31589                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         18705537                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        18705537                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      1068942                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      1068942                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        17940                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        17940                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       255660                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       255660                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        17239                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        17239                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       748301                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       748301                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        17239                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1003961                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1021200                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        17239                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1003961                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1021200                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data       100978                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       100978                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2811                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2811                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        40494                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        40494                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2811                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141472                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        144283                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2811                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141472                       # number of overall misses
system.cpu.l2cache.overall_misses::total       144283                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8979653500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8979653500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    312476000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    312476000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   4360668500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   4360668500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    312476000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13340322000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13652798000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    312476000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13340322000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13652798000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      1068942                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      1068942                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        17940                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        17940                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       356638                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       356638                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        20050                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        20050                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       788795                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       788795                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        20050                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1145433                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1165483                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        20050                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1145433                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1165483                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.283139                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.283139                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.140200                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.140200                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.051337                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.051337                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.140200                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.123510                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.123797                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.140200                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.123510                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.123797                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        97528                       # number of writebacks
system.cpu.l2cache.writebacks::total            97528                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           13                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           13                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           13                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           13                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100978                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       100978                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2810                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2810                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        40481                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        40481                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2810                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141459                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       144269                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2810                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141459                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       144269                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7969873500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7969873500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    284301000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    284301000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3953966500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   3953966500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    284301000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11923840000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  12208141000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    284301000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11923840000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  12208141000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283139                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283139                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.140150                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.140150                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.051320                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.051320                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.140150                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123498                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.123785                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.140150                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123498                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.123785                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      2324998                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159585                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4997                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2618                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2615                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        808845                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      1166470                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        18178                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        87628                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       356638                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       356638                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        20050                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       788795                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58278                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432203                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3490481                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2446592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141720000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          144166592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      112761                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               6241792                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      1278244                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.006015                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.077350                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            1270559     99.40%     99.40% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               7682      0.60%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1278244                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2249619000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      30098453                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1718157983                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests        254412                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       110315                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp              43291                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        97528                       # Transaction distribution
system.membus.trans_dist::CleanEvict            12615                       # Transaction distribution
system.membus.trans_dist::ReadExReq            100978                       # Transaction distribution
system.membus.trans_dist::ReadExResp           100978                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         43291                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       398681                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 398681                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15475008                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15475008                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            144269                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  144269    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              144269                       # Request fanout histogram
system.membus.reqLayer0.occupancy           685127000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          765884750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------
