
---------- Begin Simulation Statistics ----------
host_inst_rate                                  77433                       # Simulator instruction rate (inst/s)
host_mem_usage                                 260740                       # Number of bytes of host memory used
host_seconds                                  7232.86                       # Real time elapsed on the host
host_tick_rate                               50600448                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   560059971                       # Number of instructions simulated
sim_seconds                                  0.365986                       # Number of seconds simulated
sim_ticks                                365986074500                       # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits                140387936                       # Number of BTB hits
system.cpu.BPredUnit.BTBLookups             174401300                       # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect           15511612                       # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted          191766015                       # Number of conditional branches predicted
system.cpu.BPredUnit.lookups                191766015                       # Number of BP lookups
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches              110089780                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events           3558142                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples    662070266                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean     0.847952                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev     1.257926                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0    343782937     51.93%     51.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1    194895590     29.44%     81.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2     65587700      9.91%     91.27% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3     25120372      3.79%     95.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4     18782135      2.84%     97.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5      6815428      1.03%     98.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6      2394801      0.36%     99.29% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7      1133161      0.17%     99.46% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8      3558142      0.54%    100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total    662070266                       # Number of insts commited each cycle
system.cpu.commit.COM:count                 561403855                       # Number of instructions committed
system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
system.cpu.commit.COM:int_insts             464140463                       # Number of committed integer instructions.
system.cpu.commit.COM:loads                 128127024                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                  184987501                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts          26429304                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts      561403855                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls          157189                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts       399418051                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                   560059971                       # Number of Instructions Simulated
system.cpu.committedInsts_total             560059971                       # Number of Instructions Simulated
system.cpu.cpi                               1.306953                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.306953                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses          149905369                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10172.883940                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency  6761.781933                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits              148899998                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency    10227522500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.006707                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses              1005371                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits            179403                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency   5585015500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.005510                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses          825968                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses          55727847                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14757.173065                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13626.207417                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              54433003                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency   19108237000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.023235                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses             1294844                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits           947408                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency   4734235000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.006235                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses         347436                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                 173.284886                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           205633216                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12753.485870                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency  8794.286111                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               203333001                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency     29335759500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.011186                       # miss rate for demand accesses
system.cpu.dcache.demand_misses               2300215                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits            1126811                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency  10319250500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.005706                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses          1173404                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0                   0.992547                       # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0           4065.472807                       # Average occupied blocks per context
system.cpu.dcache.overall_accesses          205633216                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12753.485870                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency  8794.286111                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              203333001                       # number of overall hits
system.cpu.dcache.overall_miss_latency    29335759500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.011186                       # miss rate for overall accesses
system.cpu.dcache.overall_misses              2300215                       # number of overall misses
system.cpu.dcache.overall_mshr_hits           1126811                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency  10319250500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.005706                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses         1173404                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                1169307                       # number of replacements
system.cpu.dcache.sampled_refs                1173403                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4065.472807                       # Cycle average of tags in use
system.cpu.dcache.total_refs                203333005                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle             6053772000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                  1049504                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles       23915687                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts      1082602718                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles         296214320                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles          338871926                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles        65446321                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles        3068332                       # Number of cycles decode is unblocking
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.fetch.Branches                   191766015                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                 122748340                       # Number of cache lines fetched
system.cpu.fetch.Cycles                     351971872                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes               3710699                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                      938893733                       # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles              4527385                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles                26711690                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.261985                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles          122748340                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches          140387936                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        1.282691                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples          727516586                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.537241                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.455426                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                376259318     51.72%     51.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                167730540     23.06%     74.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 28515235      3.92%     78.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 34553707      4.75%     83.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 26720758      3.67%     87.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 10947410      1.50%     88.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 11409505      1.57%     90.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 11171933      1.54%     91.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 60208180      8.28%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            727516586                       # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.icache.ReadReq_accesses          122748340                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13369.913613                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency  9679.346455                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits              122731555                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      224414000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000137                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                16785                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits               933                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency    153437000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000129                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses           15852                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                7742.827266                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses           122748340                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13369.913613                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency  9679.346455                       # average overall mshr miss latency
system.cpu.icache.demand_hits               122731555                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       224414000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000137                       # miss rate for demand accesses
system.cpu.icache.demand_misses                 16785                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                933                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    153437000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000129                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses            15852                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_%::0                   0.543111                       # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0           1112.290548                       # Average occupied blocks per context
system.cpu.icache.overall_accesses          122748340                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13369.913613                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency  9679.346455                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits              122731555                       # number of overall hits
system.cpu.icache.overall_miss_latency      224414000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000137                       # miss rate for overall accesses
system.cpu.icache.overall_misses                16785                       # number of overall misses
system.cpu.icache.overall_mshr_hits               933                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    153437000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000129                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses           15852                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                  14002                       # number of replacements
system.cpu.icache.sampled_refs                  15851                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1112.290548                       # Cycle average of tags in use
system.cpu.icache.total_refs                122731555                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                         4455564                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches                125457274                       # Number of branches executed
system.cpu.iew.EXEC:nop                      13838185                       # number of nop insts executed
system.cpu.iew.EXEC:rate                     0.981178                       # Inst execution rate
system.cpu.iew.EXEC:refs                    229700627                       # number of memory reference insts executed
system.cpu.iew.EXEC:stores                   72018658                       # Number of stores executed
system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
system.cpu.iew.WB:consumers                 714382081                       # num instructions consuming a value
system.cpu.iew.WB:count                     665966048                       # cumulative count of insts written-back
system.cpu.iew.WB:fanout                     0.510315                       # average fanout of values written-back
system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers                 364559924                       # num instructions producing a value
system.cpu.iew.WB:rate                       0.909824                       # insts written-back per cycle
system.cpu.iew.WB:sent                      705629563                       # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts             29041716                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles                 2636135                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts             199993331                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts             162274                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts          12088796                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts            140409395                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts           960810723                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts             157681969                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          32008551                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts             718194992                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                 117672                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                  3801                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles               65446321                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                180324                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads         4458450                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses         9743                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation       347516                       # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads        11819                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads     71866306                       # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores     83548918                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents         347516                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect     14571260                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect       14470456                       # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads               1616277270                       # number of integer regfile reads
system.cpu.int_regfile_writes               504274200                       # number of integer regfile writes
system.cpu.ipc                               0.765138                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.765138                       # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu       504696330     67.27%     67.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult         349129      0.05%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd            80      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead      162553860     21.67%     88.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite      82604141     11.01%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total        750203543                       # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt              11563965                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.015414                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu            153469      1.33%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      1.33% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead          5982996     51.74%     53.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite         5427500     46.93%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples    727516586                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean     1.031184                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.359043                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0     340760839     46.84%     46.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1     195196887     26.83%     73.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2     103112393     14.17%     87.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3      43508042      5.98%     93.82% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4      23307105      3.20%     97.03% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5      12389030      1.70%     98.73% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6       3383235      0.47%     99.19% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7       4087676      0.56%     99.76% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8       1771379      0.24%    100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total    727516586                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate                     1.024907                       # Inst issue rate
system.cpu.iq.fp_alu_accesses                     100                       # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads                 196                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes                598                       # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses              761767408                       # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads         2247505915                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses    665966032                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes        1323699335                       # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded                  946810264                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                 750203543                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded              162274                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined       376428693                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued           8018474                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved           5085                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined    702572396                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses          347863                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34247.596496                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.740070                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits              228350                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency   4093033000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate       0.343563                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            119513                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency   3705469500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.343563                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       119513                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses            841391                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34185.632593                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.780138                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                726325                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency    3933604000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.136757                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses              115066                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits               30                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency   3568621500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.136721                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses         115036                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_hits                  1                       # number of UpgradeReq hits
system.cpu.l2cache.Writeback_accesses         1049504                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits             1049504                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  6.339320                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses            1189254                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34217.201881                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.097476                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                 954675                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency     8026637000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.197249                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses               234579                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                30                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency   7274091000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.197224                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses          234549                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0                  0.185910                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1                  0.449873                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0          6091.890422                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1         14741.450627                       # Average occupied blocks per context
system.cpu.l2cache.overall_accesses           1189254                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34217.201881                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.097476                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                954675                       # number of overall hits
system.cpu.l2cache.overall_miss_latency    8026637000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.197249                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses              234579                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits               30                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency   7274091000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.197224                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses         234549                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                215449                       # number of replacements
system.cpu.l2cache.sampled_refs                235636                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             20833.341048                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1493772                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          262779341000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                  171632                       # number of writebacks
system.cpu.memDep0.conflictingLoads          58798533                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         76400324                       # Number of conflicting stores.
system.cpu.memDep0.insertedLoads            199993331                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           140409395                       # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads              1169227072                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 344748                       # number of misc regfile writes
system.cpu.numCycles                        731972150                       # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles          7146790                       # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps      435368498                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents         5207540                       # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles         311739226                       # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents        9258079                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents             25                       # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups     2640447492                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts      1043812056                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands    713532745                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles          325976886                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles        65446321                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles       15480980                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps         278164244                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups         1939                       # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups   2640445553                       # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles      1726383                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts       233275                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts           49072391                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts       185712                       # count of temporary serializing insts renamed
system.cpu.rob.rob_reads                   1619326892                       # The number of ROB reads
system.cpu.rob.rob_writes                  1987147936                       # The number of ROB writes
system.cpu.timesIdled                           95874                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls

---------- End Simulation Statistics   ----------
