
================ Begin RubySystem Configuration Print ================

RubySystem config:
  random_seed: 1234
  randomization: 1
  cycle_period: 1
  block_size_bytes: 64
  block_size_bits: 6
  memory_size_bytes: 134217728
  memory_size_bits: 27

Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: 

virtual_net_0: active, unordered
virtual_net_1: active, unordered
virtual_net_2: active, unordered
virtual_net_3: inactive
virtual_net_4: inactive
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive


Profiler Configuration
----------------------
periodic_stats_period: 1000000

================ End RubySystem Configuration Print ================


Real time: Feb/08/2011 17:31:55

Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0

Virtual_time_in_seconds: 0.79
Virtual_time_in_minutes: 0.0131667
Virtual_time_in_hours:   0.000219444
Virtual_time_in_days:    9.14352e-06

Ruby_current_time: 352261
Ruby_start_time: 0
Ruby_cycles: 352261

mbytes_resident: 33.6719
mbytes_total: 208.004
resident_ratio: 0.161956

ruby_cycles_executed: [ 352262 ]

Busy Controller Counts:
L1Cache-0:0  
L2Cache-0:0  
Directory-0:0  


Busy Bank Count:0

sequencer_requests_outstanding: [binsize: 1 max: 16 count: 986 average: 15.8337 | standard deviation: 1.12966 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 45 927 ]

All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 256 max: 33636 count: 971 average: 5617.58 | standard deviation: 7479.54 | 86 25 67 61 60 60 59 49 37 31 22 33 21 30 13 6 17 12 14 11 11 7 4 2 6 3 6 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 2 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 3 5 2 2 4 3 6 4 3 3 2 4 2 4 3 4 5 7 1 2 5 5 5 4 0 3 2 8 5 5 2 7 2 2 4 1 2 1 0 2 3 2 2 1 0 0 3 2 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 256 max: 26910 count: 54 average: 5436.72 | standard deviation: 7279.79 | 4 1 3 3 5 5 2 1 3 1 2 5 1 2 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 256 max: 33636 count: 871 average: 5875.94 | standard deviation: 7609.86 | 82 18 51 47 46 53 53 48 33 30 20 28 20 28 12 5 16 12 14 11 11 6 4 2 6 3 5 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 1 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 2 5 1 1 4 3 6 3 3 3 2 3 2 4 3 3 5 7 1 2 5 5 5 4 0 3 2 8 5 5 1 7 1 2 4 1 1 1 0 2 3 2 2 1 0 0 3 1 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_NULL: [binsize: 256 max: 33636 count: 971 average: 5617.58 | standard deviation: 7479.54 | 86 25 67 61 60 60 59 49 37 31 22 33 21 30 13 6 17 12 14 11 11 7 4 2 6 3 6 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 2 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 3 5 2 2 4 3 6 4 3 3 2 4 2 4 3 4 5 7 1 2 5 5 5 4 0 3 2 8 5 5 2 7 2 2 4 1 2 1 0 2 3 2 2 1 0 0 3 2 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0
miss_latency_IFETCH_NULL: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_NULL: [binsize: 256 max: 26910 count: 54 average: 5436.72 | standard deviation: 7279.79 | 4 1 3 3 5 5 2 1 3 1 2 5 1 2 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_NULL: [binsize: 256 max: 33636 count: 871 average: 5875.94 | standard deviation: 7609.86 | 82 18 51 47 46 53 53 48 33 30 20 28 20 28 12 5 16 12 14 11 11 6 4 2 6 3 5 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 1 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 2 5 1 1 4 3 6 3 3 3 2 3 2 4 3 3 5 7 1 2 5 5 5 4 0 3 2 8 5 5 1 7 1 2 4 1 1 1 0 2 3 2 2 1 0 0 3 1 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]

All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------


filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 64 max: 2190 count: 6931 average: 40.0967 | standard deviation: 160.683 | 6308 139 36 64 26 28 59 37 45 37 29 33 14 29 9 11 5 2 4 1 1 4 1 2 1 1 2 0 1 0 0 0 1 0 1 0 0 0 0 0 0 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4457 average:     0 | standard deviation: 0 | 4457 ]
  virtual_network_0_delay_cycles: [binsize: 64 max: 2190 count: 2474 average: 112.332 | standard deviation: 253.445 | 1851 139 36 64 26 28 59 37 45 37 29 33 14 29 9 11 5 2 4 1 1 4 1 2 1 1 2 0 1 0 0 0 1 0 1 0 0 0 0 0 0 ]
  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 569 average:     0 | standard deviation: 0 | 569 ]
  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3888 average:     0 | standard deviation: 0 | 3888 ]
  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 9831
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0

Network Stats
-------------

total_msg_count_Control: 5232 41856
total_msg_count_Request_Control: 1707 13656
total_msg_count_Response_Data: 7498 539856
total_msg_count_Response_Control: 7664 61312
total_msg_count_Writeback_Data: 3668 264096
total_msg_count_Writeback_Control: 126 1008
total_msgs: 25895 total_bytes: 921784

switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.107585
  links_utilized_percent_switch_0_link_0: 0.0330614 bw: 640000 base_latency: 1
  links_utilized_percent_switch_0_link_1: 0.182109 bw: 160000 base_latency: 1

  outgoing_messages_switch_0_link_0_Request_Control: 569 4552 [ 569 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_0_Response_Data: 890 64080 [ 0 890 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_0_Response_Control: 738 5904 [ 0 738 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Response_Control: 888 7104 [ 0 44 844 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Writeback_Data: 1223 88056 [ 698 525 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_0_link_1_Writeback_Control: 42 336 [ 42 0 0 0 0 0 0 0 0 0 ] base_latency: 1

switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.15911
  links_utilized_percent_switch_1_link_0: 0.0756009 bw: 640000 base_latency: 1
  links_utilized_percent_switch_1_link_1: 0.242618 bw: 160000 base_latency: 1

  outgoing_messages_switch_1_link_0_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_0_Response_Data: 849 61128 [ 0 849 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_0_Response_Control: 1731 13848 [ 0 887 844 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_0_Writeback_Data: 1222 87984 [ 698 524 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_0_Writeback_Control: 42 336 [ 42 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Control: 851 6808 [ 851 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Request_Control: 569 4552 [ 569 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Response_Data: 1650 118800 [ 0 1650 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_1_link_1_Response_Control: 823 6584 [ 0 823 0 0 0 0 0 0 0 0 ] base_latency: 1

switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.0740786
  links_utilized_percent_switch_2_link_0: 0.0275932 bw: 640000 base_latency: 1
  links_utilized_percent_switch_2_link_1: 0.120564 bw: 160000 base_latency: 1

  outgoing_messages_switch_2_link_0_Control: 851 6808 [ 851 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_0_Response_Data: 760 54720 [ 0 760 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_0_Response_Control: 85 680 [ 0 85 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_1_Response_Data: 850 61200 [ 0 850 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_2_link_1_Response_Control: 844 6752 [ 0 844 0 0 0 0 0 0 0 0 ] base_latency: 1

switch_3_inlinks: 3
switch_3_outlinks: 3
links_utilized_percent_switch_3: 0.181721
  links_utilized_percent_switch_3_link_0: 0.132246 bw: 160000 base_latency: 1
  links_utilized_percent_switch_3_link_1: 0.302546 bw: 160000 base_latency: 1
  links_utilized_percent_switch_3_link_2: 0.110373 bw: 160000 base_latency: 1

  outgoing_messages_switch_3_link_0_Request_Control: 569 4552 [ 569 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_0_Response_Data: 890 64080 [ 0 890 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_0_Response_Control: 738 5904 [ 0 738 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Control: 893 7144 [ 893 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Response_Data: 849 61128 [ 0 849 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Response_Control: 1732 13856 [ 0 888 844 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Writeback_Data: 1223 88056 [ 698 525 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_1_Writeback_Control: 42 336 [ 42 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_2_Control: 851 6808 [ 851 0 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_2_Response_Data: 760 54720 [ 0 760 0 0 0 0 0 0 0 0 ] base_latency: 1
  outgoing_messages_switch_3_link_2_Response_Control: 85 680 [ 0 85 0 0 0 0 0 0 0 0 ] base_latency: 1

Cache Stats: system.l1_cntrl0.L1IcacheMemory
  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0


Cache Stats: system.l1_cntrl0.L1DcacheMemory
  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0


 --- L1Cache ---
 - Event Counts -
Load [57 ] 57
Ifetch [361 ] 361
Store [873 ] 873
Inv [569 ] 569
L1_Replacement [496874 ] 496874
Fwd_GETX [0 ] 0
Fwd_GETS [0 ] 0
Fwd_GET_INSTR [0 ] 0
Data [0 ] 0
Data_Exclusive [50 ] 50
DataS_fromL1 [0 ] 0
Data_all_Acks [840 ] 840
Ack [0 ] 0
Ack_all [0 ] 0
WB_Ack [738 ] 738

 - Transitions -
NP  Load [52 ] 52
NP  Ifetch [46 ] 46
NP  Store [794 ] 794
NP  Inv [0 ] 0
NP  L1_Replacement [0 ] 0

I  Load [0 ] 0
I  Ifetch [1 ] 1
I  Store [0 ] 0
I  Inv [0 ] 0
I  L1_Replacement [138 ] 138

S  Load [0 ] 0
S  Ifetch [0 ] 0
S  Store [0 ] 0
S  Inv [27 ] 27
S  L1_Replacement [9 ] 9

E  Load [0 ] 0
E  Ifetch [0 ] 0
E  Store [0 ] 0
E  Inv [7 ] 7
E  L1_Replacement [43 ] 43
E  Fwd_GETX [0 ] 0
E  Fwd_GETS [0 ] 0
E  Fwd_GET_INSTR [0 ] 0

M  Load [4 ] 4
M  Ifetch [0 ] 0
M  Store [77 ] 77
M  Inv [96 ] 96
M  L1_Replacement [697 ] 697
M  Fwd_GETX [0 ] 0
M  Fwd_GETS [0 ] 0
M  Fwd_GET_INSTR [0 ] 0

IS  Load [0 ] 0
IS  Ifetch [0 ] 0
IS  Store [0 ] 0
IS  Inv [10 ] 10
IS  L1_Replacement [27672 ] 27672
IS  Data_Exclusive [50 ] 50
IS  DataS_fromL1 [0 ] 0
IS  Data_all_Acks [36 ] 36

IM  Load [0 ] 0
IM  Ifetch [0 ] 0
IM  Store [0 ] 0
IM  Inv [0 ] 0
IM  L1_Replacement [468305 ] 468305
IM  Data [0 ] 0
IM  Data_all_Acks [794 ] 794
IM  Ack [0 ] 0

SM  Load [0 ] 0
SM  Ifetch [0 ] 0
SM  Store [0 ] 0
SM  Inv [0 ] 0
SM  L1_Replacement [0 ] 0
SM  Ack [0 ] 0
SM  Ack_all [0 ] 0

IS_I  Load [0 ] 0
IS_I  Ifetch [0 ] 0
IS_I  Store [0 ] 0
IS_I  Inv [0 ] 0
IS_I  L1_Replacement [10 ] 10
IS_I  Data_Exclusive [0 ] 0
IS_I  DataS_fromL1 [0 ] 0
IS_I  Data_all_Acks [10 ] 10

M_I  Load [0 ] 0
M_I  Ifetch [314 ] 314
M_I  Store [0 ] 0
M_I  Inv [429 ] 429
M_I  L1_Replacement [0 ] 0
M_I  Fwd_GETX [0 ] 0
M_I  Fwd_GETS [0 ] 0
M_I  Fwd_GET_INSTR [0 ] 0
M_I  WB_Ack [311 ] 311

E_I  Load [0 ] 0
E_I  Ifetch [0 ] 0
E_I  Store [0 ] 0
E_I  L1_Replacement [0 ] 0

SINK_WB_ACK  Load [1 ] 1
SINK_WB_ACK  Ifetch [0 ] 0
SINK_WB_ACK  Store [2 ] 2
SINK_WB_ACK  Inv [0 ] 0
SINK_WB_ACK  L1_Replacement [0 ] 0
SINK_WB_ACK  WB_Ack [427 ] 427

Cache Stats: system.l2_cntrl0.L2cacheMemory
  system.l2_cntrl0.L2cacheMemory_total_misses: 0
  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
  system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
  system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
  system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0


 --- L2Cache ---
 - Event Counts -
L1_GET_INSTR [47 ] 47
L1_GETS [51 ] 51
L1_GETX [817 ] 817
L1_UPGRADE [0 ] 0
L1_PUTX [393 ] 393
L1_PUTX_old [3893 ] 3893
Fwd_L1_GETX [0 ] 0
Fwd_L1_GETS [0 ] 0
Fwd_L1_GET_INSTR [0 ] 0
L2_Replacement [266 ] 266
L2_Replacement_clean [24885 ] 24885
Mem_Data [849 ] 849
Mem_Ack [844 ] 844
WB_Data [494 ] 494
WB_Data_clean [30 ] 30
Ack [0 ] 0
Ack_all [43 ] 43
Unblock [0 ] 0
Unblock_Cancel [0 ] 0
Exclusive_Unblock [844 ] 844
MEM_Inv [0 ] 0

 - Transitions -
NP  L1_GET_INSTR [38 ] 38
NP  L1_GETS [50 ] 50
NP  L1_GETX [763 ] 763
NP  L1_PUTX [0 ] 0
NP  L1_PUTX_old [167 ] 167

SS  L1_GET_INSTR [0 ] 0
SS  L1_GETS [0 ] 0
SS  L1_GETX [9 ] 9
SS  L1_UPGRADE [0 ] 0
SS  L1_PUTX [0 ] 0
SS  L1_PUTX_old [0 ] 0
SS  L2_Replacement [0 ] 0
SS  L2_Replacement_clean [37 ] 37
SS  MEM_Inv [0 ] 0

M  L1_GET_INSTR [9 ] 9
M  L1_GETS [1 ] 1
M  L1_GETX [22 ] 22
M  L1_PUTX [0 ] 0
M  L1_PUTX_old [0 ] 0
M  L2_Replacement [266 ] 266
M  L2_Replacement_clean [12 ] 12
M  MEM_Inv [0 ] 0

MT  L1_GET_INSTR [0 ] 0
MT  L1_GETS [0 ] 0
MT  L1_GETX [0 ] 0
MT  L1_PUTX [311 ] 311
MT  L1_PUTX_old [0 ] 0
MT  L2_Replacement [0 ] 0
MT  L2_Replacement_clean [532 ] 532
MT  MEM_Inv [0 ] 0

M_I  L1_GET_INSTR [0 ] 0
M_I  L1_GETS [0 ] 0
M_I  L1_GETX [23 ] 23
M_I  L1_UPGRADE [0 ] 0
M_I  L1_PUTX [0 ] 0
M_I  L1_PUTX_old [260 ] 260
M_I  Mem_Ack [844 ] 844
M_I  MEM_Inv [0 ] 0

MT_I  L1_GET_INSTR [0 ] 0
MT_I  L1_GETS [0 ] 0
MT_I  L1_GETX [0 ] 0
MT_I  L1_UPGRADE [0 ] 0
MT_I  L1_PUTX [0 ] 0
MT_I  L1_PUTX_old [0 ] 0
MT_I  WB_Data [0 ] 0
MT_I  WB_Data_clean [0 ] 0
MT_I  Ack_all [0 ] 0
MT_I  MEM_Inv [0 ] 0

MCT_I  L1_GET_INSTR [0 ] 0
MCT_I  L1_GETS [0 ] 0
MCT_I  L1_GETX [0 ] 0
MCT_I  L1_UPGRADE [0 ] 0
MCT_I  L1_PUTX [0 ] 0
MCT_I  L1_PUTX_old [1530 ] 1530
MCT_I  WB_Data [494 ] 494
MCT_I  WB_Data_clean [30 ] 30
MCT_I  Ack_all [7 ] 7

I_I  L1_GET_INSTR [0 ] 0
I_I  L1_GETS [0 ] 0
I_I  L1_GETX [0 ] 0
I_I  L1_UPGRADE [0 ] 0
I_I  L1_PUTX [0 ] 0
I_I  L1_PUTX_old [0 ] 0
I_I  Ack [0 ] 0
I_I  Ack_all [36 ] 36

S_I  L1_GET_INSTR [0 ] 0
S_I  L1_GETS [0 ] 0
S_I  L1_GETX [0 ] 0
S_I  L1_UPGRADE [0 ] 0
S_I  L1_PUTX [0 ] 0
S_I  L1_PUTX_old [0 ] 0
S_I  Ack [0 ] 0
S_I  Ack_all [0 ] 0
S_I  MEM_Inv [0 ] 0

ISS  L1_GET_INSTR [0 ] 0
ISS  L1_GETS [0 ] 0
ISS  L1_GETX [0 ] 0
ISS  L1_PUTX [0 ] 0
ISS  L1_PUTX_old [0 ] 0
ISS  L2_Replacement [0 ] 0
ISS  L2_Replacement_clean [768 ] 768
ISS  Mem_Data [49 ] 49
ISS  MEM_Inv [0 ] 0

IS  L1_GET_INSTR [0 ] 0
IS  L1_GETS [0 ] 0
IS  L1_GETX [0 ] 0
IS  L1_PUTX [0 ] 0
IS  L1_PUTX_old [0 ] 0
IS  L2_Replacement [0 ] 0
IS  L2_Replacement_clean [1122 ] 1122
IS  Mem_Data [37 ] 37
IS  MEM_Inv [0 ] 0

IM  L1_GET_INSTR [0 ] 0
IM  L1_GETS [0 ] 0
IM  L1_GETX [0 ] 0
IM  L1_PUTX [0 ] 0
IM  L1_PUTX_old [0 ] 0
IM  L2_Replacement [0 ] 0
IM  L2_Replacement_clean [10668 ] 10668
IM  Mem_Data [763 ] 763
IM  MEM_Inv [0 ] 0

SS_MB  L1_GET_INSTR [0 ] 0
SS_MB  L1_GETS [0 ] 0
SS_MB  L1_GETX [0 ] 0
SS_MB  L1_UPGRADE [0 ] 0
SS_MB  L1_PUTX [0 ] 0
SS_MB  L1_PUTX_old [0 ] 0
SS_MB  L2_Replacement [0 ] 0
SS_MB  L2_Replacement_clean [0 ] 0
SS_MB  Unblock_Cancel [0 ] 0
SS_MB  Exclusive_Unblock [9 ] 9
SS_MB  MEM_Inv [0 ] 0

MT_MB  L1_GET_INSTR [0 ] 0
MT_MB  L1_GETS [0 ] 0
MT_MB  L1_GETX [0 ] 0
MT_MB  L1_UPGRADE [0 ] 0
MT_MB  L1_PUTX [82 ] 82
MT_MB  L1_PUTX_old [1936 ] 1936
MT_MB  L2_Replacement [0 ] 0
MT_MB  L2_Replacement_clean [11746 ] 11746
MT_MB  Unblock_Cancel [0 ] 0
MT_MB  Exclusive_Unblock [835 ] 835
MT_MB  MEM_Inv [0 ] 0

M_MB  L1_GET_INSTR [0 ] 0
M_MB  L1_GETS [0 ] 0
M_MB  L1_GETX [0 ] 0
M_MB  L1_UPGRADE [0 ] 0
M_MB  L1_PUTX [0 ] 0
M_MB  L1_PUTX_old [0 ] 0
M_MB  L2_Replacement [0 ] 0
M_MB  L2_Replacement_clean [0 ] 0
M_MB  Exclusive_Unblock [0 ] 0
M_MB  MEM_Inv [0 ] 0

MT_IIB  L1_GET_INSTR [0 ] 0
MT_IIB  L1_GETS [0 ] 0
MT_IIB  L1_GETX [0 ] 0
MT_IIB  L1_UPGRADE [0 ] 0
MT_IIB  L1_PUTX [0 ] 0
MT_IIB  L1_PUTX_old [0 ] 0
MT_IIB  L2_Replacement [0 ] 0
MT_IIB  L2_Replacement_clean [0 ] 0
MT_IIB  WB_Data [0 ] 0
MT_IIB  WB_Data_clean [0 ] 0
MT_IIB  Unblock [0 ] 0
MT_IIB  MEM_Inv [0 ] 0

MT_IB  L1_GET_INSTR [0 ] 0
MT_IB  L1_GETS [0 ] 0
MT_IB  L1_GETX [0 ] 0
MT_IB  L1_UPGRADE [0 ] 0
MT_IB  L1_PUTX [0 ] 0
MT_IB  L1_PUTX_old [0 ] 0
MT_IB  L2_Replacement [0 ] 0
MT_IB  L2_Replacement_clean [0 ] 0
MT_IB  WB_Data [0 ] 0
MT_IB  WB_Data_clean [0 ] 0
MT_IB  Unblock_Cancel [0 ] 0
MT_IB  MEM_Inv [0 ] 0

MT_SB  L1_GET_INSTR [0 ] 0
MT_SB  L1_GETS [0 ] 0
MT_SB  L1_GETX [0 ] 0
MT_SB  L1_UPGRADE [0 ] 0
MT_SB  L1_PUTX [0 ] 0
MT_SB  L1_PUTX_old [0 ] 0
MT_SB  L2_Replacement [0 ] 0
MT_SB  L2_Replacement_clean [0 ] 0
MT_SB  Unblock [0 ] 0
MT_SB  MEM_Inv [0 ] 0

Memory controller: system.dir_cntrl0.memBuffer:
  memory_total_requests: 1611
  memory_reads: 851
  memory_writes: 760
  memory_refreshes: 734
  memory_total_request_delays: 1055
  memory_delays_per_request: 0.654873
  memory_delays_in_input_queue: 156
  memory_delays_behind_head_of_bank_queue: 4
  memory_delays_stalled_at_head_of_bank_queue: 895
  memory_stalls_for_bank_busy: 156
  memory_stalls_for_random_busy: 0
  memory_stalls_for_anti_starvation: 0
  memory_stalls_for_arbitration: 62
  memory_stalls_for_bus: 325
  memory_stalls_for_tfaw: 0
  memory_stalls_for_read_write_turnaround: 273
  memory_stalls_for_read_read_turnaround: 79
  accesses_per_bank: 48  41  46  89  53  46  79  49  58  36  59  56  46  58  63  58  56  48  30  39  32  49  59  31  36  68  44  52  47  42  46  47  

 --- Directory ---
 - Event Counts -
Fetch [851 ] 851
Data [760 ] 760
Memory_Data [850 ] 850
Memory_Ack [759 ] 759
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
CleanReplacement [85 ] 85

 - Transitions -
I  Fetch [851 ] 851
I  DMA_READ [0 ] 0
I  DMA_WRITE [0 ] 0

ID  Fetch [0 ] 0
ID  Data [0 ] 0
ID  Memory_Data [0 ] 0
ID  DMA_READ [0 ] 0
ID  DMA_WRITE [0 ] 0

ID_W  Fetch [0 ] 0
ID_W  Data [0 ] 0
ID_W  Memory_Ack [0 ] 0
ID_W  DMA_READ [0 ] 0
ID_W  DMA_WRITE [0 ] 0

M  Data [760 ] 760
M  DMA_READ [0 ] 0
M  DMA_WRITE [0 ] 0
M  CleanReplacement [85 ] 85

IM  Fetch [0 ] 0
IM  Data [0 ] 0
IM  Memory_Data [850 ] 850
IM  DMA_READ [0 ] 0
IM  DMA_WRITE [0 ] 0

MI  Fetch [0 ] 0
MI  Data [0 ] 0
MI  Memory_Ack [759 ] 759
MI  DMA_READ [0 ] 0
MI  DMA_WRITE [0 ] 0

M_DRD  Data [0 ] 0
M_DRD  DMA_READ [0 ] 0
M_DRD  DMA_WRITE [0 ] 0

M_DRDI  Fetch [0 ] 0
M_DRDI  Data [0 ] 0
M_DRDI  Memory_Ack [0 ] 0
M_DRDI  DMA_READ [0 ] 0
M_DRDI  DMA_WRITE [0 ] 0

M_DWR  Data [0 ] 0
M_DWR  DMA_READ [0 ] 0
M_DWR  DMA_WRITE [0 ] 0

M_DWRI  Fetch [0 ] 0
M_DWRI  Data [0 ] 0
M_DWRI  Memory_Ack [0 ] 0
M_DWRI  DMA_READ [0 ] 0
M_DWRI  DMA_WRITE