144 lines
6.0 KiB
BibTeX
144 lines
6.0 KiB
BibTeX
@ARTICLE{joukah_15,
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author={Jouppi, Norman P. and Kahng, Andrew B. and Muralimanohar, Naveen and Srinivas, Vaishnav},
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journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
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title={CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models},
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year={2015},
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volume={23},
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number={7},
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pages={1254-1267},
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keywords={Timing;Integrated circuit interconnections;Random access memory;Clocks;Servers;Jitter;Mobile communication;CACTI;CACTI-IO;dynamic random access memory (DRAM);IO;memory interface;power and timing models;CACTI;CACTI-IO;dynamic random access memory (DRAM);IO;memory interface;power and timing models},
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doi={10.1109/TVLSI.2014.2334635}}
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@inproceedings{joukah_12,
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author = {Jouppi, Norman P. and Kahng, Andrew B. and Muralimanohar, Naveen and Srinivas, Vaishnav},
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title = {CACTI-IO: CACTI with off-chip power-area-timing models},
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year = {2012},
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isbn = {9781450315739},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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url = {https://doi.org/10.1145/2429384.2429446},
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doi = {10.1145/2429384.2429446},
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booktitle = {Proceedings of the International Conference on Computer-Aided Design},
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pages = {294–301},
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numpages = {8},
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keywords = {CACTI, DRAM, IO, memory interface, power and timing models},
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location = {San Jose, California},
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series = {ICCAD '12}
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}
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@misc{micron_ddr3_11_kopie_ipsj,
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title = {{Micron System Power Calculator}},
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author = {{Micron}},
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howpublished = {last access 2024-11-12},
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url={https://www.micron.com/sales-support/design-tools/dram-power-calculator},
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year={2014}
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}
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@misc{kargoo_14,
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title = {{{DRAMPower}}: {{Open-source DRAM}} Power \& Energy Estimation Tool},
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author = {Chandrasekar, Karthik and Weis, Christian and Li, Yonghui and Akesson, Benny and Naji, Omar and Jung, Matthias and Wehn, Norbert and Goossens, Kees},
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year = {Last Access 15.08.2019},
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address = {http://www.drampower.info/},
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owner = {Brugger},
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timestamp = {2019-08-15}
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}
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@inproceedings{junmat_16b,
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title = {A {{New Bank Sensitive DRAMPower Model}} for {{Efficient Design Space Exploration}}},
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booktitle = {International Workshop on Power and Timing Modeling, Optimization and Simulation ({{PATMOS}} 2016)},
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author = {Jung, Matthias and Mathew, Deepak M. and Zulian, {\'E}der F. and Weis, Christian and Wehn, Norbert},
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year = {2016},
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owner = {MJ},
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timestamp = {2017-06-15}
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}
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@inproceedings{matzul_17,
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author = {Mathew, Deepak M. and Zulian, \'{E}der F. and Kannoth, Subash and Jung, Matthias and Weis, Christian and Wehn, Norbert},
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title = {A Bank-Wise DRAM Power Model for System Simulations},
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year = {2017},
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isbn = {9781450348409},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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url = {https://doi.org/10.1145/3023973.3023978},
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doi = {10.1145/3023973.3023978},
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booktitle = {Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
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articleno = {5},
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numpages = {7},
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keywords = {DRAM, Power, Simulation},
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location = {Stockholm, Sweden},
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series = {RAPIDO '17}
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}
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@article{ghoyag_18,
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title = {What {{Your DRAM Power Models Are Not Telling You}}: {{Lessons}} from a {{Detailed Experimental Study}}},
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shorttitle = {What {{Your DRAM Power Models Are Not Telling You}}},
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author = {Ghose, Saugata and Yaglik{\c c}i, Abdullah Giray and Gupta, Raghav and Lee, Donghyuk and Kudrolli, Kais and Liu, William X. and Hassan, Hasan and Chang, Kevin K. and Chatterjee, Niladrish and Agrawal, Aditya and O'Connor, Mike and Mutlu, Onur},
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year = {2018},
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month = dec,
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journal = {Proc. ACM Meas. Anal. Comput. Syst.},
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volume = {2},
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number = {3},
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pages = {38:1--38:41},
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doi = {10.1145/3224419},
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urldate = {2024-10-25},
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file = {/Users/myzinsky/Zotero/storage/NYBYGMFT/Ghose et al. - 2018 - What Your DRAM Power Models Are Not Telling You Lessons from a Detailed Experimental Study.pdf}
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}
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@ARTICLE{holsta_19,
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author={Hollis, Timothy M. and Stave, Eric and Ovard, Dave and Greeff, Roy and Spirkl, Worfgang and Brox, Martin and Taylor, Jennifer and Butterfield, Justin},
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journal={IEEE Solid-State Circuits Magazine},
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title={Recent Evolution in the DRAM Interface: Mile-Markers Along Memory Lane},
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year={2019},
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volume={11},
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number={2},
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pages={14-30},
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keywords={Random access memory;Bandwidth;DRAM chips;Graphics;Memory management;Semiconductor devices},
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doi={10.1109/MSSC.2019.2910617}}
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@article{balkah_17,
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author = {Balasubramonian, Rajeev and Kahng, Andrew B. and Muralimanohar, Naveen and Shafiee, Ali and Srinivas, Vaishnav},
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title = {CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories},
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year = {2017},
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issue_date = {June 2017},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {14},
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number = {2},
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issn = {1544-3566},
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url = {https://doi.org/10.1145/3085572},
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doi = {10.1145/3085572},
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journal = {ACM Trans. Archit. Code Optim.},
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month = jun,
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articleno = {14},
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numpages = {25},
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keywords = {DRAM, Memory, NVM, interconnects, tools}
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}
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@ARTICLE{donxu_12,
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author={Dong, Xiangyu and Xu, Cong and Xie, Yuan and Jouppi, Norman P.},
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journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
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title={NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory},
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year={2012},
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volume={31},
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number={7},
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pages={994-1007},
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keywords={Nonvolatile memory;Arrays;Phase change random access memory;Wires;Distributed databases;Integrated circuit modeling;Analytical circuit model;MRAM;NAND Flash;nonvolatile memory;phase-change random-access memory (PCRAM);resistive random-access memory (ReRAM);spin-torque-transfer memory (STT-RAM)},
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doi={10.1109/TCAD.2012.2185930}}
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@book{dalpou_98,
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place={Cambridge},
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title={Digital Systems Engineering},
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publisher={Cambridge University Press},
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author={Dally, William J. and Poulton, John W.},
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year={1998}
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}
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@book{bak_90,
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title={Circuits, Interconnections, and Packaging for VLSI},
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author={Bakoglu, H.B.},
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isbn={9780201060089},
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lccn={87022964},
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series={Addison-Wesley VLSI systems series},
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year={1990},
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publisher={Addison-Wesley Publishing Company}
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} |