From ffbfaa5a21b0fed8b8e3874c4a13982767476cff Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 6 Mar 2025 09:27:04 +0000 Subject: [PATCH] Update on Overleaf. --- data/benchmarks.csv | 5 - data/benchmarks_drampower.csv | 3 + data/benchmarks_dramsys.csv | 5 + data/hynix_nointerface.csv | 625 ++++++++++++++++++++ data/hynix_v1.csv | 625 ++++++++++++++++++++ data/hynix_v2.csv | 625 ++++++++++++++++++++ data/micron_nointerface.csv | 625 ++++++++++++++++++++ data/micron_v1.csv | 625 ++++++++++++++++++++ data/micron_v2.csv | 625 ++++++++++++++++++++ data/samsung_nointerface.csv | 625 ++++++++++++++++++++ data/samsung_v1.csv | 625 ++++++++++++++++++++ data/samsung_v2.csv | 625 ++++++++++++++++++++ drampower-abstract.tex | 27 - drampower-acknowledgements.tex | 1 - drampower-appendix.tex | 34 -- drampower-authors.tex | 36 -- drampower-settings.tex | 32 - drampower.bib | 8 - img/bankwise_current.tex | 2 +- img/power_plot.tex | 8 +- img/refresh_currents.tex | 59 +- drampower-main.tex => main.tex | 1004 ++++++++++++++------------------ 22 files changed, 6081 insertions(+), 768 deletions(-) delete mode 100644 data/benchmarks.csv create mode 100644 data/benchmarks_drampower.csv create mode 100644 data/benchmarks_dramsys.csv create mode 100644 data/hynix_nointerface.csv create mode 100644 data/hynix_v1.csv create mode 100644 data/hynix_v2.csv create mode 100644 data/micron_nointerface.csv create mode 100644 data/micron_v1.csv create mode 100644 data/micron_v2.csv create mode 100644 data/samsung_nointerface.csv create mode 100644 data/samsung_v1.csv create mode 100644 data/samsung_v2.csv delete mode 100644 drampower-abstract.tex delete mode 100644 drampower-acknowledgements.tex delete mode 100644 drampower-appendix.tex delete mode 100644 drampower-authors.tex delete mode 100644 drampower-settings.tex rename drampower-main.tex => main.tex (54%) diff --git a/data/benchmarks.csv b/data/benchmarks.csv deleted file mode 100644 index 7deb17f..0000000 --- a/data/benchmarks.csv +++ /dev/null @@ -1,5 +0,0 @@ -Name,CPU_Time_ms,Real_Time_ms,Iterations -nopower-nostore,559.0857695,561.6144617524697,4 -power-nostore,774.2795032500001,777.8368692524964,4 -nopower-store,895.49864875,901.2260472518392,4 -power-store,1004.3982304999998,1009.4151812518248,4 diff --git a/data/benchmarks_drampower.csv b/data/benchmarks_drampower.csv new file mode 100644 index 0000000..fd882d3 --- /dev/null +++ b/data/benchmarks_drampower.csv @@ -0,0 +1,3 @@ +Name,CPU_Time_ms,Real_Time_ms,Iterations,command_count +drampower-bitset,278.53786654999993,279.55197155242786,20,400000 +drampower-vector,11445.01951335,11485.002198501023,20,400000 diff --git a/data/benchmarks_dramsys.csv b/data/benchmarks_dramsys.csv new file mode 100644 index 0000000..2440c2e --- /dev/null +++ b/data/benchmarks_dramsys.csv @@ -0,0 +1,5 @@ +Name,CPU_Time_ms,Real_Time_ms,Iterations,Requests +nopower-nostore,6946.6400635,6972.69602669985,20,1000000 +power-nostore,8435.135265600002,8466.875247750431,20,1000000 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article. -\begin{abstract} - - DRAMPower is a cool thing that makes things and allows you to do things. Very cool! - - - - - - - - - - - - - - - - - - - - -\end{abstract} diff --git a/drampower-acknowledgements.tex b/drampower-acknowledgements.tex deleted file mode 100644 index b37957e..0000000 --- a/drampower-acknowledgements.tex +++ /dev/null @@ -1 +0,0 @@ -\section{Acknowledgements} diff --git a/drampower-appendix.tex b/drampower-appendix.tex deleted file mode 100644 index 55a6c32..0000000 --- a/drampower-appendix.tex +++ /dev/null @@ -1,34 +0,0 @@ - -%% -%% If your work has an appendix, this is the place to put it. -\appendix - -\section{Research Methods} - -\subsection{Part One} - -Lorem ipsum dolor sit amet, consectetur adipiscing elit. Morbi -malesuada, quam in pulvinar varius, metus nunc fermentum urna, id -sollicitudin purus odio sit amet enim. Aliquam ullamcorper eu ipsum -vel mollis. Curabitur quis dictum nisl. Phasellus vel semper risus, et -lacinia dolor. Integer ultricies commodo sem nec semper. - -\subsection{Part Two} - -Etiam commodo feugiat nisl pulvinar pellentesque. Etiam auctor sodales -ligula, non varius nibh pulvinar semper. Suspendisse nec lectus non -ipsum convallis congue hendrerit vitae sapien. Donec at laoreet -eros. Vivamus non purus placerat, scelerisque diam eu, cursus -ante. Etiam aliquam tortor auctor efficitur mattis. - -\section{Online Resources} - -Nam id fermentum dui. Suspendisse sagittis tortor a nulla mollis, in -pulvinar ex pretium. Sed interdum orci quis metus euismod, et sagittis -enim maximus. Vestibulum gravida massa ut felis suscipit -congue. Quisque mattis elit a risus ultrices commodo venenatis eget -dui. Etiam sagittis eleifend elementum. - -Nam interdum magna at lectus dignissim, ac dignissim lorem -rhoncus. Maecenas eu arcu ac neque placerat aliquam. Nunc pulvinar -massa et mattis lacinia. diff --git a/drampower-authors.tex b/drampower-authors.tex deleted file mode 100644 index 5e31581..0000000 --- a/drampower-authors.tex +++ /dev/null @@ -1,36 +0,0 @@ - -%% -%% The "author" command and its associated commands are used to define -%% the authors and their affiliations. -%% Of note is the shared affiliation of the first two authors, and the -%% "authornote" and "authornotemark" commands -%% used to denote shared contribution to the research. - -\author{Thomas Psota} -\email{thomas.psota@iese.fraunhofer.de} -\orcid{0009-0009-3368-5396} -\affiliation{% - \institution{Fraunhofer IESE} - \city{Kaiserslautern} - \country{Germany} -} - -\author{Lukas Steiner} -\email{lukas.steiner@rptu.de} -\orcid{0009-0009-3368-5396} -\affiliation{% - \institution{RPTU Kaiserslautern-Landau} - \city{Kaiserslautern} - \country{Germany} -} - -\author{Matthias Jung} -\email{m.jung@uni-wuerzburg.de} -\orcid{0000-0003-0036-2143} -\affiliation{% - \institution{Julius-Maximilians-Universität Würzburg} - \city{Würzburg} - \country{Germany} -} - - diff --git a/drampower-settings.tex b/drampower-settings.tex deleted file mode 100644 index 9afe963..0000000 --- a/drampower-settings.tex +++ /dev/null @@ -1,32 +0,0 @@ -%% -%% Set the title of the paper here -\newcommand{\papertitle}{ - DRAMPower - A simulator for DRAM power consumption -} - -%% -%% Conference settings -\acmConference[IESE'24]{IESE Basement Party}{August 2024}{Kaiserslautern, Germany}% - -%% -%% Paper logo settings -\newcommand{\paperlogo}{ -\begin{teaserfigure} - \includegraphics[width=\textwidth]{figs/logo_drampower_5_0.png} - \caption{DRAMPower 5.0 Logo} - \Description{DRAMPower 5.0 Logo.} - \label{fig:logo} -\end{teaserfigure} -} - -%% -%% Keyword settings -\newcommand{\paperkeywords}{\keywords{ - DRAM, DDR, simulation, power -}} - -%\received{20 February 2007} -%\received[revised]{12 March 2009} -%\received[accepted]{5 June 2009} - -\newcommand{\todo}[1]{\textcolor{\red}{#1}} diff --git a/drampower.bib b/drampower.bib index 4f7eb57..a7cb68b 100644 --- a/drampower.bib +++ b/drampower.bib @@ -6,7 +6,6 @@ volume={23}, number={7}, pages={1254-1267}, - keywords={Timing;Integrated circuit interconnections;Random access memory;Clocks;Servers;Jitter;Mobile communication;CACTI;CACTI-IO;dynamic random access memory (DRAM);IO;memory interface;power and timing models;CACTI;CACTI-IO;dynamic random access memory (DRAM);IO;memory interface;power and timing models}, doi={10.1109/TVLSI.2014.2334635}} @inproceedings{joukah_12, @@ -122,7 +121,6 @@ keywords = {DRAM, Memory, NVM, interconnects, tools} volume={31}, number={7}, pages={994-1007}, - keywords={Nonvolatile memory;Arrays;Phase change random access memory;Wires;Distributed databases;Integrated circuit modeling;Analytical circuit model;MRAM;NAND Flash;nonvolatile memory;phase-change random-access memory (PCRAM);resistive random-access memory (ReRAM);spin-torque-transfer memory (STT-RAM)}, doi={10.1109/TCAD.2012.2185930}} @book{dalpou_98, @@ -155,7 +153,6 @@ number = {2}, issn = {0362-1340}, url = {https://doi.org/10.1145/3296957.3173177}, doi = {10.1145/3296957.3173177}, -abstract = {We are experiencing an explosive growth in the number of consumer devices, including smartphones, tablets, web-based computers such as Chromebooks, and wearable devices. For this class of devices, energy efficiency is a first-class concern due to the limited battery capacity and thermal power budget. We find that data movement is a major contributor to the total system energy and execution time in consumer devices. The energy and performance costs of moving data between the memory system and the compute units are significantly higher than the costs of computation. As a result, addressing data movement is crucial for consumer devices. In this work, we comprehensively analyze the energy and performance impact of data movement for several widely-used Google consumer workloads: (1) the Chrome web browser; (2) TensorFlow Mobile, Google's machine learning framework; (3) video playback, and (4) video capture, both of which are used in many video services such as YouTube and Google Hangouts. We find that processing-in-memory (PIM) can significantly reduce data movement for all of these workloads, by performing part of the computation close to memory. Each workload contains simple primitives and functions that contribute to a significant amount of the overall data movement. We investigate whether these primitives and functions are feasible to implement using PIM, given the limited area and power constraints of consumer devices. Our analysis shows that offloading these primitives to PIM logic, consisting of either simple cores or specialized accelerators, eliminates a large amount of data movement, and significantly reduces total system energy (by an average of 55.4\% across the workloads) and execution time (by an average of 54.2\%).}, journal = {SIGPLAN Not.}, month = mar, pages = {316–331}, @@ -206,7 +203,6 @@ series = {ASPLOS '18} issn = {2379-3155}, doi = {10.1109/MICRO.2010.42}, urldate = {2024-11-14}, - abstract = {Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible to calculate the energy consumption of currently available DRAMs from their datasheets, but datasheets don't allow extrapolation to future DRAM technologies and don't show how other changes like increasing bandwidth requirements change DRAM energy consumption. This paper first presents a flexible DRAM power model which uses a description of DRAM architecture, technology and operation to calculate power usage and verifies it against datasheet values. Then the model is used together with assumptions about the DRAM roadmap to extrapolate DRAM energy consumption to future DRAM generations. Using this model we evaluate some of the proposed DRAM power reduction schemes.}, keywords = {Arrays,Capacitance,DRAM,Driver circuits,Logic gates,power,Random access memory,Transistors}, file = {/Users/myzinsky/Zotero/storage/3LW3ARUS/Vogelsang - 2010 - Understanding the Energy Consumption of Dynamic Random Access Memories.pdf;/Users/myzinsky/Zotero/storage/HEEPHYEU/5695550.html} } @@ -217,7 +213,6 @@ series = {ASPLOS '18} author = {Yang, Lita and Kao, Changjung and Srikanth, Sriseshan and Morris, Daniel and Sumbul, H Ekin and Wu, Tony F and Beign{\'e}, Edith}, year = {2024}, address = {Washingron}, - abstract = {Image Signal Processing (ISP) is an important component in augmented and virtual reality (AR/VR) applications. With the goal of running these applications on battery-powered edge devices, the ISP unit must satisfy rigorous power, performance, and form factor requirements. However, ISP workloads incur large memory footprints and intensive DRAM accesses that are prohibitively expensive for the stringent requirements of all-day wearable AR/VR products. Recent progress in 3D integration provides a promising solution for increasing memory capacities for iso-footprint, while achieving lower I/O power with shorter, vertical 3D interconnections. In this work, we explore and characterize two types of advanced 3D-stacked memories for ISP workloads: 3D-SRAM and 3D-DRAM. Our analysis demonstrates that by allocating additional 3D-stacked local memory to the ISP unit, we reduce expensive off-chip DRAM accesses by 57-92\%, allowing us to deploy larger ISP workloads within power budgets not previously feasible with the 2D ISP baseline architecture. Comparing the two 3D-stacked memories, we observe that the use of 3D-DRAM reduces the total ISP power consumption by up to 53\%, while 3D-SRAM achieves up to 32\% power savings due to significant leakage contribution at increasing SRAM capacities. Finally, we propose a 3D-stacked hybrid memory ISP solution, combining both 3D-SRAM and 3DDRAM, which can further improve the ISP power efficiency by an additional 9-16\% on top of a 3D-DRAM-only memory architecture. To our knowledge, this is the first study to explore the benefits of advanced 3D-stacked memory for deploying ISP workloads on AR/VR devices.}, langid = {english}, file = {/Users/myzinsky/Zotero/storage/22TRQV4G/Yang et al. - Characterization and Design of 3D-Stacked Memory for Image Signal Processing on ARVR Devices.pdf} } @@ -247,9 +242,6 @@ and Jung, Matthias and Prado, Felipe S. and Bykov, Kirill and Wehn, Norbert", -editor="Orailoglu, Alex -and Jung, Matthias -and Reichenbach, Marc", title="{DRAMSys4.0}: A Fast and Cycle-Accurate {SystemC/TLM}-Based {DRAM} Simulator", booktitle="Embedded Computer Systems: Architectures, Modeling, and Simulation", year="2020", diff --git a/img/bankwise_current.tex b/img/bankwise_current.tex index c6b3714..8660f81 100644 --- a/img/bankwise_current.tex +++ b/img/bankwise_current.tex @@ -80,4 +80,4 @@ black,decorate,decoration={brace,amplitude=10pt,mirror},xshift=0.0pt,yshift=-0.0 -- (\SEVEN,0) node[black,midway,yshift=-0.6cm] {\footnotesize $1-\rho$}; -\end{tikzpicture} \ No newline at end of file +\end{tikzpicture}% \ No newline at end of file diff --git a/img/power_plot.tex b/img/power_plot.tex index 7813302..b6c8c64 100644 --- a/img/power_plot.tex +++ b/img/power_plot.tex @@ -93,12 +93,12 @@ % Legend \begin{scope} \draw[green!50!black,line width=0.9pt] (-0.15, -1) -- (0.15, -1); - \node[anchor=west] at (0.2,-1) {Sim. Datasheet IDDs}; + \node[anchor=west] at (0.2,-1) {Sim. Datasheet $I_{DD}$}; \draw[red!50,line width=0.9pt] (3.4-0.15, -1) -- (3.4+0.15, -1); - \node[anchor=west] at (3.6,-1) {Sim. Measured IDDs}; + \node[anchor=west] at (3.6,-1) {Sim. Measured $I_{DD}$}; \draw[blue!50,line width=0.9pt] (-0.15, -1.5) -- (0.15, -1.5); - \node[anchor=west] at (0.2,-1.5) {Measurement}; + \node[anchor=west] at (0.2,-1.5) {Real Measurement}; \end{scope} -\end{tikzpicture}% +\end{tikzpicture}% \ No newline at end of file diff --git a/img/refresh_currents.tex b/img/refresh_currents.tex index 09e5fc6..0c60df2 100644 --- a/img/refresh_currents.tex +++ b/img/refresh_currents.tex @@ -1,23 +1,30 @@ \begin{tikzpicture} - +% % Define colors \definecolor{idlecolor}{RGB}{255, 204, 153} % Light orange \definecolor{refcolor}{RGB}{153, 204, 255} % Light blue \definecolor{backgroundcolor}{RGB}{255, 255, 153} % Light yellow - -\newcommand{\ya}{1} -\newcommand{\yb}{2.6} -\newcommand{\yc}{6} - +% +\newcommand{\ya}{0.5} +\newcommand{\yb}{1.5} +\newcommand{\yc}{3.5}%6 +% +%\newcommand{\ya}{0.8} +%\newcommand{\yb}{2.08} +%\newcommand{\yc}{4.8} +% \pgfdeclarelayer{background} \pgfsetlayers{background, main} % Define the axis \begin{axis}[ %width=15cm, height=8cm, + axis equal image, xlabel={Time}, ylabel={Current}, - xmin=0, xmax=6, - ymin=0, ymax=7, + xmin=0, + xmax=6, + ymin=0, + ymax=4, xtick=\empty, ytick=\empty, extra y ticks={\ya, \yb, \yc}, @@ -36,24 +43,9 @@ \begin{pgfonlayer}{background} \draw[pattern=north east lines, pattern color=red!50, draw=none] (axis cs:1,\ya) rectangle (axis cs:2,\yc); \draw[pattern=north east lines, pattern color=red!50, draw=none] (axis cs:4,\ya) rectangle (axis cs:5,\yc); -\draw[pattern=north east lines, pattern color=green!50, draw=none] (axis cs:0,0) rectangle (axis cs:6,1); +\draw[pattern=north east lines, pattern color=green!50, draw=none] (axis cs:0,0) rectangle (axis cs:6,\ya); \draw[pattern=north west lines, pattern color=blue!50, draw=none] (axis cs:0,\ya) rectangle (axis cs:6,\yb); \end{pgfonlayer} -%\addplot[domain=3.7:7, fill=idlecolor, pattern=north east lines, draw=none] {1.5} \closedcycle; -%\addplot[domain=7.4:10, fill=idlecolor, pattern=north east lines, draw=none] {1.5} \closedcycle; -%% IDD5PB_B Background energy (yellow stripes) -%\addplot[domain=0:3.3, fill=backgroundcolor, pattern=north west lines, draw=none] {2.5} \closedcycle; -%\addplot[domain=3.7:7, fill=backgroundcolor, pattern=north west lines, draw=none] {2.5} \closedcycle; -%\addplot[domain=7.4:10, fill=backgroundcolor, pattern=north west lines, draw=none] {2.5} \closedcycle; -%% REFpb Foreground energy (blue stripes) -%\addplot[domain=1:2.3, fill=refcolor, pattern=north east lines, draw=none] {4.5} \closedcycle; -%\addplot[domain=4.7:6, fill=refcolor, pattern=north east lines, draw=none] {4.5} \closedcycle; -%\addplot[domain=7.7:9, fill=refcolor, pattern=north east lines, draw=none] {4.5} \closedcycle; -% Plot the current curve (in blue) -%\addplot[domain=0:10, samples=100, thick, blue] -% ({x}, {x < 1 || (x > 3 && x < 4.7) || x > 7.4 ? 2.5 : -% (x >= 1 && x <= 2.3) || (x >= 4.7 && x <= 6) || (x >= 7.7 && x <= 9) ? -% 4.5 : 1.5}) ; \addplot[thick] coordinates {(0,\ya) (1,\ya)}; \addplot[thick] coordinates {(1,\ya) (1,\yc)}; \addplot[thick] coordinates {(1,\yc) (2,\yc)}; @@ -67,21 +59,9 @@ \addplot[dashed] coordinates {(0,\ya) (6,\ya)}; % IDD2N \addplot[dashed] coordinates {(0,\yb) (6,\yb)}; % IDD5PB \addplot[dashed] coordinates {(0,\yc) (6,\yc)}; % IDD5PB_B -% Text Annotations -%\node[align=left] at (axis cs:9.8,5.8) {\textbf{IDD5B}}; -%\node[align=left] at (axis cs:9.8,4.3) {\textbf{IDD5A}}; -%%\node[align=left] at (axis cs:9.8,2.3) {\textbf{I\_0}}; -%\node[align=left] at (axis cs:9.8,1.3) {\textbf{IDD2N}}; % Labels for periods tRFCpb and tREFI8 -\draw[thick, {Latex}-{Latex}] (axis cs:1,5) -- (axis cs:2,5) node[midway,below] {$t_{RFC}$}; -%\draw[thick, {Latex}-{Latex}] (axis cs:4,5) -- (axis cs:5,5) node[midway,below] {$tRFC$}; -\draw[thick, {Latex}-{Latex}] (axis cs:1,4) -- (axis cs:4,4) node[midway,below] {$t_{REFI}$}; -%\draw[thick, <->] (axis cs:1,0.5) -- (axis cs:2.3,0.5) node[midway,below] {$tRFC_{pb}$}; -%\draw[thick, <->] (axis cs:0,0.5) -- (axis cs:3.3,0.5) node[midway,below] {$tREFI8$}; -%\draw[thick, <->] (axis cs:4.7,0.5) -- (axis cs:6,0.5) node[midway,below] {$tRFC_{pb}$}; -%\draw[thick, <->] (axis cs:3.7,0.5) -- (axis cs:7,0.5) node[midway,below] {$tREFI8$}; -%\draw[thick, <->] (axis cs:7.7,0.5) -- (axis cs:9,0.5) node[midway,below] {$tRFC_{pb}$}; -%\draw[thick, <->] (axis cs:7.4,0.5) -- (axis cs:10,0.5) node[midway,below] {$tREFI8$}; +\draw[thick, {Latex}-{Latex}] (axis cs:1,2.9) -- (axis cs:2,2.9) node[midway,below] {$t_{RFC}$}; +\draw[thick, {Latex}-{Latex}] (axis cs:1,2.1) -- (axis cs:4,2.1) node[midway,below] {$t_{REFI}$}; \end{axis} % Legend \begin{scope} @@ -92,8 +72,5 @@ \node[draw,pattern=north west lines, pattern color=blue!50] at (0.0,-1.5) {~}; \node[anchor=west] at (0.2,-1.5) {Average Refresh Energy}; \end{scope} -%\draw[pattern=north east lines, pattern color=red!50, draw=none] (axis cs:1,1) rectangle (axis cs:2,6); -%\draw[pattern=north east lines, pattern color=red!50, draw=none] (axis cs:4,1) rectangle (axis cs:5,6); -%\draw[pattern=north east lines, pattern color=green!50, draw=none] (axis cs:0,0) rectangle (axis cs:6,1); % \end{tikzpicture}% \ No newline at end of file diff --git a/drampower-main.tex b/main.tex similarity index 54% rename from drampower-main.tex rename to main.tex index f65769f..f078ea0 100644 --- a/drampower-main.tex +++ b/main.tex @@ -22,8 +22,8 @@ %% for your publication. %% %% -\documentclass[sigconf, anonymous, review, nonacm=true]{acmart} -%\documentclass[sigconf]{acmart} +%\documentclass[sigconf, anonymous, review, nonacm=true]{acmart} +\documentclass[sigconf]{acmart} %% %% \BibTeX command to typeset BibTeX logo in the docs @@ -31,45 +31,23 @@ \providecommand\BibTeX{{% Bib\TeX}}} - +%% Rights management information. This information is sent to you +%% when you complete the rights form. These commands have SAMPLE +%% values in them; it is your responsibility as an author to replace +%% the commands and values with those provided to you when you +%% complete the rights form. +\copyrightyear{2025} +\acmYear{2025} +\setcopyright{rightsretained} +\acmConference[RAPIDO '25]{Rapid Simulation and Performance Evaluation for Design}{January 21, 2025}{Barcelona, Spain} +\acmBooktitle{Rapid Simulation and Performance Evaluation for Design (RAPIDO '25), January 21, 2025, Barcelona, Spain} +\acmPrice{} +\acmDOI{10.1145/3721848.3721850} +\acmISBN{979-8-4007-1471-9/25/01} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %% Document Settings %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%\input{drampower-settings} -%% -%% Set the title of the paper here -\newcommand{\papertitle}{ - DRAMPower~5: An Open-Source Power Simulator for Current Generation DRAM Standards -} - -%% -%% Conference settings -%\copyrightyear{2025} -%\acmYear{2025} -%\setcopyright{acmlicensed}\acmConference[RAPIDO 2025]{Proceedings of the 2023 Workshop on System Engineering for constrained embedded systems}{January 17--18, 2023}{Toulouse, France} -%\acmBooktitle{Proceedings of the 2023 Workshop on System Engineering for constrained embedded systems (RAPIDO 2023), January 17--18, 2023, Toulouse, France} -%\acmPrice{15.00} -%\acmDOI{10.1145/3579170.3579259} -%\acmISBN{979-8-4007-0045-3/23/01} - -%% -%% Paper logo settings -\newcommand{\paperlogo}{ -\begin{teaserfigure} - \includegraphics[width=\textwidth]{figs/logo_drampower_5_0.png} - \caption{DRAMPower 5.0 Logo} - \Description{DRAMPower 5.0 Logo.} - \label{fig:logo} -\end{teaserfigure} -} - -%% -%% Keyword settings -\newcommand{\paperkeywords}{\keywords{ - DRAMPower, DRAM, power, simulation, interface -}} - \usepackage{subcaption} \usepackage{siunitx} \usepackage{tikz} @@ -128,20 +106,25 @@ \newcommand\todo[1]{\textcolor{red}{#1}} \hyphenation{pre-charged} \hyphenation{DRAMPower} +\hyphenation{DRAMSys} +\hyphenation{VAMPIRE} %\received{20 February 2007} %\received[revised]{12 March 2009} %\received[accepted]{5 June 2009} + + %% %% end of the preamble, start of the body of the document source. \begin{document} + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %% Header %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\title{\papertitle} +\title{DRAMPower~5: An Open-Source Power~Simulator for Current~Generation DRAM~Standards} %% %% The "author" command and its associated commands are used to define @@ -151,74 +134,108 @@ %% used to denote shared contribution to the research. \author{Lukas Steiner} -\email{lukas.steiner@rptu.de} -\orcid{0009-0009-3368-5396} +\orcid{0000-0003-2677-6475} \affiliation{% \institution{University of Kaiserslautern-Landau} \city{Kaiserslautern} \country{Germany} } +\email{lukas.steiner@rptu.de} \author{Thomas Psota} -\email{thomas.psota@iese.fraunhofer.de} \orcid{0009-0009-3368-5396} \affiliation{% \institution{Fraunhofer IESE} \city{Kaiserslautern} \country{Germany} } +\email{thomas.psota@iese.fraunhofer.de} \author{Marco Mörz} -\email{marco.moerz@iese.fraunhofer.de} \orcid{} \affiliation{% \institution{Fraunhofer IESE} \city{Kaiserslautern} \country{Germany} } +\email{marco.moerz@iese.fraunhofer.de} \author{Derek Christ} -\email{derek.christ@uni-wuerzburg.de} -\orcid{} +\orcid{0009-0005-4234-6362} \affiliation{% \institution{Julius-Maximilians-Universität} \city{Würzburg} \country{Germany} } +\email{derek.christ@uni-wuerzburg.de} \author{Matthias Jung} -\email{m.jung@uni-wuerzburg.de} \orcid{0000-0003-0036-2143} \affiliation{% \institution{Julius-Maximilians-Universität} \city{Würzburg} \country{Germany} } +\email{m.jung@uni-wuerzburg.de} \author{Norbert Wehn} -\email{norbert.wehn@rptu.de} \orcid{0000-0002-9010-086X} \affiliation{% \institution{University of Kaiserslautern-Landau} \city{Kaiserslautern} \country{Germany} } +\email{norbert.wehn@rptu.de} + +%% +%% By default, the full list of authors will be used in the page +%% headers. Often, this list is too long, and will overlap +%% other information printed in the page headers. This command allows +%% the author to define a more concise list +%% of authors' names for this purpose. +\renewcommand{\shortauthors}{Steiner et al.} %% %% The abstract is a short summary of the work to be presented in the %% article. \begin{abstract} -\todo{frequency vs. data rate} -As memory-intensive applications continue to drive demand for high DRAM bandwidth and capacity, accurately modeling the DRAM power consumption has become critical for optimizing system design and meeting power budgets. -Unfortunately, existing open-source DRAM power simulators only support older generations of DRAM standards, while current system designs mainly rely on the newest generation including DDR5, LPDDR5 or HBM3. -These standards support very high data rates beyond 10\,Gbps/pin -This paper presents DRAMPower 5, a revised version of the popular DRAMPower simulator, - - - -%DRAMPower 5 addresses this need by offering an open-source, detailed power analysis tool that now supports the latest JEDEC standards, including DDR5 and LPDDR5. This latest version introduces a refined interface power model, capturing specific interface dynamics that are increasingly relevant for emerging DRAM technologies, enhancing the accuracy of power estimations. Furthermore, DRAMPower 5 is designed with a flexible, modular architecture, enabling straightforward extensibility to support future DRAM standards and custom configurations. These features make DRAMPower 5 an essential tool for researchers and engineers focused on precise, scalable power analysis for current and next-generation DRAM systems. +As off-chip memory accesses nowadays dominate the overall power consumption of many compute platforms, accurate DRAM power simulation models are an important tool for system designers. +Unfortunately, existing open-source models only support older generations of DRAM standards, while current system designs mainly rely on the newest generation including DDR5, LPDDR5 or HBM3. +In addition, the existing models are not directly applicable to the new standards because of the much higher data rates and newly introduced features. +This paper presents DRAMPower~5, a completely revised version of the popular DRAMPower simulator, which uses newly developed core and interface power models to support the current generation of DRAM standards. +In addition, DRAMPower~5 features a redesigned software architecture that enables both fast and accurate simulation. +The tool is open source and available on GitHub. \end{abstract} -%\paperlogo + +%% +%% +\begin{CCSXML} + + + 10010583.10010662.10010674 + Hardware~Power estimation and optimization + 500 + + + 10010583.10010600.10010607.10010608 + Hardware~Dynamic memory + 500 + + + 10010147.10010341.10010342 + Computing methodologies~Model development and analysis + 300 + + +\end{CCSXML} + +\ccsdesc[500]{Hardware~Power estimation and optimization} +\ccsdesc[500]{Hardware~Dynamic memory} +\ccsdesc[300]{Computing methodologies~Model development and analysis} + +%% Keyword settings +\keywords{DRAMPower, DRAM, power, energy, simulation, interface} + \maketitle %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -233,80 +250,95 @@ This paper presents DRAMPower 5, a revised version of the popular DRAMPower simu \section{Introduction} % The recent expansion of memory-intensive applications has led to increased demand for DRAM bandwidth and capacity in current computing systems. -This demand is particularly pronounced in \textit{Artificial Intelligence} (AI) applications, where specialized accelerator chips with immense DRAM bandwidths beyond 1\,TBps are used. -However, these bandwidths come at the cost of high power consumption. -In datacenters very often around 90\,\% of the system power is consumed by memory~\cite{bou_24}. -Even in embedded augmented reality devices for the Metaverse, memory can account for more than 40\,\% of power consumption \cite{yankao_24}. -Therefore, an accurate estimation of DRAM power consumption is critical in the early stages of design in order to properly dimension the power supply circuits and cooling. -In mobile devices, on the other hand, the overall power budget is constrained to only a few watts. -Nevertheless, it is equally important to accurately estimate DRAM power consumption, for example to explore the power saving potential of new DRAM standards and their additional features to extend battery life.\cite{borgho_18} -In the current state of the art, there are two widely used open-source simulation tools for estimating DRAM power consumption, namely \textit{DRAMPower}~\cite{kargoo_14} and \textit{CACTI-IO}~\cite{joukah_12,joukah_15}. -DRAMPower focuses on the power consumption of the DRAM core, while CACTI-IO models the power consumption of the DRAM interface. -Unfortunately, both tools have not been updated in recent years, so they only provide support for older DRAM standards. -At the same time, current generation DRAM standards like DDR5, LPDDR5 and HBM3 operate at much higher data rates than their predecessors, use novel interconnection techniques, and offer many new features, which requires special consideration for power modeling. -To the best of our knowledge, there is no open-source DRAM power simulator that provides accurate models of both the DRAM core and interface, and supports current generation DRAM standards such as DDR5, LPDDR5 and HBM3. -To fill this gap, this paper presents DRAMPower 5, a completely revised version of the DRAMPower simulator, with a greatly enhanced feature set including both core and interface power modeling, an efficient simulation kernel, \todo{accuracy?} and support for the latest DRAM standards. +This demand is particularly pronounced in AI applications, where specialized accelerator chips with immense DRAM bandwidths beyond 1\,TBps are used. +On these platforms, memory dominates the total power consumption. +%However, these bandwidths come at the cost of high power consumption. +When training large AI models, it was found that up to \SI{90}{\percent} of the system power is consumed by memory accesses~\cite{bou_24}. +%Even in embedded augmented reality devices for the Metaverse, memory can account for more than 40\,\% of power consumption \cite{yankao_24}. +Therefore, an accurate estimation of DRAM power consumption is critical in the early stages of design to properly dimension the power supply circuits and cooling. +In consumer devices, on the other hand, it was also found that in average more than \SI{60}{\percent} of the total system power is spent on memory accesses~\cite{borgho_18}. +While the overall power budget for these devices is limited to only a few watts, it is equally important to accurately estimate the DRAM power consumption, for example, to explore the power saving potential of software improvements during system design. -This paper makes the following new contributions: +In the current state of the art, there are two widely used open-source simulation tools for estimating DRAM power consumption, namely \textit{DRAMPower}~\cite{kargoo_14} and \textit{CACTI-IO}~\cite{joukah_15}. +DRAMPower focuses on the DRAM core, while CACTI-IO models the DRAM interface. +Unfortunately, both tools only provide support for older standards. +At the same time, current generation standards like DDR5, LPDDR5 and HBM3 enable much higher interface speeds and offer new features, which requires special consideration for power modeling. +In addition, the standards are inconsistent in specifying operating currents, making it difficult to create a universal power model. +To the best of our knowledge, there is no open-source DRAM power simulator that provides accurate models of both the DRAM core and interface and supports the current generation of DRAM standards, including DDR5, LPDDR5 and HBM3. +To fill this gap, we introduce DRAMPower~5, a completely revised version of the DRAMPower simulator with more accurate power models, an improved software architecture, and support for the latest DRAM standards. + +In this paper, we make the following new contributions: \begin{itemize} - \item We present newly developed core and interface power models that are required to accurately capture current generation DRAM standards. - \item We explain how the inconsistent and incomplete operating current specifications provided in the DRAM standards need to be treated to model core power. - \item We show that at high operating frequencies, the approximations commonly used for interface power modeling result in large errors and a different modeling approach is required. - \item We present a new simulator architecture that can be easily extended by new standards or features and achieves high simulation speeds. - \item \todo{Accuracy simulations} - \item \todo{supported standards!!!} + \item We present a universal core power model that can handle the different operating current specifications of each standard. + \item We introduce a newly developed interface power model with improved accuracy at high operating frequencies. + \item We present the updated software architecture of the simulator and evaluate its simulation speed and accuracy. + %\item We present newly developed core and interface power models that are required to accurately capture current generation DRAM standards. + %\item We explain how the inconsistent and incomplete operating current specifications provided in the DRAM standards need to be treated to model core power. + %\item We show that at high operating frequencies, the approximations commonly used for interface power modeling result in large errors and a different modeling approach is required. + %\item We present a new simulator architecture that can be easily extended by new standards or features and achieves high simulation speeds. + %\item \todo{Accuracy simulations} + %\item \todo{supported standards!!!} \end{itemize} - -The rest of the paper is structured as follows \todo{...} - -%\input{content/02_related_works} -\section{Related Work} -In this section we provide an overview of the related work. -A well-known and often used DRAM power model is the System Power Calculator by Micron~\cite{micron_ddr3_11_kopie_ipsj}. -It is provided in the form of spreadsheets for various JEDEC standards including DDR/2/3/4 and LPDDR2/3/4/4X. -The power estimation is based on data sheet currents and timings for a specific DRAM device and workload specifications like the read-write-ratio or time that the DRAM is in each state. +% +The remainder of the paper is structured as follows. +Section~\ref{sec:related} discusses related work on DRAM power modeling. +Section~\ref{sec:background} provides the reader with the necessary background on DRAM. +In Section~\ref{sec:core_power_modeling}, the core power modeling is explained, while Section~\ref{sec:interface_power_modeling} addresses the interface power modeling. +Section~\ref{sec:simulator} provides a short overview of the new simulator. +Finally, Section~\ref{sec:conclusion} concludes the paper and gives an outlook on future work. +% +% +\section{Related Work}\label{sec:related} +% +In this section, we provide an overview of related work. +An often used DRAM power model is the System Power Calculator by Micron~\cite{micron_ddr3_11_kopie_ipsj}. +It is provided in the form of spreadsheets for various JEDEC standards. % (DDR/2/3/4, LPDDR2/3/4/4X). +%The power estimation is based on datasheet currents and timings for a specific DRAM device and workload specifications like the read/write ratio and time that the DRAM is in each state. +The power estimation is based on DRAM timing and current datasheet values and workload specifications like the read/write ratio. However, this modeling approach can only achieve a limited accuracy because the actual command trace that is issued to the DRAM by the memory controller is not considered. In addition, there exist no spreadsheets for current generation standards. -%However, this model is not accurate enough, as it assumes only certain workload characteristics and it is not looking on the actual executed application. There are further limitations in that model: Micron uses the minimal timing constrains from the datasheet specifications instead of the actual timings. -%But in practice there are dependencies between consecutive memory accesses so that the controller may accelerate or postpone commands. Furthermore, Micron assumes that the controller uses a close-page policy (precharge after each memory access) and that there is only one bank open at the same time. Due to this, a large lack of flexibility and accuracy exists in this model. -% -A more accurate simulation tool is DRAMPower~\cite{kargoo_14} , which also relies on data sheet values, but in addition uses a real DRAM command trace as input to model the internal state transitions with cycle accuracy. -However, the internal DRAM states are simplified and the power dependence on the number of active DRAM banks is not considered. -Thus, DRAMPower was enhanced with a bank-sensitive model in~\cite{junmat_16b,matzul_17} to improve its accuracy. +A more accurate simulation tool is DRAMPower~\cite{kargoo_14}, which also relies on datasheet values, but in addition uses a real DRAM command trace as input to model the internal state transitions with cycle accuracy. +%Since the internal DRAM states were initially simplified and the power dependence on the number of active DRAM banks was not taken into account, DRAMPower was later extended by a bank-sensitive model in~\cite{junmat_16b,matzul_17} to improve its accuracy. +Since initially the power dependence on the number of active DRAM banks was not taken into account, DRAMPower was later extended with a bank-sensitive model~\cite{junmat_16b,matzul_17} to improve its accuracy. Still, the tool has two drawbacks: it only models core power, but no interface power, and it has not been updated to the latest standards yet. -Another simulation tools similar to DRAMPower is VAMPIRE~\cite{ghoyag_18}. +Another simulator similar to DRAMPower is VAMPIRE~\cite{ghoyag_18}. This tool puts its focus on the power variations between different DRAM modules, within one DRAM module depending on the access location, and the data value dependency. VAMPIRE is calibrated with measurements of real DRAM modules and provides very accurate results. -However, this presupposes that real measurements are available for the devices to be used, which is not usually the case in the early stages of design. VAMPIRE also supports DDR3 only. -% -There exists an analytical DRAM core-power model by Vogelsang~\cite{vog_10}. This model reflects a DDR memory but is also used to extrapolate future memory power consumption behavior. -When it comes to DRAM interface power modeling, the most popular software is CACTI-IO~\cite{joukah_12,joukah_15}. -CACTI-IO does not rely on data sheet currents, but it uses an equivalent circuit diagram of the DRAM subsystem's real interface architecture as this architecture is not fixed for a specific device. -The power consumption is then calculated using a simplified network analysis. -While this approach leads to accurate results for older generation DRAM standards, the error introduced by the simplifications is significantly higher for current generation standards as they support much higher data rates. +However, this presupposes that real measurements are available for the devices to be used, which is not usually the case in the early stages of design. +Additionally, VAMPIRE supports DDR3 only. +In~\cite{vog_10}, an analytical DRAM core power model is presented. +It approximates the power consumption based on the internal device architecture and technology and can also be extrapolated to future technologies. +Since the model was already developed 15 years ago, it is not clear whether an extrapolation to current technologies will still provide accurate results. +%When it comes to DRAM interface power modeling, the most popular software is CACTI-IO~\cite{joukah_12,joukah_15}. +The most popular tool for DRAM interface power modeling is CACTI-IO~\cite{joukah_15}. +CACTI-IO does not rely on datasheet currents, but it uses an equivalent circuit diagram of the interface between DRAM controller and devices. +The power consumption is then calculated with a simplified network analysis. +While the results are accurate for older generation standards, the simplifications introduce a large error for current generation standards as they support higher data rates. In summary, there is no publicly available DRAM power simulation tool capable of modeling both core and interface power of current generation DRAM standards with high accuracy. -%\input{content/03_overview} -\section{DRAM Background} % -This section provides the necessary background on the DRAM core and interface that is relevant for power modeling. -It also briefly introduces the different families of DRAM standards and explains their main differences. +% +\section{DRAM Background}\label{sec:background} +% +This section provides the necessary background on the DRAM core and interface relevant to power modeling. +It also briefly introduces the different families of DRAM standards and explains their key differences. % \subsection{Core} % -DRAM is a type of memory mainly optimized for a low cost per bit. -To achieve a high storage density, the chips are internally organized in a hierarchical fashion consisting of columns, rows, banks and for newer standards bank groups. -When data should be read or written from or to a column, the corresponding row must be activated first. -Within each bank, only one row can be active at a time and the bank must be precharged before a new row can be activated. -Data is transferred over the interface in a burst fashion, i.e. for a read operation, a large amount of data is fetched internally in parallel from the array to the interface, which is then transferred to the memory controller in multiple beats (usually 8 or 16). +DRAM is a type of memory primarily optimized for low cost per bit. +To achieve high memory density, the chips are internally organized in a hierarchical fashion consisting of \textit{columns}, \textit{rows}, \textit{banks} and, for newer standards, \textit{bank groups}. +When data should be read or written from or to a column, the corresponding row must be \textit{activated} first. +Within each bank, only one row can be active at a time and the bank must be \textit{precharged} before a new row can be activated. +Data is transferred over the interface in a burst fashion, i.e., for a read operation, a large amount of data is first fetched internally in parallel from the array to the interface, before it is transferred to the memory controller in multiple beats. Information is stored as an electrical charge held in a tiny capacitor. -As the capacitor leaks this charge over time, each DRAM cell must be refreshed regularly (usually every 32 to 64\,ms). +As the capacitor leaks this charge over time, each DRAM cell must be \textit{refreshed} regularly (usually every 32 to \SI{64}{\milli\second}). The refresh operation is triggered externally by the memory controller with a refresh command. During refresh, no data can be accessed within the target bank(s). Thus, only a few rows are refreshed each time to avoid long access delays and a refresh command is sent every few microseconds. -To save energy, DRAM devices can be put into a power down mode when no data accesses are performed. +To save energy, DRAM devices can be put into a \textit{power-down} mode when no data accesses are performed. This disables parts of the core and interface. -However, in order to perform refreshes for data retention, it is necessary to interrupt the power down mode periodically. -To avoid this, the self refresh mode can be entered where data retention is managed by the device itself and no refresh commands need to be provided by the memory controller. +%However, in order to perform refreshes for data retention, it is necessary to interrupt the power-down mode periodically. +However, the power-down mode must be interrupted periodically to perform refreshes. +To avoid this, the \textit{self refresh} mode can be entered where data retention is managed by the device itself and no refresh commands need to be provided by the memory controller.% any more. % \subsection{Interface}\label{subsec:background_interface} % @@ -315,21 +347,22 @@ To sample the data at the correct time, a differential \textit{data strobe} pair Since data is sampled both at the rising and the falling edge of the data strobe (intersection of DQS\_t and DQS\_c), the bus operates at \textit{double data rate} (DDR). Commands and addresses are transferred from the memory controller to the DRAM devices over a unidirectional \textit{command/address bus} (CA). They are sampled on the edges of a differential clock signal pair (CK\_t/CK\_c) that is also driven by the memory controller. -Depending on the standard, the command/address bus is either operated at \textit{single data rate} (SDR) or double data rate. -In addition, the transfer of a single command can take one or multiple clock cycles depending on the standard because the width of the command/address bus varies. -Since all modern DRAM standard operate at frequencies in the gigahertz range with data rates reaching up to 10\,Gbps/pin, termination at the receiver side is required to ensure signal integrity. +%Depending on the standard, the command/address bus is either operated at \textit{single data rate} (SDR) or double data rate. +%In addition, the transfer of a single command can take one or multiple clock cycles depending on the standard because the width of the command/address bus varies. +Since all modern DRAM standards operate at frequencies in the gigahertz range with data rates reaching more than 8\,Gbps/pin, the signals are terminated at the receiver side to ensure their integrity. % -To increase the memory capacity, multiple DRAM devices can be connected to the same memory controller, sharing the command/address as well as data bus (so-called ranks). -Each target device can be selected using a dedicated \textit{chip select} signal (CS). -The physical (inter)connection between memory controller and DRAM can be realized in different ways, e.g., through a classical printed circuit board (PCB), a package on package (PoP) arrangement or a silicon interposer. +To increase the memory capacity of a DRAM channel, multiple devices can be connected to the same memory controller, sharing the command/address and data bus (so-called ranks). +The target device is selected by the controller via a \textit{chip select} signal (CS). +The physical interconnect between memory controller and DRAM can be realized in different ways, e.g., through a classical \textit{printed circuit board} (PCB), a \textit{package on package} (PoP) arrangement or a silicon interposer. All these channels have different characteristics in terms of load capacitances, reflections and loss, so they need to be modeled individually for an accurate power estimation. -One connection type widely used in PCs and servers is the dual inline memory module (DIMM). +One special interconnection type widely used in PCs and servers is the \textit{dual inline memory module} (DIMM). Multiple DRAM chips are soldered onto a small PCB with pins on the bottom edge, which is then plugged into a socket on the main PCB. -DIMMs require special considerations for power modeling as there are different wiring topologies, off-die termination schemes and in some cases additional buffer chips for the command/address bus and data bus. +DIMMs require extra considerations for power modeling as there are different wiring topologies, off-die termination, and in some cases additional buffer chips for the command/address bus and data bus. +Due to space limitations, this is not discussed in detail in this paper. % \subsection{DRAM Standards} % -\todo{Special features see Luizas Master Thesis, e.g., DBI, write X, new refresh modes etc.} +%\todo{Special features see Luizas Master Thesis, e.g., DBI, write X, new refresh modes etc.} Over the last quarter century, JEDEC has published more than 20 different DRAM standards. As DRAM application fields become more heterogeneous, so do the standards. Currently, there are four major families: @@ -340,54 +373,58 @@ Currently, there are four major families: \item \textit{High Bandwidth Memory (HBM)} provides even higher bandwidths than GDDR by utilizing a much wider data bus and a silicon interposer for connection. It is mainly used in high-performance GPUs and ASICs. \end{itemize} % -While the DRAM core is structured similarly for all the standards, the interfacing between memory controller and DRAM differs greatly. -These differences reach from the pin count over the termination scheme and signaling voltage to the clocking architecture. -In addition, newer standards add additional commands for an optimized performance and power consumption. -\todo{In this first release of the revised version of DRAMPower, we focus on the DDR and LPDDR families, more specifically on DDR3/4/5 and LPDDR4/4X/5/5X. -GDDR and HBM will be added in a future release.} -Figure~\ref{tab:standards} provides an overview of the most important features and characteristics of each standard. - - -Interface depends on controller and devices -> not fixed for one device - - -% -DDR3: push pull termination DQ -DDR4: pseudo open drain logic (PODL) DQ, DBI, -LPDDR4: low voltage swing termination logic (LVSTL) -HBM: active inductor, doubled current (Active-Inductive CTLE continuous-time linear equalizer) - -Input/output capacitance is specified in standard - -%\begin{table*} -% \centering -% \caption{Feature Overview of JEDEC Standards} -% \label{tab:standards} -% \begin{tabular}{c|c|c|c} -% Standard & Termination & Operating Voltages & Special Features\\ -% DDR3 & SSTL & 1.5/1.5 & \\ -% DDR4 & PODL & 2.5/1.2/1.2 & Data Bus Inversion\\ -% DDR5 & PODL & 1.8/1.1/1.1 & Write Pattern, Command \& Address Inversion\\ -% LPDDR4 & LVSTL & 1.8/1.1/1.1\\ -% LPDDR4X & LVSTL & 1.8/1.1/0.6\\ -% LPDDR5 & LVSTL & 1.8/1.05/0.5 & Write Clock\\ -% \end{tabular} -%\end{table*} - -DIMM Features: -DDR3 UDIMM: Fly-By topology except for DQ/DM and DQS, Push-Pull Termination CK\_t, CK\_c, CTRL (S0\_n, ODT0, CKE0), CMD, Series resistor Rs for DQ/DM and DQS\_t/DQS\_c, other DIMMs: LRDIMM, RDIMM, SODIMM... -DDR4 UDIMM: Fly-By topology except for DQ/DM and DQS, Push-Pull Termination ... -DDR5 UDIMM: Fly-By , other DIMMs: LRDIMM, RDIMM, SODIMM, CUDIMM (clocked unbuffered)... +The DRAM core architecture is similar across all standards and has not changed much over the years. +Newer standards usually come with higher memory capacities, a slightly reduced core supply voltage and some new commands to improve the performance or power efficiency. +An example of this is the different refresh modes, which will be explained in more detail in Section~\ref{subsec:refresh}. +However, the interface between memory controller and devices differs greatly from standard to standard. +These differences include pin data rate, pin count, termination scheme, channel loss characteristics, signaling voltage and clocking architecture. +In order to achieve an accurate interface power modeling, all these differences need to be considered in the calculations. +More details are provided in Section~\ref{sec:interface_power_modeling}. +%\todo{In this first release of the revised version of DRAMPower, we focus on the DDR and LPDDR families, more specifically on DDR3/4/5 and LPDDR4/4X/5/5X. +%GDDR and HBM will be added in a future release.} +%Figure~\ref{tab:standards} provides an overview of the most important features and characteristics of each standard. % % -\section{Core Power Modeling} +%Interface depends on controller and devices -> not fixed for one device +% +% +%% +%DDR3: push pull termination DQ +%DDR4: pseudo open drain logic (PODL) DQ, DBI, +%LPDDR4: low voltage swing termination logic (LVSTL) +%HBM: active inductor, doubled current (Active-Inductive CTLE continuous-time linear equalizer) +% +%Input/output capacitance is specified in standard +% +%%\begin{table*} +%% \centering +%% \caption{Feature Overview of JEDEC Standards} +%% \label{tab:standards} +%% \begin{tabular}{c|c|c|c} +%% Standard & Termination & Operating Voltages & Special Features\\ +%% DDR3 & SSTL & 1.5/1.5 & \\ +%% DDR4 & PODL & 2.5/1.2/1.2 & Data Bus Inversion\\ +%% DDR5 & PODL & 1.8/1.1/1.1 & Write Pattern, Command \& Address Inversion\\ +%% LPDDR4 & LVSTL & 1.8/1.1/1.1\\ +%% LPDDR4X & LVSTL & 1.8/1.1/0.6\\ +%% LPDDR5 & LVSTL & 1.8/1.05/0.5 & Write Clock\\ +%% \end{tabular} +%%\end{table*} +% +%DIMM Features: +%DDR3 UDIMM: Fly-By topology except for DQ/DM and DQS, Push-Pull Termination CK\_t, CK\_c, CTRL (S0\_n, ODT0, CKE0), CMD, Series resistor Rs for DQ/DM and DQS\_t/DQS\_c, other DIMMs: LRDIMM, RDIMM, SODIMM... +%DDR4 UDIMM: Fly-By topology except for DQ/DM and DQS, Push-Pull Termination ... +%DDR5 UDIMM: Fly-By , other DIMMs: LRDIMM, RDIMM, SODIMM, CUDIMM (clocked unbuffered)... +% +% +\section{Core Power Modeling}\label{sec:core_power_modeling} % This section explains the modeling of core power, while the modeling of interface power is covered in the next section. -Core and interface can be considered completely independent of each other because they always use different supply voltages. +Core and interface can be considered completely independent of each other because they use different supply voltages. Core power refers to the power consumed by the internal circuitry of the DRAM device, i.e., the memory arrays, sense amplifiers, row and column decoders, I/O gating and control logic. The receiver circuits at the interface are also operated with the core supply voltage and are therefore included in the core power. -As the internal architecture of modern DRAM devices is very complex and highly proprietary, core power calculation cannot be based on network analysis. -However, each DRAM standard defines a set of currents for fixed operating scenarios, which are listed in vendor datasheets. +As the internal architecture of modern DRAM devices is very complex and highly proprietary, core power calculation cannot be based on classical network analysis. +Thus, each DRAM standard defines a set of currents for fixed operating scenarios, which are listed in vendor datasheets. Based on these currents, the core power can be estimated. %%%% %%%% @@ -398,61 +435,65 @@ The following section provides an overview of these currents. The minimum set specified in all DRAM standards includes the following nine currents: % \begin{itemize} - \item $I_{DD0}$ (Operating one bank active-precharge current): Activate and precharge commands are sent alternately with minimum spacing. The target bank is toggled with each activate command. + \item $I_{DD0}$ (Operating one bank active-precharge current): Activate and precharge commands are sent alternately with minimum spacing.% The target bank is toggled with each activate command. \item $I_{DD2N}$ (Precharge standby current): All banks are precharged and no commands are issued. \item $I_{DD2P}$ (Precharge power-down current): All banks are precharged, no commands are issued and the device is in power-down mode. \item $I_{DD3N}$ (Active standby current): All banks are active and no commands are issued. \item $I_{DD3P}$ (Active power-down current): All banks are active, no commands are issued and the device is in power-down mode. - \item $I_{DD4R}$ (Operating burst read current): All banks are active and read commands are issued with minimum spacing. The target bank is toggled with each read command. - \item $I_{DD4W}$ (Operating burst write current): All banks are active and write commands are issued with minimum spacing. The target bank is toggled with each write command. + \item $I_{DD4R}$ (Operating burst read current): All banks are active and read commands are issued with minimum spacing.% The target bank is toggled with each read command. + \item $I_{DD4W}$ (Operating burst write current): All banks are active and write commands are issued with minimum spacing.% The target bank is toggled with each write command. \item $I_{DD5B}$ (Burst refresh current): Refresh commands are issued with minimum spacing. - \item $I_{DD6}$ (Self refresh current): The device is in self-refresh operation and the external clock is turned off. + \item $I_{DD6}$ (Self refresh current): The device is in self refresh mode and the external clock is turned off. \end{itemize} % Unfortunately, the different JEDEC subcommittees, which are responsible for formulating DRAM standards, are very inconsistent in specifying the currents. -Apart from different naming schemes\footnote{To avoid confusion, we use our own naming scheme, which is a mixture of several standards.}, the measurement conditions mentioned above only apply for standards of the DDR family, while they differ for LPDDR, GDDR and HBM. +%Apart from different naming schemes\footnote{To avoid confusion, we use our own naming scheme, which is a mixture of several standards.}, the measurement conditions mentioned above only apply for standards of the DDR family, while they differ for LPDDR, GDDR and HBM. +Apart from different naming schemes, the measurement conditions mentioned above only apply for standards of the DDR family, while they differ for LPDDR, GDDR and HBM. For example, LPDDR measures $I_{DD3N}$, $I_{DD3P}$, $I_{DD4R}$ and $I_{DD4W}$ with only one bank active. GDDR measures $I_{DD3N}$ and $I_{DD3P}$ with one bank active, while $I_{DD4R}$ and $I_{DD4W}$ are measured with one bank in each bank group active. HBM, in turn, measures $I_{DD3N}$ and $I_{DD3P}$ with one bank active and $I_{DD4R}$ as well as $I_{DD4W}$ with all banks active. Section~\ref{subsec:bankwise} explains how these different measurement conditions are treated to achieve a universal bank-sensitive power model. -Similarly, the refresh currents are also measured under various conditions. +Similarly, the refresh currents are also measured under varying conditions. While DDR standards specify a burst refresh current $I_{DD5B}$ for all available refresh modes, LPDDR standards specify a burst refresh current only for all-bank refresh, while for per-bank refresh, an average current $I_{DD5A}$ is provided. The difference between $I_{DD5B}$ and $I_{DD5A}$ is the spacing between two consecutive refresh commands. -It is the refresh cycle time $t_{RFC}$ (i.e., the duration of a single refresh operation) for $I_{DD5B}$ and the much longer average refresh interval $t_{REFI}$ (i.e., the interval at which refresh commands need to be issued in normal operation) for $I_{DD5A}$. +It is the refresh cycle time $t_{RFC}$ (i.e., the duration of a single refresh operation) for $I_{DD5B}$ and the much longer average refresh interval $t_{REFI}$ (i.e., the interval at which refresh commands need to be issued in normal operation) for $I_{DD5A}$ as shown in Figure~\ref{fig:refresh_currents}. %GDDR5/5X/6 and HBM1/2 do not specify a current for per-bank refresh at all although they support it. -Section~\ref{subsec:refresh} shows how refresh power can be modeled using the provided currents of each standard. -Even if all missing currents are calculated, the used approach for core power calculation still faces two problems, which have been highlighted in~\cite{ghoyag_18}. -First, the device-to-device variations are very large, which forces the vendors to be very pessimistic when specifying operating currents. +Section~\ref{subsec:refresh} explains how refresh power can be modeled using the provided currents of each standard. +However, even if all missing currents can be calculated, the used approach for core power calculation still faces two problems, which have also been highlighted in~\cite{ghoyag_18}. +First, there are large device-to-device variations, which forces the vendors to be very pessimistic when specifying operating currents. As a consequence, power is overestimated in most cases. Second, the currents are measured for fixed data and address patterns, i.e., no data dependencies and structural variations within the device are considered. If a more accurate modeling is required, the calculations have to be refined with additional device measurements. -\todo{last subsection? extra features, maybe future work?} -\todo{multiple supply voltages!} - +This will be demonstrated in Section~\ref{subsec:sim_accuracy}. +%\todo{last subsection? extra features, maybe future work?} +%\todo{multiple supply voltages!} +% \subsection{Universal Bank-Sensitive Model}\label{subsec:bankwise} % The DRAM core power is composed of background power and command power. A bank-sensitive model is used for the background power, i.e. the more banks are active, the higher the power consumption. -This model was already introduced in previous versions of the tool~\cite{junmat_16b,matzul_17} and provides higher accuracy compared to a model that only distinguishes between two states (either active or precharged) like the Micron system power calculator~\cite{micron_ddr3_11_kopie_ipsj}. +This model was already introduced in previous versions of the tool~\cite{junmat_16b,matzul_17} and provides higher accuracy compared to a model that only distinguishes between two states (either active or precharged) like the one from Micron~\cite{micron_ddr3_11_kopie_ipsj}. As shown in Figure~\ref{fig:bank_sensitive_currents} for a DRAM of the DDR family with $B$ banks, $I_{DD2N}$ is drawn when all banks are precharged and $I_{DD3N}$ is drawn when all $B$ banks are active. The span in between is not divided linearly depending on the number of active banks, but there is an offset when activating the first bank. This is due to the fact that additional logic must be switched on when the first bank is activated. % \begin{figure} \centering + \resizebox{.9\linewidth}{!}{% \input{img/bankwise_current} + } \caption{Bank-Sensitive Currents~\cite{junmat_16b}} \label{fig:bank_sensitive_currents} \end{figure} % $\rho$ is a vendor- and device-specific factor between 0 and 1, which can be determined by measurement~\cite{junmat_16b}. -Alternatively, the pessimistic assumption of $\rho = 1$ can be made, which leads to the simplified model with only two distinct states as used by Micron~\cite{micron_ddr3_11_kopie_ipsj}. +Alternatively, the pessimistic assumption of $\rho = 1$ can be made, which leads to the simplified model with only two distinct states. For standards of the DDR family, it is $I_{DD3N} = I_{\circled{B}}$, while for LPDDR, GDDR and HBM, it is $I_{DD3N} = I_{\circled{1}}$. This difference must be taken into account when calculating the background power. -If the current $I_{DD2N}$, the factor $\rho$, a current $I_{DD3N}$ measured with N banks active, and the total number of banks $B$ is given, all other currents can be calculated. +If the current $I_{DD2N}$, the factor $\rho$, a current $I_{DD3N}$ measured with M banks active, and the total number of banks $B$ is given, all other currents can be calculated. It is \begin{equation} - I_{\circled{N}} = I_{DD2N} + (I_{\circled{B}} - I_{DD2N}) \cdot \left(\rho + (1-\rho)\cdot \frac{N}{B}\right) + I_{\circled{M}} = I_{DD2N} + (I_{\circled{B}} - I_{DD2N}) \cdot \left(\rho + (1-\rho)\cdot \frac{M}{B}\right). \end{equation} When the DRAM is in power-down mode, the dependence of the current on the number of active banks is much smaller, so we only distinguish between two states characterized by $I_{DD2P}$ and $I_{DD3P}$. @@ -468,52 +509,9 @@ However, this equation only works if $I_{DD4R}$ and $I_{DD3N}$ are measured with Thus, the equations need to be adapted accordingly, i.e., for GDDR, $I_{DD3N}$ must be replaced with $I_{\circled{BG}}$ with $BG$ being the number of bank groups, while for HBM, $I_{DD3N}$ must be replaced with $I_{\circled{B}}$. % % -%\subsection{Current Measurement Conditions} -%% -%All JEDEC standards specify multiple currents for different operating scenarios. -%Using the provided values of vendor datasheets, the power consumption of the devices can be estimated. -%However, JEDEC is very inconsistent with the current measurement conditions, meaning that the same current can describe different operating scenarios depending on the standard. -%For example, the active standby current IDD3N is measured with all banks active for DDR standards, while it is measured with only a single bank active for LPDDR standards. -%Similarly, for IDD4R and IDD4W, all banks are active for DDR, while only a single bank is active for LPDDR. -%This has to be taken into account... -% -% -% -%All modern JEDEC standards specify at least three supply voltages. -%Most standards denote them as VDD, VPP and VDDQ, while LPDDR standards use VDD1, VDD2 and VDDQ. -%VDD/VDD1: main supply voltage -%VPP/VDD2: pump voltage/wordline boost/activation -%VDDQ: supply voltage for output drivers (DQ, DQS\_t, DQS\_c) -% -%The currents specified by the JEDEC standards are provided separately for each supply voltage in the datasheets. -%Most important currents exemplarily for VDD specified in table -%\begin{table} -%\caption{} -%\label{tab:configs} -%\centering -%\resizebox{\linewidth}{!}{% -%\input{img/currents_table} -%} -%\end{table} -%, which is responsible for performing the core memory operations. -%, i.e., storing data in the memory array that was received on the interface, transferring like reading, writing, refreshing, and storing data. -%% -%Components: -%Memory array operations: Power consumed during data access, including charging and discharging the DRAM cells when data is read from or written to them. -%Refresh operations: DRAM cells need to be refreshed periodically to retain their data, and this refresh process consumes core power. -%Row and column decoders: These circuits select which rows and columns in the memory array are accessed during a read or write operation. -%Sense amplifiers: These are used to detect the small charge differences in the memory cells when reading data, and they also contribute to core power consumption. -%Key Characteristics: -%Dependent on the internal operations and how frequently the memory is accessed or refreshed. -%Affected by DRAM timing parameters (like tRCD, tRAS, etc.) and the DRAM's operational state (active vs idle). -% -%Core power is hard to calculate based on physical equations/properties because the DRAM vendors do not publish any information about the internal structure of the DRAM devices. -%However, the vendors publish data sheets of their devices with measured currents for specific operations (see Section current measurement conditions). -%Although these measurements are very pessimistic, they can be used as a rough estimate for core power calculations, can also be refined with own measurements of devices. -% \subsection{Refresh Power}\label{subsec:refresh} % -Depending on the DRAM standard, various refresh modes are offered. +Depending on the DRAM standard, various refresh modes are supported. They differ in the number of banks that are refreshed with a single command. All-bank refresh commands target all banks of the device at once. As no data can be accessed in banks where a refresh is in progress, this mode can cause a large drop in bandwidth. @@ -521,130 +519,24 @@ Thus, newer DRAM standards offer improved refresh modes where only a single bank The duration of a single refresh command is the refresh cycle time $t_{RFC}$, which is also the spacing of refresh commands when measuring the burst refresh current $I_{DD5B}$. Thus, when a burst refresh current is provided, the energy for a single refresh command $E_{REF}$ can be calculated as \begin{equation} - E_{REF} = V_{DD} \cdot \left(I_{DD5B} - I_{\circled{N}}\right) \cdot t_{RFC} + E_{REF} = V_{DD} \cdot \left(I_{DD5B} - I_{\circled{M}}\right) \cdot t_{RFC} \end{equation} -where $N$ is the number of refreshed banks. -As the equation shows, banks with a refresh in progress are considered active, which the most accurate way of modeling because internally the refresh is performed by successively activating multiple rows within each target bank. +where $M$ is the number of refreshed banks. +As the equation shows, banks with a refresh in progress are considered active, which is the most accurate way of modeling because internally the refresh is performed by successively activating multiple rows within each target bank. In the cases where only an average refresh current $I_{DD5A}$ is provided, an approximated value for $I_{DD5B}$ can be determined. -Figure demonstrates the relation between both refresh currents graphically, where the dashed boxes represent the energy that is consumed. -The voltage is neglected because it is constant. +Figure~\ref{fig:refresh_currents} demonstrates the relation between both refresh currents graphically, where the dashed boxes represent the energy that is consumed. +The voltage is constant and can be neglected. % \begin{figure} \centering - \resizebox{\linewidth}{!}{% + \resizebox{.85\linewidth}{!}{% \input{img/refresh_currents} } - \caption{Relation between Refresh Currents} + \caption{Relation between Burst Refresh Current and Average Refresh Current} \label{fig:refresh_currents} \end{figure} % -From the definitions of the two currents, we know that burst refresh energy and the average refresh energy within one refresh interval $t_{REFI}$ are identical. -This relationship can be translated into the following equation to calculate $I_{DD5B}$ from $I_{DD5A}$: -\begin{equation} - I_{DD5B} = I_{DD2N} + \left(I_{DD5A} - I_{DD2N}\right) \cdot \frac{t_{REFI}}{t_{RFC}} -\end{equation} -% -%The equation can be used to calculate the burst refresh current of different refresh modes by substituting the average refresh current $I_{DD5A}$, refresh interval $t_{REFI}$ and refresh cycle time $t_{RFC}$ with the appropriate values. -%During refresh, the device is considered in active state because internally the banks are constantly activated and refreshed. -%The energy for an all-bank refresh command can be calculated as -%\begin{equation} -% E_{REFab} = V_{DD} \cdot \left(I_{DD5Bab} - I_{DD3N}\right) \cdot t_{RFCab} -%\end{equation} -%When per-bank refresh is used, only a single bank is refreshed at a time. -%Thus, only a single bank is considered active and the equation changes to -%\begin{equation} -% E_{REFpb} = V_{DD} \cdot \left(I_{DD5Bpb} - I_{\circled{1}}\right) \cdot t_{RFCpb} -%\end{equation} -%% -%Same-bank refresh for device with \textit{BG} bank groups and \textit{BA} banks per bank group -%\begin{equation} -% E_{REFpb} = V_{DD} \cdot \left(I_{DD5Bsb} - I_{\circled{BG}}\right) \cdot t_{RFCsb} -%\end{equation} -% -% -\section{Interface Power Modeling}\label{sec:interface_power_modeling} -% -Interface power refers to the power consumed by the drivers for the communication between memory controller and DRAM devices. -In contrast to the core power, which is fixed for a specific device, the interface power depends on the complete DRAM subsystem architecture, i.e., the physical layer (PHY) of the memory controller, the channel architecture (number of ranks, possible usage of DIMMs, etc.) , the channel characteristics (e.g., channel loss and parasitic capacitances) and the DRAM PHYs. -Thus, a modeling based on the operating currents specified in vendor datasheets is not possible as they are only measured for one specific subsystem architecture. -Instead, we calculate the interface power based on an equivalent circuit diagram of the real interface architecture as is also done by CACTI-IO. -Interface power can be divided into \textit{termination power}, which is dissipated across the termination resistances required for signal integrity, and \textit{dynamic power}, which is dissipated through the lossy charging and discharging of parasitic capacitances and the signaling over a lossy transmission line. -In the following two sections, the calculation of termination power and dynamic power is explained. -% -\subsection{Termination Power} -% -%%%% -%\begin{figure} -% \centering -% \begin{circuitikz} -% \ctikzset{bipoles/resistor/height=0.15} -% \ctikzset{bipoles/resistor/width=0.4} -% %\ctikzset{bipoles/tline/width=0.6} -% \draw (0,0) node[ieeestd buffer port, anchor=in](driver){}; -% \draw (driver.in) to[short, -o] ++(0,0); -% \draw (driver.up) -- ++(0,1) node[tground](VDDQ){$V_{DDQ}$}; -% \draw (driver.down) -- ++(0,-1) node[tlground](VSSQ){$V_{SSQ}$}; -% \draw (driver.bout) to[tline=$Z_0$, bipoles/tline/width=1, -*] ++(3,0) coordinate(TL); -% \draw (TL) to[R, a=$2R_{TT}$] (TL|-VDDQ) node[tground]{$V_{DDQ}$}; -% \draw (TL) to[R=$2R_{TT}$] (TL|-VSSQ) node[tlground]{}; -% \end{circuitikz} -% \caption{Low Voltage Swing Terminated Logic (LVSTL) Interface} -% \label{fig:term_push_pull} -%\end{figure} -%%%%% -%\begin{figure} -% \centering -% \begin{circuitikz} -% \ctikzset{bipoles/resistor/height=0.15} -% \ctikzset{bipoles/resistor/width=0.4} -% \draw (0,0) node[tground](VDDQ){} to[R=$R_{ON}$] ++(0,-1.5) to[short=$"1"$] ++(3,0) to[R=$R_{TT}$] ++(0,-1.5) node[tground](VDDQ2){}; -% \node[anchor=south] at (VDDQ) {$V_{DDQ}$}; -% \node[anchor=north] at (VDDQ2) {$V_{DDQ}/2$}; -% \end{circuitikz} -% \caption{Driving Logic 1 on Push Pull Termination Interface} -% \label{fig:term_push_pull} -%\end{figure} -%% -%\begin{figure} -% \centering -% \begin{circuitikz} -% \ctikzset{bipoles/resistor/height=0.15} -% \ctikzset{bipoles/resistor/width=0.4} -% \draw (0,0) node[tlground]{} to[R,a=$R_{ON}$] ++(0,1.5) to[short=$"0"$] ++(3,0) to[R,a=$R_{TT}$] ++(0,1.5) node[tground](VDDQ2){}; -% \node[anchor=south] at (VDDQ2) {$V_{DDQ}/2$}; -% \end{circuitikz} -% \caption{Driving Logic 0 on Push Pull Termination Interface} -% \label{fig:term_push_pull} -%\end{figure} -%% -%\begin{figure} -% \centering -% \begin{circuitikz} -% \ctikzset{bipoles/resistor/height=0.15} -% \ctikzset{bipoles/resistor/width=0.4} -% \draw (0,0) node[tlground]{} to[R,a=$R_{ON}$] ++(0,1.5) to[short=$"0"$] ++(3,0) to[R,a=$R_{TT}$] ++(0,1.5) node[tground](VDDQ){}; -% \node[anchor=south] at (VDDQ) {$V_{DDQ}$}; -% \end{circuitikz} -% \caption{Driving Logic 0 on POD Interface} -% \label{fig:term_push_pull} -%\end{figure} -%% -%\begin{figure} -% \centering -% \begin{circuitikz} -% \ctikzset{bipoles/resistor/height=0.15} -% \ctikzset{bipoles/resistor/width=0.4} -% \draw (0,0) node[tground](VDDQ){} to[R=$R_{ON}$] ++(0,-1.5) to[short=$"1"$] ++(3,0) to[R=$R_{TT}$] ++(0,-1.5) node[tlground](VSSQ){}; -% \node[anchor=south] at (VDDQ) {$V_{DDQ}$}; -% \end{circuitikz} -% \caption{Driving Logic 1 on LVSTL Interface} -% \label{fig:term_push_pull} -%\end{figure} -% -The termination power depends on the termination scheme, the ratio between the two logic levels, and the time at which the termination is enabled, but it is independent of the operating frequency. -There are three commonly used termination schemes for DRAM, shown in Figure~\ref{fig:term} for a simple point-to-point connection. -% \begin{figure*} \centering \begin{subfigure}[b]{0.32\linewidth} @@ -672,7 +564,7 @@ There are three commonly used termination schemes for DRAM, shown in Figure~\ref \caption{Pseudo Open Drain Logic (PODL)} \label{fig:term_podl} \end{subfigure} -% + \hfill \begin{subfigure}[b]{0.32\linewidth} \centering \resizebox{\linewidth}{!}{% @@ -697,7 +589,7 @@ There are three commonly used termination schemes for DRAM, shown in Figure~\ref \caption{Low Voltage Swing Term. Logic (LVSTL)} \label{fig:term_lvstl} \end{subfigure} - % + \hfill \begin{subfigure}[b]{0.32\linewidth} \centering \resizebox{\linewidth}{!}{% @@ -729,75 +621,97 @@ There are three commonly used termination schemes for DRAM, shown in Figure~\ref \label{fig:term} \end{figure*} % -\textit{Pseudo open drain logic} (PODL) and \textit{low voltage swing terminated logic} (LVSTL) only use a pull-up or a pull-down resistor, respectively. -In contrast, \textit{stub series terminated logic} (SSTL) uses both a pull-up and a pull-down resistor. +From the definitions of the two currents, we know that within a refresh interval $t_{REFI}$, the burst refresh energy and the average refresh energy are identical. +This relationship can be translated into the following equation to calculate $I_{DD5B}$ from $I_{DD5A}$: +\begin{equation} + I_{DD5B} = I_{DD2N} + \left(I_{DD5A} - I_{DD2N}\right) \cdot \frac{t_{REFI}}{t_{RFC}} +\end{equation} +% +\section{Interface Power Modeling}\label{sec:interface_power_modeling} +% +Interface power refers to the power consumed by the drivers for the communication between memory controller and DRAM devices. +In contrast to the core power, which is fixed for a specific device, the interface power depends on the complete DRAM subsystem architecture, i.e., the \textit{physical layer} (PHY) of the memory controller, the channel architecture (number of ranks, possible usage of DIMMs, etc.), the channel characteristics (e.g., channel loss and parasitic capacitances) and the DRAM PHYs. +Thus, a modeling based on the operating currents specified in vendor datasheets is not possible as they are only measured for one specific subsystem architecture. +Instead, we calculate the interface power based on an equivalent circuit diagram of the real interface architecture as is also done by CACTI-IO. +Interface power can be divided into \textit{termination power}, which is dissipated across the termination resistances required for signal integrity, and \textit{dynamic power}, which is dissipated through the lossy charging and discharging of parasitic capacitances and the signaling over a lossy transmission line. +In the following two sections, the calculation of termination power and dynamic power is explained. +% +\subsection{Termination Power} +% +The termination power depends on the termination scheme and the number of logic zeros and ones transmitted, but it is independent of the operating frequency. +There are three commonly used termination schemes for DRAM, shown in Figure~\ref{fig:term} for a simple point-to-point connection. +\textit{Pseudo open drain logic} (PODL) and \textit{low voltage swing terminated logic} (LVSTL) only use a pull-up or a pull-down resistor for termination, respectively. +\textit{Stub series terminated logic} (SSTL) uses both a pull-up and a pull-down resistor. In all three cases, the termination resistance is matched the characteristic impedance of the transmission line, i.e., $R_{TT} \approx Z_0$ (remember that in AC analysis a DC voltage source is treated as a short). To calculate the power, both logic levels are considered separately. -The transistor of the driver that is switched on is replaced with an equivalent resistor with resistance $R_{ON}$, while the transistor that is switched off is replaced with an open line. +The transistor of the driver that is switched on is replaced with an equivalent resistor with resistance $R_{ON}$, while the transistor that is switched off is replaced with an open circuit. As an example, Figure~\ref{fig:terminations} shows the two equivalent circuit diagrams for a PODL interface. % \begin{figure} \centering - \begin{circuitikz} - \ctikzset{bipoles/resistor/height=0.15} - \ctikzset{bipoles/resistor/width=0.4} - \draw (0,0) - node[tground](VDDQ1){} - to [R=$R_{ON}$] ++(0,-1.5) coordinate(x1) - to [short=$"1"$, name={s1}] ++(2,0) coordinate(x2) - to [R,a=$R_{TT}$] ++(0,1.5) node[tground](VDDQ2){}; - \node[anchor=south] at (VDDQ1) {$V_{DDQ}$}; - \node[anchor=south] at (VDDQ2) {$V_{DDQ}$}; - \draw(x2) to [open] ++(1.75,0) coordinate(x3) - to [R=$R_{ON}$] ++(0,-1.0) node[ground](x4){}; - \draw(x3) - to [short=$"0"$, name={s2}] ++(2,0) - to [R,a=$R_{TT}$] ++(0,1.5) node[tground](VDDQ3){}; - \node[anchor=south] at (VDDQ3) {$V_{DDQ}$}; - \path(x4) ++(0,-1.0) coordinate(x5); - \draw(s1|-x5) node[](){\bfseries (a) Driving Logic "1"}; - \draw(s2|-x5) node[](){\bfseries (b) Driving Logic "0"}; - \end{circuitikz}% - %\begin{subfigure}[t]{0.49\linewidth} - %\centering - %\resizebox{\linewidth}{!}{% - % \begin{circuitikz} - % \ctikzset{bipoles/resistor/height=0.15} - % \ctikzset{bipoles/resistor/width=0.4} - % \draw (0,0) - % node[tground](VDDQ1){} - % to [R=$R_{ON}$] ++(0,-1.5) coordinate(foo) - % to [short=$"1"$] ++(3,0) - % to [R,l=$R_{TT}$] ++(0,1.5) node[tground](VDDQ2){}; - % \node[anchor=south] at (VDDQ1) {$V_{DDQ}$}; - % \node[anchor=south] at (VDDQ2) {$V_{DDQ}$}; - % \draw[white](foo) to [R] ++(0,-1.0) node[ground](VDDQ){}; - % \end{circuitikz}} - %\caption{Driving Logic "1"} - %\label{fig:term_logic_1} - %\end{subfigure} - %% - %\begin{subfigure}[t]{0.49\linewidth} - %\centering - %\resizebox{\linewidth}{!}{% - % \begin{circuitikz} - % \ctikzset{bipoles/resistor/height=0.15} - % \ctikzset{bipoles/resistor/width=0.4} - % \draw (0,0) node[tlground]{} to[R,a=$R_{ON}$] ++(0,1.5) to[short=$"0"$] ++(3,0) to[R,l=$R_{TT}$] ++(0,1.5) node[tground](VDDQ){}; - % \node[anchor=south] at (VDDQ) {$V_{DDQ}$}; - % \end{circuitikz}} - %\caption{Driving Logic "0"} - %\label{fig:term_logic_0} - %\end{subfigure} +% \begin{circuitikz} +% \ctikzset{bipoles/resistor/height=0.15} +% \ctikzset{bipoles/resistor/width=0.4} +% \draw (0,0) +% node[tground](VDDQ1){} +% to [R=$R_{ON}$] ++(0,-1.5) coordinate(x1) +% to [short=$"1"$, name={s1}] ++(2,0) coordinate(x2) +% to [R,a=$R_{TT}$] ++(0,1.5) node[tground](VDDQ2){}; +% \node[anchor=south] at (VDDQ1) {$V_{DDQ}$}; +% \node[anchor=south] at (VDDQ2) {$V_{DDQ}$}; +% \draw(x2) to [open] ++(1.75,0) coordinate(x3) +% to [R=$R_{ON}$] ++(0,-1.0) node[ground](x4){}; +% \draw(x3) +% to [short=$"0"$, name={s2}] ++(2,0) +% to [R,a=$R_{TT}$] ++(0,1.5) node[tground](VDDQ3){}; +% \node[anchor=south] at (VDDQ3) {$V_{DDQ}$}; +% \path(x4) ++(0,-1.0) coordinate(x5); +% \draw(s1|-x5) node[](){\bfseries (a) Driving Logic "1"}; +% \draw(s2|-x5) node[](){\bfseries (b) Driving Logic "0"}; +% \end{circuitikz}% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + \begin{subfigure}[b]{0.37\linewidth} + \centering + \resizebox{\linewidth}{!}{% + \begin{circuitikz} + \ctikzset{bipoles/resistor/height=0.15} + \ctikzset{bipoles/resistor/width=0.4} + \draw (0,0) + node[tground](VDDQ1){} + to [R=$R_{ON}$] ++(0,-1.5) + to [short=$"1"$] ++(3,0) coordinate(foo) + to [R,l=$R_{TT}$] ++(0,1.5) node[tground](VDDQ2){}; + \node[anchor=south] at (VDDQ1) {$V_{DDQ}$}; + \node[anchor=south] at (VDDQ2) {$V_{DDQ}$}; + \draw[white](foo) to [R] ++(0,-1.5) node[tlground](VDDQ){}; + \end{circuitikz}} + \caption{Driving Logic "1"} + \label{fig:term_logic_1} + \end{subfigure} + % + \hspace{15pt} + % + \begin{subfigure}[b]{0.34\linewidth} + \centering + \resizebox{\linewidth}{!}{% + \begin{circuitikz} + \ctikzset{bipoles/resistor/height=0.15} + \ctikzset{bipoles/resistor/width=0.4} + \draw (0,0) node[tlground]{} to[R,a=$R_{ON}$] ++(0,1.5) to[short=$"0"$] ++(3,0) to[R,l=$R_{TT}$] ++(0,1.5) node[tground](VDDQ){}; + \node[anchor=south] at (VDDQ) {$V_{DDQ}$}; + \end{circuitikz}} + \caption{Driving Logic "0"} + \label{fig:term_logic_0} + \end{subfigure} \caption{Equivalent Circuit Diagrams for PODL Termination Power} \label{fig:terminations} \end{figure} % -When driving a logic "1", both ends of the circuit are connected to $V_{DDQ}$, which means that no current is flowing and no power is dissipated, i.e., +When driving a logic one, both ends of the circuit are connected to $V_{DDQ}$, which means that no current is flowing and no power is dissipated, i.e., \begin{equation} P_{term,1}^{PODL} = 0. \end{equation} -In contrast, when driving a logic "0", one side is connected to ground, while the other side is connected to $V_{DDQ}$. +In contrast, when driving a logic zero, one side is connected to ground, while the other side is connected to $V_{DDQ}$. The dissipated power is calculated as \begin{equation} P_{term,0}^{PODL} = \frac{V_{DDQ}^2}{R_{ON} + R_{TT}}. @@ -816,8 +730,8 @@ It can be calculated as P_{term,0}^{SSTL} = P_{term,1}^{SSTL} = \frac{V_{DDQ}^2}{(R_{ON}||2R_{TT})+2R_{TT}}. \end{equation} % -The average termination power for transmitting $n_0$ logic zeros and $n_1$ logic ones is -\begin{equation} +The average termination power when transmitting $n_0$ logic zeros and $n_1$ logic ones is +\begin{equation}\label{eq:term_total} P_{term} = \frac{P_{term,0} \cdot n_0 + P_{term,1} \cdot n_1}{n_0 + n_1} \end{equation} %dissipated termination energy depends on the bit period $t_b$ (minimum time that signal is at one logic level) and the number of transmitted logic zeros $n_0$ and logic ones $n_1$. @@ -828,7 +742,7 @@ The average termination power for transmitting $n_0$ logic zeros and $n_1$ logic Because with PODL and LVSTL only one logic level consumes power, data bus inversion can be used to reduce the termination power consumption. With SSTL, the termination power is independent of the transmitted data. -When using channel configurations with multiple ranks or DIMMs, the interconnect network can change from a simple point-to-point topology to a more complex topology, e.g., because the non-target dies also terminate the bus. +For channel configurations with multiple ranks or DIMMs, the interconnect network can change from a simple point-to-point topology to a more complex topology, e.g., because the non-target dies also terminate the bus. In these cases, termination power can be calculated in the same way by determining the equivalent circuit diagrams for both logic levels. % %Figures show simplest networks consisting of driver with pull-up and pull-down on resistance $R_{ON}$, lossless transmission line with impedance $Z_0$ and termination resistance $R_{TT}$. @@ -858,12 +772,12 @@ In these cases, termination power can be calculated in the same way by determini % As shown in the previous section, termination power is frequency independent because it is dissipated across a purely resistive network. Termination power represents a lower bound for the total power consumption and also dominates at low operating frequencies. -However, since current generation DRAM standards support data rates of 10\,Gbps/pin and more, the impact of parasitic capacitances is much more significant. +However, since current generation DRAM standards support data rates of 8\,Gbps/pin and more, the impact of parasitic capacitances is much more significant. Figure~\ref{fig:load_caps} shows the simple point-to-point connection with PODL termination scheme as already presented in Figure~\ref{fig:term_podl}, but with two added parasitic capacitances, one at the driver side and one at the receiver side. % \begin{figure} \centering - \resizebox{\linewidth}{!}{% + \resizebox{.9\linewidth}{!}{% \begin{circuitikz} \ctikzset{bipoles/resistor/height=0.15} \ctikzset{bipoles/resistor/width=0.4} @@ -884,13 +798,13 @@ Figure~\ref{fig:load_caps} shows the simple point-to-point connection with PODL \draw (D1) to[C=$C_{TX}$] (D1|-VSSQ) node[tlground]{}; \draw (D3) to[C,a=$C_{RX}$] (D3|-VSSQ) node[tlground]{}; \end{circuitikz}} - \caption{Point-to-Point Connection with Parasitic Capacitances} + \caption{Point-to-Point Connection with Parasitic Caps} \label{fig:load_caps} \end{figure} % We analyze the power dissipation of this circuit for different operating frequencies as input using SPICE. The components are dimensioned as $R_{ON}$ = \SI{48}{\ohm}, $R_{TT}$ = \SI{60}{\ohm}, $C_{TX}$ = $C_{RX}$ = \SI{1}{\pico\farad} and $V_{DDQ}$ = \SI{1.1}{\volt}, which is in the order of a real DDR5 interface. -For now, the transmission line is also only modeled as a parasitic capacitance with $C_{TL}$ = \SI{2}{\pico\farad}. +For now, the transmission line losses are also modeled with a parasitic capacitance with $C_{TL}$ = \SI{2}{\pico\farad}. % %\begin{figure} % \centering @@ -913,7 +827,7 @@ For now, the transmission line is also only modeled as a parasitic capacitance w % At a frequency of \SI{100}{\mega\hertz}, the dissipated power is \SI{5.7}{\milli\watt}, which is close to the termination power of the circuit of \SI{5.6}{\milli\watt}. However with increasing frequencies, the power also increases because the capacitors start to conduct. -At \SI{1600}{\mega\hertz} (i.e., DDR5-3200), the dissipated power is already \SI{8.6}{\milli\watt}, i.e., \SI{40}{\percent} higher than the pure termination power. +At \SI{1600}{\mega\hertz} (i.e., DDR5-3200), the dissipated power is already \SI{8.6}{\milli\watt}, i.e., over \SI{50}{\percent} higher than the pure termination power. To calculate the power dissipation analytically, the clock signal with frequency $f$ and voltage swing $V_{DDQ}$ can be expressed as a Fourier series \begin{equation} v(t) = \frac{V_{DDQ}}{2} + \Re \left\{\frac{-2j \cdot V_{DDQ}}{\pi} \sum_{k=1,3,5,\dots}^{\infty} \frac{1}{k} \exp(j 2 \pi f k t)\right\}. @@ -926,7 +840,7 @@ The complex amplitudes $\underline{\hat{V}}_k$ of the frequency components can b \end{equation} With the frequency-dependent complex impedances $\underline{Z}_k$ calculated as \begin{equation} - \underline{Z}_k = R_{ON} + \frac{1}{j 2 \pi f k (C_{TX} + C_{RX}) + \frac{1}{R_{TT}}}, + \underline{Z}_k = R_{ON} + \frac{1}{j 2 \pi f k (C_{TX} + C_{RX} + C_{TL}) + \frac{1}{R_{TT}}}, \end{equation} the DC resistance $R_{DC}$ calculated as \begin{equation} @@ -942,60 +856,66 @@ the total power dissipation $P_{total}$ can be calculated as \end{equation} % In reality, the series needs to be terminated at a certain $k$, which can be chosen to match the finite slew rate of the signal. -For LVSTL the same equations can be applied, while for SSTL the calculation of the DC component needs to be adapted. +For LVSTL, the same equations can be applied, while for SSTL, the calculation of the DC component needs to be adapted. The dynamic power $P_{dyn}$, which adds to the termination power due to the toggling between both logic levels, is finally calculated as \begin{equation} P_{dyn} = P_{total} - P_{term}. \end{equation} -One alternative formula, which is often used to calculate the dynamic power $P_{dyn}$, is given by +One alternative formula, which is often used to approximate the dynamic power $P_{dyn}$, is given by \begin{equation}\label{eq:approx} - P_{dyn} = \left(\sum_i C_i V_{sw,i}\right) \frac{V_{DDQ} \cdot f}{2} + P_{dyn} = \left(\sum_i C_i \cdot V_{sw,i}\right) \frac{V_{DDQ} \cdot f}{2} \end{equation} -where $C_i$ are the capacitances along the channel and $V_{sw,i}$ the respective voltage swings at each capacitance~\cite{bak_90,joukah_12,joukah_15}. +where $C_i$ are the capacitances along the channel and $V_{sw,i}$ are the respective voltage swings at each capacitance~\cite{bak_90,joukah_15}. The voltage swings are usually determined using a DC analysis for both logic levels. -While this approximation provides accurate results at low operating frequencies, current generation DRAM interfaces do not reach full swing anymore due to the large parasitic capacitances in combination with high operating frequencies. -Figure~\ref{fig:power_comp} shows the total power dissipation at different operating frequencies calculated with SPICE, Equation~\ref{eq:fourier} and Equation~\ref{eq:approx}. +This is also done by CACTI-IO. +While this approximation provides accurate results at low operating frequencies, current generation DRAM interfaces do not reach full voltage swing anymore due to the large parasitic capacitances in combination with high operating frequencies. +Figure~\ref{fig:power_comp} shows the total power dissipation of the previous circuit (Figure~\ref{fig:load_caps}) at different operating frequencies calculated with SPICE, Equation~\ref{eq:fourier} and Equation~\ref{eq:term_total} plus Equation~\ref{eq:approx}. % \begin{figure} \centering + \resizebox{.9\linewidth}{!}{% \begin{tikzpicture} \begin{axis}[ + axis equal image, xlabel={Operating Frequency [MHz]}, ylabel={Power Dissipation [mW]}, %xmode=log, xmin=0, - xmax=8, - xtick={1,2,3,4,5,6,7}, + xmax=16, + xtick={2,4,6,8,10,12,14}, xticklabels={100,200,400,800,1600,3200,4200}, + ymin=0, + ymax=12, ybar, bar width=2mm, legend pos=north west ] - \addplot+ coordinates {(1,5.7) (2,5.9) (3,6.2) (4,6.8) (5,7.75) (6,8.6) (7,8.8)}; - \addplot+ coordinates {(1,5.7) (2,5.9) (3,6.2) (4,6.8) (5,7.75) (6,8.6) (7,8.8)}; - \addplot+ coordinates {(1,5.7) (2,5.9) (3,6.1) (4,6.7) (5,7.75) (6,9.9) (7,11.2)}; + \addplot+ coordinates {(2,5.7) (4,5.9) (6,6.2) (8,6.8) (10,7.75) (12,8.6) (14,8.8)}; + \addplot+ coordinates {(2,5.7) (4,5.9) (6,6.2) (8,6.8) (10,7.75) (12,8.6) (14,8.8)}; + \addplot+ coordinates {(2,5.7) (4,5.9) (6,6.1) (8,6.7) (10,7.75) (12,9.9) (14,11.2)}; \legend{SPICE, Fourier Series (This Work), Approximation (CACTI-IO)} \end{axis} - \end{tikzpicture} + \end{tikzpicture}% + } \caption{Comparison of Different Calculation Methods for Power Dissipation} \label{fig:power_comp} \end{figure} % -While Equation~\ref{eq:fourier} always provides the same results as SPICE, Equation~\ref{eq:approx} is accurate at low frequencies, but overestimates the power dissipation at higher frequencies, e.g., by \SI{15}{\percent} at \SI{3200}{\mega\hertz} (DDR5-6400) and even \SI{27}{\percent} at \SI{4200}{\mega\hertz} (DDR5-8400, the highest specified data rate in the standard). +While the Fourier series based formula consistently provides the same results as SPICE, the approximate formula is accurate at low frequencies, but overestimates the power dissipation at higher frequencies, e.g., by \SI{15}{\percent} at \SI{3200}{\mega\hertz} (DDR5-6400) and even \SI{27}{\percent} at \SI{4200}{\mega\hertz} (DDR5-8400, the currently highest specified data rate of the standard). -\todo{The impact of the transmission line can be handled in different ways.} +The loss characteristic of the transmission line can be handled in different ways. In \cite{holsta_19}, the authors have analyzed various physical DRAM interfaces, i.e., multi DIMM, package on package, PCB trace and silicon interposer. They show that the channels have very distinct insertion loss characteristics, which need to be taken into consideration for an accurate power estimation. -A linear loss characteristic can be approximated with matching capacitances, while more complex loss characteristics can be approximated with frequency-dependent resistance values in the Fourier series based calculation. +A linear loss characteristic can be approximated with an additional capacitance, while more complex loss characteristics can be modeled with frequency-dependent impedance values in the Fourier series based calculation. Up until now, the formulas for dynamic power consumption assume a switching activity of $\alpha = 1$, i.e., the signals transition from logic zero to logic one once every period. While this is true for clock and data strobe signals, the command/address bus and data bus usually experience lower switching activities. -Especially when the bus is only operated at SDR, the switching activity is limited to $\alpha_{max} = 0.5$. +Especially when a signal is only operated at SDR, the switching activity is limited to $\alpha_{max} = 0.5$. The problem is that the switching activity $\alpha$ and number of transmitted zeros $n_0$ and ones $n_1$ alone do not determine the complete signal behavior, which is demonstrated in Figure~\ref{fig:switching_signals}. % \begin{figure} \centering - \resizebox{\linewidth}{!}{% + \resizebox{.85\linewidth}{!}{% \input{img/switching_signals} } \caption{Two Different Signals with Identical $\alpha$, $n_0$ and $n_1$} @@ -1005,8 +925,8 @@ The problem is that the switching activity $\alpha$ and number of transmitted ze Both S1 and S2 have a switching activity of $\alpha = 0.5$ and the number of transmitted zeros and ones is $n_0 = n_1 = 8$. However, S1 operates at half the clock frequency for the whole time, while S2 operates at the full clock frequency in the beginning and only one fifth of the clock frequency in the end. When the dissipated power is calculated section by section using Equation~\ref{eq:fourier}, the results for S1 and S2 differ because different voltage swings are reached in each section. -In the corner cases, a signal with switching activity $\alpha$ can be either modeled with a constant switching activity or with a maximum switching activity $\alpha_{max}$ for one part of the time and a switching activity of 0 for the other part of the time. -The actual dynamic power consumption lies between these two corner cases and is in the rest of the paper approximated by the mean value +In the corner cases, a signal with switching activity $\alpha$ can be either modeled with a constant switching activity for the whole time or with a maximum switching activity $\alpha_{max}$ for one part of the time and a switching activity of 0 for the other part of the time. +The actual dynamic power consumption lies between these two corner cases and can be approximated by the mean value \begin{equation} \overline{P}_{dyn}(\alpha) = \frac{P_{dyn}(f=\alpha \cdot f_{max}) + \frac{\alpha}{\alpha_{max}} \cdot P_{dyn}(f = \alpha_{max} \cdot f_{max})}{2}. \end{equation} @@ -1015,110 +935,27 @@ Finally, the switching activity $\alpha$ can be determined by counting the numbe \begin{equation} \alpha = \frac{n_{0 \rightarrow 1}}{\tau \cdot f_{max}}. \end{equation} - -\todo{data dependent interface power calc, we count n0, n1 and toggles for CMD/ADDR and data bus} - % % -%the assumption was that full toggle rate/ switching activity, only the case for clock signal -%-> calculate energy for one toggle, count toggles, figure for full toggle no toggle vs half toggle whole time +\section{Simulator Overview}\label{sec:simulator} % -%While these equations work for a clock signal -% -%only depends on resistances independent of the frequency, -% -% -% -%To calculate the dynamic power, all parasitic capacitances and transmission lines along the DRAM channel need to be considered. -%The simplest case is a point-to-point connection between the memory controller and a single DRAM device. -%Figure~\ref{fig:load_caps} shows the equivalent circuit diagram for this case, assuming low voltage swing terminated logic. -%On the driver side, all parasitic capacitances (on-chip pad and IC package) are combined into the driver load capacitance $C_{TX}$, while on the receiver side, all parasitic capacitances are combined into the receiver load capacitance $C_{RX}$. -% -% -% -% -%Load capacitances are charged and discharged, power is dissipated in driver, dynamic power, only when switching happens. -%Simple case without multiple ranks: Effective line capacitance of channel $C_{line}$ and pad + package both on driver and receiver side ($C_{TX}$ and $C_{RX}$) -% -% -% -% -% -%CACTI-IO: Several capacitances: -%$C_{int}$: Internal IO loading (loading within the IO, due to predriver nets), full swing -%$C_{tx}$: IO TX self-load including package (loading at the CPU TX pin), lower swing -%$C_{data}$: Device loading per memory data pin (DRAM device load for DQ per die) -%$C_{addr}$: Device loading per memory address pin (DRAM device load for CA per die) -%!!!different capacitances for different package types!!! -%If the signal rise time $t_r$ is less than or comparable to the transmission line flight time $t_f$, transmission line behavior becomes significant. Rule of thumb: $t_r < 2.5 t_f$ -%Up to 1GHz transmission lines can be considered lossless -%Transmission line with impedance $Z_0$ can be expressed by effective line capacitance $C_{line}$, which depends on flight time: -%\begin{equation} -% C_{line} = \frac{t_f}{Z_0} -%\end{equation} -%If half bit period $\frac{t_b}{2}$ is less than flight time $t_f$, $C_{line}$ depends on $t_b$: -%\begin{equation} -% C_{line} = \frac{t_b}{Z_0} = \frac{1}{2f Z_0} -%\end{equation} -% -%intrinsic capacitance of driver with full swing VDDQ, capacitance of pad, -%Interconnect Power: -%Interconnect acts as lossless? transmission line, has characteristic impedance, dynamic power dissipated in driver when switching happens -%Termination Power: -%Far-end termination, static power depending on signal value and termination type, power is dissipated in driver (Ron), target termination resistor (and non-target termination resistor) -%\begin{equation} -% P_{dyn} = N_{pins} D_c \alpha \left(\sum_i C_i V_{sw,i}\right) V_{DDQ} f -%\end{equation} -%Voltage swing is usually less than VDD, duty cycle should be 1 because charging process takes the complete period at high frequencies -> driven signal looks like rectangle -% -%\todo{Lossless transmission line up to 1 GHz} -%\todo{Gewichtung von average Swing mit alpha} -% -%This power is associated with the transfer of commands from the memory controller to the DRAM devices and transferring data in and out of the DRAM. -%Components: -%I/O buffers: These circuits drive the data onto the external data bus when the DRAM reads or receives data from the bus during a write. -%Data and command/address bus activity: Every time data is transferred to or from the DRAM, the I/O circuitry consumes power. This includes driving the clock signals, data lines (DQ), address lines, and control signals. -%Key Characteristics: -%Dependent on the activity of the external data bus, i.e., how frequently data is transferred to and from the DRAM. -%Scales with data rate: Higher data rates (e.g., DDR4, DDR5) increase interface power due to more frequent toggling of the I/O signals. -%Often includes power consumed by termination resistances, which are used to improve signal integrity on the high-speed bus. -%While interface power is generally lower than core power, it can become significant at high memory speeds, especially in modern DRAM technologies like DDR4 and DDR5. -%% -%In contrast to core power, interface characteristics are mainly specified in standard (caps, resistors, termination, driving strength, voltage etc.) -%Depending on interface topology, power can vary greatly. Although standard also defines currents that are drawn over interface supply voltage (typically VDDQ), these currents only describe one specific test setup. -%Data that is transmitted has fixed patterns. -%In addition, power consumption of memory controller PHY is not considered, also contributes to power consumption of DRAM subsystem. -%Thus, we calculate interface power based on physical equations. -%% -%DRAM interface connections: differential clock signal ->, command/address bus ->, data bus <->, data strobe <-> -%Depending on standard, there are more/different signals -%% -%While the core power is fixed for a specific device and characterized in the datasheet with different operating currents, the interface power not only depends on the device itself, but also on the physical interface (PHY) of the memory controller, the interconnect channel (PCB, TSV etc.) and other chips connected to the same channel (multi-rank configurations). -%Thus, the currents specified in the datasheet for the I/O driver supply voltage VDDQ cannot be used for accurate estimations. -%Instead, the I/O power calculation is based on physical equations to model transmission lines as shown in \cite{joukah_15,joukah_12}. -%Interface power depends on package type (TSV, POP, device soldered on PCB, DIMM: UDIMM, RDIMM, LRDIMM...), ranks etc. -% -% -% -\section{Simulator Overview} -% -This section provides a short introduction to the internal software architecture of DRAMPower. +This section provides a short introduction to the internal software architecture of DRAMPower~5. Afterwards, the simulation speed and simulation accuracy are evaluated. % -\subsection{Simulator Architecture} +\subsection{Software Architecture} % -The new version of DRAMPower is not designed as a standalone simulator, but as a library that is coupled to a DRAM subsystem simulator which models the DRAM controller and translates incoming read and write requests into DRAM commands. +The new version of DRAMPower is not designed as a standalone simulator, but as a library that is coupled to a DRAM subsystem simulator which models the memory controller and translates incoming read and write requests into DRAM commands. Alternatively, a DRAM command trace can be provided as an input file. For the interface power calculation, the provided commands, addresses and data are translated into equivalent bit patterns using the command truth table of the simulated standard. Based on this data, the number of transmitted zeros $n_0$, transmitted ones $n_1$ and zero to one transitions $n_{0 \rightarrow 1}$ can be calculated. To achieve high simulation speeds, bit manipulation instructions including the population count (\texttt{POPCNT}) instruction are used. -If no data is provided, a switching activity $\alpha$ and a duty cycle $D$ has to be provided. +Instead of real data, it is also possible to provide a switching activity $\alpha$ and a duty cycle $D$ (ratio between logic one and logic zero). In addition to the command/address and data bus, the remaining signals like the clock signal pair, data strobe pairs or chip select need to be considered (see Section~\ref{subsec:background_interface}). %As explained in Section~\ref{sec:interface_power_modeling}, the interface power calculation can depend on lots of parameters and, thus, can become very complex. %\todo{In order to avoid the complexity within DRAMPower, the tool only receives the precalculated termination and dynamic power values for all signals as inputs.} %These calculations need to be carried out externally using the provided equations. -The core power calculation is more complex because in addition to counting the number of issued commands of each type, DRAMPower needs to keep track of the clock cycles that the DRAM is in a specific state (i.e., 0 - B banks active, active/precharge power down, self refresh). +The core power calculation is more complex because in addition to counting the number of issued commands of each type, DRAMPower needs to keep track of the clock cycles that the DRAM is in a specific state (i.e., 0 - B banks active, active/precharge power-down, self refresh). If a configuration with multiple ranks is simulated, the counting has to be done separately for each rank. A further difficulty arises from the fact that the internal state is not always changed immediately by an external command, but it can also change after a certain delay. An example for this behavior is shown in Figure~\ref{fig:implicit_commands}. @@ -1132,20 +969,20 @@ An example for this behavior is shown in Figure~\ref{fig:implicit_commands}. \label{fig:implicit_commands} \end{figure} % -When a read with auto precharge command (\texttt{RDA}) is issued, the target bank is automatically precharged after the read to precharge delay $t_{RTP}$ has expired. +When a \textit{read with auto precharge} command (\texttt{RDA}) is issued, the target bank is automatically precharged after the read to precharge delay $t_{RTP}$ has expired. This means that the DRAM will internally issue what we call an \textit{implicit command} in the future. Unfortunately, DRAMPower is not based on an event-driven simulation kernel like SystemC where an event can be directly notified in the future. Instead, it is only triggered from the outside when new commands are issued, so the implicit commands need to be handled differently. -The actions that are performed by one implicit command are formulated as a lambda expression, which is stored in an internal list ordered by the time stamp of execution. -Whenever DRAMPower is triggered from the outside, first, the list is searched from the beginning for implicit commands with time stamps less than or equal to the current simulation time. -The lambda expressions of these list entries are then evaluated first before the external command is handled. -The total power consumption can be queried at any time even when the simulation is still running, which allows to analyze the power consumption over time. +The actions that are performed by an implicit command are formulated as a lambda expression, which is stored in an internal list ordered by the time stamp of execution. +Whenever DRAMPower is triggered from the outside, first, this list is searched from the beginning for implicit commands with time stamps less than or equal to the current simulation time. +The lambda expressions of these list entries are then evaluated before the external command is handled. +The total power consumption can be queried at any time even when the simulation is still running, which allows to analyze the change of power consumption over time. % %\subsection{Simulation Kernel} %% %Windowing: Power can be evaluated during running simulation -> power over time is possible %Handling implicit commands: -%Examples: Power Down Entry is not done when command is issued, but might be delayed +%Examples: Power-Down Entry is not done when command is issued, but might be delayed %RDA/WRA: auto-precharge is done after RD/WR is internally completed or only after tRAS is expired %when command is issued, implicit command (lambda) is inserted into deque of implicit commands that is ordered by timestamp %before we execute a new command or we request the window stats, we check if there are still outstanding requests in the implicit command queue with a timestamp smaller or equal to the current time @@ -1196,39 +1033,39 @@ The total power consumption can be queried at any time even when the simulation % \subsection{Simulation Speed} % -Since DRAMPower is not used as a standalone tool in the normal use case, but rather coupled to a behavioral DRAM subsystem simulator, we evaluate its simulation speed in terms of the overhead of adding power simulation. -For this analysis, DRAMPower is coupled to the well-known DRAM subsystem simulator DRAMSys~\cite{stejun_20}. -Within DRAMSys, \todo{one million read and write requests with random addresses and random data are generated.} +Since DRAMPower is not operated as a standalone tool in the normal use case, but rather coupled to a behavioral DRAM subsystem simulator, we evaluate its simulation speed in terms of the overhead of adding power simulation. +For this analysis, DRAMPower is coupled with DRAMSys~\cite{stejun_20}, a well-known DRAM subsystem simulator, and executed on a server with two Intel Xeon Silver 4210R processors. +Within DRAMSys, one million read and write requests with random addresses and data are generated. % TODO The data is always 0 This simulation is carried out both with and without power simulation enabled. Moreover, the simulations are also performed without actual data. In this case, DRAMPower is provided with a switching activity $\alpha$ and a duty cycle $D$. -For the simulations with data, DRAMSys alone requires 896\,ms to finish, while with added power simulation, -it takes 1004\,ms to finish. -This corresponds to an overhead of 12\,\%. -When no data is simulated, DRAMSys alone requires only 559\,ms to finish, while with DRAMPower enabled, the simulation time increases to 774\,ms. -In this case, the overhead is 38\,\%. -While this overhead is relatively large, there are two things to consider. -First, DRAMSys is highly optimized for simulation speed and outperforms all other simulators - -\begin{figure} - \centering - \resizebox{\linewidth}{!}{% - \input{img/benchmark_plot} - } - \caption{DRAMSys Benchmarks} - \label{fig:benchmark_plot} -\end{figure} - - -DRAMPower not standlone, simulated together with DRAMSys. DRAMSys is already fast (ref paper DRAMSys4.0), we have benchmarked DRAMPower coupled to DRAMSys, overhead of DRAMPower negligible. -if we couple additionally to core simulator (e.g., gem5), overhead is even smaller. -The benchmarks in figure~\ref{fig:benchmark_plot} show the overhead of drampower for a simulation with 1,000,000 requests. The benchmarks suffixed "nostore" are simulated without data. DRAMPower uses a toggling rate for calculating the databus energy. -\todo{DRAMPower popcnt. Comparison vector to std::bitset?} -\todo{Marco: Vielleicht kannst du hier ein paar Zahlen zur Simulationsgeschwindigkeit nennen, erstens bzgl. POPCNT und vielleicht auch zweitens im Vergleich zu DRAMSys, damit man sieht, dass die Simulationszeit von DRAMPower eigentlich nicht ins Gewicht fällt.} -dynamic power -> number of 0-1 toggles, calculated as (not p and q) -alternatively, duty cycle/toggling rates can be used - (drampower lässt sich unterteilen in zwei aspekte: statisch und dynamisch) +For the simulations with data, DRAMSys alone requires on average \SI{9.10}{\second} to finish, while with added power simulation, the average simulation time increases to \SI{11.37}{\second}. +This corresponds to an overhead of \SI{25}{\percent}. +When no data is simulated, DRAMSys alone requires on average only \SI{6.95}{\second} to finish, while with DRAMPower enabled, the simulation time increases to \SI{8.44}{\second}. +In this case, the overhead is \SI{21}{\percent}. +While this overhead may seem relatively large at first glance, there are two things to consider. +Firstly, DRAMSys is highly optimized for simulation speed as was already shown in~\cite{stejun_20}. +Secondly, if a full system simulation is performed where DRAMSys is additionally coupled to a much slower processor simulator such as gem5, the overhead of adding DRAMPower becomes negligible. +% +%\begin{figure} +% \centering +% \resizebox{\linewidth}{!}{% +% \input{img/benchmark_plot} +% } +% \caption{DRAMSys Benchmarks} +% \label{fig:benchmark_plot} +%\end{figure} +% +% +%DRAMPower not standlone, simulated together with DRAMSys. DRAMSys is already fast (ref paper DRAMSys4.0), we have benchmarked DRAMPower coupled to DRAMSys, overhead of DRAMPower negligible. +%if we couple additionally to core simulator (e.g., gem5), overhead is even smaller. +%The benchmarks in figure~\ref{fig:benchmark_plot} show the overhead of drampower for a simulation with 1,000,000 requests. The benchmarks suffixed "nostore" are simulated without data. DRAMPower uses a toggling rate for calculating the databus energy. +%\todo{DRAMPower popcnt. Comparison vector to std::bitset?} +%\todo{Marco: Vielleicht kannst du hier ein paar Zahlen zur Simulationsgeschwindigkeit nennen, erstens bzgl. POPCNT und vielleicht auch zweitens im Vergleich zu DRAMSys, damit man sieht, dass die Simulationszeit von DRAMPower eigentlich nicht ins Gewicht fällt.} +%dynamic power -> number of 0-1 toggles, calculated as (not p and q) +%alternatively, duty cycle/toggling rates can be used +% (drampower lässt sich unterteilen in zwei aspekte: statisch und dynamisch) %% statisch: wie sind die versch. standards implementiert %%% standard -> instruction set %%% mapping von bitcode auf instruction ( 011010101 -> REF ) @@ -1255,51 +1092,60 @@ alternatively, duty cycle/toggling rates can be used %% %\input{content/05_exp_results} -\subsection{Simulation Accuracy} +\subsection{Simulation Accuracy}\label{subsec:sim_accuracy} % -\todo{ -Interface -> comparison with SPICE, maybe use a random pattern in spice with fixed n0, n1 and alpha -Core -> we do not yet have a measurement platform for DDR5/LPDDR5/HBM3... where we can issue specific command patterns to DRAM and compare it with the results provided by DRAMPower. -} +%\todo{ +%Interface -> comparison with SPICE, maybe use a random pattern in spice with fixed n0, n1 and alpha +%Core -> we do not yet have a measurement platform for DDR5/LPDDR5/HBM3... where we can issue specific command patterns to DRAM and compare it with the results provided by DRAMPower. +%} % IDD Patterns mit Daimler Messung vergleichen -To verify the power estimates of the new DRAMPower implementation, we use core and interface power measurements of DRAMs from three different vendors, as reported in a study of a real LPDDR4 memory measurement platform~\cite{feldmann_23}. +To verify the power estimates of the new DRAMPower implementation, we use core and interface power measurements\footnote{The measurements do not include the interface power of the memory controller PHY.} of LPDDR4 devices from three different vendors, as reported in a study of a memory measurement platform~\cite{feldmann_23}. +Unfortunately, no measurement results for a newer standard are publicly available. Each DRAM is operated with six different access patterns, which are analogous to the following $I_{DD}$ currents: +% \tikz{\node[circle,draw,inner sep=1pt] {\tiny 1}}~$I_{DD0*}$, \tikz{\node[circle,draw,inner sep=1pt] {\tiny 2}}~$I_{DD4R}$, \tikz{\node[circle,draw,inner sep=1pt] {\tiny 3}}~$I_{DD4W}$, \tikz{\node[circle,draw,inner sep=1pt] {\tiny 4}}~$I_{DD5B}$, \tikz{\node[circle,draw,inner sep=1pt] {\tiny 5}}~$I_{DD2N}$ and \tikz{\node[circle,draw,inner sep=1pt] {\tiny 6}}~$I_{DD6}$. -As it was not possible to reproduce the usual $I_{DD0}$ pattern of ACT-PRE for the measurement platform, $I_{DD0*}$ is a variation using the ACT-RD-PRE pattern, which is also resembled in the DRAMPower simulation. -In addition, the measurement platform could not accurately measure the write current $I_{DD4W}$ because only one write request could be issued at a time, the simulation was also configured to limit the number of outstanding write requests to one. -The initial simulations are based on the current values specified in the datasheet of the specific vendor. +% +As it was not possible to reproduce the usual $I_{DD0}$ pattern of activate-precharge for the measurement platform, $I_{DD0*}$ is a variation using an activate-read-precharge pattern, which is also resembled in the DRAMPower simulation. +In addition, the platform could not accurately measure the operating burst write current $I_{DD4W}$ because only one write request could be issued at a time. +Thus, the simulation was also configured to limit the number of outstanding write requests to one. +The initial simulations are based on the current values specified in the vendor datasheets. Then, based on the actual measurements, the current values are reapplied to a second simulation. The results are shown in Figure~\ref{fig:power_plot}. +% \begin{figure} - \centering - \input{img/power_plot} - \caption{Average Power Consumption of Simulations and Measurements for Different Vendors} - \label{fig:power_plot} + \centering + \resizebox{.89\linewidth}{!}{% + \input{img/power_plot} + } + \caption{Average Power Consumption of Simulations and Measurements for Different Vendors} + \label{fig:power_plot} \end{figure} -As it can be seen, the $I_{DD}$ currents in the datasheet are overly pessimistic for all vendors: -The simulations based on the datasheets show on average a $2.9\times$ higher power consumption than the actual power measurements. -However, when the measured currents are applied to the simulation, the deviation drops to only around $18.8\%$. -The largest deviation comes from the $I_{DD0*}$ current. It is unclear whether the measurement platform was able to fully saturate the memory controller's buffer and therefore report a lower average power consumption than in the simulation. - -% LP4 vs LP5 -% DDR4 vs. DDR5 -% Vgl. DRAMPower3/4 und Vampire ggf. Messungen - - -% Concluison: -\section{Conclusion and Future Work} -New standards, PAM4 (GDDR6X) or PAM3 (GDDR7) instead of NRZ -> more complex interface calculation -%% mehr Standards in DRAMPower - -%% drampower kann dies und das - -%\section*{Acknowledgements} -%DI-DERAMSys +% +As it can be seen, the currents specified in the datasheets are overly pessimistic for all three vendors: +The simulations based on the datasheets show on average a \SI{2.9}{\times} higher power consumption than the actual measurements. +However, when the measured currents are applied to the simulation, the deviation drops to only around \SI{18.8}{\percent}. +The largest share is caused by $I_{DD0*}$. +For this pattern, it is unclear whether the measurement platform was actually able to fully saturate the memory controller's buffer and therefore reports a lower average power consumption than the simulations. +Without $I_{DD0*}$, the deviation is only \SI{2.8}{\percent}. +This again highlights that truly accurate core power simulations are only possible with measured currents, while datasheet values provide a worst-case estimate. +%\todo{This deviation is caused by the interface power modeling ($I_{DD4R}$ and $I_{DD4W}$) because the interface parasitics are estimated values.} +% +% +\section{Conclusion and Future Work}\label{sec:conclusion} +% +In this paper, we have presented DRAMPower~5, a power simulator for current generation DRAM standards. +It uses newly developed core and interface power models to flexibly support different standards and accurately capture the effects of high operating frequencies. +%DRAMPower~5 is open source and available on GitHub. +In the future, we will continue to update the simulator to emerging standards and new features. +%This will also include pulse-amplitude modulation (PAM) signaling, which is already used in GDDR6X and GDDR7, and poses new challenges for the interface power modeling. +% +\section*{Acknowledgements} +This work was funded in part by the German Federal Ministry of Education and Research (BMBF) under grants 16ME0935, 16ME0936 and 16ME0934K (\mbox{DI-DERAMSys}) as well as grants 16ME0717 and 16ME0716K (MANNHEIM-MEMTONOMY). %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %% Footer