Update on Overleaf.

This commit is contained in:
Lukas Steiner
2024-11-14 13:56:09 +00:00
committed by node
parent 9ec1f7db1b
commit c063c5f18f
2 changed files with 19 additions and 10 deletions

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@@ -277,9 +277,9 @@ Still, the tool has two drawbacks: it only models core power, but no interface p
Another simulation tools similar to DRAMPower is VAMPIRE~\cite{ghoyag_18}. Another simulation tools similar to DRAMPower is VAMPIRE~\cite{ghoyag_18}.
This tool puts its focus on the power variations between different DRAM modules, within one DRAM module depending on the access location, and the data value dependency. This tool puts its focus on the power variations between different DRAM modules, within one DRAM module depending on the access location, and the data value dependency.
VAMPIRE is calibrated with measurements of real DRAM modules and provides very accurate results. VAMPIRE is calibrated with measurements of real DRAM modules and provides very accurate results.
However, this presupposes that real measurements are available for the devices to be used, which is not usually the case in the early stages of design. However, this presupposes that real measurements are available for the devices to be used, which is not usually the case in the early stages of design. VAMPIRE also supports DDR3 only.
VAMPIRE also supports DDR3 only. %
\todo{analytical core power model Vogelsang, highly proprietary IP} There exists an analytical DRAM core-power model by Vogelsang~\cite{vog_10}. This model reflects a DDR memory but is also used to extrapolate future memory power consumption behavior.
When it comes to DRAM interface power modeling, the most popular software is CACTI-IO~\cite{joukah_12,joukah_15}. When it comes to DRAM interface power modeling, the most popular software is CACTI-IO~\cite{joukah_12,joukah_15}.
CACTI-IO does not rely on data sheet currents, but it uses an equivalent circuit diagram of the DRAM subsystem's real interface architecture as this architecture is not fixed for a specific device. CACTI-IO does not rely on data sheet currents, but it uses an equivalent circuit diagram of the DRAM subsystem's real interface architecture as this architecture is not fixed for a specific device.
The power consumption is then calculated using a simplified network analysis. The power consumption is then calculated using a simplified network analysis.
@@ -525,21 +525,29 @@ Thus, when a burst refresh current is provided, the energy for a single refresh
E_{REF} = V_{DD} \cdot \left(I_{DD5B} - I_{\circled{N}}\right) \cdot t_{RFC} E_{REF} = V_{DD} \cdot \left(I_{DD5B} - I_{\circled{N}}\right) \cdot t_{RFC}
\end{equation} \end{equation}
where $N$ is the number of refreshed banks. where $N$ is the number of refreshed banks.
As the equation shows, banks with a refresh in progress are considered active, which the most accurate way of modeling because internally the refresh is performed by successively activating multiple rows within each target bank.
In the cases where only an average refresh current $I_{DD5A}$ is provided, an approximated value for $I_{DD5B}$ can be determined.
During refresh, the targeted banks are considered active because Figure demonstrates the relation between both refresh currents graphically, where the dashed boxes represent the energy that is consumed.
The voltage is neglected because it is a constant.
As explained in Section~\ref{subsec:current_measurement}, JEDEC
% %
\begin{figure} \begin{figure}
\centering \centering
\resizebox{\linewidth}{!}{% \resizebox{\linewidth}{!}{%
\input{img/refresh_currents} \input{img/refresh_currents}
} }
\caption{Refresh Currents} \caption{Relation between Refresh Currents}
\label{fig:refresh_currents} \label{fig:refresh_currents}
\end{figure} \end{figure}
% %
This means that refreshed banks have to be considered as active in the background power calculation.
During refresh, the targeted banks are considered active because
As explained in Section~\ref{subsec:current_measurement}, JEDEC
%
%
\begin{equation} \begin{equation}
I_{DD5B} = I_{DD2N} + \left(I_{DD5A} - I_{DD2N}\right) \cdot \frac{t_{REFI}}{t_{RFC}} I_{DD5B} = I_{DD2N} + \left(I_{DD5A} - I_{DD2N}\right) \cdot \frac{t_{REFI}}{t_{RFC}}
\end{equation} \end{equation}

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@@ -8,6 +8,7 @@
\newcommand{\ya}{1} \newcommand{\ya}{1}
\newcommand{\yb}{2.6} \newcommand{\yb}{2.6}
\newcommand{\yc}{6} \newcommand{\yc}{6}
\newcommand{\yd}{7}
\pgfdeclarelayer{background} \pgfdeclarelayer{background}
\pgfsetlayers{background, main} \pgfsetlayers{background, main}
@@ -20,7 +21,7 @@
ymin=0, ymax=7, ymin=0, ymax=7,
xtick=\empty, xtick=\empty,
ytick=\empty, ytick=\empty,
extra y ticks={\ya, \yb, \yc}, extra y ticks={\ya, \yb, \yc, \yd},
extra y tick labels={$I_{DD2N}$, $I_{DD5A}$, $I_{DD5B}$}, extra y tick labels={$I_{DD2N}$, $I_{DD5A}$, $I_{DD5B}$},
axis x line=middle, axis x line=middle,
axis y line=middle, axis y line=middle,