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Update on Overleaf.

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Lukas Steiner
2024-11-14 14:05:53 +00:00
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50
drampower-main.tex
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@@ -236,7 +236,7 @@ The recent expansion of memory-intensive applications has led to increased deman
This demand is particularly pronounced in \textit{Artificial Intelligence} (AI) applications, where specialized accelerator chips with immense DRAM bandwidths beyond 1\,TBps are used. This demand is particularly pronounced in \textit{Artificial Intelligence} (AI) applications, where specialized accelerator chips with immense DRAM bandwidths beyond 1\,TBps are used.
However, these bandwidths come at the cost of high power consumption. However, these bandwidths come at the cost of high power consumption.
Google recently demonstrated that for large machine learning models, more than 90\,\% of the system power is consumed by memory. Google recently demonstrated that for large machine learning models, more than 90\,\% of the system power is consumed by memory.
In augmented reality devices for the Metaverse, memory can account for up to 80\,\% of power consumption.\todo{quellen} In augmented reality devices for the Metaverse, memory can account for up to 80\,\% of power consumption.\todo{quellen} \cite{yankao_24}
Therefore, an accurate estimation of DRAM power consumption is critical in the early stages of design in order to properly dimension the power supply circuits and cooling. Therefore, an accurate estimation of DRAM power consumption is critical in the early stages of design in order to properly dimension the power supply circuits and cooling.
In mobile devices, on the other hand, the overall power budget is constrained to only a few watts. In mobile devices, on the other hand, the overall power budget is constrained to only a few watts.
Nevertheless, it is equally important to accurately estimate DRAM power consumption, for example to explore the power saving potential of new DRAM standards and their additional features to extend battery life.\cite{borgho_18} Nevertheless, it is equally important to accurately estimate DRAM power consumption, for example to explore the power saving potential of new DRAM standards and their additional features to extend battery life.\cite{borgho_18}
@@ -526,9 +526,10 @@ Thus, when a burst refresh current is provided, the energy for a single refresh
\end{equation} \end{equation}
where $N$ is the number of refreshed banks. where $N$ is the number of refreshed banks.
As the equation shows, banks with a refresh in progress are considered active, which the most accurate way of modeling because internally the refresh is performed by successively activating multiple rows within each target bank. As the equation shows, banks with a refresh in progress are considered active, which the most accurate way of modeling because internally the refresh is performed by successively activating multiple rows within each target bank.
In the cases where only an average refresh current $I_{DD5A}$ is provided, an approximated value for $I_{DD5B}$ can be determined. In the cases where only an average refresh current $I_{DD5A}$ is provided, an approximated value for $I_{DD5B}$ can be determined.
Figure demonstrates the relation between both refresh currents graphically, where the dashed boxes represent the energy that is consumed. Figure demonstrates the relation between both refresh currents graphically, where the dashed boxes represent the energy that is consumed.
The voltage is neglected because it is a constant. The voltage is neglected because it is constant.
% %
\begin{figure} \begin{figure}
\centering \centering
@@ -539,35 +540,28 @@ The voltage is neglected because it is a constant.
\label{fig:refresh_currents} \label{fig:refresh_currents}
\end{figure} \end{figure}
% %
From the definitions of the two currents, we know that burst refresh energy and the average refresh energy within one refresh interval $t_{REFI}$ are identical.
This relationship can be translated into the following equation to calculate $I_{DD5B}$ from $I_{DD5A}$:
This means that refreshed banks have to be considered as active in the background power calculation.
During refresh, the targeted banks are considered active because
As explained in Section~\ref{subsec:current_measurement}, JEDEC
%
%
\begin{equation} \begin{equation}
I_{DD5B} = I_{DD2N} + \left(I_{DD5A} - I_{DD2N}\right) \cdot \frac{t_{REFI}}{t_{RFC}} I_{DD5B} = I_{DD2N} + \left(I_{DD5A} - I_{DD2N}\right) \cdot \frac{t_{REFI}}{t_{RFC}}
\end{equation} \end{equation}
%
The equation can be used to calculate the burst refresh current of different refresh modes by substituting the average refresh current $I_{DD5A}$, refresh interval $t_{REFI}$ and refresh cycle time $t_{RFC}$ with the appropriate values. %The equation can be used to calculate the burst refresh current of different refresh modes by substituting the average refresh current $I_{DD5A}$, refresh interval $t_{REFI}$ and refresh cycle time $t_{RFC}$ with the appropriate values.
During refresh, the device is considered in active state because internally the banks are constantly activated and refreshed. %During refresh, the device is considered in active state because internally the banks are constantly activated and refreshed.
The energy for an all-bank refresh command can be calculated as %The energy for an all-bank refresh command can be calculated as
\begin{equation} %\begin{equation}
E_{REFab} = V_{DD} \cdot \left(I_{DD5Bab} - I_{DD3N}\right) \cdot t_{RFCab} % E_{REFab} = V_{DD} \cdot \left(I_{DD5Bab} - I_{DD3N}\right) \cdot t_{RFCab}
\end{equation} %\end{equation}
When per-bank refresh is used, only a single bank is refreshed at a time. %When per-bank refresh is used, only a single bank is refreshed at a time.
Thus, only a single bank is considered active and the equation changes to %Thus, only a single bank is considered active and the equation changes to
\begin{equation} %\begin{equation}
E_{REFpb} = V_{DD} \cdot \left(I_{DD5Bpb} - I_{\circled{1}}\right) \cdot t_{RFCpb} % E_{REFpb} = V_{DD} \cdot \left(I_{DD5Bpb} - I_{\circled{1}}\right) \cdot t_{RFCpb}
\end{equation} %\end{equation}
% %%
Same-bank refresh for device with \textit{BG} bank groups and \textit{BA} banks per bank group %Same-bank refresh for device with \textit{BG} bank groups and \textit{BA} banks per bank group
\begin{equation} %\begin{equation}
E_{REFpb} = V_{DD} \cdot \left(I_{DD5Bsb} - I_{\circled{BG}}\right) \cdot t_{RFCsb} % E_{REFpb} = V_{DD} \cdot \left(I_{DD5Bsb} - I_{\circled{BG}}\right) \cdot t_{RFCsb}
\end{equation} %\end{equation}
% %
% %
\section{Interface Power Modeling} \section{Interface Power Modeling}

11
drampower.bib
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@@ -212,3 +212,14 @@ series = {ASPLOS '18}
keywords = {Arrays,Capacitance,DRAM,Driver circuits,Logic gates,power,Random access memory,Transistors}, keywords = {Arrays,Capacitance,DRAM,Driver circuits,Logic gates,power,Random access memory,Transistors},
file = {/Users/myzinsky/Zotero/storage/3LW3ARUS/Vogelsang - 2010 - Understanding the Energy Consumption of Dynamic Random Access Memories.pdf;/Users/myzinsky/Zotero/storage/HEEPHYEU/5695550.html} file = {/Users/myzinsky/Zotero/storage/3LW3ARUS/Vogelsang - 2010 - Understanding the Energy Consumption of Dynamic Random Access Memories.pdf;/Users/myzinsky/Zotero/storage/HEEPHYEU/5695550.html}
} }
@inproceedings{yankao_24,
title = {Characterization and {{Design}} of {{3D-Stacked Memory}} for {{Image Signal Processing}} on {{AR}}/{{VR Devices}}},
booktitle = {{{MEMSYS}}},
author = {Yang, Lita and Kao, Changjung and Srikanth, Sriseshan and Morris, Daniel and Sumbul, H Ekin and Wu, Tony F and Beign{\'e}, Edith},
year = {2024},
address = {Washingron},
abstract = {Image Signal Processing (ISP) is an important component in augmented and virtual reality (AR/VR) applications. With the goal of running these applications on battery-powered edge devices, the ISP unit must satisfy rigorous power, performance, and form factor requirements. However, ISP workloads incur large memory footprints and intensive DRAM accesses that are prohibitively expensive for the stringent requirements of all-day wearable AR/VR products. Recent progress in 3D integration provides a promising solution for increasing memory capacities for iso-footprint, while achieving lower I/O power with shorter, vertical 3D interconnections. In this work, we explore and characterize two types of advanced 3D-stacked memories for ISP workloads: 3D-SRAM and 3D-DRAM. Our analysis demonstrates that by allocating additional 3D-stacked local memory to the ISP unit, we reduce expensive off-chip DRAM accesses by 57-92\%, allowing us to deploy larger ISP workloads within power budgets not previously feasible with the 2D ISP baseline architecture. Comparing the two 3D-stacked memories, we observe that the use of 3D-DRAM reduces the total ISP power consumption by up to 53\%, while 3D-SRAM achieves up to 32\% power savings due to significant leakage contribution at increasing SRAM capacities. Finally, we propose a 3D-stacked hybrid memory ISP solution, combining both 3D-SRAM and 3DDRAM, which can further improve the ISP power efficiency by an additional 9-16\% on top of a 3D-DRAM-only memory architecture. To our knowledge, this is the first study to explore the benefits of advanced 3D-stacked memory for deploying ISP workloads on AR/VR devices.},
langid = {english},
file = {/Users/myzinsky/Zotero/storage/22TRQV4G/Yang et al. - Characterization and Design of 3D-Stacked Memory for Image Signal Processing on ARVR Devices.pdf}
}