Update on Overleaf.

drampower-main.tex

@@ -236,33 +236,18 @@ DRAMPower focuses on the power consumption of the DRAM core, while CACTI-IO mode
 Unfortunately, both tools have not been updated in recent years, so they only provide support for older DRAM standards.
 At the same time, current generation DRAM standards like DDR5, LPDDR5 and HBM3 operate at much higher frequencies than their predecessors, use novel interconnection techniques, and offer many new features, which requires special consideration for power modeling.
 To the best of our knowledge, there is no open-source DRAM power simulator that provides accurate models of both the DRAM core and interface, and supports current generation DRAM standards such as DDR5, LPDDR5 and HBM3.
-To close this gap, this paper presents DRAMPower 5, a completely revised version of the DRAMPower simulator, 
+To fill this gap, this paper presents DRAMPower 5, a completely revised version of the DRAMPower simulator, with a greatly enhanced feature set including both core and interface power modeling, an efficient simulation kernel, \todo{accuracy?} and support for the latest DRAM standards.
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-old calculations cannot be directly applied.
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-%However, modeling the power consumption of DRAM is intricate due to the diverse range of DRAM standards tailored for different applications, each with unique interface architectures (such as DIMM, POP, TSV, \dots), and varied power characteristics, particularly concerning the interface. Moreover, these standards present a significantly expanded feature set compared to earlier ones, including new types of refresh operations or power-down mechanisms.
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-%To the best of our knowledge, there exists no simulation tool that accurately models interface power and supports latest standards including DDR5, LPDDR5 and HBM3. Thus this paper presents a new DRAMPower simulator, called DRAMPower 5, which includes a new simulation kernel for a very efficient simulation, as well as the latest DRAM JEDEC standards. 
 
 This paper makes the following new contributions:
 \begin{itemize}
-    \item An accurate interface power modeling based on physical equations for different topologies and using either real data that is transmitted or toggling rates
+    \item We present newly developed core and interface power models that are required to accurately capture current generation DRAM standards.
-    \item Support of latest standards including DDR5, LPDDR5 and HBM3
+    \item We explain how the inconsistent and incomplete operating current specifications provided in the DRAM standards need to be treated to model core power.
-    \item Measurement conditions + Included new features like same/per-bank refresh, DBI, etc.
+    \item We show that at high operating frequencies, the approximations commonly used for interface power modeling result in large errors and a different modeling approach is required.
-    \item A new simulation kernel for fast DRAM power simulations, data-dependent POPCNT...
+    \item We present a new simulator architecture that can be easily extended by new standards or features and achieves high simulation speeds.
+    \item \todo{Accuracy simulations}
 \end{itemize}
 
-The rest of the paper is structured as follows ... 
+The rest of the paper is structured as follows \todo{...} 
 
 %\input{content/02_related_works}
 \section{Related Work}
@@ -555,11 +540,14 @@ Same-bank refresh for device with \textit{BG} bank groups and \textit{BA} banks
     E_{REFpb} = V_{DD} \cdot \left(I_{DD5Bsb} - I_{\circled{BG}}\right) \cdot t_{RFCsb}
 \end{equation}
 %
+%
 \section{Interface Power Modeling}
-\todo{in contrast to core power which is fixed for specific device, interface power depends on complete DRAM subsystem architecture}
-\todo{cite \cite{dalpou_98} \cite{bak_90}}
 %
 Interface power refers to the power consumed/dissipated by the input/output (I/O) circuitry that connects the memory controller and DRAM devices.
+In contrast to the core power, which is fixed for a specific device, the interface power depends on the complete DRAM subsystem architecture, i.e., the physical layer (PHY) of the memory controller, the channel architecture (ranks...), interconnect type...
+
+\todo{cite \cite{dalpou_98} \cite{bak_90}}
+%
 It can be divided into two parts:
 %
 \begin{itemize}
@@ -1075,7 +1063,7 @@ Finally, the switching activity $\alpha$ can be determined by counting the numbe
 %
 %
 %
-\section{Simulator Overview}
+\section{Simulator Architecture}
 %
 \todo{ranks}
 \todo{count 1, 0 and 0->1 based on issued commands and data, alternatively use average values}