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Update on Overleaf.

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Lukas Steiner
2024-11-14 15:31:46 +00:00
committed by node
parent d47c8d8f7c
commit 3bc18f10ac
2 changed files with 27 additions and 30 deletions
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drampower-main.tex
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@@ -891,7 +891,7 @@ Figure~\ref{fig:load_caps} shows the simple point-to-point connection with PODL
\end{figure}
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We analyze the power dissipation of this circuit for different operating frequencies as input using SPICE.
The components are dimensioned as $R_{ON}$ = \SI{40}{\ohm}, $R_{TT}$ = \SI{60}{\ohm}, $C_{TX}$ = $C_{RX}$ = \SI{1}{\pico\farad} and $V_{DDQ}$ = \SI{1.1}{\volt}, which is in the order of a real DDR5 interface.
The components are dimensioned as $R_{ON}$ = \SI{48}{\ohm}, $R_{TT}$ = \SI{60}{\ohm}, $C_{TX}$ = $C_{RX}$ = \SI{1}{\pico\farad} and $V_{DDQ}$ = \SI{1.1}{\volt}, which is in the order of a real DDR5 interface.
For now, the transmission line is also only modeled as a parasitic capacitance with $C_{TL}$ = \SI{2}{\pico\farad}.
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%\begin{figure}
@@ -913,7 +913,7 @@ For now, the transmission line is also only modeled as a parasitic capacitance w
% \label{fig:enter-label}
%\end{figure}
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At a frequency of \SI{100}{\mega\hertz}, the dissipated power is \SI{6.2}{\milli\watt}, which is close to the termination power of the circuit of \SI{6.1}{\milli\watt}.
At a frequency of \SI{100}{\mega\hertz}, the dissipated power is \SI{5.7}{\milli\watt}, which is close to the termination power of the circuit of \SI{6.1}{\milli\watt}.
However with increasing frequencies, the power also increases because the capacitors start to conduct.
At \SI{1600}{\mega\hertz} (i.e., 3.2\,Gbps/pin at DDR), the dissipated power is already \SI{8.6}{\milli\watt}, i.e., \SI{40}{\percent} higher than the pure termination power.
To calculate the power dissipation analytically, the clock signal with frequency $f$ and voltage swing $V_{DDQ}$ can be expressed as a Fourier series