Update on Overleaf.

drampower-main.tex

@@ -913,9 +913,9 @@ For now, the transmission line is also only modeled as a parasitic capacitance w
 %    \label{fig:enter-label}
 %\end{figure}
 %
-At a frequency of \SI{100}{\mega\hertz}, the dissipated power is \SI{5.7}{\milli\watt}, which is close to the termination power of the circuit of \SI{6.1}{\milli\watt}. 
+At a frequency of \SI{100}{\mega\hertz}, the dissipated power is \SI{5.7}{\milli\watt}, which is close to the termination power of the circuit of \SI{5.6}{\milli\watt}. 
 However with increasing frequencies, the power also increases because the capacitors start to conduct.
-At \SI{1600}{\mega\hertz} (i.e., 3.2\,Gbps/pin at DDR), the dissipated power is already \SI{8.6}{\milli\watt}, i.e., \SI{40}{\percent} higher than the pure termination power.
+At \SI{1600}{\mega\hertz} (i.e., DDR5-3200), the dissipated power is already \SI{8.6}{\milli\watt}, i.e., \SI{40}{\percent} higher than the pure termination power.
 To calculate the power dissipation analytically, the clock signal with frequency $f$ and voltage swing $V_{DDQ}$ can be expressed as a Fourier series 
 \begin{equation}
     v(t) = \frac{V_{DDQ}}{2} + \Re \left\{\frac{-2j \cdot V_{DDQ}}{\pi} \sum_{k=1,3,5,\dots}^{\infty} \frac{1}{k} \exp(j 2 \pi f k t)\right\}.  
@@ -964,18 +964,18 @@ Figure~\ref{fig:power_comp} shows the total power dissipation at different opera
         \begin{axis}[
             xlabel={Operating Frequency [MHz]},
             ylabel={Power Dissipation [mW]},
-            xmode=log,
-            xmin=50,
-            xmax=12800,
-            xtick={100,200,400,800,1600,3200,6400},
-            xticklabels={100,200,400,800,1600,3200,6400},
+            %xmode=log,
+            xmin=0,
+            xmax=8,
+            xtick={1,2,3,4,5,6,7},
+            xticklabels={100,200,400,800,1600,3200,4200},
             ybar,
             bar width=2mm,
             legend pos=north west
         ]
-        \addplot+ coordinates {(100,6.2) (200,5.1) (400,5.2) (800,5.4) (1600,5.8) (3200,6.47) (6400,7.09)};
-        \addplot+ coordinates {(100,6.2) (200,5.1) (400,5.2) (800,5.4) (1600,5.8) (3200,6.47) (6400,7.09)};
-        \addplot+ coordinates {(100,6.2) (200,5.1) (400,5.2) (800,5.4) (1600,5.8) (3200,6.6) (6400,8.2)};
+        \addplot+ coordinates {(1,5.7) (2,5.9) (3,6.2) (4,6.8) (5,7.75) (6,8.6) (7,8.8)};
+        \addplot+ coordinates {(1,5.7) (2,5.9) (3,6.2) (4,6.8) (5,7.75) (6,8.6) (7,8.8)};
+        \addplot+ coordinates {(1,5.7) (2,5.9) (3,6.1) (4,6.7) (5,7.75) (6,9.9) (7,11.2)};
         \legend{SPICE, Fourier Series (This Work), Approximation (CACTI-IO)}
         \end{axis}
     \end{tikzpicture}
@@ -983,8 +983,7 @@ Figure~\ref{fig:power_comp} shows the total power dissipation at different opera
     \label{fig:power_comp}
 \end{figure}
 % 
-While Equation~\ref{eq:fourier} always provides the same results as SPICE, Equation~\ref{eq:approx} is accurate at low frequencies, but overestimates the power dissipation at higher frequencies, e.g., by \SI{16}{\percent} at \SI{6400}{\mega\hertz}.
-If the capacitances $C_{TX}$ and $C_{RX}$ are increased from \SI{1}{\pico\farad} to \SI{2}{\pico\farad}, the error at \SI{6400}{\mega\hertz} is as high as \SI{54}{\percent}.
+While Equation~\ref{eq:fourier} always provides the same results as SPICE, Equation~\ref{eq:approx} is accurate at low frequencies, but overestimates the power dissipation at higher frequencies, e.g., by \SI{15}{\percent} at \SI{3200}{\mega\hertz} (DDR5-6400) and even \SI{27}{\percent} at \SI{4200}{\mega\hertz} (DDR5-8400, the highest specified data rate in the standard).
 
 The impact of the transmission line can be handled in different ways. 
 In \cite{holsta_19}, the authors have analyzed various physical DRAM interfaces, i.e., multi DIMM, package on package, PCB trace and silicon interposer.
@@ -1105,6 +1104,12 @@ Finally, the switching activity $\alpha$ can be determined by counting the numbe
 %
 \section{Simulator Architecture}
 %
+The new version of DRAMPower is not designed as a standalone simulator, but as a library that has to be coupled to a DRAM subsystem simulator, which models the DRAM controller and translates incoming read and write requests into DRAM commands. 
+Alternatively, a DRAM command trace can be provided as an input file.
+For interface power calculation, the provided commands, addresses and data are translated into equivalent series of logic levels. 
+Based on this data, the number of transmitted zeros $n_0$, transmitted ones $n_1$ and zero to one transitions $n_{0 \rightarrow 1}$ can be calculated.
+
+
 No standalone simulator, but coupled to e.g. DRAMSys
 \todo{ranks}
 \todo{count 1, 0 and 0->1 based on issued commands and data, alternatively use average values}