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\AtBeginDocument{%
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\copyrightyear{2023}
\acmYear{2023}
\setcopyright{acmlicensed}\acmConference[MEMSYS '23]{The International Symposium on Memory Systems}{October 2--5, 2023}{Alexandria, VA, USA}
\acmBooktitle{The International Symposium on Memory Systems (MEMSYS '23), October 2--5, 2023, Alexandria, VA, USA}
\acmPrice{15.00}
\acmDOI{10.1145/3631882.3631899}
\acmISBN{979-8-4007-1644-7/23/10}

\begin{document}

\title{A Precise Measurement Platform for LPDDR4 Memories}

\author{Johannes Feldmann}
\orcid{0009-0007-8989-7510}
\email{j.feldmann@rptu.de}
\affiliation{%
  \institution{University of Kaiserslautern-Landau}
  \city{Kaiserslautern}
  \country{Germany}
}

\author{Lukas Steiner}
\orcid{0000-0003-2677-6475}
\email{lukas.steiner@rptu.de}
\affiliation{%
  \institution{University of Kaiserslautern-Landau}
  \city{Kaiserslautern}
  \country{Germany}
}

\author{Derek Christ}
\orcid{0009-0005-4234-6362}
\email{derek.christ@iese.fraunhofer.de}
\affiliation{%
  \institution{Fraunhofer IESE}
  \city{Kaiserslautern}
  \country{Germany}
}

\author{Thomas Psota}
\orcid{0009-0009-3368-5396}
\email{thomas.psota@iese.fraunhofer.de}
\affiliation{%
  \institution{Fraunhofer IESE}
  \city{Kaiserslautern}
  \country{Germany}
}

\author{Matthias Jung}
\orcid{0000-0003-0036-2143}
\email{m.jung@uni-wuerzburg.de}
\affiliation{%
  \institution{JMU Würzburg}
  \city{Würzburg}
  \country{Germany}
}

\author{Norbert Wehn}
\orcid{0000-0002-9010-086X}
\email{norbert.wehn@rptu.de}
\affiliation{%
  \institution{University of Kaiserslautern-Landau}
  \city{Kaiserslautern}
  \country{Germany}
}

\renewcommand{\shortauthors}{Feldmann and Steiner et al.}

\begin{abstract}
LPDDR4, the most widely used low-power DRAM standard in the industry, plays a crucial role in modern system design. Understanding the non-functional properties of these DRAMs such as power consumption and reliability is essential for accurate system design, as the values reported in vendor's data sheets tend to be overly pessimistic compared to real-world performance. This research paper aims to characterize LPDDR4 memories of the three major vendors by conducting retention time and current measurements. To achieve these results, a custom measurement platform was developed, capable of precisely heating up the DRAM within a range of~$\pm\qty{1.0}{\celsius}$.
\end{abstract}

\begin{CCSXML}
<ccs2012>
   <concept>
       <concept_id>10010583.10010600.10010607.10010608</concept_id>
       <concept_desc>Hardware~Dynamic memory</concept_desc>
       <concept_significance>500</concept_significance>
       </concept>
   <concept>
       <concept_id>10010583.10010737.10010746</concept_id>
       <concept_desc>Hardware~Memory test and repair</concept_desc>
       <concept_significance>500</concept_significance>
       </concept>
   <concept>
       <concept_id>10010583.10010737.10010747</concept_id>
       <concept_desc>Hardware~Hardware reliability screening</concept_desc>
       <concept_significance>500</concept_significance>
       </concept>
   <concept>
       <concept_id>10010583.10010662.10010674</concept_id>
       <concept_desc>Hardware~Power estimation and optimization</concept_desc>
       <concept_significance>500</concept_significance>
       </concept>
 </ccs2012>
\end{CCSXML}

\ccsdesc[500]{Hardware~Dynamic memory}
\ccsdesc[300]{Hardware~Memory test and repair}
\ccsdesc[300]{Hardware~Hardware reliability screening}
\ccsdesc[500]{Hardware~Power estimation and optimization}
\keywords{DRAM, LPDDR4, Measurement}

%\received{20 February 2007}
%\received[revised]{12 March 2009}
%\received[accepted]{5 June 2009}

\maketitle

\section{Introduction}
Data-driven applications are increasingly becoming the focus of our information technology society. AI techniques disruptively change almost all areas of our society and economy. A common feature of all these applications is the enormous amount of data that needs to be captured, stored, and processed. As a result, external memory systems, particularly in System-on-Chip (SoC) or compute architectures, are gaining greater prominence. The state-of-the-art external memory systems are known as \textit{Dynamic Random Access Memories} (DRAM), which come in various types (DDRx, LPDDRx, HBMx, etc.). These different DRAM types vary significantly in their maximum bandwidths and latencies, storage capacity, reliability, and energy consumption. Of particular importance is energy consumption. Google recently demonstrated that more than \qty{90}{\percent} of system energy is consumed by large machine learning models in memory. In \textit{Augmented Reality Devices} for the Metaverse, according to Meta, memory can account for up to \qty{80}{\percent} of energy consumption. Hence, selecting the appropriate DRAM memory based on applications and system context is of utmost importance. Moreover, in autonomous systems, AI-driven signal processing of numerous sensor data requires DRAM memory, where reliability takes precedence alongside power consumption. Therefore, it is crucial for system design to thoroughly characterize the reliability and power consumption of DRAM memories.

This paper presents an in-depth analysis of LPDDR4 DRAMs, which recently hold significant usage in the industry, including consumer products and safety-critical systems such as \textit{Advanced Driving Assistant Systems} (ADAS) in automobiles. The primary focus of this analysis lies in assessing reliability, specifically retention errors, and power consumption. To accomplish this characterization, we devised a customized measurement platform to meticulously examine the DRAMs from the three major vendors.

\noindent In summary, the paper makes the following new contributions:
%
\begin{itemize}
    \item We present a precise retention error analysis that includes different temperature and data patterns, and compare the results of the measurements with the latest memory modules with previous measurements in literature.
    \item We present, to the best of our knowledge, for the first time, a current analysis of LPDDR4 DRAMs and compare the data with the vendor's data sheets. 
    \item We analyze the impact of the internal SEC-ECC on the reliability at different temperatures.
    \item From our results, we can conclude the internal array architectures of the different vendors.
    \item We present a sophisticated measurement platform that is capable to precisely heat up the DRAM and provide current measurements on all LPDDR4 voltage domains.
\end{itemize}

The paper is structured as follows: Section~\ref{sec:rel} presents the related work. The measurement platform is presented in~\ref{sec:meas}, whereas Section~\ref{sec:res} presents the experimental results. The paper is then finally concluded in Section~\ref{sec:con}.
%
\section{Related Work}\label{sec:rel}
%
There are several studies that analyze the retention behavior of DRAM chips. Kim and Lee presented in 2009 a detailed study on data retention times of nanoscaled DDR3 DRAMs~\cite{kimlee_09}. Most of the following investigations, for instance \cite{liujai_12,naikim_13,lucalv_14} and \cite{linshe_12}, are based on these results. However, the authors of \cite{junmat_16} showed with Wide I/O that even with high temperatures the majority of cells in this device can hold data much longer than 10,000s for a \texttt{0xFF} data pattern. Later they confirmed in~\cite{junmat_17} for a similar DDR3 DRAM Device (same vendor) from 2009 that the presented numbers by~\cite{kimlee_09} are way too pessimistic in the average case; DRAM cells can hold their value up to two orders of magnitude longer than assumed. 

All previously presented platforms for measuring DRAM reliability and power consumption have been DIMM-based (e.g., \cite{junmat_17} for DDR3 or \cite{matsch_18} for DDR4) and employ Peltier elements to heat up the DRAM. Other studies have utilized a thermal chamber to house the entire DRAM measurement system (e.g., \cite{patkim_17}). They present a study on 368 LPDDR4 devices. However, the authors do not disclose any details about their measurement platform beside that they used a thermal chamber. The authors of~\cite{liujai_13} analyze the data retention behavior with respect to temperature, DPD, and VRT. However, they measure the retention times only for several seconds (< \qty{10}{\second}) and use a thermal chamber. 

Rahmati et al. \cite{rahhic_14} also use a thermal chamber, but moreover, they analyze a DRAM device from the 90's. Therefore, their results have absolutely no relevance for nowadays DDR4/5 world. The authors of~\cite{houli_13} measure only short retention times (<\qty{3}{\second}) and only one bank of one single DDR3 DRAM. Therefore, their results do not consider process variations. Moreover, they do not disclose details about their measurement setup, e.g. how they heat up the DRAM.

However, placing the entire measurement system within the thermal chamber may introduce undesired effects on the system itself, potentially influencing the results. Moreover, these platforms utilize the DIMM's temperature sensor, which does not provide the actual chip temperature as it is not physically integrated into the DRAM chips. Therefore, it is important to directly heat up and measure the devices in order to obtain realistic results. 

In~\cite{venher_06} the authors measure the number of faulty pages with respect to ambient temperature and time. They heat up the DRAM chip manually by using a heat gun, which has the drawback that stabilizing the temperature over several hours is impossible.  

\section{Measurement Platform}\label{sec:meas}
%
\begin{figure}
    \centering
    \includegraphics[width=\linewidth]{block_diagram.pdf}
    \caption{Block-Diagramm of Measurement Plattform}
    \label{fig:block}
\end{figure}
%
DIMM-based systems offer more convenient measurement, since off-the-shelf FPGA boards can be used. In such scenarios, currents can be measured using a specially designed adapter, as shown in~\cite{junmat_17, matsch_18}. However, low-power DRAM systems like LPDDR4 do not utilize DIMMs; instead, the devices are directly soldered onto the \textit{Printed Circuit Board} (PCB) of the computing system or even use \textit{Package on Package} (PoP) technology. This presents a significant challenge, as it necessitates the design of an entire PCB, including FPGA and device socket, as a single adapter is insufficient for the measurement process. Therefore, we designed a custom measurement platform which allows a precise current and retention measurement while temperatures can be regulated with an accuracy of $\pm\qty{1.0}{\celsius}$. In the following we will describe the components of the platform, shown in Figure~\ref{fig:block}.

\paragraph{System on Chip (SoC)}
The measurement platform utilizes the Xilinx Zynq Ultrascale+ XCZU3EG-1SFVA625E, a \textit{Multiprocessor System on Chip} (MPSoC), as its primary control unit. All essential tasks for conducting the measurements are executed on this platform. These tasks encompass heat regulation, generation of DRAM data patterns, measurement of current and retention time, and the storage of acquired data.

Since the DRAM itself is the subject to test, it remains unavailable for use by the measurement software. The sole available main memory accessible to the software was a 256 kB on-chip SRAM memory. As a solution, we developed a microkernel tailored to operate on the four cores, optimized to fully reside within the platform's on-chip memory. The purpose of the microkernel was to run diagnostics by filling the whole DRAM with certain specified patterns, while simultaneously controlling the output of the heating component. Each core was allocated for distinct functions within the system, encompassing tasks such as pattern writing and reading, heat control, and communication. Interaction with the platform was facilitated through the serial bus, enabling the exchange of JSON messages. These messages facilitated operations such as triggering new test runs, soliciting board diagnostics, and retrieving test results, all managed by external PC software written in Qt, as depicted in Figure~\ref{fig:software}.

\paragraph{DRAM Connection and Socket}
In contrast to DDR4, which is typically linked to the target platform through a DIMM inserted into the appropriate socket, LPDDR4 is commonly soldered directly onto the PCB. This soldered configuration poses challenges for a measurement platform, as replacing the DRAM devices could lead to damage to both the device and the PCB. To address this, our measurement platform features an Ironwood SBT-BGA200 socket, facilitating swift interchangeability of LPDDR4 devices, including those of varying dimensions. This socket-based approach obviates the need for soldering of both the socket and the device itself. All test devices are connected to the hard IP memory controller of the Xilinx Zynq Ultrascale+. The measurement platform achieves a maximum data rate of \qty{2133}{Mb/s/pin}. 

\paragraph{Current Measurement Circuit}
The measurement platform features four independent current measurement channels to measure all three supply currents of the LPDDR4 ($VDD_1$, $VDD_2$, $VDD_Q$) and the $VCCO_{PSDDR}$ voltage domain of the Zynq Ultrascale+.
Each current is measured using a shunt resistor, which is connected in series to the device.
All resistance values were carefully selected to maximize the voltage drop across the shunt resistor while guaranteeing sufficient supply voltage to the device.
The chosen values are listed in Table~\ref{tab:shunt_res}. 
The voltage drop across each resistor is first filtered using a low-pass filter with a cut-off frequency of \qty{1.6}{MHz} and amplified with a factor of 200 using high-precision current sense amplifiers (Analog Devices MAX44284W).
The amplified voltages are synchronously sampled by a 24-bit analog-to-digital converter (ADC) of type MAX11040K as well as the corresponding supply voltages itself using a cascaded device.
These ADCs are connected to the Xilinx Zynq Ultrascale+, which processes the data.
The measurement board provides also the option to measure the amplified voltages using a oscilloscope.

\begin{table}[!ht]
    \centering
    \begin{tblr}{l|c}
        Voltage domain & Shunt resistance \\
        \hline
        $VDD_1$ & $ 750\, m \Omega $ \\
        $VDD_2$ & $ 27\, m \Omega $ \\
        $VDD_Q$ & $ 120\, m \Omega $ \\
        $VCCO_{PSDDR}$ & $ 50\, m \Omega $ \\
    \end{tblr}
    \caption{Shunt resistor of current measurement circuit}
    \label{tab:shunt_res}
\end{table}

\paragraph{I/O Interfaces}
The measurement platform offers a variety of I/O interfaces. A 1000BASE-T Ethernet connection provides remote access to the platform. A separate UART is used to print debug outputs which offers the opportunity to monitor the measurement procedure in detail. The UART can be accessed via USB using an FTDI UART-to-USB IC. Two micro-sd card slots are available to store all measured data. Additionally, there are several buttons, switches, leds, and I/O header which offer user communication as well as extension capabilities.

\paragraph{Heating Element}
The heating element, which is attached to the LPDDR4 socket, consists of a CNC manufactured copper block which contains a \qty{12}{V} heating cartridge as well as a temperature sensor. To isolate the heating element from the surrounding air, a 3D-printed cover, called the \enquote{Dome}, consisting of air-filled chambers is put over the heating element and the socket containing the DRAM, c.f. Figure~\ref{fig:plattform:image}. The \qty{20}{W} heating cartridge can be controlled by the SoC using pulse width modulation. The current temperature is measured using a MCP9700A sensor, which is connected to the internal ADC of the Xilinx Zynq Ultrascale+.

\begin{figure}
    \centering
    \includegraphics[width=\linewidth]{layout.png}
    \caption{PCB Layout}
    \label{fig:layout}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=\linewidth]{sw.png}
    \caption{Control Software}
    \label{fig:software}
\end{figure}

\begin{figure*}
    \begin{tikzpicture}
        \node[anchor=south west,inner sep=0] at (0,0)       
            {\includegraphics[width=\textwidth]{DSC03604.JPG}};
        \draw[red,ultra thick,rounded corners]
            (12.25,3.3) rectangle (17.0,8.2);
        \draw[red](14.625,8.75) node[](){\Large The \enquote{Dome}};
        \draw[red](11.0,4.5) node[](){\Large FPGA};
        \draw[red](15.0,2.5) node[](){\Large Current Measurement};
    \end{tikzpicture}
    \caption{Developed Measurement Platform}
    \label{fig:plattform:image}
\end{figure*}
%
\section{Experimental Results}\label{sec:res}
%
With the presented platform of Section~\ref{sec:meas} we conducted several measurements with respect to retention time and power consumption. 
%
\subsection{Retention Analysis}

The first set of experiments is an analysis of the data pattern dependencies that have been reported in previous studies, e.g.,~\cite{matsch_18}. Therefore, we conducted experiments with LPDDR4 using \texttt{0x00}, \texttt{0x55}, \texttt{0xAA}, \texttt{0xFF} and random data patterns. With these patterns it is possible to reverse engineer the internal DRAM architecture. Some DRAM vendors use only true-cells, other vendors are mixing true- and anti-cells in their DRAM architectures, where a true-cell stores the data value as it is and an anti-cell stores the inverse~\cite{liujai_13}. The reason for that is the architecture of the array and the primary sense amplifier. In order to analyze the data pattern dependencies, we analyzed one LPDDR4 device for each vendor. With these measurements it is also possible to rate the reliability, e.g., for \textit{Approximate DRAM} scenarios. 

For this purpose, the DRAM refresh is temporarily disabled, and the number of errors is measured within this time frame. It is important to highlight that all vendors meet the claimed reliability standards for typical refresh rates as required in the JEDEC standards (e.g., \qty{64}{\milli\second}).

For Vendor-A, we observe errors for all data patterns, as shown in Figure~\ref{fig:micron}, indicating the usage of a mixed true- and anti-cell DRAM. In contrast, Vendor-B (Figure~\ref{fig:samsung}) and Vendor-C (Figure~\ref{fig:hynix}) do not exhibit errors for the \texttt{0x00} data pattern, implying a true-cell DRAM. The data pattern dependency for Vendor-A is minimal, while the other two vendors show a much higher data pattern dependency. Notably, for Vendor-B and Vendor-C, the majority of errors occur with the \texttt{0xFF} pattern, which aligns with the true-cell architecture. Conversely, Vendor-A experiences most errors with random data patterns. 

To estimate the variance across multiple devices, we conducted measurements on five different devices from each vendor using a random pattern. The results are illustrated in Figure~\ref{fig:spread}, where we present the maximum, minimum, and average errors. Among the vendors, Vendor-A exhibits the highest variance, while Vendor-C shows a medium variance, and Vendor-B has the lowest variance. A direct comparison between the vendors is depicted in Figure~\ref{fig:comp}, whereas Figure~\ref{fig:comp} shows the same results in a linear form instead of logarithmic. Notably, at elevated temperatures, the performance disparity becomes evident, particularly with Vendor-A being considerably less reliable compared to Vendor-B and Vendor-C. Nonetheless, as mentioned before, all vendors meet the claimed reliability standards when the DRAM is used within the specification. Table~\ref{tab:comp} summarizes the qualitatively the measured results. 

LPDDR4 is the first JEDEC standard that allows the integration of in-DRAM ECC into devices. For the tested devices the used ECC is a \textit{Single Error Correction} (SEC) (136,128) shortened Hamming code~\cite{kwoseo_17, leeeom_17}. 
We analyzed the performance of this ECC for Vendor-A and compared it with previous DDR4 measurements for the same vendor from~\cite{matsch_18}, as shown in Figure~\ref{fig:ddr4}. 

It is important to note that DDR4 uses an external ECC engine placed inside the memory controller, which covers all errors from the DRAM cell up to the memory controller, whereas LPDDR4's ECC engine can only correct errors that appear within the memory array. Furthermore, it might be that for both devices different DRAM technologies are used.
However, from an information-theoretical perspective, the (136,128) shortened Hamming code used in LPDDR4 devices has a higher code rate than the (72,64) shortened Hamming code of DDR4's external ECC engine. Thus, its error correction capability is lower. This general trend can also be observed in our measurements. 

Furthermore, we compared our results with prior art~\cite{patkim_17}, as shown in Figure~\ref{fig:onur}. They measured at \qty{45}{\celsius} in a thermal chamber. Their values are closer to our \qty{60}{\celsius} results than to our \qty{30}{\celsius}. This might be because of the usage of a thermal chamber, which also extensively heats up the DRAM interface on the FPGA side, or they have used an earlier generation of LPDDR4 devices. Unfortunately, they do not disclose their measurement setup and the DRAMs they have analyzed.
%
\subsection{Current Measurements}
%
Using the measurement circuit presented in Section~\ref{sec:meas}, we conducted current measurements for all three voltage domains, namely $VDD_1$, $VDD_2$, and $VDD_Q$. Figure~\ref{fig:current} illustrates the measured currents, and the total current $I_{\text{total}}$ is calculated as the sum of $I_1$, $I_2$, and $I_Q$. However, it was not possible to accurately measure the write current IDD4W*, as the FPGA platform cannot send two write requests consecutively. Similarly, measuring the \texttt{ACT-PRE} current IDD0* in a JEDEC-compliant manner was not feasible, as it was not possible to execute \texttt{ACT} and \texttt{PRE} commands consecutively due to the absence of this feature in hard-IP memory controller of the FPGA. Instead, IDD0* reflects the sequence \texttt{ACT-RD-PRE}. Therefore, these two currents only provide approximate values, but they are still valid for comparing different vendors. For Vendor-C, no datasheet was provided. Notably, we observed that the values in the datasheet are overly pessimistic (especially for Vendor-B) compared to the measured results.  These measurements can be invaluable to system designers in optimizing the power planning and ensuring a more optimistic design.

\begin{table}[]
    \centering
    \begin{tblr}{c|lllll}
        ~ & Type & DPD & Variance & SEC & Most Errors\\\hline
        A & Mixed-Cell & very low & medium & yes & random\\
        B & True-Cell & low & low & yes & 0xFF\\
        C & True-Cell & low & very low & yes & 0xFF\\
    \end{tblr}
    \caption{Qualitative Comparison of Vendors}
    \label{tab:comp}
\end{table}

%
\section{Conclusion}\label{sec:con}
This paper focuses on the analysis of LPDDR4 DRAMs, which are widely used in various applications, including consumer products and safety-critical systems like \textit{Advanced Driving Assistant Systems} (ADAS) in cars. The study centers around assessing the reliability and power consumption of these DRAMs. To achieve this, we designed a customized measurement platform capable of accurately characterizing the DRAMs from the three major vendors. The paper makes several notable contributions, including a precise retention error analysis with different temperature and data patterns, a current analysis of LPDDR4 DRAMs, an evaluation of internal SEC-ECC impact on reliability at different temperatures, and insights into the internal array architectures of the vendors. We demonstrated that the datasheet values provided by the vendors were overly pessimistic. The study's results offer valuable information to system designers for optimizing power planning and layout design. 
%
\begin{acks}
We thank \anon{Martin Schultheis} and Mercedes-Benz for their support. This paper was partially funded by the Federal Minestry of Education and Research (BMBF) within the \anon{MEMTONOMY-2} project (\anon{16ME0716K}).
\end{acks}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\begin{figure*}[p]
     \centering
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/micron_30}
         \caption{\qty{30}{\celsius}}
         \label{fig:micron:30}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/micron_60}
         \caption{\qty{60}{\celsius}}
         \label{fig:micron:60}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/micron_80}
         \caption{\qty{80}{\celsius}}
         \label{fig:micron:80}
     \end{subfigure}
        \caption{Data Pattern Analysis Vendor-A}
        \label{fig:micron}
\end{figure*}
%
\begin{figure*}[p]
     \centering
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/samsung_30}
         \caption{\qty{30}{\celsius}}
         \label{fig:samsung:30}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/samsung_60}
         \caption{\qty{60}{\celsius}}
         \label{fig:samsung:60}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/samsung_80}
         \caption{\qty{80}{\celsius}}
         \label{fig:samsung:80}
     \end{subfigure}
        \caption{Data Pattern Analysis Vendor-B}
        \label{fig:samsung}
\end{figure*}
%
\begin{figure*}[p]
     \centering
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/hynix_30}
         \caption{\qty{30}{\celsius}}
         \label{fig:hynix:30}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/hynix_60}
         \caption{\qty{60}{\celsius}}
         \label{fig:hynix:60}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/hynix_80}
         \caption{\qty{80}{\celsius}}
         \label{fig:hynix:80}
     \end{subfigure}
        \caption{Data Pattern Analysis Vendor-C}
        \label{fig:hynix}
\end{figure*}

\newpage

\begin{figure*}[p]
     \centering
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/micron_spread}
         \caption{Vendor-A}
         \label{fig:spread:a}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/samsung_spread}
         \caption{Vendor-B}
         \label{fig:spread:b}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/hynix_spread}
         \caption{Vendor-C}
         \label{fig:spread:c}
     \end{subfigure}
        \caption{Spread of Retention Errors for 5 Devices for each Vendor with Random Data Pattern}
        \label{fig:spread}
\end{figure*}

\begin{figure*}[p]
     \centering
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/comp_30}
         \caption{\qty{30}{\celsius}}
         \label{fig:comp:30}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/comp_60}
         \caption{\qty{60}{\celsius}}
         \label{fig:comp:60}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/comp_80}
         \caption{\qty{80}{\celsius}}
         \label{fig:comp:80}
     \end{subfigure}
        \caption{Comparison of Different Vendors with Random Data Pattern (log)}
        \label{fig:comp}
\end{figure*}

\begin{figure*}[p]
     \centering
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/comp2_30}
         \caption{\qty{30}{\celsius}}
         \label{fig:comp2:30}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/comp2_60}
         \caption{\qty{60}{\celsius}}
         \label{fig:comp2:60}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/comp2_80}
         \caption{\qty{80}{\celsius}}
         \label{fig:comp2:80}
     \end{subfigure}
        \caption{Comparison of Different Vendors with Random Data Pattern (linear)}
        \label{fig:comp2}
\end{figure*}

\newpage

%%%%%%%%%%%%%%%%%%

\begin{figure*}[p]
     \centering
     \begin{subfigure}[b]{0.45\textwidth}
         \centering
         \input{plots/ddr4_30}
         \caption{\qty{30}{\celsius}}
         \label{fig:ddr4:30}
     \end{subfigure}
     \hfill
     \begin{subfigure}[b]{0.45\textwidth}
         \centering
         \input{plots/ddr4_60}
         \caption{\qty{60}{\celsius}}
         \label{fig:ddr4:60}
     \end{subfigure}
     %\hfill
     %\begin{subfigure}[b]{0.33\textwidth}
     %    \centering
     %    \input{plots/ddr4_90}
     %    \caption{\qty{80}{\celsius}}
     %    \label{fig:ddr4:90}
     %\end{subfigure}
        \caption{Comparison of DDR4 SECDED with LPDDR4 SEC}
        \label{fig:ddr4}
\end{figure*}


\begin{figure*}[p]
    \centering
    \input{plots/onur}
    \caption{Comparison with Results of \cite{patkim_17}}
    \label{fig:onur}
\end{figure*}

\begin{figure*}[p]
     \centering
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/micron_current}
         \caption{Vendor-A}
         \label{fig:current:30}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/samsung_current}
         \caption{Vendor-B}
         \label{fig:current:60}
     \end{subfigure}
     %\hfill
     \begin{subfigure}[b]{0.33\textwidth}
         \centering
         \input{plots/hynix_current}
         \caption{Vendor-C}
         \label{fig:current:90}
     \end{subfigure}
        \caption{Currents for Different Vendors}
        \label{fig:current}
\end{figure*}


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