From ec68db33d7f6f59ee39b33f259b491efac8b1b7d Mon Sep 17 00:00:00 2001
From: Anonymous <anonymous@overleaf.com>
Date: Thu, 15 Aug 2024 01:18:15 +0000
Subject: [PATCH] Update on Overleaf.

---
 analyzer.png                                  |   Bin 0 -> 488246 bytes
 analyzer_DDR5.png                             |   Bin 0 -> 221170 bytes
 dram.pdf                                      |   Bin 0 -> 53297 bytes
 dram.svg                                      |  5324 ++
 dramsys-thermal-fraunhofer-iese.png           |   Bin 0 -> 1760567 bytes
 dramsys-traceanalyzer-fraunhofer-iese.png     |   Bin 0 -> 1077105 bytes
 dramsys_tc.pdf                                |   Bin 0 -> 39792 bytes
 dramsys_tc_small.pdf                          |   Bin 0 -> 39063 bytes
 ...cies_all_bank_DDR5_4000_16Gb_SR_counts.csv |   954 +
 ...es_no_refresh_DDR5_4000_16Gb_SR_counts.csv |   802 +
 ...ies_same_bank_DDR5_4000_16Gb_SR_counts.csv |   782 +
 main.tex                                      |  2915 +
 methology.pdf                                 |   Bin 0 -> 27079 bytes
 methology.svg                                 |   700 +
 references_JR.bib                             | 56012 ++++++++++++++++
 test.csv                                      |     7 +
 tool_demo.tex                                 |   181 +
 17 files changed, 67677 insertions(+)
 create mode 100644 analyzer.png
 create mode 100644 analyzer_DDR5.png
 create mode 100644 dram.pdf
 create mode 100644 dram.svg
 create mode 100644 dramsys-thermal-fraunhofer-iese.png
 create mode 100644 dramsys-traceanalyzer-fraunhofer-iese.png
 create mode 100644 dramsys_tc.pdf
 create mode 100644 dramsys_tc_small.pdf
 create mode 100644 latencies_all_bank_DDR5_4000_16Gb_SR_counts.csv
 create mode 100644 latencies_no_refresh_DDR5_4000_16Gb_SR_counts.csv
 create mode 100644 latencies_same_bank_DDR5_4000_16Gb_SR_counts.csv
 create mode 100644 main.tex
 create mode 100644 methology.pdf
 create mode 100644 methology.svg
 create mode 100644 references_JR.bib
 create mode 100644 test.csv
 create mode 100644 tool_demo.tex

diff --git a/analyzer.png b/analyzer.png
new file mode 100644
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diff --git a/dram.svg b/dram.svg
new file mode 100644
index 0000000..9acd3cc
--- /dev/null
+++ b/dram.svg
@@ -0,0 +1,5324 @@
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+
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+   xmlns:xlink="http://www.w3.org/1999/xlink"
+   xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
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+   id="svg8"
+   inkscape:version="0.92.4 (5da689c313, 2019-01-14)"
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diff --git a/latencies_all_bank_DDR5_4000_16Gb_SR_counts.csv b/latencies_all_bank_DDR5_4000_16Gb_SR_counts.csv
new file mode 100644
index 0000000..ac621eb
--- /dev/null
+++ b/latencies_all_bank_DDR5_4000_16Gb_SR_counts.csv
@@ -0,0 +1,954 @@
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diff --git a/latencies_no_refresh_DDR5_4000_16Gb_SR_counts.csv b/latencies_no_refresh_DDR5_4000_16Gb_SR_counts.csv
new file mode 100644
index 0000000..054df0a
--- /dev/null
+++ b/latencies_no_refresh_DDR5_4000_16Gb_SR_counts.csv
@@ -0,0 +1,802 @@
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diff --git a/latencies_same_bank_DDR5_4000_16Gb_SR_counts.csv b/latencies_same_bank_DDR5_4000_16Gb_SR_counts.csv
new file mode 100644
index 0000000..28eb35d
--- /dev/null
+++ b/latencies_same_bank_DDR5_4000_16Gb_SR_counts.csv
@@ -0,0 +1,782 @@
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diff --git a/main.tex b/main.tex
new file mode 100644
index 0000000..b406ede
--- /dev/null
+++ b/main.tex
@@ -0,0 +1,2915 @@
+\makeatletter
+\p@=1bp
+\makeatother\documentclass[10pt,oneside,twocolumn,a4paper]{article}
+\usepackage{graphicx}
+\usepackage[dvipsnames]{xcolor}
+\usepackage{pgfplots}
+\usepackage{rotating}
+\pgfplotsset{compat=1.12}
+%% Font: Times
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage{tabularx}
+\usepackage{ragged2e}
+\usepackage[singlelinecheck=false]{caption}
+\usepackage[T1]{fontenc}
+\usepackage[numbers]{natbib}
+\usepackage{amsmath}
+\usepackage{xcolor}
+\usepackage{caption}
+\usepackage{subcaption}
+\usepackage[english]{babel}
+\newcommand\todo[1]{\textcolor{blue}{#1}}
+\def\figurename{Figure}%
+\def\tablename{Table}%
+\RequirePackage[blocks]{authblk}
+\usepackage{babel}
+\pagestyle{empty}
+\hoffset-1in
+\voffset-1in
+\oddsidemargin20truemm
+
+\usepackage{multirow}
+%\usepackage{draftwatermark}
+%\SetWatermarkText{Draft}
+%\SetWatermarkScale{2}
+
+\usepackage{listings}
+\definecolor{darkgreen}{rgb}{0,0.43,0}
+
+\lstdefinelanguage{DRAMml}{
+    keywords={},
+    otherkeywords={% Operators
+    ->, ->>, -<>, -o, *\\
+    },
+    keywordstyle=\color{blue}\bfseries,
+    keywords=[2]{DRAM, Timings, Bank, Bankgroup, Places, Transitions, Arcs, TimingConstraints, WARNING},
+    keywordstyle=[2]\color{darkgreen}\bfseries,
+    identifierstyle=\color{black},
+    sensitive=false,
+    comment=[l]{//},
+    morecomment=[s]{/*}{*/},
+    commentstyle=\color{gray},
+    stringstyle=\color{red},
+    morestring=[b]',
+    morestring=[b]"
+}
+
+\makeatletter
+\let\ps@plain\ps@empty
+\def\@xivpt{14bp}
+
+\setcounter{secnumdepth}{4}
+\columnsep5mm
+\def\@sect#1#2#3#4#5#6[#7]#8{%
+  \ifnum #2>\c@secnumdepth
+    \let\@svsec\@empty
+  \else
+    \refstepcounter{#1}%
+    \protected@edef\@svsec{%
+      \ifnum #2<4
+        \hb@xt@10mm{\csname the#1\endcsname}\relax
+      \else
+        \hb@xt@12mm{\csname the#1\endcsname}\relax
+      \fi}%
+  \fi
+  \@tempskipa #5\relax
+  \ifdim \@tempskipa>\z@
+    \begingroup
+      #6{%
+        \@hangfrom{\hskip #3\relax\@svsec}%
+          \interlinepenalty \@M #8\@@par}%
+    \endgroup
+    \csname #1mark\endcsname{#7}%
+    \addcontentsline{toc}{#1}{%
+      \ifnum #2>\c@secnumdepth \else
+        \protect\numberline{\csname the#1\endcsname}%
+      \fi
+      #7}%
+  \else
+    \def\@svsechd{%
+      #6{\hskip #3\relax
+      \@svsec #8}%
+      \csname #1mark\endcsname{#7}%
+      \addcontentsline{toc}{#1}{%
+        \ifnum #2>\c@secnumdepth \else
+          \protect\numberline{\csname the#1\endcsname}%
+        \fi
+        #7}}%
+  \fi
+  \@xsect{#5}}
+    %
+\renewcommand\LARGE{\@setfontsize\LARGE{16}{20}}
+%\def\abstract#1{\def\@abstract{#1}}
+\def\abstractEn#1{\def\@abstractEn{#1}}
+\def\titleEn#1{\def\@titleEn{#1}}
+%% Def. Titelei
+\headheight0bp
+\headsep0mm
+\topskip10bp
+\topmargin18mm
+\textwidth170mm
+\textheight60\baselineskip
+\def\@maketitle{%
+  \newpage
+  \null
+  \let \footnote \thanks
+    %{\LARGE\bfseries\RaggedRight \@title \par}%
+    {\LARGE\bfseries\RaggedRight \@titleEn \par}%
+    \vskip 1\baselineskip%
+    {\normalsize
+      % \lineskip 1ex%
+      \@author\par}%
+    \vskip 2\baselineskip%
+    %{\section*{Kurzfassung}
+    %  \@abstract}%
+    %\vskip \baselineskip%
+    {\section*{Abstract}
+      \@abstractEn}%
+  \par
+  \vskip 3\baselineskip}
+
+\renewcommand\section{\@startsection {section}{1}{\z@}%
+                                   {-3.5ex \@plus -1ex \@minus -.2ex}%
+                                   {\baselineskip}%
+                                   {\normalfont\Large\bfseries\RaggedRight}}
+\renewcommand\subsection{\@startsection{subsection}{2}{\z@}%
+                                     {\baselineskip}%
+                                     {1ex}%
+                                     {\normalfont\large\bfseries\RaggedRight}}
+\renewcommand\subsubsection{\@startsection{subsubsection}{3}{\z@}%
+                                     {1\baselineskip}%
+                                     {3bp}%
+                                     {\normalfont\normalsize\bfseries\RaggedRight}}
+\renewcommand\paragraph{\@startsection{paragraph}{4}{\z@}%
+                                    {1\baselineskip\@plus1ex \@minus.2ex}%
+                                    {3bp}%
+                                    {\normalfont\normalsize\RaggedRight}}
+\renewcommand\subparagraph{\@startsection{subparagraph}{5}{\parindent}%
+                                       {3.25ex \@plus1ex \@minus .2ex}%
+                                       {-1em}%
+                                      {\normalfont\normalsize\bfseries\RaggedRight}}
+\affilsep0pt
+\parindent\p@
+\makeatother
+\bibsep3bp
+\raggedbottom
+\DeclareCaptionLabelSeparator{enskip}{\enskip}
+\captionsetup{labelsep=enskip,justification=RaggedRight,labelfont=bf,skip=10pt}
+\renewcommand\bibsection{\section{Bibliography}}
+%\title{Beitragstitel (16 pt fett)}
+\titleEn{Exploration of DDR5 with the Open-Source Simulator DRAMSys}
+\author{M.Sc. Lukas Steiner$\,^1$,
+Dr.-Ing. Matthias Jung$\,^2$,
+Prof. Dr.-Ing. Norbert Wehn$\,^1$
+}
+\affil{%
+1: Technische Universität Kaiserslautern, Germany \{lsteiner, wehn\}@eit.uni-kl.de\\
+2: Fraunhofer IESE, Kaiserslautern, Germany, matthias.jung@iese.fraunhofer.de
+}
+
+\abstractEn{%
+Over the last five decades, we have seen a continuous evolution in DRAM technology, always targeting lower cost per bit, higher device capacity, higher bandwidth, and lower power consumption. The most recent DRAM standard released by JEDEC in mid 2020 is DDR5. It exhibits several new features, for example two channels on a single DIMM, same-bank refresh, and data rates up to 8400\,MT/s. As a result, DDR5 greatly enlarges the DRAM device options, while the selection of a suitable device heavily depends on the application. In this paper, we investigate the performance of the new DDR5 standard in depth, compare it to its predecessor DDR4, and derive key observations that help selecting a suitable DRAM configuration. We present a new DDR5 simulation model based on the open-source simulator DRAMSys. This is to the best of our knowledge the first DDR5 simulation model. The model is the base for all of our investigations.
+% Extremfälle für Anwendung
+% seine Stärken ausspielen
+% zwei grundverschiedene Benchmarks
+% In recent years, more and more DRAM standards have been specified, which in parts differ significantly from previous ones. The latest standard released by JEDEC in mid 2020 is DDR5.
+% It poses new features, for example two channels on a DIMM, same bank refresh and data rates up to 8400 MT/s. For system designers, DDR5 greatly enlarges the total DRAM design space, where certain design choices are not trivial depending on the application that uses the memory system. 
+% In this paper, we present for the first time a new DDR5 simulation model based on the open-source simulator DRAMSys. This simulation model can help designers to efficiently explore the DRAM design space and to find the best fitting DRAM solution for their application, and moreover, to find suitable optimizations for the memory subsystem. Furthermore, we show a first quantitative comparison between DDR4 and DDR5 for two typical example benchmarks.
+%
+}
+% TODOs: make DRAMSys DRAMSys4.0 consistent
+
+\hyphenation{DRAMSys} % prevent DRAMSys to be hyphened
+
+\begin{document}
+
+\maketitle
+
+\section{Introduction}
+Currently, we see a strong shift to memory-dominated applications. Thus, \textit{Dynamic Random Access Memories} (DRAMs) play a large role in compute platforms. Over the last years, the number of DRAM standards specified by the \textit{JEDEC Solid State Technology Association} has been growing rapidly. The most recent DRAM standard is DDR5, which was released in mid 2020. Because of the large amount of new features, system designers are either challenged to adopt the new standard or they can move on with well-established standards like DDR4. If DDR5 is a potential candidate for a specific application, a further challenge is the configuration of the DDR5 subsystem, which features a lot of parameter choices. Fast and accurate simulation models are mandatory to explore the new features and compare different configurations.
+
+For our investigations we use the design space exploration framework DRAMSys, which relies on a \textit{Domain Specific Language} (DSL) to specify the DRAM's architecture, states, and timing behavior in a compressed and comprehensive fashion. This DSL, called \textit{DRAMml}~\cite{junkra_19}, is based on a Petri Net semantic~\cite{pet_62} and allows correct-by-construction source code generation for DRAMSys. To achieve a high simulation speed and high accuracy at the same time, the framework makes use of SystemC \textit{Transaction Level Modeling} (TLM) and only simulates relevant state changes instead of individual signal changes in each clock cycle. In this way, the overall number of events is reduced drastically and performance results can be generated several orders of magnitude faster compared to an RTL simulation while maintaining the same accuracy.
+
+By using DRAMml for the source code generation, we were able to create a full-featured DDR5 simulation model from scratch within two weeks. This shows the applicability of the DRAMml methodology within the DRAMSys framework for the adoption of new DRAM standards.
+
+In this paper, we compare the DDR5 standard to its predecessor DDR4 and investigate advantages and disadvantages for specific applications. Furthermore, we perform an in-depth analysis of different DDR5 configurations.
+%
+\begin{figure*}[t]
+    \includegraphics[width=\textwidth]{dram.pdf}
+    \caption{DRAM Architecture}
+    \label{fig:dram}
+\end{figure*}
+%
+In summary, the paper presents three new contributions:
+\begin{itemize}
+    \item We present the first DDR5 simulation model, which is integrated in the DRAMSys framework.
+    \item We provide an in-depth comparison between DDR5 and DDR4. 
+    \item We investigate the performance of different DDR5 configurations.
+\end{itemize}
+%qual., quant.
+The paper is structured as follows: Section 2 gives some background on DRAM technology and the new main features of the DDR5 standard. In Section 3 we describe the DRAM design space exploration framework DRAMSys. The integration of the DDR5 model is described in Section 4. Experiments and key observations are presented in Section 5. In Section 6 the related work is reviewed and the paper is concluded by Section 7.
+%
+%
+\section{DRAM Background and DDR5}
+%
+In this section we introduce the basic terminology of DRAM devices and their controllers and give an overview on the new features of the DDR5 standard.
+%
+\newcommand{\rot}[0]{22.4}
+\begin{figure}[t]
+\resizebox{\columnwidth}{!}{% <------ Don't forget this %
+\begin{tikzpicture}
+\begin{loglogaxis}[
+	ylabel={\textbf{Bandwidth [GB/s]}},
+	xlabel={\textbf{Pin Data Rate [MT/s]}},
+    height = 14cm,
+    grid=both,
+    major grid style={black!50},
+    width = \textwidth,
+    height = 0.9\textheight,
+    xmin = 600,
+    xmax = 13000
+]
+
+% HBM
+\addplot[Orange, line width=3.1mm, line cap=round] coordinates { (2*500,  16.00) (2*1800,   57.6) }
+         node[below, pos=0.5, rotate=\rot] {1 Channel $\times$128};
+\addplot[Orange, line width=3.1mm, line cap=round] coordinates { (2*500, 128.00) (2*1800,  460.8) }
+         node[above, pos=0.5, rotate=\rot] {8 Channels $\times$1024};
+\addplot[Orange, line width=3.1mm, line cap=round] coordinates { (2*500, 512.00) (2*1800, 1843.2) }
+         node[above, pos=0.5, rotate=\rot] {4 Stacks with 8 Channels $\times$4096};
+         
+
+% DDR3
+\addplot[Gray, line width=1.8mm, line cap=round] coordinates { (2*400, 0.800/2) (2*1066, 2.1300/2) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$4};
+\addplot[Gray, line width=1.8mm, line cap=round] coordinates { (2*400, 0.800) (2*1066, 2.1300) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$8};
+\addplot[Gray, line width=1.8mm, line cap=round] coordinates { (2*400, 1.600) (2*1066, 4.2600) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$16};
+\addplot[Gray, line width=1.8mm, line cap=round] coordinates { (2*400, 6.400) (2*1066, 17.060) }
+         node[above, pos=0.5, rotate=\rot] {DIMM $\times$64};
+\addplot[Gray, line width=1.8mm, line cap=round] coordinates { (2*400, 6.400*2) (2*1066, 17.060*2) }
+         node[above, yshift=+2pt, pos=0.5, rotate=\rot] {2 Channels $\times$128};
+\addplot[Gray, line width=1.8mm, line cap=round] coordinates { (2*400, 6.400*4) (2*1066, 17.060*4) }
+         node[above, pos=0.5, rotate=\rot] {4 Channels $\times$256};
+%
+%
+% DDR5
+\addplot[MidnightBlue, line width=2mm, line cap=round] coordinates { (2*1600, 1.600) (2*4200, 4.200) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$4};
+\addplot[MidnightBlue, line width=2mm, line cap=round] coordinates { (2*1600, 3.200) (2*4200, 8.400) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$8};
+\addplot[MidnightBlue, line width=2mm, line cap=round] coordinates { (2*1600, 6.400) (2*4200, 16.80) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$16};
+\addplot[MidnightBlue, line width=2mm, line cap=round] coordinates { (2*1600, 12.80) (2*4200, 33.60) }
+         node[above, pos=0.5, rotate=\rot] {1 Channel $\times$32};
+\addplot[MidnightBlue, line width=2mm, line cap=round] coordinates { (2*1600, 25.60) (2*4200, 67.20) }
+         node[above, pos=0.7, rotate=\rot] {2 Channels on 1 DIMM $\times$64};
+\addplot[MidnightBlue, line width=2mm, line cap=round] coordinates { (2*1600, 51.20) (2*4200, 134.4) }
+         node[above, pos=0.7, rotate=\rot] {4 Channels on 2 DIMMs $\times$128};
+\addplot[MidnightBlue, line width=2mm, line cap=round] coordinates { (2*1600, 102.4) (2*4200, 268.8) }
+         node[above, pos=0.7, rotate=\rot] {8 Channels on 4 DIMMs $\times$256};
+%
+% DDR4
+\addplot[BrickRed, ultra thick, line cap=round] coordinates { (2*800, 0.800) (2*2100, 2.1000) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$4};
+\addplot[BrickRed, ultra thick, line cap=round] coordinates { (2*800, 1.600) (2*2100, 4.2000) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$8};
+\addplot[BrickRed, ultra thick, line cap=round] coordinates { (2*800, 3.200) (2*2100, 8.4000) }
+         node[above, pos=0.5, rotate=\rot] {Device $\times$16};
+\addplot[BrickRed, ultra thick, line cap=round] coordinates { (2*800, 12.80) (2*2100, 33.600) }
+         node[above, pos=0.5, rotate=\rot] {DIMM $\times$64};
+\addplot[BrickRed, ultra thick, line cap=round] coordinates { (2*800, 51.20/2) (2*2100, 134.40/2) }
+         node[above, yshift=+4pt, pos=0.5, rotate=\rot] {2 Channels $\times$128};
+\addplot[BrickRed, ultra thick, line cap=round] coordinates { (2*800, 51.20) (2*2100, 134.40) }
+         node[above, pos=0.5, rotate=\rot] {4 Channels $\times$256};
+
+% LPDDR5
+\addplot[Green, line width=1.2mm, line cap=round] coordinates { (2*2750, 11.00) (2*3200, 12.80) }
+         node[below, pos=0.5, rotate=\rot] {Device $\times$16};
+\addplot[Green, line width=1.2mm, line cap=round] coordinates { (2*2750, 22.00) (2*3200, 25.60) }
+         node[below, pos=0.5, rotate=\rot] {2 Devices $\times$32};
+\addplot[Green, line width=1.2mm, line cap=round] coordinates { (2*2750, 44.00) (2*3200, 51.20) }
+         node[below, pos=0.5, rotate=\rot] {4 Devices $\times$64};
+\addplot[Green, line width=1.2mm, line cap=round] coordinates { (2*2750, 88.00) (2*3200, 102.4) }
+         node[below, pos=0.5, rotate=\rot] {8 Devices $\times$128};
+
+\legend{HBM2E,,,DDR3,,,,,,DDR5,,,,,,,DDR4,,,,,,LPDDR5,,,,,,}
+\end{loglogaxis}
+\end{tikzpicture}%
+}
+  \caption{Bandwidth Evolution of DRAM Standards}
+  \label{fig:evolution}
+\end{figure}
+\subsection{DRAM Basics}\label{sec:dram:basics}
+%\todo{(Physical) RANKs, Channels, DIMMs etc. sollte noch dazu und Bankgruppen wegen Same-Bank Refresh, Prefetch erklärt?}
+As shown in Figure~\ref{fig:dram}, DRAM can be organized in a multi-hierarchical fashion of \textit{DIMMs}, \textit{channels}, \textit{physical ranks}, \textit{devices}, \textit{logical ranks}, \textit{bank groups}, \textit{banks}, \textit{memory arrays}, \textit{sub arrays}, \textit{rows}, and \textit{columns}.
+%
+Several DRAM \textit{channels} can be connected to the \textit{Multi-Processor System on Chip}~(MPSoC). These channels are completely independent of each other and have separate command/address and data buses. A channel can be composed of one or multiple \textit{physical ranks}, which are sharing the data and command/address bus. A \textit{Dual Inline Memory Module}~(DIMM) is a small PCB that accommodates several DRAM devices, which work completely synchronously.
+%
+One single device is called $\times16$\footnote{pronunciation: \textit{by-sixteen}} if it has an I/O data width of 16 bit. A DIMM is assembled for instance out of four $\times16$ devices in order to have a total I/O data width $n=64~\mbox{bit}$ (called $\times64$). While the I/O data width is usually very limited, inside the DRAM a lot of data can be fetched or stored in parallel. However, the time between consecutive internal data accesses is very long due to the optimization for storage density, while the interface can be operated on much higher frequencies. To align this mismatch DRAM uses a so-called \textit{prefetching} technique. For a read large chunks of data are concurrently fetched to the interface and then transferred in one burst to the requester, for a write the process is reversed. In addition, data is transferred at the doubled interface frequency (\textit{double data rate}, short DDR). Current devices such as DDR4 use an 8n prefetch architecture, where n is the I/O data width, 8 the \textit{Burst Length}~(BL) and 8n the number of bits for an internal data transfer. That means with each DRAM access the total amount of data received or delivered is $BL\cdot n = 8 \cdot 64~\mbox{bit} = 512~\mbox{bit} = 64~\mbox{B}$, which is the usual cache line size in today's computing systems. In combination with interface frequencies up to 1600\,MHz or pin transfer rates up to 3200\,MT/s (megatransfers per second) DDR4 reaches a maximum bandwidth of 25.6\,GB/s per channel.
+
+Each device itself can consist of several 3D-stacked \textit{logical ranks}, which can form several \textit{bank groups} that include several \textit{banks}. The concept of bank groups was introduced with GDDR5 and DDR4 in order to reduce the bank switching times to support a seamless burst behavior at high data rates and therefore a high bandwidth.
+% 
+All banks in a whole channel can be used concurrently (so-called \textit{bank parallelism}). However, there are some constraints due to the shared buses. Each bank usually consists of $2^{12}$ to $2^{18}$ \textit{rows}, and each row can usually store $512\,\mbox{B}$ to $2\,\mbox{KB}$ of data in its \textit{columns}.
+
+A memory controller is composed of a \textit{front end} and a \textit{back end}. The front end performs arbitration and scheduling of incoming read and write requests, whereas the task of the back end is to translate these incoming requests into a sequence of DRAM commands, which have to be orchestrated with respect to the current state of the device. To access data in a row of a certain bank, an \textit{activate} (\texttt{ACT}) command must be issued by the controller before any column access, i.e., \textit{read} (\texttt{RD}) or \textit{write} (\texttt{WR}) commands, can be executed. The \texttt{ACT} command opens an entire row of the memory array, which is transferred into the bank’s \textit{row buffer}\footnote{The row buffer is a model that abstracts the real physical DRAM architecture. It is basically a combination of \textit{Primary Sense Amplifiers} (PSAs) and \textit{Secondary Sense Amplifiers} (SSAs) of the memory arrays in one bank. This model is useful to describe the functionality of a memory controller and its scheduling algorithms. Unfortunately, it often leads to a misunderstanding of the real DRAM architecture. For further details on the internal DRAM architecture we refer to~\cite{jacng_10}.}.
+%
+It acts like a small cache that stores the most recently accessed row of the bank. The latency of a memory access to a bank largely varies depending on the state of this row buffer. If a memory access targets the same row as the currently cached row in the buffer (called~\textit{row hit}), it results in a low latency and low energy memory access. Whereas, if a memory access targets a different row as the current row in the buffer (called~\textit{row miss}), it results in a higher latency and energy consumption. 
+%
+If a certain row in a bank is active it must first be \textit{precharged} (\texttt{PRE}) before another row can be activated. In addition to the normal \texttt{RD} and \texttt{WR} commands, there exist read and write commands with an integrated \textit{auto-precharge} (\texttt{RDA}, \texttt{WRA}). If auto-precharge is selected, the row being accessed will be precharged automatically at the end of the read or write access. Because a DRAM cell uses a capacitor with leakage effects for data storage, it usually has to be refreshed every $64\,\mbox{ms}$ to retain the data stored in it. Modern DRAMs are equipped with an \textit{all-bank refresh} (\texttt{REFab}) command to perform this operation automatically on all banks of a rank in parallel. However, a prerequisite is that all banks are in a precharged state. This can be achieved by issuing a special \textit{all-bank precharge} (\texttt{PREab}) command in advance.
+
+In addition to the commands, each DRAM standard defines a set of timing dependencies, which are temporal constraints that must be satisfied between issued commands. For example, between two \texttt{ACT} commands to the same bank the timing dependency $t_{RC}$ (\textit{row cycle time}) must be satisfied. Timing dependencies can also exist on other hierarchies of the DRAM, e.g., between commands to the same bank group, to the same logical/physical rank or to different logical/physical ranks.
+%
+%Besides the normal active mode operations presented above, a DRAM is capable to enter power-down modes to save energy by setting the clock-enable signal \texttt{cke} to low. There exist three major power-down modes called \textit{Precharge Power-Down} (PDNP), \textit{Active Power-Down} (PDNA) and \textit{Self-Refresh} (SREF).
+%%
+%
+The selection of a DRAM subsystem usually has three main dimensions: bandwidth, latency, and capacity. Bandwidth is the amount of data that can be transferred between DRAM and a computational unit within a given time. As shown in Figure~\ref{fig:evolution}, the maximum theoretical DRAM bandwidth is limited to the number of data pins times the interface pin data rate (number of accesses per time per pin). Latency is the time that it takes to complete an access. In fact, latency helps bandwidth, but not vice versa~\cite{pat_04}. For instance, lower DRAM latency results in more accesses per time, and therefore higher bandwidth, whereas increasing the number of data pins increases the bandwidth without decreasing latency. In realistic scenarios, the full theoretical bandwidth is never reached due to many timing dependencies, interference between different requests, and refresh. The actual achieved bandwidth for a specific application is called \textit{sustainable bandwidth}.
+%
+\subsection{DDR5 Standard}
+\begin{table}[]
+\caption{Comparison of DDR4 and DDR5 Key Parameters}
+\centering
+\resizebox{\columnwidth}{!}{% <------ Don't forget this %
+\begin{tabular}{|l|l|l|}
+\hline
+ $~$                            & \textbf{DDR4} & \textbf{DDR5} \\ \hline
+ \textbf{Data Rates [MT/s]}              & 1600 - 3200   & 3200 - 8400   \\ \hline
+ \textbf{Max. Channel BW [GB/s]}         & 25.6          & 33.6          \\ \hline
+ \textbf{Max. DIMM BW [GB/s]}            & 25.6          & 67.2          \\ \hline
+ \textbf{Error Correction}               & -             & On-Die        \\ \hline
+ \textbf{Device Capacity [Gb]}           & 2 - 16        & 8 - 64        \\ \hline
+ \textbf{Max. Stacked Devices}           & 8             & 16            \\ \hline
+ %\textbf{\todo{DIMM Capacity??}}         & ?             & ?             \\ \hline
+ \textbf{Channel Width [bit]}            & 64            & 32            \\ \hline
+ \textbf{Channels per DIMM}              & 1             & 2             \\ \hline
+ \textbf{Prefetch}                       & 8n            & 16n           \\ \hline
+ \textbf{Max. Banks}                     & 16            & 32            \\ \hline
+ \textbf{Max. Bank Groups}               & 4             & 8             \\ \hline
+ \multirow{2}{*}{\textbf{Refresh Modes}} & \multirow{2}{*}{All-Bank}  & All-Bank, \\ 
+                                &               & Same-Bank     \\ \hline
+ \textbf{Burst Length}                   & 8             & 16, 32        \\ \hline
+ \textbf{Supply Voltage [V]}             & 1.2           & 1.1           \\ \hline
+ \end{tabular}%
+ }
+ \label{tab:comparison}
+\end{table}
+% tREFI = 3.9us, but tRFC shorter
+% higher bandwidth -> higher interface frequency -> increase of internal prefetch, interface is small but fast, internal DRAM is slow but highly parallel
+% DDR3 used 8n prefetch, DDR4 introduced concept of bank groups (separate power supplies for each bank group) and kept 8n prefetch because with 16n prefetch each burst would be 128 Bytes, but cache line size only 64 Bytes
+% DDR5 increased prefetch to 16n, but data bus is only 32 bit wide -> 2 channels per DIMM
+% 8 bank groups instead of 4, up to 32 banks for higher bank parallelism -> hide row misses
+% up to 16 logical ranks (stacked devices)
+% total device size up to 512 Gb (DDR4 only 128 Gb)
+% power supply located on DIMM, new timings: same bank, different bank same bank group, different bank group same logical rank, different logical rank same physical rank, different physical rank same DIMM
+% internal ECC
+% same bank refresh: refresh only one bank of each group -> other banks can still be accessed -> with increasing device size (more banks and rows) refresh overhead becomes bigger and bigger -> this way refresh can be hidden, no idle phases on data bus 
+% no per-bank refresh because 32 banks, high command bus utilization
+%
+\begin{figure*}[t!]
+    \centering
+    \includegraphics[width=.8\linewidth]{dramsys_tc.pdf}
+    \caption{Architecture of DRAMSys}
+    \label{fig:dramsys}
+\end{figure*}
+
+With the development of a new DRAM standard generation there are always several key parameters that should be enhanced, e.g., bandwidth, power consumption, and device capacity. Table~\ref{tab:comparison} shows a comparison between key parameters of the new DDR5 standard and its predecessor DDR4. In the following we will also describe the most important differences in more detail.
+
+For a higher bandwidth DDR5 raises the maximum pin data rate to 8400\,MT/s compared to 3200\,MT/s for DDR4. Because the frequency of internal data accesses stays more or less the same as a result of the capacity- and cost-optimized architecture, the prefetch was incremented from 8n to 16n. When using the same 64-bit-wide data bus for one channel as all previous DDR generations, this would result in 128\,B of transferred data per access. However, since the usual cache line size of modern processors is only 64\,B, the data bus of each DDR5 DIMM is split up into two independent channels of 32\,bit width. That way only 64\,B of data are transferred per access. Theoretical transfer rates then reach a maximum of 33.6\,GB/s per channel and 67.2\,GB/s per DIMM compared to 25.6\,GB/s per channel/DIMM for DDR4, as shown in Figure~\ref{fig:evolution}.
+%
+At the same time supply voltages are reduced from 1.2\,V to 1.1\,V for an improved power consumption. 
+
+The maximum number of banks per device increases from 16 to 32 distributed over 8 instead of 4 bank groups, the total capacity of a single device from 16\,Gb to 64\,Gb. In addition, up to 16 instead of 8 devices can now be stacked in a three-dimensional fashion (logical ranks)\footnote{The initial DDR4 standard did not specify any stacked devices. This feature was first introduced with an addendum in 2017.}. This enables stack capacities of up to 512\,Gb (max. 16 $\times$ 32\,Gb or 8 $\times$ 64\,Gb because of limited address bits). One problem that always arises with higher device capacities is the increased refresh overhead, because each cell still has to be refreshed approximately every 64\,ms. As a consequence, either the controller has to issue refresh commands more frequently or the individual refresh cycles take a longer time. Since all banks of a rank cannot be accessed during an all-bank refresh, it can lead to significant performance drops. 
+
+To overcome this problem, DDR5 introduces \textit{same-bank refresh} (REFsb) and associated \textit{same-bank precharge} (PREsb) commands as an alternative to \textit{all-bank refresh} (REFab) and \textit{all-bank precharge} (PREab) commands. When issuing them, only one bank in each bank group of the target rank is refreshed and unaccessible, while all other banks can still process incoming read and write requests. Most modern DRAM controllers use advanced reordering techniques for an improved performance so they can try to hide the same-bank refresh by sending requests to other banks in the meantime.
+
+Finally, DDR5 devices implement an on-die error correction to improve the data integrity.
+
+\section{DRAMSys}
+The simulation of DRAMs on system level requires highly accurate models due to their complex timing and latency behavior. However, conventional cycle-accurate DRAM controller models often become the bottleneck for the overall simulation speed~\cite{liver_19}. A promising alternative are DRAM simulation models based on TLM, which can be fast and accurate at the same time.
+%
+In this paper we use the open-source simulator DRAMSys~\cite{stejun_20}, which is, to the best of our knowledge, the fastest cycle-accurate open-source DRAM simulator and has a large range of functionalities. It features a very high simulation speed while maintaining full temporal accuracy. DRAMSys has a simulator architecture that enables a fast adaptation to new DRAM standards using a DSL. In the following we describe the DRAMSys simulation model, the internal architecture, the DSL-based code generation, and the integration of DDR5.
+%
+\subsection{The DRAMSys Simulation Model}
+%
+DRAMSys uses the concept of the SystemC/TLM2.0 IEEE 1666 Standard for a fast and fully cycle-accurate simulation. In accordance with the standard, all components are designed as \textit{SystemC modules} and connected by \textit{TLM sockets}. Each memory request is modelled with a special TLM transaction object, the so-called \textit{generic payload}. It stores all relevant information of the request, e.g., the address, the transfer direction (read or write) or corresponding data, and is passed by reference between the modules. The simulator utilizes the \textit{Approximately Timed} (AT) coding style, which defines a \textit{non-blocking four-phase handshake protocol}. This protocol is required to model the DRAM subsystem's pipelined behavior and out-of-order responses to the initiators. However, since a single memory access can cause the issuance of multiple DRAM commands depending on the device's current state (e.g., \texttt{PRE}, \texttt{ACT}, \texttt{RD/WR} for a row miss), four phases are still not sufficient to model the communication between controller and device with full temporal accuracy. To close this gap, a custom TLM protocol (called DRAM-AT) that defines application-specific phases for all DRAM commands was introduced in~\cite{junwei_13}. These phases allow a projection of the cycle-accurate DRAM protocol to TLM.
+
+The rule of thumb for making cycle-accurate simulations fast is to reduce the number of simulated events and the executed control flow overhead. Therefore, DRAMSys only simulates relevant state changes instead of individual signal changes in each clock cycle. Especially in scenarios where the memory access density is low, this approach can lead to an enormous event reduction and a resulting simulation speedup of several orders of magnitude while still yielding fully cycle-accurate results~\cite{stejun_20}.
+%
+\begin{figure*}[t!]
+    \centering
+    \includegraphics[width=.95\linewidth]{analyzer_DDR5.png}
+    \caption{Graphical User Interface of the Trace Analyzer}
+    \label{fig:traceanalyzer}
+\end{figure*}
+%
+\subsection{Architecture}\label{sec:dramsys:arch}
+As shown in Figure~\ref{fig:dramsys}, DRAMSys consists of three main components: a shared \textit{arbitration \& mapping unit} (short arbiter), a \textit{channel controller} for each memory channel and a \textit{DRAM device} for each memory channel. The arbiter cross-couples multiple initiators and DRAM channels and translates the address of each request into a corresponding channel, logical/physical rank, bank group, bank, row, and column. This translation is done on the basis of a predefined \textit{address mapping}. Different address mappings can have a large impact on the overall system performance because of the timing dependencies between commands, which not only depend on the commands themselves, but also on the target location they are issued to (see Section~\ref{sec:dram:basics}). Thus, the address mapping should always be chosen with consideration of the application's memory access pattern and the DRAM configuration. 
+
+Following the arbiter each memory channel has a channel controller. It is composed of five components that will be explained shortly. The \textit{scheduler} enqueues incoming requests and reorders them on the basis of a specific \textit{scheduling policy} to improve, e.g., bandwidth and latency by avoiding row misses. For each bank in the whole channel there is a separate \textit{bank machine}. It keeps track of the current bank state and makes sure that commands are issued in a valid sequence, e.g., \texttt{PRE}, \texttt{ACT}, \texttt{RD/WR} for a row miss. The issuance of refresh commands to each DRAM rank at the right time is managed by \textit{refresh managers}. To ensure that all timing dependencies between commands are satisfied and DRAMSys behaves compliant to the corresponding JEDEC standard, both bank machines and refresh managers ask the \textit{timing checker} for the earliest point in time a command can be issued. The timing checker stores the relevant command history and all timing dependencies to calculate the right time. For each JEDEC standard there is a separate timing checker that can be instantiated. Finally, each channel controller includes a \textit{command multiplexer} to resolve conflicts between all bank machines and refresh managers, since only one request can be issued at a time due to the shared command/address bus. 
+
+As last component each channel controller is connected to a DRAM device. It manages the data storage and in addition can establish a connection to simulation tools for power estimation, thermal modeling or error modeling. 
+
+%
+\subsection{Trace Analyzer}
+To enable better analysis capabilities for the DRAM subsystem performance than the usual outputs to the console or a text file and to deeply investigate the channel controller's scheduling decisions, DRAMSys provides the Trace Analyzer. During a simulation there is a functionality to record all TLM transactions of the channel controller in an SQLite trace database. Afterwards, this database can be evaluated graphically using the Trace Analyzer. The user interface is shown in Figure~\ref{fig:traceanalyzer}. It illustrates a time window of requests, DRAM commands and the utilization of all banks. This can help system designers to understand the subsystem's internal behavior and to find limiting issues. Exploiting the power of SQL, the data aggregation happens very fast and the tool provides a user-friendly handling that offers a quick navigation through the whole trace database, sometimes with millions of requests and associated DRAM commands. 
+
+In addition, an evaluation of the traces can be performed with the powerful Python interface of the Trace Analyzer. Different metrics are described as SQL statements and formulas in Python and can be customized or extended without recompiling the tool. Typical metrics are for instance memory utilization (bandwidth), average response latency or number of accesses per activate (row hit rate).
+%
+\subsection{DRAMml: A DSL for DRAMs}
+%
+As stated in the introduction, an increasing number of different DRAM standards has been presented by JEDEC in recent years. Since each new standard comes with challenging changes in the DRAM protocol compared to previous ones, the memory simulation models as well as the RTL models must be modified and validated repeatedly. In order to keep pace with these frequent changes and the large variety of standards, a robust and error-free methodology for a fast adaption must be established.
+
+In~\cite{junkra_19} we presented a comprehensive and formal DSL called DRAMml, which is based on a Petri Net~\cite{pet_62} semantic. DRAMml can describe the entire memory functionality of a DRAM standard including all timing dependencies in just a few lines of code. Using the formal description of a corresponding Petri Net, different simulation and validation models can be generated automatically and correct by construction, as shown in Figure~\ref{fig:methodology}. One of the simulation models is also the channel controller's standard-specific timing checker (see Section~\ref{sec:dramsys:arch}). In this way, the error-prone handwritten source code is replaced by source code generated from a high-level description.
+
+%\todo{Furthermore, DRAMSys offers functionalities for embedding an RTL model of a memory controller into the framework and for recording the executed DRAM commands in an output trace database. Using the formal DSL descriptions, a standard-specific executable C++ validation model can be created, which analyses a recorded DRAM command trace for standard compliance. This approach provides fast feedback to an RTL developer if a change in the RTL description led to a protocol violation.}\todo{Das ist doppelt, weil der Teil auch nochmal bei Integration of DDR5 kommt. \textbf{Macht nix.. kann ruhig nochmal gesagt werden...}}
+%
+\begin{figure}
+    \centering
+    \includegraphics[width=0.7\columnwidth]{methology.pdf}
+    \caption{DRAMml Methodology}
+    \label{fig:methodology}
+\end{figure}
+%
+%
+\subsection{Integration of DDR5}
+%
+%\textcolor{red}{Major difference between two DRAM standards: maximum operating frequency, timings, data bus width, burst length, timing dependencies between commands; timing values, bus width and burst length are specified in JSON config files that are loaded during runtime -> new config files for DDR5 have to be created from the standard; timing dependencies are modeled in a standard-specific timing checker, timing checker is created from DRAMml, DRAMml is less error prone, dependencies can only be inserted at specific locations, source code is then generated. Functionality of new refresh manager: specific order must be observed, try to refresh idle banks first, DRAMml: 3D-DDR4: slr and dlr, DDR5 in addition dpr, timing dependencies on six hierarchies, two new commands REFsb and PREsb, maybe explain PREab and PREsb in advance, DRAMml code excerpt}
+
+
+In order to expand DRAMSys by a DDR5 simulation model three steps had to be performed. All architectural parameters (e.g., number of channels/banks/bank groups, data bus width, burst length) as well as temporal parameters (frequency and timing values) of one specific DRAM subsystem configuration are defined in a JSON file and passed to the simulator as an argument. From the new DDR5 JEDEC standard JSON files for various speed grades and device sizes were put together first.
+
+Second, a DRAMml description was created. Since DDR5 introduces same-bank refresh and specifies timing dependencies between commands to (1) the same bank, (2) different banks (same bank group), (3) different bank groups (same logical rank), (4) different logical ranks (same physical rank), (5) different physical ranks (same DIMM) and (6) different DIMMs\footnote{This increase results from the three-dimensional stacking of devices and the move of the power management integrated circuit (PMIC) from the main PCB onto the DIMM.}, the overall length of the description has increased by around 50\,\% compared to the predecessor DDR4. Nevertheless, it still fits on two pages and is very compact when considering the length of the actual JEDEC standard of almost 500 pages. In addition, the complexity has not increased. Because DRAMml fully relies on a Petri Net semantic, it is modular and could be adapted to all protocol changes of DDR5 without adding any language extensions. Listing~\ref{lst:DRAMml} shows an excerpt of the initial DRAMml descriptions of DDR4 and DDR5 for the timing dependencies between two \texttt{ACT} commands. The increase in hierarchies (additional logical and physical ranks) could be directly applied to the code. From this description the new DDR5 timing checker source code for DRAMSys was generated automatically and correct by construction. 
+
+\lstset{
+   language=DRAMml,
+   extendedchars=true,
+   basicstyle=\footnotesize\ttfamily,
+   showstringspaces=false,
+   showspaces=false,
+   tabsize=2,
+   breaklines=true,
+   showtabs=false
+}
+
+\begin{lstlisting}[
+    caption={Timing Dependencies between \texttt{ACT} Commands},
+    label={lst:DRAMml},
+    frame=single]
+# DDR4:
+ACT -<> ACT (tRC, tRRD_L, tRRD_S, 0);
+# DDR5:
+ACT -<> ACT (tRC, tRRD_L_slr, tRRD_S_slr, tRRD_dlr, 0, 0);
+\end{lstlisting}
+
+The third and final step was to derive a new same-bank refresh manager from the existing all-bank refresh manager. This was the only source code written by hand. Besides the change from \texttt{PREab} and \texttt{REFab} to \texttt{PREsb} and \texttt{REFsb} commands, the new component required some extra logic because \texttt{REFsb} commands have to be issued in a specific order to refresh all banks evenly. All in all, the whole integration process could be performed within two weeks. This time also included the study of the new JEDEC standard as well as testing and debugging. One major benefit of our DRAMml approach is that the major part of the source code can be generated correct by construction, so there are only very limited possibilities for introducing any errors, which keeps the debugging effort low.
+
+%
+%In order to expand DRAMSys by a DDR5 model only three steps had to be performed. First, a new refresh manager for the same-bank refresh was developed. Second, a DRAMml description for DDR5 was written on the basis of the JEDEC standard. Third, the source code for the DDR5 timing checker was automatically generated from the DRAMml and added to DRAMSys. Modeling two channels per DIMM could simply be achieved by instantiating two separate channel controllers connected to one shared arbiter device and thus carried no additional integration effort with it.
+
+%Although the number of timing dependencies and thus the lines of code for the timing checker have largely increased for DDR5 compared to previous standards\footnote{DDR5 specifies timing dependencies between commands to the same bank, same bank group, same logical rank, same physical rank and different physical ranks. This results from the three-dimensional stacking of devices and the move of the power management integrated circuit (PMIC) from the main PCB onto the DIMM.}, the whole integration process could still be performed within two weeks. This time also included the study of the new JEDEC standard and the testing and debugging process. One major benefit of the DRAMml approach is that most of the source code can be generated correct by construction, so there are only very limited possibilities for introducing any errors and the debugging effort is low.
+
+% 2 channels -> no problem, simply instantiate 2 memory controllers connected to one arbiter
+% power supply located on DIMM??
+% timings same bank, different bank same bank group, different bank group same logical rank, different logical rank same physical rank, different physical rank same DIMM
+% "automatic" generation of timing checker using DRAMPetri -> less error prone, lots of timing dependencies!!! (e.g. ACT -> ACT has ... dependencies), still fast because no loops (comparison simulation speed DDR4 and DDR5?)
+% same bank refresh -> new refresh manager
+
+\section{Experiments and Observations}
+In this section we analyze the bandwidth and latency behavior of different DDR5 device configurations with respect to two common application characteristics and compare it to DDR4. We will describe the experimental setup, the results and conclude with several key observations.
+%
+\subsection{Experimental Setup}
+To evaluate the performance we use two characteristic benchmarks: (1) accesses with linearly-increasing addresses and (2) accesses with a random address distribution over the whole address space. These two benchmarks are the extreme borderline cases of all possible applications. Therefore, they are well suited to show the different limits, e.g., for server applications with many cores (random) and data-flow-oriented tasks (linear). 
+
+In both benchmarks the number of read requests is twice as high as the number of write requests. The total number of requests is set to 100,000 to omit short-time effects and to obtain results in a reasonable amount of time. For the linear benchmark a burst of 16 read requests is followed by a burst of 8 write requests, for the random benchmark read-write switches are also done randomly. The frequency in which requests are issued to the DRAM subsystem can be chosen arbitrarily and depends on the test case. 
+
+For DDR5 we use DIMMs with 8\,Gb (1\,Gb\,$\times$8) devices containing 16 banks and with 16\,Gb (2\,Gb\,$\times$8) devices containing 32 banks to find out the impact of the bank increase. Each channel is then composed of 4 devices and the whole DIMM of 8 devices. In addition to single-rank DIMMs (SR) we also use dual-rank DIMMs (DR) with 16 devices. Speed grades are varied from the slowest one (DDR5-3200) up to the fastest one (DDR5-6400) finally specified by JEDEC\footnote{Speed grades up to DDR5-8400 are planned but not yet finally specified.}. For comparison we use a DDR4 DIMM with 16\,Gb (2\,Gb\,$\times$8) devices containing 16 banks. The channel/DIMM is then composed of 8 devices. As for DDR5 we also investigate the behavior of a dual-rank DIMM with 16 devices. Speed grades are again varied from the slowest one (DDR4-1600) up to the fastest one specified in the standard (DDR4-3200). All-bank refresh is selected by default for both standards. In the case of DDR5 we always show the bandwidth sum of both channels, however, the number of data pins, which usually limits the amount of channels, is identical for DDR5 and DDR4.
+
+All channel controllers implement separate queues for reads and writes with a queue depth of 32 each. Smaller and larger queue depths (16 and 64) were also investigated for completeness but only caused small shifts in all results, the general observations were the same. Thus, they are not presented in this work. As scheduling policy for incoming requests \textit{First-Ready First Come First Served} (FR-FCFS)~\cite{rixdal_00} is applied. The address mapping is chosen to yield the highest performance for the linear benchmark using techniques like channel and bank group interleaving. This means subsequent requests are mapped to different channels or bank groups and row or bank switching penalties are minimized. For the random benchmark the address mapping does not influence the performance at all because toggling rates for all address bits are uniformly distributed. Finally, for the linear benchmark a row is kept open after a read or write access because row hits are likely to happen (\textit{open-page policy}), while for the random benchmark a row is automatically precharged after each read or write access because row hits practically never happen (\textit{closed-page policy}).
+%
+\subsection{Experimental Results}
+%
+In the following we present the experimental results for different DDR5 device configurations, for the comparison of DDR5 and DDR4 and for the different DDR5 refresh modes. All results have been analyzed and verified with the Trace Analyzer.
+%
+\vspace{-5pt}
+\subsubsection{Different DDR5 Configurations} 
+%
+First, we investigate the bandwidth of all DDR5 configurations both for the linear and the random benchmark. The requests are issued as fast as possible such that either the read or the write queue is always filled up completely. The corresponding results are presented in Figure~\ref{fig:bw:linear_DDR5} and \ref{fig:bw:random_DDR5}. What stands out most obviously is that for the linear benchmark all four configurations come much closer to the maximum bandwidth as for the random benchmark. This is because the address mapping is optimized for the linear case to reduce switching penalties. Only the refresh and read-write switches cannot be omitted and constantly decrease the bandwidth. Hence, also the bank increase from 16 (8\,Gb device) to 32 (16\,Gb device) and the move from single rank to dual rank yield rather small improvements (on average 2.7\,\% and 11.4\,\%), the 8\,Gb dual rank configuration even outperforms the 16\,Gb dual rank configuration due to shorter refresh cycles. For increasing data rates the slope slightly drops because refresh cycles take a fixed amount of time and thus more clock cycles. The waviness of some graphs is caused by timings that limit the maximum bandwidth and do not take a fixed amount of time, but a fixed amount of clock cycles. This behavior can also be observed in Figure~\ref{fig:bw:linear_DDR4_DDR5} and \ref{fig:bw:random_DDR4_DDR5} and in Figure~\ref{fig:refresh}.
+
+However, the random benchmark results in Figure~\ref{fig:bw:random_DDR5} look a lot different. While at low data rates all configurations are still in a close range, they largely drift apart when the data rates become higher. Then the gap between 16 and 32 banks and the move from single to dual rank is enormous (up to 41.8\,\% and up to 63.4\,\% bandwidth increase, on average 26.4\,\% and 42.4\,\%). When we consider that an 8\,Gb dual-rank configuration also provides in total 32 banks per channel it clearly shows that for high data rates and random accesses DDR5 requires at least the parallelism of 32 banks to keep the bandwidth up. To find a simple explanation for this behavior we have to recall several things into our minds. For the chosen configuration random requests always translate into a full row cycle consisting of an \texttt{ACT} and a \texttt{RDA/WRA}. These row cycles require the fixed minimal amount of time $t_{RC}$ (minimum time between \texttt{ACT} commands to the same bank, see Section~\ref{sec:dram:basics}). With increasing data rates the absolute time $t_{RC}$ stays more or less constant and therefore the corresponding number of clock cycles increases (around 74 for DDR5-3200 and 149 for DDR5-6400). But at the same time the number of clock cycles each request occupies the data bus stays constant (for DDR5 8 clock cycles at burst length 16). To successfully align this mismatch, hide the delays, and achieve a high data bus utilization and high sustainable bandwidth, a certain amount of bank parallelism is required to do row cycles in parallel on all banks. Simply put, with 149 clock cycles for one row cycle and 16 banks we can issue a new request every $\frac{149}{16}=9.3$ clock cycles, but each request only takes 8 on the bus. This means even for an ideal command placement, a perfectly uniform distribution of requests over all banks and without refresh we will never reach the theoretical bandwidth limit. However, with 32 banks we can issue a new request every $\frac{149}{32}=4.7$ clock cycles, which is fast enough even for the highest data rates of DDR5.
+%
+\vspace{-5pt}
+\subsubsection{DDR4 versus DDR5} 
+%
+Next up, we compare the bandwidth of DDR5 to its predecessor DDR4 for single- and dual-rank configurations with 16\,Gb devices (16 banks per rank for DDR4, 32 banks per rank for DDR5). The corresponding results are provided in Figure~\ref{fig:bw:linear_DDR4_DDR5} and \ref{fig:bw:random_DDR4_DDR5}. Each figure starts on the left side with DDR4-1600, the results for DDR5 start at a data rate of 3200\,MT/s. DDR4 finishes at this data rate but is additionally extrapolated to DDR4-4400. This extrapolation is done because by this time there are lots of overclocked DDR4 devices on the market with data rates up to 4400\,MT/s, so in reality the data rate limits specified in the JEDEC standard are not valid any more. For the linear benchmark the bandwidths of DDR4 and DDR5 come very close to each other at data rates where they overlap (average increase of 7.5\,\% with SR and 8.2\,\% with DR from DDR4 to DDR5). The slightly better performance of DDR5 can be explained when we look on the number of read-write switches for each standard. While the total number of requests issued to each subsystem is identical, the DDR5 DIMM is composed of two channels, both of which receive only half of the requests. Considering that a read-write switch on each channel is always done after a fixed amount of requests (usually when the write buffer is full and the read buffer empty or the other way round), the number of switches on each of them is divided in half. However, the total runtime is not divided in half but almost identical for DDR4 and DDR5 because of the doubled burst length of DDR5. To sum it up, when choosing the memory for a platform where transfer rates lower than 4400\,MT/s are targeted and the application's memory access scheme is rather linear, an upgrade from DDR4 to DDR5 is not worth the effort especially because prices for DDR5 at release are expected to be higher. 
+
+For the random benchmark the results in Figure~\ref{fig:bw:random_DDR4_DDR5} tell a completely different story. DDR4 with a single rank cannot keep up the bandwidth at all for increasing data rates, the dual-rank configuration performs better but also flattens for higher data rates. Their gap to DDR5 is large in both cases (approximately up to 130\,\% and 57\,\%, on average 107\,\% and 42\,\%). The problem is the same as for the 8\,Gb DDR5 device mentioned previously. In the case of DDR4 a single data transfer occupies the data bus only for 4 clock cycles and the device only has 16 banks. With two ranks the number of banks increases to 32, however the burst length is still to small. As a result, the data bus turns idle because row cycle delays cannot be hidden completely. With 32 or even 64 banks and a burst length of 16, both DDR5 configurations perform a lot better over the whole range. This shows that DDR5 is especially optimized for random workloads and is clearly ahead of DDR4 even at low data rates. %To sum it up, in the random case DDR5 with its 32 banks is clearly ahead of DDR4 even at the lowest data rates.
+
+To compare both standards also from a different point of view, we fix the data rate to 3200\,MT/s and vary the frequency requests are issued to the DRAM subsystem. Starting at 25\,MHz and increasing in steps of 25\,MHz we then plot the average response latency of all requests (average latency from entry of requests until data has been transferred over the bus) over the bandwidth. These results are presented in Figure~\ref{fig:lat_bw}. For the linear case (Figures~\ref{fig:lat_bw:linear_16Gb_SR} and \ref{fig:lat_bw:linear_16Gb_DR}) DDR4 and DDR5 show a very similar behavior. In the beginning the bandwidth increases directly proportional to the frequency increase while the latency stays almost constant (around 40\,ns). Each request is immediately serviced by the DRAM in this region and the latency is mainly composed of the read or write latency (latency from issuing a \texttt{RD} or \texttt{WR} command until the data transfer starts) and the data transfer over the bus. At higher input frequencies multiple requests are in the DRAM subsystem in parallel and interfere with each other. The controller starts reordering requests to keep the bandwidth up but to the disadvantage of the response latency, which increases exponentially. At an input frequency around 350\,MHz the maximum sustainable bandwidth ($\sim$\,22\,GB/s) is reached and both bandwidth and response latency remain unchanged. These values come close to the maximum theoretical bandwidth of 25.6\,GB/s at an input frequency of 400\,MHz. DDR5 has a worse average response latency at this point mainly due to the doubled burst length ($\sim$\,270\,ns vs. 150\,ns), however, real systems would never be operated at this point anyway. Advanced memory controllers rather take a slight loss in bandwidth with the advantage of a much lower average response latency, which is a lot more beneficial for the overall system performance. The memory controller configuration we used for our experiments is only optimized for bandwidth and therefore also allows these operating points.
+
+When both standards are compared for the random benchmark on the basis of these facts (Figures~\ref{fig:lat_bw:random_16Gb_SR} and \ref{fig:lat_bw:random_16Gb_DR}), the benefits of DDR5 are large again. At the same speed grade DDR5 can handle random request streams with much higher frequencies and the average response latency rises much slower. For the single-rank configuration DDR4 exceeds an average response latency of 100\,ns already at an input frequency of 125\,MHz, DDR5 reaches this latency at input frequencies between 200 and 225\,MHz. As a consequence, there is also a large gap between the maximum sustainable bandwidths of both standards ($\sim$\,11\,GB/s for DDR4 vs. 21\,GB/s for DDR5). In the case of two ranks the gap becomes smaller, but DDR5 still offers a big advantage over DDR4 both with respect to average response latency and bandwidth. These results confirm the optimization of DDR5 for random input patterns once more and show the advantage of the architectural changes compared to DDR4 (higher bank count, higher burst length, two channels per DIMM). 
+%
+\vspace{-5pt}
+\subsubsection{DDR5 Refresh Modes} 
+%
+Finally, we investigate the performance of the new same-bank refresh in comparison to all-bank refresh. Again, this is done with 16\,Gb DDR5 devices for both benchmarks, for single- and dual-rank DIMMs and for all available DDR5 speed grades. The corresponding bandwidth results are shown in Figure~\ref{fig:refresh}. For reference, also the maximum theoretical bandwidth and the sustainable bandwidth without any refresh is shown. In the linear case (Figures~\ref{fig:refresh:linear_16Gb_SR} and \ref{fig:refresh:linear_16Gb_DR}) same-bank refresh clearly leads to a higher bandwidth compared to all-bank refresh over the whole range of data rates and for both DIMM configurations (on average 7.9\,\% for single rank and 9.1\,\% for dual rank). Also, the gap to the bandwidth completely without refresh is very little (in some cases less than 1\,\%). In the case of a single rank, all-bank refresh causes a large drop in performance because the data bus turns idle during the whole refresh cycle. With two ranks, refresh commands are staggered, i.e., there is an offset between them and only one rank is refreshed at a time. The other rank can still process requests in the meanwhile, but only as long as requests for it are available in the queues. Since the selected address mapping makes sure that work is equally distributed over both ranks for an increased average performance, at some point the queues are completely filled with requests for the blocked rank and the data bus also turns idle. In addition, refresh commands have to be issued twice as often compared to a single rank. An increased queue depth could solve this issue, but at the same time would require more hardware resources and would make the scheduling more complex. In contrast, during a same-bank refresh cycle only every fourth (SR) or every eighth (DR) bank is unaccessible and each refresh cycle is also shorter. In that case the blocking on individual banks can easily be compensated by the remaining banks and the data bus does not turn idle. 
+
+For the random benchmark the results with two ranks (Figure~\ref{fig:refresh:random_16Gb_DR}) are more or less identical (on average 10.0\,\% bandwidth increase), but with only a single rank (Figure~\ref{fig:refresh:random_16Gb_SR}) same-bank refresh does not bring an advantage (on average less than 1\,\% bandwidth increase). The reason for this behavior is already well-known and also occurred in the previous results: not enough bank parallelism. Although a single 16\,Gb DDR5 device already offers 32 banks, the blocking times of refresh cycles still noticeably lower the performance. In this case the refresh mode makes no difference because the overall bank blocking times induced by both modes are nearly identical. With all-bank refresh there are less but longer idle phases on the data bus, with same-bank refresh more but shorter ones. Only with two ranks and 64 banks the bank parallelism is large enough to compensate the refresh penalty and the performance depends on the queue depth as for the linear case. As a conclusion, DDR5's new same-bank refresh strategy performs better or at least just as good as the all-bank refresh in all tested configurations and should therefore always be preferred.
+
+
+% trotz besserer Verteilung Datenbus nicht voll, Reduzierung des Bank Parallelism zu stark
+% Bank Parallelism zwar hoch, aber kann Refresh Penalty nicht vollständig kompensieren
+
+% IMPORTANCE OF TA!!!!!
+
+%%%%%%%%%% ...
+% stream and random
+% different read:write ratios
+% different frequencies
+% 1/2 ranks, 16/32 banks for DDR5
+% performance gain same bank refresh
+% performance gain DDR3 -> DDR4 not so large (cite)
+% refresh overhead becoming more and more problematic with increasing memory capacity
+%
+%
+% Refresh is staggered! That way it can be hidden!
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%% Old Figures
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% \begin{sidewaysfigure*}[p]
+%     \centering
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Bandwidth [GB/s]}},
+%         	xlabel={\textbf{Pin Data Rate [MT/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 2*1200,
+%             ymin = 15,
+%             xmax = 2*3400,
+%             legend style={at={(0.05,0.7)}, anchor=west}
+%         ]
+        
+%         % Max
+%         \addplot[Black, thick, line cap=round, smooth] coordinates {
+%             (2*1600,204.8/8)
+%             (2*1800,230.4/8)
+%             (2*2000,256  /8)
+%             (2*2200,281.6/8)
+%             (2*2400,307.2/8)
+%             (2*2600,332.8/8)
+%             (2*2800,358.4/8)
+%             (2*3000,384  /8) 
+%             (2*3200,409.6/8) 
+%         };
+        
+%         % DDR5 8Gb SR
+%         \addplot[Purple, thick, line cap=round, smooth] coordinates {
+%           (2*1600,178.44/8)
+%           (2*1800,197.16/8)
+%           (2*2000,219.04/8)
+%           (2*2200,237.38/8)
+%           (2*2400,257.80/8)
+%           (2*2600,276.02/8)
+%           (2*2800,295.48/8)
+%           (2*3000,315.32/8)
+%           (2*3200,331.86/8)
+ 
+%         };
+        
+%         % DDR5 16Gb SR
+%         \addplot[Magenta, thick, line cap=round, smooth] coordinates {
+%             (2*1600,180.3 /8)
+%             (2*1800,200.5 /8)
+%             (2*2000,222.76/8)
+%             (2*2200,242.74/8)
+%             (2*2400,264.28/8)
+%             (2*2600,285.1 /8)
+%             (2*2800,306.88/8)
+%             (2*3000,327.4 /8)
+%             (2*3200,346.16/8)
+%         };
+        
+%         % DDR5 8Gb DR
+%         \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+%             (2*1600,197.52/8)
+%             (2*1800,215.02/8)
+%             (2*2000,243.36/8)
+%             (2*2200,264.08/8)
+%             (2*2400,288.86/8)
+%             (2*2600,307.5 /8)
+%             (2*2800,331.7 /8)
+%             (2*3000,353.92/8)
+%             (2*3200,374.92/8)
+%         };
+
+%         % 
+%         \addplot[BlueGreen, thick, line cap=round, smooth] coordinates {
+%             (2*1600,186.46/8)
+%             (2*1800,214.44/8)
+%             (2*2000,239.36/8)
+%             (2*2200,245.44/8)
+%             (2*2400,272.26/8)
+%             (2*2600,301.7 /8)
+%             (2*2800,315   /8)
+%             (2*3000,335.24/8)
+%             (2*3200,364.18/8)
+%         };
+        
+%         \legend{
+%             Max,%
+%             DDR5 8\,Gb SR,%
+%             DDR5 16\,Gb SR,%
+%             DDR5 8\,Gb DR,%
+%             DDR5 16\,Gb DR%
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{DDR5, Linear}
+%         \label{fig:bw:linear_DDR5}
+%     \end{subfigure}
+%     %%%
+%     \hfill
+%     %%%
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Bandwidth [GB/s]}},
+%         	xlabel={\textbf{Pin Data Rate [MT/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 2*1200,
+%             ymin = 15,
+%             xmax = 2*3400,
+%             legend style={at={(0.05,0.70)}, anchor=west}
+%         ]
+        
+%         % Max
+%         \addplot[Black, thick, line cap=round, smooth] coordinates {
+%             (2*1600, 204.8/8)
+%             (2*1800, 230.4/8)
+%             (2*2000, 256  /8)
+%             (2*2200, 281.6/8)
+%             (2*2400, 307.2/8)
+%             (2*2600, 332.8/8)
+%             (2*2800, 358.4/8)
+%             (2*3000, 384  /8) 
+%             (2*3200, 409.6/8) 
+%         };
+        
+%         % DDR5 8Gb SR
+%         \addplot[Purple, thick, line cap=round, smooth] coordinates {
+%             (2*1600,154.2 /8)
+%             (2*1800,159.76/8)
+%             (2*2000,169.26/8)
+%             (2*2200,169.6 /8)
+%             (2*2400,176.2 /8)
+%             (2*2600,173.18/8)
+%             (2*2800,179.3 /8)
+%             (2*3000,184   /8)
+%             (2*3200,183.56/8)
+%         };
+        
+%         % 
+%         \addplot[Magenta, thick, line cap=round, smooth] coordinates {
+%             (2*1600,165.18/8)
+%             (2*1800,178.04/8)
+%             (2*2000,196.66/8)
+%             (2*2200,208.58/8)
+%             (2*2400,224.62/8)
+%             (2*2600,234.14/8)
+%             (2*2800,244.94/8)
+%             (2*3000,256.16/8)
+%             (2*3200,260.22/8)
+%         };
+        
+%         % 
+%         \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+%             (2*1600,179.98/8)
+%             (2*1800,198   /8)
+%             (2*2000,219   /8)
+%             (2*2200,233.72/8)
+%             (2*2400,251.58/8)
+%             (2*2600,264.92/8)
+%             (2*2800,279.62/8)
+%             (2*3000,292.44/8)
+%             (2*3200,299.98/8)
+%         };
+
+%         % 
+%         \addplot[BlueGreen, thick, line cap=round, smooth] coordinates {
+%             (2*1600,180.6 /8)
+%             (2*1800,199.1 /8)
+%             (2*2000,219.08/8)
+%             (2*2200,235.34/8)
+%             (2*2400,256.92/8)
+%             (2*2600,271.6 /8)
+%             (2*2800,291.44/8)
+%             (2*3000,310   /8)
+%             (2*3200,325.9 /8)
+
+%         };
+        
+%         \legend{
+%             Max,
+%             DDR5 8\,Gb SR,
+%             DDR5 16\,Gb SR,
+%             DDR5 8\,Gb DR,
+%             DDR5 16\,Gb DR
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{DDR5, Random}
+%         \label{fig:bw:random_DDR5}
+%     \end{subfigure}
+%     %\caption{Sustainable Bandwidth for Different DDR5 Configurations, SR: Single Rank, DR: Dual Rank}
+%     \par\bigskip 
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Bandwidth [GB/s]}},
+%         	xlabel={\textbf{Pin Data Rate [MT/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 2*400,
+%             ymin = 5,
+%             xmax = 2*3400,
+%             legend style={at={(0.05,0.7)}, anchor=west}
+%         ]
+        
+%         % Max
+%         \addplot[Black, thick, line cap=round, smooth] coordinates {
+%             (2*800   , 102.4  /8)
+%             (2*933   , 119.424/8)
+%             (2*1066.5, 136.512/8)
+%             (2*1200  , 153.6  /8)
+%             (2*1333  , 170.624/8)
+%             (2*1466.5, 187.712/8)
+%             (2*1600  , 204.8  /8)
+%             (2*1800  , 230.4  /8)
+%             (2*2000  , 256    /8)
+%             (2*2200  , 281.6  /8)
+%             (2*2400  , 307.2  /8)
+%             (2*2600  , 332.8  /8)
+%             (2*2800  , 358.4  /8)
+%             (2*3000  , 384    /8) 
+%             (2*3200  , 409.6  /8) 
+%         };
+        
+%         % DDR4 SR
+%         \addplot[BrickRed, thick, line cap=round, smooth] coordinates {
+%             (2*800    , 88.26 /8)
+%             (2*933    , 101.31/8)
+%             (2*1066.5 , 114.62/8)
+%             (2*1200   , 128.43/8)
+%             (2*1333   , 140.64/8)
+%             (2*1466.5 , 153.37/8)
+%             (2*1600   , 166.5 /8)
+%         };
+        
+%         \addplot[BrickRed, thick, line cap=round, smooth, dashed] coordinates {
+%             (2*1600   , 166.5/8)
+%             (2*1800   , 187  /8)
+%             (2*2000   , 207  /8)
+%             (2*2200   , 227  /8)
+%         };
+        
+%         % DDR4 DR
+%         \addplot[Orange, thick, line cap=round, smooth] coordinates {
+%             (2*800   , 91.4  /8)
+%             (2*933   , 106.43/8)
+%             (2*1066.5, 116.63/8)
+%             (2*1200  , 132.34/8)
+%             (2*1333  , 147.23/8)
+%             (2*1466.5, 160.98/8)
+%             (2*1600  , 174.02/8)
+%         };
+        
+%         \addplot[Orange, line cap=round, smooth, dashed] coordinates {
+%             (2*1600  , 174.02/8)
+%             (2*1800  , 195   /8)
+%             (2*2000  , 215   /8)
+%             (2*2200  , 235   /8)
+%         };
+        
+%         % DDR5 SR
+%         \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+%             (2*1600,180.3 /8)
+%             (2*1800,200.5 /8)
+%             (2*2000,222.76/8)
+%             (2*2200,242.74/8)
+%             (2*2400,264.28/8)
+%             (2*2600,285.1 /8)
+%             (2*2800,306.88/8)
+%             (2*3000,327.4 /8)
+%             (2*3200,346.16/8)
+%         };
+
+%         % DDR5 DR
+%         \addplot[BlueGreen, thick, line cap=round, smooth] coordinates {
+%             (2*1600, 186.46/8)
+%             (2*1800, 214.44/8)
+%             (2*2000, 239.36/8)
+%             (2*2200, 245.44/8)
+%             (2*2400, 272.26/8)
+%             (2*2600, 301.7 /8)
+%             (2*2800, 315   /8)
+%             (2*3000, 335.24/8)
+%             (2*3200, 364.18/8)
+%         };
+        
+%         \legend{
+%             Max,
+%             DDR4 16\,Gb SR,,
+%             DDR4 16\,Gb DR,,
+%             DDR5 16\,Gb SR,
+%             DDR5 16\,Gb DR
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{DDR4 vs. DDR5, Linear}
+%         \label{fig:bw:linear_DDR4_DDR5}
+%     \end{subfigure}
+%     %%%
+%     \hfill
+%     %%%
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Bandwidth [GB/s]}},
+%         	xlabel={\textbf{Pin Data Rate [MT/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 2*400,
+%             ymin = 5,
+%             xmax = 2*3400,
+%             legend style={at={(0.05,0.70)}, anchor=west}
+%         ]
+        
+%         % Max
+%         \addplot[Black, thick, line cap=round, smooth] coordinates {
+%             (2*800   , 102.4  /8)
+%             (2*933   , 119.424/8)
+%             (2*1066.5, 136.512/8)
+%             (2*1200  , 153.6  /8)
+%             (2*1333  , 170.624/8)
+%             (2*1466.5, 187.712/8)
+%             (2*1600  , 204.8  /8)
+%             (2*1800  , 230.4  /8)
+%             (2*2000  , 256    /8)
+%             (2*2200  , 281.6  /8)
+%             (2*2400  , 307.2  /8)
+%             (2*2600  , 332.8  /8)
+%             (2*2800  , 358.4  /8)
+%             (2*3000  , 384    /8) 
+%             (2*3200  , 409.6  /8) 
+%         };
+        
+%         % DDR4 SR
+%         \addplot[BrickRed, thick, line cap=round, smooth] coordinates {
+%             (2*800   , 74.64/8)
+%             (2*933   , 79.12/8)
+%             (2*1066.5, 85.81/8)
+%             (2*1200  , 86.68/8)
+%             (2*1333  , 89.09/8)
+%             (2*1466.5, 88.52/8)
+%             (2*1600  , 88.51/8)
+%         };
+        
+%         \addplot[BrickRed, thick, line cap=round, smooth, dashed] coordinates {
+%             (2*1600  , 88.51/8)
+%             (2*1800  , 90   /8)
+%             (2*2000  , 91   /8)
+%             (2*2200  , 91   /8)
+%         };
+        
+%         % DDR4 DR
+%         \addplot[Orange, thick, line cap=round, smooth] coordinates {
+%             (2*800   , 87.33 /8)
+%             (2*933   , 95.61 /8)
+%             (2*1066.5, 101.87/8)
+%             (2*1200  , 113.43/8)
+%             (2*1333  , 124.85/8)
+%             (2*1466.5, 134.69/8)
+%             (2*1600  , 141.27/8)
+%         };
+        
+%         \addplot[Orange, thick, line cap=round, smooth, dashed] coordinates {
+%             (2*1600  , 141.27/8)
+%             (2*1800  , 146   /8)
+%             (2*2000  , 148   /8)
+%             (2*2200  , 150   /8)
+%             % Alt
+%             %(2*1600  , 141.27/8)
+%             %(2*1800  , 150   /8)
+%             %(2*2000  , 160   /8)
+%             %(2*2200  , 170   /8)
+%         };
+        
+%         % DDR5 SR
+%         \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+%             (2*1600,165.18/8)
+%             (2*1800,178.04/8)
+%             (2*2000,196.66/8)
+%             (2*2200,208.58/8)
+%             (2*2400,224.62/8)
+%             (2*2600,234.14/8)
+%             (2*2800,244.94/8)
+%             (2*3000,256.16/8)
+%             (2*3200,260.22/8)
+%         };
+
+%         % DDR5 DR
+%         \addplot[BlueGreen, thick, line cap=round, smooth] coordinates {
+%             (2*1600,180.6 /8)
+%             (2*1800,199.1 /8)
+%             (2*2000,219.08/8)
+%             (2*2200,235.34/8)
+%             (2*2400,256.92/8)
+%             (2*2600,271.6 /8)
+%             (2*2800,291.44/8)
+%             (2*3000,310   /8)
+%             (2*3200,325.9 /8)
+%         };
+        
+%         \legend{
+%             Max,
+%             DDR4 16\,Gb SR,,
+%             DDR4 16\,Gb DR,,
+%             DDR5 16\,Gb SR,
+%             DDR5 16\,Gb DR
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{DDR4 vs. DDR5, Random}
+%         \label{fig:bw:random_DDR4_DDR5}
+%     \end{subfigure}
+%     \caption{Sustainable Bandwidth for Different DDR5 Configurations and DDR4 vs. DDR5, SR: Single Rank, DR: Dual Rank}
+%     \label{fig:bw}
+% \end{sidewaysfigure*}%*}
+% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% \begin{sidewaysfigure*}[p]
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Latency [ns]}},
+%         	xlabel={\textbf{Bandwidth [GB/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             %height = 0.9\columnwidth,
+%             xmin = 0,
+%             ymin = 0,
+%             xmax = 30,
+%             ymax = 300,
+%             legend style={at={(0.05,0.85)}, anchor=west}
+%             %xmax = 10000
+%         ]
+        
+        
+%         % DDR4 16Gb SR
+%         \addplot[BrickRed, thick, mark=square, line cap=round, smooth] coordinates {
+%         (12.8  /8,  39.9 )
+%         (25.6  /8,  41.1 )
+%         (38.4  /8,  43.1 )
+%         (51.2  /8,  43.9 )
+%         (64.0  /8,  44.6 )
+%         (76.8  /8,  45.1 )
+%         (89.6  /8,  46.2 )
+%         (102.34/8,  46.8 )
+%         (115.21/8,  50.9 )
+%         (127.99/8,  57.0 )
+%         (140.81/8,  66.8 )
+%         (153.61/8,  86.5 )
+%         (166.18/8,  146.5)
+%         %(166.52,  151.9)
+%         %(166.52,  154.3)
+%         %(166.52,  154.9)
+%         %(166.52,  154.9)
+%         %(166.52,  154.9)
+%         };
+        
+%         % DDR5 16Gb SR
+%         \addplot[MidnightBlue, thick, mark=square, line cap=round, smooth] coordinates {
+%             (12.8  /8,  42.2 )
+%             (25.6  /8,  39.2 )
+%             (38.4  /8,  39.2 )
+%             (51.2  /8,  41.9 )
+%             (64    /8,  43.6 )
+%             (76.8  /8,  46.5 )
+%             (89.6  /8,  49.7 )
+%             (102.4 /8,  53.9 )
+%             (115.2 /8,  59.3 )
+%             (128   /8,  69.1 )
+%             (140.78/8,  79.3 )
+%             (153.6 /8,  99.2 )
+%             (166.38/8,  138.6)
+%             (178.94/8,  237.9)
+%             (180.14/8,  279.1)
+%             %(180.22,  279.9)
+%             %(180.22,  279.8)
+%             %(180.26,  280.6)
+%         };
+        
+%         \addplot[Black, thick, line cap=round, smooth, dashed] coordinates {
+%             (25.6, 0)
+%             (25.6,  300)
+%         } node[below, pos=0.5, rotate=90] {Max. Bandwidth 25.6\,GB/s};
+        
+%         \legend{
+%             DDR4,% 16Gb SR
+%             DDR5,% 16Gb SR
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{16\,Gb Single Rank, Linear}
+%         \label{fig:lat_bw:linear_16Gb_SR}
+%     \end{subfigure}
+%     \hfill
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Latency [ns]}},
+%         	xlabel={\textbf{Bandwidth [GB/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             %height = 0.9\columnwidth,
+%             xmin = 0,
+%             ymin = 0,
+%             xmax = 30,
+%             ymax = 300,
+%             legend style={at={(0.05,0.85)}, anchor=west}
+%             %xmax = 10000
+%         ]
+        
+%         % DDR4 16Gb DR
+%         \addplot[BrickRed, thick, mark=square, line cap=round, smooth] coordinates {
+%             (12.8  /8 ,  38.4 )
+%             (25.6  /8 ,  39.4 )
+%             (38.4  /8 ,  39.2 )
+%             (51.2  /8 ,  41   )
+%             (63.98 /8 ,  42.8 )
+%             (76.8  /8 ,  44.7 )
+%             (89.6  /8 ,  48.1 )
+%             (102.38/8 ,  52.8 )
+%             (115.21/8 ,  57.1 )
+%             (128   /8 ,  64.4 )
+%             (140.73/8 ,  72.3 )
+%             (153.57/8 ,  86.3 )
+%             (166.39/8 ,  111  )
+%             (173.97/8 ,  163.3)
+%             %(174.34 ,  163.5)
+%             %(174.02   164.9)
+%             %(174.34   164.8)
+%             %(174.02   165.1)
+%         };
+        
+%         % DDR5 16Gb DR
+%         \addplot[MidnightBlue, thick, mark=square, line cap=round, smooth] coordinates {
+%             (12.8  /8,  47.3 )
+%             (25.6  /8,  42.2 )
+%             (38.4  /8,  39.5 )
+%             (51.2  /8,  39.1 )
+%             (64    /8,  39.4 )
+%             (76.8  /8,  39.9 )
+%             (89.56 /8,  41.1 )
+%             (102.4 /8,  43.4 )
+%             (115.2 /8,  45.3 )
+%             (127.92/8,  49.6 )
+%             (140.8 /8,  55.6 )
+%             (153.6 /8,  65.3 )
+%             (166.38/8,  79.1 )
+%             (179.14/8,  117.6)
+%             (186.46/8,  262.6)
+%             %(187.28,  290.6)
+%             %(184.9   274  )
+%             %(184.52  252  )
+%         };
+        
+%         \addplot[Black, thick, line cap=round, smooth, dashed] coordinates {
+%             (25.6, 0)
+%             (25.6,  300)
+%         } node[below, pos=0.5, rotate=90] {Max. Bandwidth 25.6\,GB/s};
+        
+%         \legend{
+%             DDR4,
+%             DDR5,
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{16 Gb Dual Rank, Linear}
+%         \label{fig:lat_bw:linear_16Gb_DR}
+%     \end{subfigure}
+%     %%%%
+%     \centering
+%     \par\bigskip 
+%     %%%%
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Latency [ns]}},
+%         	xlabel={\textbf{Bandwidth [GB/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 0,
+%             ymin = 0,
+%             xmax = 30,
+%             ymax = 300,
+%             legend style={at={(0.05,0.85)}, anchor=west}
+%         ]
+        
+%         % DDR4 16Gb SR
+%         \addplot[BrickRed, thick, mark=square, line cap=round, smooth] coordinates {
+%             (12.8 /8,  52.3) 
+%             (25.6 /8,  60.3) 
+%             (38.4 /8,  72.2) 
+%             (51.2 /8,  84.5) 
+%             (64.0 /8, 102.1)
+%             (76.79/8, 138.4)
+%             (88.42/8, 280.1)
+%             %(88.45, 282.6)
+%             %(88.5 , 282.6)
+%             %(88.49, 282.6)
+%             %(88.48, 282.8)
+%             %(88.49, 282.7)
+%             %(88.48, 282.7)
+%             %(88.47, 282.9)
+%             %(88.49, 282.9)
+%             %(88.51, 282.7)
+%             %(88.51, 282.7)
+%             %(88.51, 282.8)
+%         };
+        
+%         % DDR5 16Gb SR
+%         \addplot[MidnightBlue, thick, mark=square, line cap=round, smooth] coordinates {
+%             (12.78 /8,  47.5 )
+%             (25.58 /8,  51.2 )
+%             (38.36 /8,  56.4 )
+%             (51.16 /8,  60.6 )
+%             (63.94 /8,  67.2 )
+%             (76.72 /8,  73   )
+%             (89.52 /8,  82.3 )
+%             (102.28/8,  92.7 )
+%             (115.1 /8,  104.3)
+%             (127.86/8,  120.3)
+%             (140.56/8,  145.2)
+%             (153.34/8,  179.4)
+%             (164.96/8,  265.7)
+%             %(165.12,  266.7)
+%             %(165.32,  267.8)
+%             %(165.38,  267.3)
+%             %(165.24,  267.2)
+%             %(165.38,  266.7)
+%         };
+        
+%         \addplot[Black, thick, line cap=round, smooth, dashed] coordinates {
+%             (25.6, 0)
+%             (25.6,  300)
+%         } node[below, pos=0.5, rotate=90] {Max. Bandwidth 25.6\,GB/s};
+        
+%         \legend{
+%             DDR4,% 16Gb SR
+%             DDR5,% 16Gb SR
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{16\,Gb Single Rank, Random}
+%         \label{fig:lat_bw:random_16Gb_SR}
+%     \end{subfigure}
+%     \hfill
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Latency [ns]}},
+%         	xlabel={\textbf{Bandwidth [GB/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 0,
+%             ymin = 0,
+%             xmax = 30,
+%             ymax = 300,
+%             legend style={at={(0.05,0.85)}, anchor=west}
+%             %xmax = 10000
+%         ]
+        
+%         % DDR4 16Gb DR
+%         \addplot[BrickRed, thick, mark=square, line cap=round, smooth] coordinates {
+%             (12.8  /8, 49.5 )
+%             (25.6  /8, 52.8 )
+%             (38.4  /8, 58.4 )
+%             (51.2  /8, 63.7 )
+%             (63.97 /8, 69.1 )
+%             (76.79 /8, 75   )
+%             (89.6  /8, 83   )
+%             (102.34/8, 94.8 )
+%             (115.19/8, 110.3)
+%             (127.97/8, 132.1)
+%             (140.6 /8, 192.2)
+%             %(141.64, 199.1)
+%             %(141.51, 200.3)
+%             %(141.52, 200.6)
+%             %(141.56, 200.5)
+%             %(141.52, 200.7)
+%             %(141.51, 200.5)
+%             %(141.55, 200.4)
+%         };
+        
+%         % DDR5 16Gb DR
+%         \addplot[MidnightBlue, thick, mark=square, line cap=round, smooth] coordinates {
+%             (12.78 /8 , 46.9 )
+%             (25.58 /8 , 48.1 )
+%             (38.36 /8 , 51.6 )
+%             (51.16 /8 , 52.9 )
+%             (63.94 /8 , 56.9 )
+%             (76.72 /8 , 59   )
+%             (89.48 /8 , 63.7 )
+%             (102.3 /8 , 67.2 )
+%             (115.1 /8 , 73.8 )
+%             (127.78/8 , 81.1 )
+%             (140.64/8 , 91.2 )
+%             (153.44/8 , 108.2)
+%             (166.18/8 , 139.8)
+%             (178.8 /8 , 232.6)
+%             (181.66/8 , 268.6)
+%             %(181.8  , 269.8)
+%             %(181.7  , 267.3)
+%             %(181.5  , 267.3)
+%         };
+        
+%         \addplot[Black, thick, line cap=round, smooth, dashed] coordinates {
+%             (25.6, 0)
+%             (25.6,  300)
+%         } node[below, pos=0.5, rotate=90] {Max. Bandwidth 25.6\,GB/s};
+        
+%         \legend{
+%             DDR4,
+%             DDR5,
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{16 Gb Dual Rank, Random}
+%         \label{fig:lat_bw:random_16Gb_DR}
+%     \end{subfigure}
+%     %%%%
+%     \caption{Average Response Latency over Bandwidth for DDR4-3200 vs. DDR5-3200}
+%     \label{fig:lat_bw}
+% \end{sidewaysfigure*}
+% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% \begin{sidewaysfigure*}[p]
+%     \centering
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Bandwidth [GB/s]}},
+%         	xlabel={\textbf{Pin Data Rate [MT/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 2*1200,
+%             ymin = 15,
+%             %xmax = 200,
+%             %ymax = 300,
+%             legend style={at={(0.05,0.7)}, anchor=west}
+%         ]
+        
+%         % Max
+%         \addplot[Black, thick, line cap=round, smooth] coordinates {
+%             (2*1600,204.8/8)
+%             (2*1800,230.4/8)
+%             (2*2000,256  /8)
+%             (2*2200,281.6/8)    
+%             (2*2400,307.2/8)    
+%             (2*2600,332.8/8)    
+%             (2*2800,358.4/8)    
+%             (2*3000,384  /8)  
+%             (2*3200,409.6/8)    
+%         };
+        
+%         % No Refresh
+%         \addplot[Red, thick, line cap=round, smooth] coordinates {
+%             (2*1600,197.08/8)
+%             (2*1800,220.14/8)
+%             (2*2000,244.2 /8)
+%             (2*2200,266.68/8)
+%             (2*2400,290.26/8)
+%             (2*2600,312.42/8)
+%             (2*2800,336.1 /8)
+%             (2*3000,359   /8)
+%             (2*3200,380.02/8)
+
+%         };
+        
+%         % all bank
+%         \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+%             (2*1600,180.3 /8)
+%             (2*1800,200.5 /8)
+%             (2*2000,222.76/8)
+%             (2*2200,242.74/8)
+%             (2*2400,264.28/8)
+%             (2*2600,285.1 /8)
+%             (2*2800,306.88/8)
+%             (2*3000,327.4 /8)
+%             (2*3200,346.16/8)
+%         };
+        
+%         % same-bank
+%         \addplot[Green, thick, line cap=round, smooth] coordinates {
+%             (2*1600,196.84/8)
+%             (2*1800,217.64/8)
+%             (2*2000,240.28/8)
+%             (2*2200,262   /8)
+%             (2*2400,284.58/8)
+%             (2*2600,306.6 /8)
+%             (2*2800,329.96/8)
+%             (2*3000,351.84/8)
+%             (2*3200,370.76/8)
+%         };
+%         %
+%         \legend{
+%             Max,
+%             No Refresh,
+%             All-Bank Refresh,
+%             Same-Bank Refresh
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{16\,Gb Single Rank, Linear}
+%         \label{fig:refresh:linear_16Gb_SR}
+%     \end{subfigure}
+%     \hfill
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Bandwidth [GB/s]}},
+%         	xlabel={\textbf{Pin Data Rate [MT/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 2*1200,
+%             ymin = 15,
+%             %xmax = 200,
+%             %ymax = 300,
+%             legend style={at={(0.05,0.7)}, anchor=west}
+%         ]
+        
+%         % Max
+%         \addplot[Black, thick, line cap=round, smooth] coordinates {
+%             (2*1600,204.8/8)
+%             (2*1800,230.4/8)
+%             (2*2000,256  /8)
+%             (2*2200,281.6/8)    
+%             (2*2400,307.2/8)    
+%             (2*2600,332.8/8)    
+%             (2*2800,358.4/8)    
+%             (2*3000,384  /8)  
+%             (2*3200,409.6/8)    
+%         };
+        
+%         % No Refresh
+%         \addplot[Red, thick, line cap=round, smooth] coordinates {
+%             (2*1600,200.92/8)
+%             (2*1800,225.9 /8)
+%             (2*2000,251.16/8)
+%             (2*2200,275.66/8)
+%             (2*2400,299.84/8)
+%             (2*2600,326.64/8)
+%             (2*2800,352.34/8)
+%             (2*3000,377.74/8)
+%             (2*3200,401.78/8)
+%         };
+        
+%         % all bank
+%         \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+%             (2*1600,186.46/8)
+%             (2*1800,214.44/8)
+%             (2*2000,239.36/8)
+%             (2*2200,245.44/8)
+%             (2*2400,272.26/8)
+%             (2*2600,301.7 /8)
+%             (2*2800,315   /8)
+%             (2*3000,335.24/8)
+%             (2*3200,364.18/8)
+%         };
+        
+%         % same-bank
+%         \addplot[Green, thick, line cap=round, smooth] coordinates {
+%             (2*1600,200.48/8)
+%             (2*1800,225.46/8)
+%             (2*2000,250.64/8)
+%             (2*2200,275.42/8)
+%             (2*2400,300.44/8)
+%             (2*2600,325.92/8)
+%             (2*2800,351.54/8)
+%             (2*3000,376.6 /8)
+%             (2*3200,400.62/8)
+%         };
+%         %
+%         \legend{
+%             Max,
+%             No Refresh,
+%             All-Bank Refresh,
+%             Same-Bank Refresh
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{16\,Gb Dual Rank, Linear}
+%         \label{fig:refresh:linear_16Gb_DR}
+%     \end{subfigure}
+%     %%%%
+%     \par\bigskip 
+%     %%%%
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Bandwidth [GB/s]}},
+%         	xlabel={\textbf{Pin Data Rate [MT/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 2*1200,
+%             ymin = 15,
+%             %xmax = 200,
+%             %ymax = 300,
+%             legend style={at={(0.05,0.7)}, anchor=west}
+%         ]
+        
+%         % Max
+%         \addplot[Black, thick, line cap=round, smooth] coordinates {
+%             (2*1600,204.8/8)
+%             (2*1800,230.4/8)
+%             (2*2000,256  /8)
+%             (2*2200,281.6/8)    
+%             (2*2400,307.2/8)    
+%             (2*2600,332.8/8)    
+%             (2*2800,358.4/8)    
+%             (2*3000,384  /8)  
+%             (2*3200,409.6/8)    
+%         };
+        
+%         % No Refresh
+%         \addplot[Red, thick, line cap=round, smooth] coordinates {
+%             (2*1600,183.06/8)
+%             (2*1800,197.48/8)
+%             (2*2000,216.9 /8)
+%             (2*2200,230.64/8)
+%             (2*2400,248.1 /8)
+%             (2*2600,258.6 /8)
+%             (2*2800,270.36/8)
+%             (2*3000,282.52/8)
+%             (2*3200,286.2 /8)
+%         };
+        
+%         % all bank
+%         \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+%             (2*1600,165.18/8)
+%             (2*1800,178.04/8)
+%             (2*2000,196.66/8)
+%             (2*2200,208.58/8)
+%             (2*2400,224.62/8)
+%             (2*2600,234.14/8)
+%             (2*2800,244.94/8)
+%             (2*3000,256.16/8)
+%             (2*3200,260.22/8)
+%         };
+        
+%         % same-bank
+%         \addplot[Green, thick, line cap=round, smooth] coordinates {
+%             (2*1600,173.7 /8)
+%             (2*1800,185.14/8)
+%             (2*2000,202.66/8)
+%             (2*2200,211.08/8)
+%             (2*2400,225.28/8)
+%             (2*2600,231.24/8)
+%             (2*2800,240.22/8)
+%             (2*3000,250.4 /8)
+%             (2*3200,253.24/8)
+%         };
+%         %
+%         \legend{
+%             Max,
+%             No Refresh,
+%             All-Bank Refresh,
+%             Same-Bank Refresh
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{16\,Gb Single Rank, Random}
+%         \label{fig:refresh:random_16Gb_SR}
+%     \end{subfigure}
+%     \hfill
+%     \begin{subfigure}[b]{0.49\textheight}
+%         \centering
+%         \begin{tikzpicture}
+%         \begin{axis}[
+%         	ylabel={\textbf{Bandwidth [GB/s]}},
+%         	xlabel={\textbf{Pin Data Rate [MT/s]}},
+%             grid=minor,
+%             width = 0.49\textheight,
+%             height = 7cm,
+%             xmin = 2*1200,
+%             ymin = 15,
+%             legend style={at={(0.05,0.7)}, anchor=west}
+%         ]
+        
+%         % Max
+%         \addplot[Black, thick, line cap=round, smooth] coordinates {
+%             (2*1600,204.8/8)
+%             (2*1800,230.4/8)
+%             (2*2000,256  /8)
+%             (2*2200,281.6/8)    
+%             (2*2400,307.2/8)    
+%             (2*2600,332.8/8)    
+%             (2*2800,358.4/8)    
+%             (2*3000,384  /8)  
+%             (2*3200,409.6/8)    
+%         };
+        
+%         % No Refresh
+%         \addplot[Red, thick, line cap=round, smooth] coordinates {
+%             (2*1600,194.2 /8)
+%             (2*1800,216.34/8)
+%             (2*2000,240.78/8)
+%             (2*2200,262.66/8)
+%             (2*2400,286.56/8)
+%             (2*2600,308.88/8)
+%             (2*2800,332.98/8)
+%             (2*3000,355.5 /8)
+%             (2*3200,376.22/8)
+%         };
+        
+%         % all bank
+%         \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+%             (2*1600,180.60/8)
+%             (2*1800,199.10/8)
+%             (2*2000,219.08/8)
+%             (2*2200,235.34/8)
+%             (2*2400,256.92/8)
+%             (2*2600,271.60/8)
+%             (2*2800,291.44/8)
+%             (2*3000,310.00/8)
+%             (2*3200,325.90/8)
+%         };
+        
+%         % same-bank
+%         \addplot[Green, thick, line cap=round, smooth] coordinates {
+%             (2*1600,192.78/8)
+%             (2*1800,214.74/8)
+%             (2*2000,238.96/8)
+%             (2*2200,260.06/8)
+%             (2*2400,283.28/8)
+%             (2*2600,303.78/8)
+%             (2*2800,325.60/8)
+%             (2*3000,345.60/8)
+%             (2*3200,360.54/8)
+%         };
+%         %
+%         \legend{
+%             Max,
+%             No Refresh,
+%             All-Bank Refresh,
+%             Same-Bank Refresh
+%         }
+%         \end{axis}
+%         \end{tikzpicture}
+%         \caption{16\,Gb Dual Rank, Random}
+%         \label{fig:refresh:random_16Gb_DR}
+%     \end{subfigure}
+%     %
+%     \caption{DDR5 All-Bank Refresh vs. Same-Bank Refresh}
+%     \label{fig:refresh}
+% \end{sidewaysfigure*}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%% New Figures
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\begin{figure*}%[h!]
+    \centering
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Bandwidth [GB/s]}},
+        	xlabel={\textbf{Pin Data Rate [MT/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 2*1200,
+            ymin = 15,
+            xmax = 2*3400,
+            legend style={legend pos=north west, font=\scriptsize}
+        ]
+        
+        % Max
+        \addplot[Black, thick, line cap=round, smooth] coordinates {
+            (2*1600,204.8/8)
+            (2*1800,230.4/8)
+            (2*2000,256  /8)
+            (2*2200,281.6/8)
+            (2*2400,307.2/8)
+            (2*2600,332.8/8)
+            (2*2800,358.4/8)
+            (2*3000,384  /8) 
+            (2*3200,409.6/8) 
+        };
+        
+        % DDR5 8Gb SR
+        \addplot[Purple, thick, line cap=round, smooth] coordinates {
+           (2*1600,178.44/8)
+           (2*1800,197.16/8)
+           (2*2000,219.04/8)
+           (2*2200,237.38/8)
+           (2*2400,257.80/8)
+           (2*2600,276.02/8)
+           (2*2800,295.48/8)
+           (2*3000,315.32/8)
+           (2*3200,331.86/8)
+ 
+        };
+        
+        % DDR5 16Gb SR
+        \addplot[Magenta, thick, line cap=round, smooth] coordinates {
+            (2*1600,180.3 /8)
+            (2*1800,200.5 /8)
+            (2*2000,222.76/8)
+            (2*2200,242.74/8)
+            (2*2400,264.28/8)
+            (2*2600,285.1 /8)
+            (2*2800,306.88/8)
+            (2*3000,327.4 /8)
+            (2*3200,346.16/8)
+        };
+        
+        % DDR5 8Gb DR
+        \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+            (2*1600,197.52/8)
+            (2*1800,215.02/8)
+            (2*2000,243.36/8)
+            (2*2200,264.08/8)
+            (2*2400,288.86/8)
+            (2*2600,307.5 /8)
+            (2*2800,331.7 /8)
+            (2*3000,353.92/8)
+            (2*3200,374.92/8)
+        };
+
+        % 
+        \addplot[BlueGreen, thick, line cap=round, smooth] coordinates {
+            (2*1600,186.46/8)
+            (2*1800,214.44/8)
+            (2*2000,239.36/8)
+            (2*2200,245.44/8)
+            (2*2400,272.26/8)
+            (2*2600,301.7 /8)
+            (2*2800,315   /8)
+            (2*3000,335.24/8)
+            (2*3200,364.18/8)
+        };
+        
+        \legend{
+            Maximum,%
+            DDR5 8\,Gb SR,%
+            DDR5 16\,Gb SR,%
+            DDR5 8\,Gb DR,%
+            DDR5 16\,Gb DR%
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{DDR5, Linear}
+        \label{fig:bw:linear_DDR5}
+    \end{subfigure}
+    %%%
+    \hfill
+    %%%
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Bandwidth [GB/s]}},
+        	xlabel={\textbf{Pin Data Rate [MT/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 2*1200,
+            ymin = 15,
+            xmax = 2*3400,
+            legend style={legend pos=north west, font=\scriptsize}
+        ]
+        
+        % Max
+        \addplot[Black, thick, line cap=round, smooth] coordinates {
+            (2*1600, 204.8/8)
+            (2*1800, 230.4/8)
+            (2*2000, 256  /8)
+            (2*2200, 281.6/8)
+            (2*2400, 307.2/8)
+            (2*2600, 332.8/8)
+            (2*2800, 358.4/8)
+            (2*3000, 384  /8) 
+            (2*3200, 409.6/8) 
+        };
+        
+        % DDR5 8Gb SR
+        \addplot[Purple, thick, line cap=round, smooth] coordinates {
+            (2*1600,154.2 /8)
+            (2*1800,159.76/8)
+            (2*2000,169.26/8)
+            (2*2200,169.6 /8)
+            (2*2400,176.2 /8)
+            (2*2600,173.18/8)
+            (2*2800,179.3 /8)
+            (2*3000,184   /8)
+            (2*3200,183.56/8)
+        };
+        
+        % 
+        \addplot[Magenta, thick, line cap=round, smooth] coordinates {
+            (2*1600,165.18/8)
+            (2*1800,178.04/8)
+            (2*2000,196.66/8)
+            (2*2200,208.58/8)
+            (2*2400,224.62/8)
+            (2*2600,234.14/8)
+            (2*2800,244.94/8)
+            (2*3000,256.16/8)
+            (2*3200,260.22/8)
+        };
+        
+        % 
+        \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+            (2*1600,179.98/8)
+            (2*1800,198   /8)
+            (2*2000,219   /8)
+            (2*2200,233.72/8)
+            (2*2400,251.58/8)
+            (2*2600,264.92/8)
+            (2*2800,279.62/8)
+            (2*3000,292.44/8)
+            (2*3200,299.98/8)
+        };
+
+        % 
+        \addplot[BlueGreen, thick, line cap=round, smooth] coordinates {
+            (2*1600,180.6 /8)
+            (2*1800,199.1 /8)
+            (2*2000,219.08/8)
+            (2*2200,235.34/8)
+            (2*2400,256.92/8)
+            (2*2600,271.6 /8)
+            (2*2800,291.44/8)
+            (2*3000,310   /8)
+            (2*3200,325.9 /8)
+
+        };
+        
+        \legend{
+            Maximum,
+            DDR5 8\,Gb SR,
+            DDR5 16\,Gb SR,
+            DDR5 8\,Gb DR,
+            DDR5 16\,Gb DR
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{DDR5, Random}
+        \label{fig:bw:random_DDR5}
+    \end{subfigure}
+    %\caption{Sustainable Bandwidth for Different DDR5 Configurations, SR: Single Rank, DR: Dual Rank}
+    \vskip\baselineskip
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Bandwidth [GB/s]}},
+        	xlabel={\textbf{Pin Data Rate [MT/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 2*400,
+            ymin = 5,
+            xmax = 2*3400,
+            legend style={legend pos=north west, font=\scriptsize}
+        ]
+        
+        % Max
+        \addplot[Black, thick, line cap=round, smooth] coordinates {
+            (2*800   , 102.4  /8)
+            (2*933   , 119.424/8)
+            (2*1066.5, 136.512/8)
+            (2*1200  , 153.6  /8)
+            (2*1333  , 170.624/8)
+            (2*1466.5, 187.712/8)
+            (2*1600  , 204.8  /8)
+            (2*1800  , 230.4  /8)
+            (2*2000  , 256    /8)
+            (2*2200  , 281.6  /8)
+            (2*2400  , 307.2  /8)
+            (2*2600  , 332.8  /8)
+            (2*2800  , 358.4  /8)
+            (2*3000  , 384    /8) 
+            (2*3200  , 409.6  /8) 
+        };
+        
+        % DDR4 SR
+        \addplot[BrickRed, thick, line cap=round, smooth] coordinates {
+            (2*800    , 88.26 /8)
+            (2*933    , 101.31/8)
+            (2*1066.5 , 114.62/8)
+            (2*1200   , 128.43/8)
+            (2*1333   , 140.64/8)
+            (2*1466.5 , 153.37/8)
+            (2*1600   , 166.5 /8)
+        };
+        
+        \addplot[BrickRed, thick, line cap=round, smooth, dashed] coordinates {
+            (2*1600   , 166.5/8)
+            (2*1800   , 187  /8)
+            (2*2000   , 207  /8)
+            (2*2200   , 227  /8)
+        };
+        
+        % DDR4 DR
+        \addplot[Orange, thick, line cap=round, smooth] coordinates {
+            (2*800   , 91.4  /8)
+            (2*933   , 106.43/8)
+            (2*1066.5, 116.63/8)
+            (2*1200  , 132.34/8)
+            (2*1333  , 147.23/8)
+            (2*1466.5, 160.98/8)
+            (2*1600  , 174.02/8)
+        };
+        
+        \addplot[Orange, line cap=round, smooth, dashed] coordinates {
+            (2*1600  , 174.02/8)
+            (2*1800  , 195   /8)
+            (2*2000  , 215   /8)
+            (2*2200  , 235   /8)
+        };
+        
+        % DDR5 SR
+        \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+            (2*1600,180.3 /8)
+            (2*1800,200.5 /8)
+            (2*2000,222.76/8)
+            (2*2200,242.74/8)
+            (2*2400,264.28/8)
+            (2*2600,285.1 /8)
+            (2*2800,306.88/8)
+            (2*3000,327.4 /8)
+            (2*3200,346.16/8)
+        };
+
+        % DDR5 DR
+        \addplot[BlueGreen, thick, line cap=round, smooth] coordinates {
+            (2*1600, 186.46/8)
+            (2*1800, 214.44/8)
+            (2*2000, 239.36/8)
+            (2*2200, 245.44/8)
+            (2*2400, 272.26/8)
+            (2*2600, 301.7 /8)
+            (2*2800, 315   /8)
+            (2*3000, 335.24/8)
+            (2*3200, 364.18/8)
+        };
+        
+        \legend{
+            Maximum,
+            DDR4 16\,Gb SR,,
+            DDR4 16\,Gb DR,,
+            DDR5 16\,Gb SR,
+            DDR5 16\,Gb DR
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{DDR4 vs. DDR5, Linear}
+        \label{fig:bw:linear_DDR4_DDR5}
+    \end{subfigure}
+    %%%
+    \hfill
+    %%%
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Bandwidth [GB/s]}},
+        	xlabel={\textbf{Pin Data Rate [MT/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 2*400,
+            ymin = 5,
+            xmax = 2*3400,
+            legend style={legend pos=north west, font=\scriptsize}
+        ]
+        
+        % Max
+        \addplot[Black, thick, line cap=round, smooth] coordinates {
+            (2*800   , 102.4  /8)
+            (2*933   , 119.424/8)
+            (2*1066.5, 136.512/8)
+            (2*1200  , 153.6  /8)
+            (2*1333  , 170.624/8)
+            (2*1466.5, 187.712/8)
+            (2*1600  , 204.8  /8)
+            (2*1800  , 230.4  /8)
+            (2*2000  , 256    /8)
+            (2*2200  , 281.6  /8)
+            (2*2400  , 307.2  /8)
+            (2*2600  , 332.8  /8)
+            (2*2800  , 358.4  /8)
+            (2*3000  , 384    /8) 
+            (2*3200  , 409.6  /8) 
+        };
+        
+        % DDR4 SR
+        \addplot[BrickRed, thick, line cap=round, smooth] coordinates {
+            (2*800   , 74.64/8)
+            (2*933   , 79.12/8)
+            (2*1066.5, 85.81/8)
+            (2*1200  , 86.68/8)
+            (2*1333  , 89.09/8)
+            (2*1466.5, 88.52/8)
+            (2*1600  , 88.51/8)
+        };
+        
+        \addplot[BrickRed, thick, line cap=round, smooth, dashed] coordinates {
+            (2*1600  , 88.51/8)
+            (2*1800  , 90   /8)
+            (2*2000  , 91   /8)
+            (2*2200  , 91   /8)
+        };
+        
+        % DDR4 DR
+        \addplot[Orange, thick, line cap=round, smooth] coordinates {
+            (2*800   , 87.33 /8)
+            (2*933   , 95.61 /8)
+            (2*1066.5, 101.87/8)
+            (2*1200  , 113.43/8)
+            (2*1333  , 124.85/8)
+            (2*1466.5, 134.69/8)
+            (2*1600  , 141.27/8)
+        };
+        
+        \addplot[Orange, thick, line cap=round, smooth, dashed] coordinates {
+            (2*1600  , 141.27/8)
+            (2*1800  , 146   /8)
+            (2*2000  , 148   /8)
+            (2*2200  , 150   /8)
+            % Alt
+            %(2*1600  , 141.27/8)
+            %(2*1800  , 150   /8)
+            %(2*2000  , 160   /8)
+            %(2*2200  , 170   /8)
+        };
+        
+        % DDR5 SR
+        \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+            (2*1600,165.18/8)
+            (2*1800,178.04/8)
+            (2*2000,196.66/8)
+            (2*2200,208.58/8)
+            (2*2400,224.62/8)
+            (2*2600,234.14/8)
+            (2*2800,244.94/8)
+            (2*3000,256.16/8)
+            (2*3200,260.22/8)
+        };
+
+        % DDR5 DR
+        \addplot[BlueGreen, thick, line cap=round, smooth] coordinates {
+            (2*1600,180.6 /8)
+            (2*1800,199.1 /8)
+            (2*2000,219.08/8)
+            (2*2200,235.34/8)
+            (2*2400,256.92/8)
+            (2*2600,271.6 /8)
+            (2*2800,291.44/8)
+            (2*3000,310   /8)
+            (2*3200,325.9 /8)
+        };
+        
+        \legend{
+            Maximum,
+            DDR4 16\,Gb SR,,
+            DDR4 16\,Gb DR,,
+            DDR5 16\,Gb SR,
+            DDR5 16\,Gb DR
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{DDR4 vs. DDR5, Random}
+        \label{fig:bw:random_DDR4_DDR5}
+    \end{subfigure}
+    \caption{Sustainable Bandwidth for Different DDR5 Configurations and DDR4 vs. DDR5, SR: Single Rank, DR: Dual Rank}
+    \label{fig:bw}
+\end{figure*}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\begin{figure*}%[h!]
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Latency [ns]}},
+        	xlabel={\textbf{Bandwidth [GB/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            %height = 0.9\columnwidth,
+            xmin = 0,
+            ymin = 0,
+            xmax = 30,
+            ymax = 300,
+            legend style={legend pos=north west, font=\small}
+            %xmax = 10000
+        ]
+        
+        
+        % DDR4 16Gb SR
+        \addplot[BrickRed, thick, mark=square, line cap=round, smooth] coordinates {
+        (12.8  /8,  39.9 )
+        (25.6  /8,  41.1 )
+        (38.4  /8,  43.1 )
+        (51.2  /8,  43.9 )
+        (64.0  /8,  44.6 )
+        (76.8  /8,  45.1 )
+        (89.6  /8,  46.2 )
+        (102.34/8,  46.8 )
+        (115.21/8,  50.9 )
+        (127.99/8,  57.0 )
+        (140.81/8,  66.8 )
+        (153.61/8,  86.5 )
+        (166.18/8,  146.5)
+        %(166.52,  151.9)
+        %(166.52,  154.3)
+        %(166.52,  154.9)
+        %(166.52,  154.9)
+        %(166.52,  154.9)
+        };
+        
+        % DDR5 16Gb SR
+        \addplot[MidnightBlue, thick, mark=square, line cap=round, smooth] coordinates {
+            (12.8  /8,  42.2 )
+            (25.6  /8,  39.2 )
+            (38.4  /8,  39.2 )
+            (51.2  /8,  41.9 )
+            (64    /8,  43.6 )
+            (76.8  /8,  46.5 )
+            (89.6  /8,  49.7 )
+            (102.4 /8,  53.9 )
+            (115.2 /8,  59.3 )
+            (128   /8,  69.1 )
+            (140.78/8,  79.3 )
+            (153.6 /8,  99.2 )
+            (166.38/8,  138.6)
+            (178.94/8,  237.9)
+            (180.14/8,  279.1)
+            %(180.22,  279.9)
+            %(180.22,  279.8)
+            %(180.26,  280.6)
+        };
+        
+        \addplot[Black, thick, line cap=round, smooth, dashed] coordinates {
+            (25.6, 0)
+            (25.6,  300)
+        } node[below, pos=0.5, rotate=90, font=\small] {Maximum (25.6\,GB/s)};
+        
+        \legend{
+            DDR4,% 16Gb SR
+            DDR5,% 16Gb SR
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{16\,Gb Single Rank, Linear}
+        \label{fig:lat_bw:linear_16Gb_SR}
+    \end{subfigure}
+    \hfill
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Latency [ns]}},
+        	xlabel={\textbf{Bandwidth [GB/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            %height = 0.9\columnwidth,
+            xmin = 0,
+            ymin = 0,
+            xmax = 30,
+            ymax = 300,
+            legend style={legend pos=north west, font=\small}
+            %xmax = 10000
+        ]
+        
+        % DDR4 16Gb DR
+        \addplot[BrickRed, thick, mark=square, line cap=round, smooth] coordinates {
+            (12.8  /8 ,  38.4 )
+            (25.6  /8 ,  39.4 )
+            (38.4  /8 ,  39.2 )
+            (51.2  /8 ,  41   )
+            (63.98 /8 ,  42.8 )
+            (76.8  /8 ,  44.7 )
+            (89.6  /8 ,  48.1 )
+            (102.38/8 ,  52.8 )
+            (115.21/8 ,  57.1 )
+            (128   /8 ,  64.4 )
+            (140.73/8 ,  72.3 )
+            (153.57/8 ,  86.3 )
+            (166.39/8 ,  111  )
+            (173.97/8 ,  163.3)
+            %(174.34 ,  163.5)
+            %(174.02   164.9)
+            %(174.34   164.8)
+            %(174.02   165.1)
+        };
+        
+        % DDR5 16Gb DR
+        \addplot[MidnightBlue, thick, mark=square, line cap=round, smooth] coordinates {
+            (12.8  /8,  47.3 )
+            (25.6  /8,  42.2 )
+            (38.4  /8,  39.5 )
+            (51.2  /8,  39.1 )
+            (64    /8,  39.4 )
+            (76.8  /8,  39.9 )
+            (89.56 /8,  41.1 )
+            (102.4 /8,  43.4 )
+            (115.2 /8,  45.3 )
+            (127.92/8,  49.6 )
+            (140.8 /8,  55.6 )
+            (153.6 /8,  65.3 )
+            (166.38/8,  79.1 )
+            (179.14/8,  117.6)
+            (186.46/8,  262.6)
+            %(187.28,  290.6)
+            %(184.9   274  )
+            %(184.52  252  )
+        };
+        
+        \addplot[Black, thick, line cap=round, smooth, dashed] coordinates {
+            (25.6, 0)
+            (25.6,  300)
+        } node[below, pos=0.5, rotate=90, font=\small] {Maximum (25.6\,GB/s)};
+        
+        \legend{
+            DDR4,
+            DDR5,
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{16 Gb Dual Rank, Linear}
+        \label{fig:lat_bw:linear_16Gb_DR}
+    \end{subfigure}
+    %%%%
+    \vskip\baselineskip
+    %%%%
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Latency [ns]}},
+        	xlabel={\textbf{Bandwidth [GB/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 0,
+            ymin = 0,
+            xmax = 30,
+            ymax = 300,
+            legend style={legend pos=north west, font=\small}
+        ]
+        
+        % DDR4 16Gb SR
+        \addplot[BrickRed, thick, mark=square, line cap=round, smooth] coordinates {
+            (12.8 /8,  52.3) 
+            (25.6 /8,  60.3) 
+            (38.4 /8,  72.2) 
+            (51.2 /8,  84.5) 
+            (64.0 /8, 102.1)
+            (76.79/8, 138.4)
+            (88.42/8, 280.1)
+            %(88.45, 282.6)
+            %(88.5 , 282.6)
+            %(88.49, 282.6)
+            %(88.48, 282.8)
+            %(88.49, 282.7)
+            %(88.48, 282.7)
+            %(88.47, 282.9)
+            %(88.49, 282.9)
+            %(88.51, 282.7)
+            %(88.51, 282.7)
+            %(88.51, 282.8)
+        };
+        
+        % DDR5 16Gb SR
+        \addplot[MidnightBlue, thick, mark=square, line cap=round, smooth] coordinates {
+            (12.78 /8,  47.5 )
+            (25.58 /8,  51.2 )
+            (38.36 /8,  56.4 )
+            (51.16 /8,  60.6 )
+            (63.94 /8,  67.2 )
+            (76.72 /8,  73   )
+            (89.52 /8,  82.3 )
+            (102.28/8,  92.7 )
+            (115.1 /8,  104.3)
+            (127.86/8,  120.3)
+            (140.56/8,  145.2)
+            (153.34/8,  179.4)
+            (164.96/8,  265.7)
+            %(165.12,  266.7)
+            %(165.32,  267.8)
+            %(165.38,  267.3)
+            %(165.24,  267.2)
+            %(165.38,  266.7)
+        };
+        
+        \addplot[Black, thick, line cap=round, smooth, dashed] coordinates {
+            (25.6, 0)
+            (25.6,  300)
+        } node[below, pos=0.5, rotate=90, font=\small] {Maximum (25.6\,GB/s)};
+        
+        \legend{
+            DDR4,% 16Gb SR
+            DDR5,% 16Gb SR
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{16\,Gb Single Rank, Random}
+        \label{fig:lat_bw:random_16Gb_SR}
+    \end{subfigure}
+    \hfill
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Latency [ns]}},
+        	xlabel={\textbf{Bandwidth [GB/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 0,
+            ymin = 0,
+            xmax = 30,
+            ymax = 300,
+            legend style={legend pos=north west, font=\small}
+            %xmax = 10000
+        ]
+        
+        % DDR4 16Gb DR
+        \addplot[BrickRed, thick, mark=square, line cap=round, smooth] coordinates {
+            (12.8  /8, 49.5 )
+            (25.6  /8, 52.8 )
+            (38.4  /8, 58.4 )
+            (51.2  /8, 63.7 )
+            (63.97 /8, 69.1 )
+            (76.79 /8, 75   )
+            (89.6  /8, 83   )
+            (102.34/8, 94.8 )
+            (115.19/8, 110.3)
+            (127.97/8, 132.1)
+            (140.6 /8, 192.2)
+            %(141.64, 199.1)
+            %(141.51, 200.3)
+            %(141.52, 200.6)
+            %(141.56, 200.5)
+            %(141.52, 200.7)
+            %(141.51, 200.5)
+            %(141.55, 200.4)
+        };
+        
+        % DDR5 16Gb DR
+        \addplot[MidnightBlue, thick, mark=square, line cap=round, smooth] coordinates {
+            (12.78 /8 , 46.9 )
+            (25.58 /8 , 48.1 )
+            (38.36 /8 , 51.6 )
+            (51.16 /8 , 52.9 )
+            (63.94 /8 , 56.9 )
+            (76.72 /8 , 59   )
+            (89.48 /8 , 63.7 )
+            (102.3 /8 , 67.2 )
+            (115.1 /8 , 73.8 )
+            (127.78/8 , 81.1 )
+            (140.64/8 , 91.2 )
+            (153.44/8 , 108.2)
+            (166.18/8 , 139.8)
+            (178.8 /8 , 232.6)
+            (181.66/8 , 268.6)
+            %(181.8  , 269.8)
+            %(181.7  , 267.3)
+            %(181.5  , 267.3)
+        };
+        
+        \addplot[Black, thick, line cap=round, smooth, dashed] coordinates {
+            (25.6, 0)
+            (25.6,  300)
+        } node[below, pos=0.5, rotate=90, font=\small] {Maximum (25.6\,GB/s)};
+        
+        \legend{
+            DDR4,
+            DDR5,
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{16 Gb Dual Rank, Random}
+        \label{fig:lat_bw:random_16Gb_DR}
+    \end{subfigure}
+    %%%%
+    \caption{Average Response Latency over Bandwidth for DDR4-3200 vs. DDR5-3200}
+    \label{fig:lat_bw}
+\end{figure*}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\begin{figure*}%[h!]
+    \centering
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Bandwidth [GB/s]}},
+        	xlabel={\textbf{Pin Data Rate [MT/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 2*1200,
+            ymin = 15,
+            %xmax = 200,
+            %ymax = 300,
+            legend style={legend pos=north west, font=\small}
+        ]
+        
+        % Max
+        \addplot[Black, thick, line cap=round, smooth] coordinates {
+            (2*1600,204.8/8)
+            (2*1800,230.4/8)
+            (2*2000,256  /8)
+            (2*2200,281.6/8)    
+            (2*2400,307.2/8)    
+            (2*2600,332.8/8)    
+            (2*2800,358.4/8)    
+            (2*3000,384  /8)  
+            (2*3200,409.6/8)    
+        };
+        
+        % No Refresh
+        \addplot[Red, thick, line cap=round, smooth] coordinates {
+            (2*1600,197.08/8)
+            (2*1800,220.14/8)
+            (2*2000,244.2 /8)
+            (2*2200,266.68/8)
+            (2*2400,290.26/8)
+            (2*2600,312.42/8)
+            (2*2800,336.1 /8)
+            (2*3000,359   /8)
+            (2*3200,380.02/8)
+
+        };
+        
+        % all bank
+        \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+            (2*1600,180.3 /8)
+            (2*1800,200.5 /8)
+            (2*2000,222.76/8)
+            (2*2200,242.74/8)
+            (2*2400,264.28/8)
+            (2*2600,285.1 /8)
+            (2*2800,306.88/8)
+            (2*3000,327.4 /8)
+            (2*3200,346.16/8)
+        };
+        
+        % same-bank
+        \addplot[Green, thick, line cap=round, smooth] coordinates {
+            (2*1600,196.84/8)
+            (2*1800,217.64/8)
+            (2*2000,240.28/8)
+            (2*2200,262   /8)
+            (2*2400,284.58/8)
+            (2*2600,306.6 /8)
+            (2*2800,329.96/8)
+            (2*3000,351.84/8)
+            (2*3200,370.76/8)
+        };
+        %
+        \legend{
+            Maximum,
+            No Refresh,
+            All-Bank,
+            Same-Bank
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{16\,Gb Single Rank, Linear}
+        \label{fig:refresh:linear_16Gb_SR}
+    \end{subfigure}
+    \hfill
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Bandwidth [GB/s]}},
+        	xlabel={\textbf{Pin Data Rate [MT/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 2*1200,
+            ymin = 15,
+            %xmax = 200,
+            %ymax = 300,
+            legend style={legend pos=north west, font=\small}
+        ]
+        
+        % Max
+        \addplot[Black, thick, line cap=round, smooth] coordinates {
+            (2*1600,204.8/8)
+            (2*1800,230.4/8)
+            (2*2000,256  /8)
+            (2*2200,281.6/8)    
+            (2*2400,307.2/8)    
+            (2*2600,332.8/8)    
+            (2*2800,358.4/8)    
+            (2*3000,384  /8)  
+            (2*3200,409.6/8)    
+        };
+        
+        % No Refresh
+        \addplot[Red, thick, line cap=round, smooth] coordinates {
+            (2*1600,200.92/8)
+            (2*1800,225.9 /8)
+            (2*2000,251.16/8)
+            (2*2200,275.66/8)
+            (2*2400,299.84/8)
+            (2*2600,326.64/8)
+            (2*2800,352.34/8)
+            (2*3000,377.74/8)
+            (2*3200,401.78/8)
+        };
+        
+        % all bank
+        \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+            (2*1600,186.46/8)
+            (2*1800,214.44/8)
+            (2*2000,239.36/8)
+            (2*2200,245.44/8)
+            (2*2400,272.26/8)
+            (2*2600,301.7 /8)
+            (2*2800,315   /8)
+            (2*3000,335.24/8)
+            (2*3200,364.18/8)
+        };
+        
+        % same-bank
+        \addplot[Green, thick, line cap=round, smooth] coordinates {
+            (2*1600,200.48/8)
+            (2*1800,225.46/8)
+            (2*2000,250.64/8)
+            (2*2200,275.42/8)
+            (2*2400,300.44/8)
+            (2*2600,325.92/8)
+            (2*2800,351.54/8)
+            (2*3000,376.6 /8)
+            (2*3200,400.62/8)
+        };
+        %
+        \legend{
+            Maximum,
+            No Refresh,
+            All-Bank,
+            Same-Bank
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{16\,Gb Dual Rank, Linear}
+        \label{fig:refresh:linear_16Gb_DR}
+    \end{subfigure}
+    %%%%
+    \vskip\baselineskip
+    %%%%
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Bandwidth [GB/s]}},
+        	xlabel={\textbf{Pin Data Rate [MT/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 2*1200,
+            ymin = 15,
+            %xmax = 200,
+            %ymax = 300,
+            legend style={legend pos=north west, font=\small}
+        ]
+        
+        % Max
+        \addplot[Black, thick, line cap=round, smooth] coordinates {
+            (2*1600,204.8/8)
+            (2*1800,230.4/8)
+            (2*2000,256  /8)
+            (2*2200,281.6/8)    
+            (2*2400,307.2/8)    
+            (2*2600,332.8/8)    
+            (2*2800,358.4/8)    
+            (2*3000,384  /8)  
+            (2*3200,409.6/8)    
+        };
+        
+        % No Refresh
+        \addplot[Red, thick, line cap=round, smooth] coordinates {
+            (2*1600,183.06/8)
+            (2*1800,197.48/8)
+            (2*2000,216.9 /8)
+            (2*2200,230.64/8)
+            (2*2400,248.1 /8)
+            (2*2600,258.6 /8)
+            (2*2800,270.36/8)
+            (2*3000,282.52/8)
+            (2*3200,286.2 /8)
+        };
+        
+        % all bank
+        \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+            (2*1600,165.18/8)
+            (2*1800,178.04/8)
+            (2*2000,196.66/8)
+            (2*2200,208.58/8)
+            (2*2400,224.62/8)
+            (2*2600,234.14/8)
+            (2*2800,244.94/8)
+            (2*3000,256.16/8)
+            (2*3200,260.22/8)
+        };
+        
+        % same-bank
+        \addplot[Green, thick, line cap=round, smooth] coordinates {
+            (2*1600,173.7 /8)
+            (2*1800,185.14/8)
+            (2*2000,202.66/8)
+            (2*2200,211.08/8)
+            (2*2400,225.28/8)
+            (2*2600,231.24/8)
+            (2*2800,240.22/8)
+            (2*3000,250.4 /8)
+            (2*3200,253.24/8)
+        };
+        %
+        \legend{
+            Maximum,
+            No Refresh,
+            All-Bank,
+            Same-Bank
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{16\,Gb Single Rank, Random}
+        \label{fig:refresh:random_16Gb_SR}
+    \end{subfigure}
+    \hfill
+    \begin{subfigure}[b]{0.49\textwidth}
+        \centering
+        \begin{tikzpicture}
+        \begin{axis}[
+        	ylabel={\textbf{Bandwidth [GB/s]}},
+        	xlabel={\textbf{Pin Data Rate [MT/s]}},
+            grid=minor,
+            width = \textwidth,
+            height = 5.25cm,
+            xmin = 2*1200,
+            ymin = 15,
+            legend style={legend pos=north west, font=\small}
+        ]
+        
+        % Max
+        \addplot[Black, thick, line cap=round, smooth] coordinates {
+            (2*1600,204.8/8)
+            (2*1800,230.4/8)
+            (2*2000,256  /8)
+            (2*2200,281.6/8)    
+            (2*2400,307.2/8)    
+            (2*2600,332.8/8)    
+            (2*2800,358.4/8)    
+            (2*3000,384  /8)  
+            (2*3200,409.6/8)    
+        };
+        
+        % No Refresh
+        \addplot[Red, thick, line cap=round, smooth] coordinates {
+            (2*1600,194.2 /8)
+            (2*1800,216.34/8)
+            (2*2000,240.78/8)
+            (2*2200,262.66/8)
+            (2*2400,286.56/8)
+            (2*2600,308.88/8)
+            (2*2800,332.98/8)
+            (2*3000,355.5 /8)
+            (2*3200,376.22/8)
+        };
+        
+        % all bank
+        \addplot[MidnightBlue, thick, line cap=round, smooth] coordinates {
+            (2*1600,180.60/8)
+            (2*1800,199.10/8)
+            (2*2000,219.08/8)
+            (2*2200,235.34/8)
+            (2*2400,256.92/8)
+            (2*2600,271.60/8)
+            (2*2800,291.44/8)
+            (2*3000,310.00/8)
+            (2*3200,325.90/8)
+        };
+        
+        % same-bank
+        \addplot[Green, thick, line cap=round, smooth] coordinates {
+            (2*1600,192.78/8)
+            (2*1800,214.74/8)
+            (2*2000,238.96/8)
+            (2*2200,260.06/8)
+            (2*2400,283.28/8)
+            (2*2600,303.78/8)
+            (2*2800,325.60/8)
+            (2*3000,345.60/8)
+            (2*3200,360.54/8)
+        };
+        %
+        \legend{
+            Maximum,
+            No Refresh,
+            All-Bank,
+            Same-Bank
+        }
+        \end{axis}
+        \end{tikzpicture}
+        \caption{16\,Gb Dual Rank, Random}
+        \label{fig:refresh:random_16Gb_DR}
+    \end{subfigure}
+    %
+    \caption{DDR5 All-Bank Refresh vs. Same-Bank Refresh}
+    \label{fig:refresh}
+\end{figure*}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%\begin{figure*}
+%    \centering
+%    \begin{subfigure}[b]{0.33\textwidth}
+%        \centering
+%        \begin{tikzpicture}
+%        \begin{axis}[
+%        	ylabel={\textbf{Occurrence}},
+%        	xlabel={\textbf{Latency [ns]}},
+%            grid=minor,
+%            width = \columnwidth,
+%            %height = 0.9\columnwidth,
+%            xmin = 0,
+%            ymin = 0,
+%            xmax = 1500,
+%            ymax = 350,
+%            legend style={at={(0.05,0.85)}, anchor=west}
+%        ]
+%        
+%        \addplot [BrickRed, fill=BrickRed, ybar interval, mark=no] table [x=latency, y=count, col sep=comma] {latencies_no_refresh_DDR5_4000_16Gb_SR_counts.csv};
+%        
+%        \end{axis}
+%        \end{tikzpicture}
+%        \caption{No Refresh}
+%        \label{fig:lat:a}
+%    \end{subfigure}
+%    \hfill
+%    \begin{subfigure}[b]{0.33\textwidth}
+%        \centering
+%        \begin{tikzpicture}
+%        \draw[Black] (2.2,2) node[]{All-Bank Refresh};
+%        \draw[Black] (2.2,1.8) -- (1.6,0.4);
+%        \begin{axis}[
+%        	ylabel={\textbf{Occurrence}},
+%        	xlabel={\textbf{Latency [ns]}},
+%            grid=minor,
+%            width = \columnwidth,
+%            %height = 0.9\columnwidth,
+%            xmin = 0,
+%            ymin = 0,
+%            xmax = 1500,
+%            ymax = 350,
+%            legend style={at={(0.05,0.85)}, anchor=west}
+%        ]
+%        
+%        \addplot [BrickRed, fill=BrickRed, ybar interval, mark=no] table [x=latency, y=count, col sep=comma] {latencies_all_bank_DDR5_4000_16Gb_SR_counts.csv};
+%        
+%        \end{axis}
+%        \end{tikzpicture}
+%        \caption{All-Bank Refresh}
+%        \label{fig:lat:b}
+%    \end{subfigure}
+%    \hfill
+%    \begin{subfigure}[b]{0.33\textwidth}
+%        \centering
+%        \begin{tikzpicture}
+%        \begin{axis}[
+%        	ylabel={\textbf{Occurrence}},
+%        	xlabel={\textbf{Latency [ns]}},
+%            grid=minor,
+%            width = \columnwidth,
+%            xmin = 0,
+%            ymin = 0,
+%            xmax = 1500,
+%            ymax = 350,
+%            legend style={at={(0.05,0.85)}, anchor=west}
+%        ]
+%        
+%        \addplot [BrickRed, fill=BrickRed, ybar interval, mark=no] table [x=latency, y=count, col sep=comma] {latencies_same_bank_DDR5_4000_16Gb_SR_counts.csv};
+%        
+%        
+%        \end{axis}
+%        \end{tikzpicture}
+%        \caption{Same-Bank Refresh}
+%        \label{fig:lat:b}
+%    \end{subfigure}
+%    
+%    \caption{Latency Histrograms w.r.t. Refresh for 16Gb DDR5-4000, Random and High Sustainable Bandwidth}
+%    \label{fig:lat}
+%\end{figure*}
+%
+%\begin{figure*}
+%    \centering
+%    \begin{subfigure}[b]{1.00\textwidth}
+%        \centering
+%        \begin{tikzpicture}
+%        \begin{axis}[
+%        	ylabel={\textbf{Occurrence}},
+%        	xlabel={\textbf{Latency [ns]}},
+%            grid=minor,
+%            width = \columnwidth,
+%            %height = 0.9\columnwidth,
+%            xmin = 0,
+%            ymin = 0,
+%            %xmax = 1500,
+%            %ymax = 350,
+%            legend style={at={(0.05,0.85)}, anchor=west}
+%        ]
+%        
+%        \addplot [Blue, fill=Blue, ybar interval, mark=no] table [x=latency, y=count, col sep=comma] {latencies_no_refresh_DDR5_4000_16Gb_SR_counts.csv};
+%        \addplot [Red, fill=Red, ybar interval, mark=no] table [x=latency, y=count, col sep=comma] {latencies_all_bank_DDR5_4000_16Gb_SR_counts.csv};
+%        \addplot [Green, fill=Green, ybar interval, mark=no] table [x=latency, y=count, col sep=comma] {latencies_same_bank_DDR5_4000_16Gb_SR_counts.csv};
+%        
+%        \end{axis}
+%        \end{tikzpicture}
+%        \caption{No Refresh}
+%        \label{fig:lat:a}
+%    \end{subfigure}
+%    \hfill
+%    \caption{Latency Histrograms w.r.t. Refresh for 16Gb DDR5-4000, Random and High Sustainable Bandwidth}
+%    \label{fig:lat}
+%\end{figure*}
+
+\subsection{Key Observations}
+In this section we summarize the key observations for the performance of different DDR5 configurations and for the comparison to DDR4:
+\begin{itemize}
+\setlength{\itemsep}{0pt}
+    \item \textit{Applications with random memory access patterns:} Each DDR5 channel should be composed of at least 32 banks to achieve a high sustainable bandwidth. 
+    \item \textit{Applications with linear memory access patterns:} DDR5 does not outperform DDR4 by much with respect to sustainable bandwidth and average response latency up to the highest DDR4 data rates. 
+    \item \textit{Applications with random memory access patterns:} DDR5 should be preferred over DDR4 at all data rates with respect to sustainable bandwidth and average response latency. 
+    \item \textit{Independent of the memory access patterns:} DDR5's same-bank refresh should always be preferred over all-bank refresh with respect to sustainable bandwidth.
+\end{itemize}
+\vspace{-15pt}
+% 1. For random benchmark each DDR5 channel needs at least 32 banks.
+%
+% stream: only small relative performance drop for higher speed grades -> small gains with DDR5, DDR4 also already available with data rates up to 4600 MT/s
+% random: large relative performance drop with increasing frequencies, DDR4 3200 only achieves ...% of the maximum bandwidth while DDR5-3200 achieves ...%
+% random performance drop for high frequencies and single rank:
+% for DDR4 data transfer takes 4tCK regardless of frequency, but all timing dependencies increase in clock cycles, with DDR5 data transfer takes 8tCK -> more time to do precharges, activates and RD/WR latencies
+% 32 banks especially beneficial with single rank random, only small differences with dual rank
+% lower response latencies for same bandwidth
+%
+%same-bank refresh beneficial for stream (refresh penalty can be hidden almost completely), for random it varies???
+%
+%
+% DDR4: What if 4 * tCCD_S < tCCD_L -> no seamless bank group hopping possible, at which frequency does this happen?
+% DDR5 has at least 8 bank groups
+%
+% same bank refresh can be hidden, performance gain especially when only 1 rank is available
+%
+% To avoid large tail latencies, clever techniques in the MC are required to balance latency vs. BW requirements!
+%
+%\begin{figure*}[p]
+%  \begin{tikzpicture}
+%  \begin{axis}[
+%        width  = 1\textwidth,
+%        height = 8cm,
+%        ymode=log,
+%        axis y line*=left,
+%        axis x line=bottom,
+%        major x tick style = transparent,
+%        ybar=5*\pgflinewidth,
+%        bar width=14pt,
+%        ymajorgrids = true,
+%        ylabel = {\textbf{Bandwidth [GiB/s]}},
+%        symbolic x coords={
+%            DDR3,
+%            DDR4,
+%            DDR5 SC,
+%            DDR5 DC,
+%            DDR5 16H SC,
+%            DDR5 16H DC},
+%        xtick = data,
+%        scaled y ticks = false,
+%        enlarge x limits=0.1,
+%        axis line style={-},
+%        legend columns=2,
+%        legend cell align=left,
+%        legend style={
+%        at={(0.5,-0.2)},
+%        anchor=north,
+%        column sep=1ex
+%        }
+%    ]
+%    % 16,7 GiB/s	37,5 GiB/s	32,8 GiB/s	32,8 GiB/s
+%        \addplot[style={black,fill=MidnightBlue,mark=none}]
+%           coordinates {
+%           (DDR3, 16.7)
+%           (DDR4, 37.5)
+%           (DDR5 SC, 32.8)
+%           (DDR5 DC, 65.6)
+%           (DDR5 16H SC, 32.8)
+%           (DDR5 16H DC, 65.6)
+%           };
+%           %136,4 GiB/s	409,6 GiB/s	716,8 GiB/s	11468,8 GiB/s
+%        \addplot[style={black,fill=BrickRed,mark=none}]
+%           coordinates {
+%           (DDR3, 136.7)
+%           (DDR4, 409.6)
+%           (DDR5 SC, 716.8)
+%           (DDR5 DC, 1433.6)
+%           (DDR5 16H SC, 11468.8)
+%           (DDR5 16H DC, 22937.6)
+%           };
+%        \legend{Max. Ext. Bandwidth, Max Int. Bandwidth}
+%    \end{axis}
+%    \begin{axis}[
+%        width  = 1\textwidth,
+%        height = 8cm,
+%        axis y line*=right,
+%        %axis x line=none,
+%        axis on top,
+%        major x tick style = transparent,
+%        enlarge x limits=0.1,
+%        axis line style={-},
+%        ylabel = {\textbf{Ratio Between Int. and Ext.}},
+%        xmin=0, xmax=5,
+%        scaled y ticks = false,
+%        xticklabel=\empty
+%    ]
+%    \addplot[YellowOrange,sharp plot,ultra thick, update limits=true]
+%        coordinates {
+%            (0,8.2)
+%            (1,10.9)
+%            (2,21.8)
+%            (3,43.7)
+%            (4,349.5)
+%            (5,699)
+%        };
+%    \end{axis}
+%  \end{tikzpicture}
+%  \caption{Bandwidth Evolvement of DDR DRAM Standards}
+%\end{figure*}
+%\begin{table}[h!]
+%  \begin{tabularx}{\hsize}{|X|X|X|X|X|}\hline
+%    & A& B& C& D \\\hline
+%    X& & & &  \\\hline
+%    y& & & &  \\\hline
+%  \end{tabularx}
+%  \caption{Tabellenunterschrift zweizeilig (10/12 pt) Tabellenunterschrift zweizeilig (10/12 pt)}\label{tab2}
+%\end{table}
+%
+\section{Related Work}
+With respect to functional and cycle-accurate DRAM simulation there exist several open-source solutions. \hbox{DrSim~\cite{jeodrsim}} was already developed several years ago but never updated over time, leading to an exclusive support of older JEDEC standards and making it unsuitable for most current system developments. DRAMSys~\cite{stejun_20}, DRAMsim3~\cite{liyan_20}, Ramulator~\cite{kimyan_15} and the gem5 DRAM model~\cite{hanaga_14} are all updated from time to time, however, only DRAMSys currently supports the DDR5 standard. Due to the Petri-Net-based source code generation~\cite{junkra_19} and the special TLM concept, DRAMSys can generate results a lot faster than the other cycle-accurate simulators. Furthermore, there are other approaches that only approximate the DRAM behavior. In~\cite{yuaaam_09} the authors propose an analytical DRAM performance model that uses traces to predict the efficiency of the DRAM subsystem. Todorov et\,al.~\cite{todmue_12} presented a statistical approach for the construction of a cycle-approximate TLM model of a DRAM controller based on a decision tree. However, these approaches suffer from a significant loss in accuracy. More promising approaches based on machine learning techniques have been presented recently. The paper~\cite{lijac_19} presents the modeling of DRAM behavior using decision trees. In \cite{junfel_20} the authors present a performance-optimized DRAM model that is based on a neural network. However, to the best of our knowledge, there exists no analytical nor approximated DDR5 simulation model so far. 
+
+In terms of the simulation-based analysis and comparison of different DRAMs there is a comprehensive study by Ghose et\,al.~\cite{gholi_19}. It features a large variety of standards and workloads and also makes some key observations. However, it was already published in 2019 and thus does not include the new DDR5 standard.
+%
+\section{Conclusion}
+%
+With the release of DDR5 the total DRAM design space is greatly enlarged, making the selection of a suitable DRAM device even more complex. In this paper, we deeply investigated the performance of the new DDR5 standard for different configurations and compared it to its predecessor DDR4. In order to generate those results, we developed a DDR5 simulation model, which is based on the open-source DRAM simulator DRAMSys. We presented several insights and key observations for two characteristic benchmarks, which will guide system designers to make the right decisions. For the future we plan to run full-system simulations with our new DDR5 model to investigate the impact on the whole system performance more accurately.
+%
+%\vspace{-7pt}
+\section*{Acknowledgements}
+%\vspace{-7pt}
+%
+This work was supported within the Fraunhofer and DFG cooperation programme (Grant no. 248750294) and supported by the Fraunhofer High Performance Center for Simulation- and Software-based Innovation. Furthermore, we thank Rambus for their support.
+%
+%\renewcommand{\baselinestretch}{1.0}\normalsize
+%
+\bibliographystyle{IEEEtran}
+\bibliography{IEEEabrv,references_JR}
+\end{document}
\ No newline at end of file
diff --git a/methology.pdf b/methology.pdf
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+       y="576.00024"
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\ No newline at end of file
diff --git a/references_JR.bib b/references_JR.bib
new file mode 100644
index 0000000..a7d3511
--- /dev/null
+++ b/references_JR.bib
@@ -0,0 +1,56012 @@
+% This file was created with JabRef 2.10.
+% Encoding: UTF8
+
+
+@InProceedings{bercle_11,
+  Title                    = {{A} low-power {VLIW} processor for 3{GPP}-{LTE} complex numbers processing},
+  Author                   = {Bernard, C. and Clermidy, F.},
+  Booktitle                = {Proc. Design, Automation \& Test in Europe Conf. \& Exhibition (DATE)},
+  Year                     = {2011},
+  Pages                    = {1--6},
+
+  Cb_grade                 = {ASIP -- Brest
+see also redcle_10},
+  Crossref                 = {redcle_10},
+  File                     = {bercle_11.pdf:bercle_11.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{boupol_04,
+  Title                    = {{E}nergy-scalability enhancement of wireless local area network transceivers},
+  Author                   = {Bougard, B. and Pollin, S. and Lenoir, G. and Eberle, W. and Vand der Perre, L. and Catthoor, F. and Dehaene, W.},
+  Booktitle                = {Proc. IEEE 5th Workshop Signal Processing Advances in Wireless Communications},
+  Year                     = {2004},
+  Pages                    = {449--453},
+
+  Cb_grade                 = {- ungelesen
+- Allgemein
+- Power distribution on components in wireless system
+- referenced in abdsha_08},
+  Crossref                 = {abdsha_08},
+  Doi                      = {10.1109/SPAWC.2004.1439283},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.26}
+}
+
+@InProceedings{liuzha_06,
+  Title                    = {{L}ow {P}ower {T}rellis {D}ecoder with {O}verscaled {S}upply {V}oltage},
+  Author                   = {Liu, Y. and Zhang, T. and Hu, J.},
+  Booktitle                = {Proc. IEEE Workshop Signal Processing Systems Design and Implementation SIPS '06},
+  Year                     = {2006},
+  Pages                    = {205--208},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Viterbi, Turbo
+- Clock skew aware scheduling},
+  Crossref                 = {abdsha_08},
+  Doi                      = {10.1109/SIPS.2006.352582},
+  File                     = {liuzha_06.pdf:liuzha_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{loiwed_10,
+  Title                    = {{C}omplete {V}erification of {W}eakly {P}rogrammable {IP}s against {T}heir {O}perational {ISA} {M}odel},
+  Author                   = {Sacha Loitz and Markus Wedler and Dominik Stoffel and Christian Brehm and Norbert Wehn and Wolfgang Kunz},
+  Booktitle                = {FDL},
+  Year                     = {2010},
+  Pages                    = {29-36},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Crossref                 = {DBLP:conf/fdl/2010},
+  File                     = {loiwed_10.pdf:loiwed_10.pdf:PDF},
+  Owner                    = {Brehm}
+}
+
+@Article{muealv_99,
+  Title                    = {{RAS strategy for IBM S/390 G5 and G6}},
+  Author                   = {Mueller, M. and Alves, LC and Fischer, W. and Fair, ML and Modi, I.},
+  Journal                  = {IBM Journal of Research and Development},
+  Year                     = {1999},
+
+  Month                    = sep,
+  Number                   = {5.6},
+  Pages                    = {875--888},
+  Volume                   = {43},
+
+  Cb_grade                 = {Ref in mayweh_10},
+  Crossref                 = {mayweh_10},
+  File                     = {muealv_99.pdf:muealv_99.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {matthias},
+  Timestamp                = {2010.09.21}
+}
+
+@Article{hamqad_11,
+  Title                    = {{U}nderstanding sources of ineffciency in general-purpose chips},
+  Author                   = {Hameed et al.},
+  Journal                  = {Communications of the ACM},
+  Year                     = {2011},
+  Number                   = {10},
+  Pages                    = {85--93},
+  Volume                   = {54},
+
+  Owner                    = {Brugger},
+  Publisher                = {ACM},
+  Timestamp                = {2014.06.15}
+}
+
+@Electronic{2012,
+  Title                    = {{TOP}500 {S}upercomputer {S}ites},
+  Author                   = {TOP500 project},
+  HowPublished             = {\url{http://www.top500.org/lists/2012/06}},
+  Language                 = {en},
+  Month                    = jun,
+  Year                     = {2012},
+
+  Owner                    = {CdS},
+  Timestamp                = {2012.06.20}
+}
+
+@Misc{boxsmartbench15,
+  Title                    = {{SmartBench: A multi-core friendly benchmark application}},
+
+  Author                   = {\mbox{123 SmartMobile}},
+  HowPublished             = {\url{play.google.com/store/apps/details?id=com.smartbench.eleven}},
+  Year                     = {2011, Last Access: 18.02.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.18}
+}
+
+@Standard{boxvis_07,
+  Title                    = {{FAILURE} {MECHANISM} {BASED} {STRESS} {TEST} {QUALIFICATION} {FOR} {INTEGRATED} {CIRCUITS}},
+  Institution              = {Component Technical Committee},
+  Organization             = {Automotive Electronics Council},
+  Author                   = {\mbox{Automotive Electronics Council}},
+  Month                    = {May},
+  Year                     = {2007},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-26}
+}
+
+@Misc{boxcadence14,
+  Title                    = {{C}adence {D}enali {DDR} {M}emory {IP}},
+
+  Author                   = {\mbox{Cadence Inc.}},
+  HowPublished             = {\url{http://ip.cadence.com/ipportfolio/ip-portfolio-overview/memory-ip/ddr-lpddr}},
+  Month                    = {October},
+  Year                     = {2014, last access 18.02.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-06-09}
+}
+
+@Misc{boxvirtual15,
+  Title                    = {{V}irtual {S}ystem {P}latform},
+
+  Author                   = {\mbox{Cadence, Inc}},
+  HowPublished             = {\url{http://www.cadence.com/products/sd/virtual_system/pages/default.aspx}},
+  Year                     = {2015, last access: 20.01.2015},
+
+  Editor                   = {Synopsys, Inc},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20}
+}
+
+@Misc{boxaceexplorer14,
+  Title                    = {{A}ce{T}hermal{M}odeler and {A}ceplorer},
+
+  Author                   = {\mbox{DOCEA Power}},
+  HowPublished             = {\url{http://www.doceapower.com}},
+  Year                     = {2014, last access: 20.01.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20}
+}
+
+@Misc{boxandebench15,
+  Title                    = {{A}nd{EB}ench: {A}n {EEMBC} {B}enchmark for {A}ndroid {D}evices},
+
+  Author                   = {\mbox{EEMBC Inc.}},
+  HowPublished             = {\url{http://www.eembc.org/andebench/about.php}},
+  Year                     = {2013, last access 18.02.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.18},
+  Url                      = {\url{http://www.eembc.org/andebench/about.php}}
+}
+
+@Misc{box0xbench13,
+  Title                    = {{0xBench: Comprehensive Benchmark Suite for Android}},
+
+  Author                   = {\mbox{Google Inc.}},
+  Year                     = {2013},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.18},
+  Url                      = {\url{http://code.google.com/p/0xbench/}}
+}
+
+@Standard{boxhmc_13,
+  Title                    = {{H}ybrid {M}emory {C}ube {S}pecification},
+  Author                   = {\mbox{Hybrid Memory Cube Consortium}},
+  Revision                 = {1.0},
+  Url                      = {http://www.hybridmemorycube.org/},
+  Year                     = {2013},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-06-16}
+}
+
+@Article{box_12a,
+  Title                    = {{IEEE} {S}tandard for {S}tandard {S}ystem{C} {L}anguage {R}eference {M}anual},
+  Author                   = {\mbox{IEEE Computer Society}},
+  Year                     = {2012},
+  Number                   = {IEEE Std 1666-2011},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-09}
+}
+
+@Article{box_15,
+  Title                    = {{H}igh {B}andwidth {M}emory ({HBM}) {DRAM}},
+  Author                   = {\mbox{JEDEC Solid State Technology Association}},
+  Journal                  = {JEDEC Standard JESD235A},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-08-19}
+}
+
+@Misc{box_14,
+  Title                    = {{LPDDR}4 ({JESD} 209-4)},
+
+  Author                   = {\mbox{Jedec Solid State Technology Association}},
+  Year                     = {2014},
+
+  Booktitle                = {{JEDEC STANDARD}},
+  Owner                    = {MJ},
+  Series                   = {{Jedec Standard}},
+  Timestamp                = {2016-08-19}
+}
+
+@Article{box_12,
+  Title                    = {{L}ow {P}ower {D}ouble {D}ata {R}ate 3 ({LPDDR}3)},
+  Author                   = {\mbox{JEDEC Solid State Technology Association}},
+  Journal                  = {JEDEC Standard JESD209-3},
+  Year                     = {2012},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-08-19}
+}
+
+@Misc{boxddr312,
+  Title                    = {{DDR}3 {SDRAM} ({JESD}79-3)},
+
+  Author                   = {\mbox{JEDEC Solid State Technology Association}},
+  Year                     = {2012},
+
+  Booktitle                = {{JEDEC STANDARD}},
+  Owner                    = {MJ},
+  Series                   = {{Jedec Standard}},
+  Timestamp                = {2015.01.20}
+}
+
+@Misc{boxddr412,
+  Title                    = {{DDR}4 {SDRAM} ({JESD}79-4)},
+
+  Author                   = {\mbox{JEDEC Solid State Technology Association}},
+  Year                     = {2012},
+
+  Booktitle                = {{JEDEC STANDARD}},
+  Owner                    = {MJ},
+  Series                   = {{Jedec Standard}},
+  Timestamp                = {2015.01.20}
+}
+
+@Misc{boxddr520,
+  Title                    = {{DDR}5 {SDRAM} ({JESD}79-5)},
+
+  Author                   = {\mbox{JEDEC Solid State Technology Association}},
+  Year                     = {2020},
+
+  Booktitle                = {{JEDEC STANDARD}},
+  Owner                    = {MJ},
+  Series                   = {{Jedec Standard}},
+  Timestamp                = {2015.01.20}
+}
+
+@Misc{boxwide11,
+  Title                    = {{W}ide {I}/{O} {S}ingle {D}ata {R}ate ({JESD} 229)},
+
+  Author                   = {\mbox{Jedec Solid State Technology Association}},
+  Month                    = {Dec.},
+  Year                     = {2011},
+
+  Booktitle                = {{JEDEC STANDARD}},
+  Owner                    = {MJ},
+  Series                   = {{Jedec Standard}},
+  Timestamp                = {2015.01.20}
+}
+
+@Misc{boxmediabench,
+  Title                    = {{M}ediabench},
+
+  Author                   = {\mbox{MediaBench Consortium}},
+  HowPublished             = {\url{http://euler.slu.edu/~fritts/mediabench/}},
+  Year                     = {2015, last access 28.02.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.12}
+}
+
+@Article{mictec_13,
+  Title                    = {4{G}b: x16, x32 {M}obile {LPDDR}3 {SDRAM}},
+  Author                   = {\mbox{Micron Technology Inc.}},
+  Year                     = {2013},
+
+  Month                    = {July},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.06}
+}
+
+@Article{box_06,
+  Title                    = {1{G}b: x4, x8, x16 {DDR}3 {SDRAM}},
+  Author                   = {\mbox{Micron Technology Inc.}},
+  Year                     = {2006},
+
+  Month                    = {July},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-08}
+}
+
+@Electronic{box_16,
+  Title                    = {{DDR}4 {SDRAM} - {MT}40{A}2{G}4},
+  Author                   = {\mbox{Micron Technology, Inc.}},
+  Url                      = {https://www.micron.com/products/dram/ddr4-sdram/8Gb#/},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17}
+}
+
+@Electronic{box_16a,
+  Title                    = {{A}utomotive {DDR}4 {SDRAM} ({MT}40{A}1{G}8)},
+  Author                   = {\mbox{Micron Technology, Inc.}},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-26}
+}
+
+@Electronic{box_15a,
+  Title                    = {8{GB} (x64, {SR}) 288-{P}in {DDR}4 {UDIMM} - {MTA}8{ATF}1{G}64{AZ} – 8{GB}},
+  Author                   = {\mbox{Micron Technology, Inc.}},
+  Url                      = {https://www.micron.com/parts/modules/ddr4-sdram/mta8atf1g64az-2g3},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17}
+}
+
+@Misc{boxmemmax,
+  Title                    = {{M}em{M}ax-{S}cheduler},
+
+  Author                   = {\mbox{Sonics}},
+  HowPublished             = {\url{http://sonicsinc.com/products/memory-subsystems/memmax-scheduler/}},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.17}
+}
+
+@Misc{boxdesignware,
+  Title                    = {{DesignWare TLM Library}},
+
+  Author                   = {\mbox{Synopsys Inc.}},
+  HowPublished             = {\url{http://www.synopsys.com/Systems/VirtualPrototyping/VPModels/Pages/DW-TLM-Library.aspx}},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.17}
+}
+
+@Misc{boxdesignware15,
+  Title                    = {{D}esign{W}are {DDR} {IP}},
+
+  Author                   = {\mbox{Synopsys, Inc.}},
+  HowPublished             = {http://www.synopsys.com/IP/InterfaceIP/DDRn/Pages/},
+  Year                     = {2015, Last Access: 18.02.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-04-19}
+}
+
+@Misc{synsynopsys12,
+  Title                    = {{S}ynopsys {V}irtual {P}rototyping {S}olution},
+
+  Author                   = {\mbox{Synopsys, Inc}},
+  HowPublished             = {\url{http://www.synopsys.com/Systems/VirtualPrototyping/Pages/default.aspx}},
+  Year                     = {2015, last access: 20.01.2015},
+
+  Editor                   = {Synopsys, Inc},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20}
+}
+
+@Misc{boxmemory15,
+  Title                    = {{M}emory {I}nterface {G}enerator ({MIG})},
+
+  Author                   = {\mbox{Xilinx, Inc.}},
+  HowPublished             = {\url{http://www.xilinx.com/products/intellectual-property/mig.html}},
+  Year                     = {2015, Last Access: 18.02.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.18}
+}
+
+@Article{boxxilinx_15,
+  Title                    = {z{C}706 {E}valuation {B}oard for the {Z}ynq-7000 {XC}7{Z}045 {A}ll {P}rogrammable {S}oc {U}ser {G}uide},
+  Author                   = {\mbox{Xilinx}},
+  Year                     = {2015},
+
+  Month                    = {April},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.15}
+}
+
+@Manual{boxzynq15,
+  Title                    = {{Z}ynq-7000 {A}ll {P}rogrammable {S}o{C} {T}echnical {R}eference {M}anual {(UG585)}},
+  Author                   = {\mbox{Xilinx}},
+  Edition                  = {v1.10},
+  Month                    = {feb},
+  Year                     = {2015},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.10.06}
+}
+
+@Manual{xilzc70215,
+  Title                    = {{ZC}702 {E}valuation {B}oard for the {Z}ynq-7000 {XC}7{Z}020 {A}ll {P}rogrammable {S}o{C}: {U}ser {G}uide {(UG850)}},
+  Author                   = {\mbox{Xilinx}},
+  Edition                  = {v1.5},
+  Month                    = {sep},
+  Year                     = {2015},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.10.06}
+}
+
+@Manual{ieworldwide,
+  Title                    = {{L}ocal and metropolitan area networks; {P}art 16: {A}ir {I}nterface for {F}ixed and {M}obile {B}roadband {W}ireless {A}ccess {S}ystems; {A}mendment 2:{P}hysical and {M}edium {A}ccess {C}ontrol {L}ayers for {C}ombined {F}ixed and {M}obile {O}peration in {L}icensed {B}ands},
+  Author                   = {IEEE 802.16},
+
+  Key                      = {WIMAX},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{aarbru_87,
+  Title                    = {{C}ircuits and {T}rees in {O}riented {L}inear {G}raphs},
+  Author                   = {Aardenne-Ehrenfest, T and de Bruijn, NG},
+  Journal                  = {Classic Papers in Combinatorics},
+  Year                     = {1987},
+  Pages                    = {149--163},
+
+  Owner                    = {MJ},
+  Publisher                = {Springer},
+  Timestamp                = {2019-09-12}
+}
+
+@Article{Abatzoglou1985,
+  Title                    = {{A} fast maximum likelihood algorithm for frequency estimation of a sinusoid based on {N}ewton's method},
+  Author                   = {Abatzoglou, T.J.},
+  Journal                  = {IEEE Transactions on Acoustics, Speech and Signal Processing},
+  Year                     = {1985},
+
+  Month                    = {Feb},
+  Number                   = {1},
+  Pages                    = {77-89},
+  Volume                   = {33},
+
+  Doi                      = {10.1109/TASSP.1985.1164541},
+  ISSN                     = {0096-3518},
+  Keywords                 = {Convergence;Frequency estimation;Interpolation;Maximum likelihood estimation;Newton method;Probability density function;Random variables;Signal processing algorithms;Signal to noise ratio;White noise},
+  Owner                    = {ali},
+  Timestamp                = {2015.03.03}
+}
+
+@Article{abbfan_17,
+  Title                    = {{H}igh-{T}hroughput and {E}nergy-{E}fficient {B}elief {P}ropagation {P}olar {C}ode {D}ecoder},
+  Author                   = {S. M. Abbas and Y. Fan and J. Chen and C. Y. Tsui},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2017},
+
+  Month                    = {March},
+  Number                   = {3},
+  Pages                    = {1098-1111},
+  Volume                   = {25},
+
+  Abstract                 = {Owing to their capacity-achieving performance and low encoding and decoding complexity, polar codes have received significant attention recently. Successive cancellation decoding (SCD) and belief propagation decoding (BPD) are two popular approaches for decoding polar codes. SCD, despite having less computational complexity when compared with BPD, suffers from long latency due to the serial nature of the SC algorithm. BPD, on the other hand, is parallel in nature and is more attractive for low-latency applications. However, due to the iterative nature of BPD, the required latency and energy dissipation increase linearly with the number of iterations. In this paper, we propose a novel scheme based on subfactor-graph freezing to reduce the average number of computations as well as the average number of iterations required by BPD, which directly translates into lower latency and energy dissipation. Simulation results show that the proposed scheme has no performance degradation and achieves significant reduction in computation complexity over the existing methods. Moreover, the hardware architecture for the proposed scheme is developed and compared with the state-of-the-art BPD implementations for (1024, 512) polar codes. A decoding throughput of 13.9 Gb/s is achieved along with a 60%-73% improvement in energy reduction and two times increase in hardware efficiency when compared with the existing BPD implementations.},
+  Doi                      = {10.1109/TVLSI.2016.2620998},
+  File                     = {abbfan_17.pdf:abbfan_17.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {codes;computational complexity;energy conservation;graph theory;iterative decoding;BPD;SCD;bit rate 13.9 Gbit/s;capacity-achieving performance;computational complexity;encoding;energy dissipation;energy-efficient belief propagation polar code decoder;iterative nature;low-latency applications;subfactorgraph freezing;successive cancellation decoding;Complexity theory;Computer architecture;Convergence;Decoding;Hardware;Iterative decoding;Throughput;Belief propagation decoding (BPD);energy efficiency;factor graph;iterative decoders;polar codes;successive cancellation decoding (SCD)},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-29}
+}
+
+@Article{abbfan_15a,
+  Title                    = {{L}ow complexity belief propagation polar code decoder},
+  Author                   = {S. M. Abbas and Y. Fan and J. Chen and C. Y. Tsui},
+  Year                     = {2015},
+
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Abstract                 = {Since their invention, polar codes have received a lot of attention because of their capacity-achieving performance and low encoding and decoding complexity. Successive cancellation decoding (SCD) and belief propagation decoding (BPD) are two approaches for decoding polar codes. SCD is able to achieve good error-correcting performance and is less computationally expensive as compared to BPD. However SCD suffers from long latency due to the serial nature of the successive cancellation algorithm. BPD is parallel in nature and hence is more attractive for low latency applications. However, since it is iterative, the required latency and energy dissipation increases linearly with the number of iterations. In this work, we borrow the idea of SCD and propose a novel scheme based on sub-factor-graph freezing to reduce the average number of computations as well as the average number of iterations required by BPD, which directly translates into lower latency and energy dissipation. Simulation results show that the proposed scheme has no performance degradation and achieves significant reduction in computation complexity over the existing methods.},
+  Booktitle                = {2015 IEEE Workshop on Signal Processing Systems (SiPS)},
+  Doi                      = {10.1109/SiPS.2015.7344986},
+  File                     = {abbfan_15a.pdf:abbfan_15a.pdf:PDF},
+  Keywords                 = {decoding;error correction codes;BPD;SCD;belief propagation decoding;capacity achieving performance;computation complexity;decoding complexity;decoding polar codes;energy dissipation;error correcting performance;low complexity belief propagation polar code decoder;low encoding;subfactor graph freezing;successive cancellation decoding;Belief propagation;Complexity theory;Convergence;Decoding;Encoding;Iterative decoding;Reliability;Belief propagation decoding (BPD);energy efficiency;factor graph;iterative decoders;polar codes;successive cancellation decoding (SCD)},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-30}
+}
+
+@InProceedings{abbfan_15,
+  Title                    = {{L}ow complexity belief propagation polar code decoder},
+  Author                   = {S. M. Abbas and YouZhe Fan and Ji Chen and Chi-Ying Tsui},
+  Booktitle                = {Signal Processing Systems (SiPS), 2015 IEEE Workshop on},
+  Year                     = {2015},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/SiPS.2015.7344986},
+  Keywords                 = {decoding;error correction codes;BPD;SCD;belief propagation decoding;capacity achieving performance;computation complexity;decoding complexity;decoding polar codes;energy dissipation;error correcting performance;low complexity belief propagation polar code decoder;low encoding;subfactor graph freezing;successive cancellation decoding;Belief propagation;Complexity theory;Convergence;Decoding;Encoding;Iterative decoding;Reliability;Belief propagation decoding (BPD);energy efficiency;factor graph;iterative decoders;polar codes;successive cancellation decoding (SCD)},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{abbdiv_07,
+  Title                    = {{A}ccumulate-{R}epeat-{A}ccumulate {C}odes},
+  Author                   = {Abbasfar, A. and Divsalar, D. and Yao, K.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2007},
+  Number                   = {4},
+  Pages                    = {692--702},
+  Volume                   = {55},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{abbkun_03,
+  Title                    = {{An efficient and practical architecture for high speed turbo decoders}},
+  Author                   = {A. Abbasfar and Y. Kung},
+  Booktitle                = {Proc. 2003-Fall Vehicular Technology Conference (VTC Fall 2003)},
+  Year                     = {2003},
+  Month                    = oct,
+  Pages                    = {337--341},
+  Volume                   = {1},
+
+  File                     = {abbkun_03.pdf:abbkun_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{abdsha_10,
+  Title                    = {{M}inimum-{E}nergy {O}peration {V}ia {E}rror {R}esiliency},
+  Author                   = {Abdallah, R. A. and Shanbhag, N. R.},
+  Journal                  = {Embedded Systems Letters, IEEE},
+  Year                     = {2010},
+  Number                   = {4},
+  Pages                    = {115--118},
+  Volume                   = {2},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Shanbhag
+- ANT, Low Complexity Estimator, see shaabd_10},
+  Doi                      = {10.1109/LES.2010.2098330},
+  File                     = {abdsha_10.pdf:abdsha_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.03.28}
+}
+
+@InProceedings{abdsha_10a,
+  Title                    = {{R}obust and energy-efficient {DSP} systems via output probability processing},
+  Author                   = {Abdallah, R. A. and Shanbhag, N. R.},
+  Booktitle                = {Proc. 2010 IEEE International Conference on Computer Design (ICCD)},
+  Year                     = {2010},
+  Month                    = oct,
+  Pages                    = {38--44},
+
+  Doi                      = {10.1109/ICCD.2010.5647569},
+  File                     = {abdsha_10a.pdf:abdsha_10a.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2012.02.21}
+}
+
+@Article{abdsha_09,
+  Title                    = {{E}rror-{R}esilient {L}ow-{P}ower {V}iterbi {D}ecoder {A}rchitectures},
+  Author                   = {Abdallah, R. A. and Shanbhag, N. R.},
+  Journal                  = {Signal Processing, IEEE Transactions on},
+  Year                     = {2009},
+  Number                   = {12},
+  Pages                    = {4906--4917},
+  Volume                   = {57},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Shanbhag, Viterbi
+- Transactions, seeh abdsha_08, abdsha_08a},
+  Doi                      = {10.1109/TSP.2009.2026078},
+  File                     = {abdsha_09.pdf:abdsha_09.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{abdsha_08,
+  Title                    = {{E}rror-resilient low-power {V}iterbi decoders via state clustering},
+  Author                   = {Abdallah, R. A. and Shanbhag, N. R.},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems SiPS 2008},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {221--226},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Shanbhag, Viterbi
+- separation of LSB part and MSB part --> smalller errors, also in error free case
+- see abdsha_08a, abdsha_09},
+  Doi                      = {10.1109/SIPS.2008.4671766},
+  File                     = {abdsha_08.pdf:abdsha_08.pdf:PDF},
+  Keywords                 = {Reliability, Convolutional},
+  Owner                    = {Brehm, May},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{abdsha_08a,
+  Title                    = {{E}rror-resilient low-power {V}iterbi decoders},
+  Author                   = {Abdallah, R. A. and Shanbhag, N. R.},
+  Booktitle                = {Proc. ACM/IEEE Int Low Power Electronics and Design (ISLPED) Symp},
+  Year                     = {2008},
+  Pages                    = {111--116},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Shanbhag, Viterbi
+- separation of LSB part and MSB part --> smalller errors, also in error free case
+- see abdsha_08, abdsha_09},
+  Doi                      = {10.1145/1393921.1393951},
+  File                     = {abdsha_08a.pdf:abdsha_08a.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{abdlee_11,
+  Title                    = {{T}iming error statistics for energy-efficient robust {DSP} systems},
+  Author                   = {Abdallah, R.A. and Yu-Hung Lee and Shanbhag, N.R.},
+  Booktitle                = {Proc. 2011 Design, Automation and Test in Europe (DATE '11)},
+  Year                     = {2011},
+  Month                    = mar,
+  Pages                    = {1--4},
+
+  File                     = {abdlee_11.pdf:abdlee_11.pdf:PDF},
+  ISSN                     = {1530-1591},
+  Keywords                 = {Reliability}
+}
+
+@InProceedings{abdker_08,
+  Title                    = {{A}n {FPGA} implementation of a soft-in soft-out decoder for block codes},
+  Author                   = {Abdul-Shakoor, A.-R. and Kerr, R. and Lodge, J. and Szwarc, V.},
+  Booktitle                = {Proc. 24th Biennial Symp. Communications},
+  Year                     = {2008},
+  Pages                    = {226--230},
+
+  Doi                      = {10.1109/BSC.2008.4563244},
+  File                     = {abdker_08.pdf:abdker_08.pdf:PDF},
+  Owner                    = {Scholl},
+  Review                   = {FPGA Implementierung vom Vector SISO Algorithmus},
+  Timestamp                = {2011.07.21}
+}
+
+@Electronic{abi_13,
+  Title                    = {{B}ig {B}rand {T}ablet {I}nstalled {B}ase to {S}urpass 285 {M}illion by {Y}ear’s {E}nd},
+  Author                   = {ABIresearch},
+  HowPublished             = {\url{https://www.abiresearch.com/press/big-brand-tablet-installed-base-to-surpass-285-mil}},
+  Language                 = {en},
+  Month                    = dec,
+  Note                     = {last access 2014-07-02},
+  Url                      = {https://www.abiresearch.com/press/big-brand-tablet-installed-base-to-surpass-285-mil},
+  Year                     = {2013},
+
+  Cds_grade                = {4},
+  Cds_read                 = {2014-01-08},
+  Cds_review               = {285 Mio. tablets in use at end of 2013},
+  File                     = {abi_13.pdf:abi_13.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.08}
+}
+
+@InProceedings{abudec_10,
+  Title                    = {{T}rapping set enumerators for specific {LDPC} codes},
+  Author                   = {Abu-Surra, S. and DeClercq, D. and Ryan, W. and Divsalar, D.},
+  Booktitle                = {Information Theory and Applications Workshop (ITA), 2010},
+  Year                     = {2010},
+  Pages                    = {1--5},
+
+  Comment                  = {enthält den (32,16) LDPC code proposed to CCSDS},
+  Doi                      = {10.1109/ITA.2010.5454095},
+  File                     = {abudec_10.pdf:abudec_10.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.11},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5454095}
+}
+
+@Other{Accenture2017,
+  Title                    = {{A}ccelerating the {J}ourney to {C}loud: {T}op 10 {C}hallenges for {I}nvestment {B}anks},
+  Author                   = {Accenture},
+  Note                     = {\url{https://www.accenture.com/t20170111T213812__w__/us-en/_acnmedia/Accenture/Designlogic/16-3360/documents/Accenture-2017-Top-10-Challenges-07-Cloud.pdf}. Last access: 05 Nov 2017},
+  Url                      = {https://www.accenture.com/t20170111T213812__w__/us-en/_acnmedia/Accenture/Designlogic/16-3360/documents/Accenture-2017-Top-10-Challenges-07-Cloud.pdf},
+  Year                     = {2017}
+}
+
+@Electronic{acc_10,
+  Title                    = {{C}loud {C}omputing and {S}ustainability: {T}he {E}nvironmental {B}enefits of {M}oving to the {C}loud},
+  Author                   = {Accenture},
+  HowPublished             = {\url{http://www.accenture.com/SiteCollectionDocuments/PDF/Accenture_Sustainability_Cloud_Computing_TheEnvironmentalBenefitsofMovingtotheCloud.pdf}},
+  Language                 = {en},
+  Note                     = {last access: 2014-06-15},
+  Url                      = {\url{http://www.accenture.com/SiteCollectionDocuments/PDF/Accenture_Sustainability_Cloud_Computing_TheEnvironmentalBenefitsofMovingtotheCloud.pdf}},
+  Year                     = {2010},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {cloud, energy, CO2},
+  File                     = {acc_10.pdf:acc_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.15}
+}
+
+@Article{cartas_02,
+  Title                    = {{O}n the coherence of {E}xpected {S}hortfall},
+  Author                   = {Carlo Acerbi and Dirk Tasche},
+  Journal                  = {Journal of Banking \& Finance},
+  Year                     = {2002},
+
+  Month                    = {Apr},
+  Number                   = {7},
+  Pages                    = {1487-1503},
+  Volume                   = {26},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@Electronic{ack_10,
+  Title                    = {{A}n algorithm for computing the inverse normal cumulative distribution function},
+  Author                   = {Peter J. Acklam},
+  Month                    = {January},
+  Url                      = {http://home.online.no/~pjacklam/notes/invnorm/},
+  Year                     = {2010},
+
+  Owner                    = {Schmidt},
+  Timestamp                = {2010.08.03}
+}
+
+@Electronic{Acklam2010,
+  Title                    = {{A}n algorithm for computing the inverse normal cumulative distribution function},
+  Author                   = {Peter J. Acklam},
+  Month                    = {January},
+  Url                      = {http://home.online.no/~pjacklam/notes/invnorm/},
+  Year                     = {2010},
+
+  Owner                    = {Schmidt},
+  Timestamp                = {2010.08.03}
+}
+
+@InProceedings{acknic_98,
+  Title                    = {{High Performance DSPs -- What's Hot and What's Not?}},
+  Author                   = {B. Ackland and C. Nicol},
+  Booktitle                = {Proc. 1998 International Symposium on Low Power Electronics and Design (ISLPED '98)},
+  Year                     = {1998},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = aug,
+  Pages                    = {1--6},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Actel2002,
+  Title                    = {{U}nderstanding {S}oft and {F}irm {E}rrors in {S}emiconductor {D}evices},
+
+  Author                   = {Actel},
+  HowPublished             = {http://www.actel.com},
+  Year                     = {2002},
+
+  File                     = {actunderstanding02.pdf:actunderstanding02.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.06}
+}
+
+@Misc{actunderstanding02,
+  Title                    = {{U}nderstanding {S}oft and {F}irm {E}rrors in {S}emiconductor {D}evices},
+
+  Author                   = {Actel},
+  HowPublished             = {http://www.actel.com},
+  Year                     = {2002},
+
+  File                     = {actunderstanding02.pdf:actunderstanding02.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.06}
+}
+
+@Electronic{acw_15,
+  Title                    = {2014 {FIA} {A}nnual {G}lobal {F}utures and {O}ptions {V}olume: {G}ains in {N}orth {A}merica and {E}urope {O}ffset {D}eclines in {A}sia-{P}acific},
+  Author                   = {Will Acworth},
+  Month                    = {mar},
+  Note                     = {last access 2015-10-19},
+  Organization             = {Futures Industry Magazine},
+  Url                      = {https://fimag.fia.org/articles/2014-fia-annual-global-futures-and-options-volume-gains-north-america-and-europe-offset},
+  Year                     = {2015},
+
+  Comment                  = {last access 2015-07-13},
+  Journal                  = {Futures Industry Magazine},
+  Owner                    = {varela},
+  Timestamp                = {2015.07.13}
+}
+
+@Misc{AdamDunkels2012,
+  Title                    = {{lwIP - A Lightweight TCP/IP stack}},
+
+  Author                   = {{Adam Dunkels}},
+  Year                     = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.10.04},
+  Url                      = {http://savannah.nongnu.org/projects/lwip}
+}
+
+@Misc{adlwip12,
+  Title                    = {{lwIP - A Lightweight TCP/IP stack}},
+
+  Author                   = {{Adam Dunkels}},
+  Year                     = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.10.04},
+  Url                      = {http://savannah.nongnu.org/projects/lwip}
+}
+
+@InProceedings{addpyn_00,
+  Title                    = {{Recent simplifications and improvements in Block Turbo Codes}},
+  Author                   = {P. Adde and R. Pyndiah},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {133--136},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{addgom_12,
+  Title                    = {{D}esign of an {E}fficient {M}aximum {L}ikelihood {S}oft {D}ecoder for {S}ystematic {S}hort {B}lock {C}odes},
+  Author                   = {P. Adde and D. Gomez Toro and C. Jego},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2012},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {3914-3919},
+  Volume                   = {60},
+
+  Doi                      = {10.1109/TSP.2012.2193575},
+  ISSN                     = {1053-587X},
+  Keywords                 = {binary codes;block codes;computational complexity;error statistics;field programmable gate arrays;linear codes;matrix algebra;maximum likelihood decoding;parity check codes;redundancy;BER performance;Chase-2 algorithm;FPGA device;classical algebraic decoding;code rate;codeword list;computational complexity;cortex codes;digital implementations;double reencoding technique;field-programmable gate array device;invertible submatrix;linear block codes;optimum maximum likelihood soft-decision decoding;parity check matrix;redundancy part;systematic binary block codes;systematic short block codes;Bit error rate;Block codes;Error correction;Error correction codes;Maximum likelihood decoding;Systematics;Computational complexity;decoder architecture;re- encoding;soft decoding;systematic short bloc codes}
+}
+
+@Conference{Adegbenga2007,
+  Title                    = {{Low-Complexity} {F}requency {E}stimator for {DVB-S2} and {B}urst {T}ransmissions at {L}ow {SNR}},
+  Author                   = {B. Adegbenga and Awoseyila and K. Christos and B. G. Evans},
+  Booktitle                = {25th AIAA International Communications Satellite Systems Conference},
+  Year                     = {2007},
+
+  Address                  = {Seoul, South Korea},
+  Month                    = {April},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.03.06}
+}
+
+@InProceedings{adeaug_15,
+  Title                    = {{O}ptimizing a pipelined {MIMO} sphere detector for energy efficiency},
+  Author                   = {Adeva, Esther and Augustin, Thomas and Fettweis, Gerhard},
+  Booktitle                = {Wireless Communications Signal Processing (WCSP), 2015 International Conference on},
+  Year                     = {2015},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/WCSP.2015.7341159},
+  File                     = {adeaug_15.pdf:adeaug_15.pdf:PDF},
+  Keywords                 = {CMOS integrated circuits;MIMO communication;integrated circuit design;low-power electronics;pipeline processing;signal detection;telecommunication power management;automated pipelining;battery powered devices;energy efficiency;pipelined MIMO sphere detector;retiming method;wireless communications;Computer architecture;Detectors;MIMO;Measurement;Pipeline processing;Receivers;Throughput;Multiple-input multiple-output (MIMO);VLSI design;pipelining;retiming;sphere detection (SD)},
+  Owner                    = {MH},
+  Timestamp                = {2016-03-09}
+}
+
+@Article{adesei_13,
+  Title                    = {{VLSI} {A}rchitecture for {MIMO} {S}oft-{I}nput {S}oft-{O}utput {S}phere {D}etection},
+  Author                   = {Adeva, Esther and Seifert, Tobias and Fettweis, Gerhard},
+  Journal                  = {Journal of Signal Processing Systems},
+  Year                     = {2013},
+  Number                   = {2},
+  Pages                    = {125-143},
+  Volume                   = {70},
+
+  Doi                      = {10.1007/s11265-012-0709-z},
+  File                     = {adesei_13.pdf:adesei_13.pdf:PDF},
+  ISSN                     = {1939-8018},
+  Keywords                 = {MIMO; Iterative detection-decoding; Soft-input soft-output (SISO) detection; Sphere detection; Tuple search detector; SIMD; Pipeline-interleaving; VLSI architecture},
+  Language                 = {English},
+  Owner                    = {Gimmler},
+  Publisher                = {Springer US},
+  Timestamp                = {2013.04.10},
+  Url                      = {http://dx.doi.org/10.1007/s11265-012-0709-z}
+}
+
+@PhdThesis{Phdadev15,
+  Title                    = {{E}fficient {MIMO} {S}phere {D}etection: {A}lgorithms and {A}rchitectures},
+  Author                   = {Ester Pérez Adeva},
+  School                   = {Technische Universität Dresden},
+  Year                     = {2015},
+
+  File                     = {Phdadev15.pdf:Phdadev15.pdf:PDF},
+  Owner                    = {MH},
+  Timestamp                = {2016-03-09}
+}
+
+@Conference{adi_16,
+  Title                    = {{CLARA}: {C}ircular {L}inked-{L}ist {A}uto and {S}elf {R}efresh {A}rchitecture},
+  Author                   = {Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel Emer, Stephen Keckler},
+  Year                     = {2016},
+
+  Journal                  = {MEMSYS 2016},
+  Owner                    = {DMM},
+  Timestamp                = {2017-07-31}
+}
+
+@InProceedings{adlfet_16,
+  Title                    = {{S}afety {E}ngineering for {A}utonomous {V}ehicles},
+  Author                   = {Adler, Rasmus and Feth, Patrick and Schneider, Daniel},
+  Booktitle                = {2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W)},
+  Year                     = {2016},
+  Month                    = {June},
+  Pages                    = {200-205},
+
+  Doi                      = {10.1109/DSN-W.2016.30},
+  Keywords                 = {decision making;safety;vehicles;safety engineering;autonomous vehicles;nonautonomous vehicles;safety criticality;decision making process;control commands;Safety;Vehicles;Accidents;Acceleration;Standards;Road transportation;Runtime;safety engineering;autonomous driving;safety cage},
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-02}
+}
+
+@InProceedings{advcha_14,
+  Title                    = {{R}efresh {E}nabled {V}ideo {A}nalytics ({REVA}): {I}mplications on power and performance of {DRAM} supported embedded visual systems},
+  Author                   = {Advani, Siddharth and Chandramoorthy, N. and Swaminathan, K. and Irick, K. and Cho, Y.C.P. and Sampson, J. and Narayanan, V.},
+  Booktitle                = {32nd IEEE International Conference on Computer Design (ICCD)},
+  Year                     = {2014},
+  Month                    = {Oct},
+  Pages                    = {501-504},
+
+  Doi                      = {10.1109/ICCD.2014.6974727},
+  Keywords                 = {DRAM chips;embedded systems;image sensors;low-power electronics;video signal processing;DRAM memory refresh energy;DRAM refresh scheme;Google Glasses;REVA system;battery lifetimes;computational power;embedded architecture;embedded systems;embedded video analytics applications;embedded visual systems;image sensors;memory storage;mobile systems;multiobject scene;refresh enabled video analytics;ubiquitous;video applications;wearable video systems;Computational modeling;Computer architecture;Object recognition;Random access memory;Standards;Streaming media;Visualization},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@TechReport{Wireless,
+  Title                    = {{D}iscovery 300: {N}ext {G}eneration {DVB-RCS} {VSAT} {H}ub},
+  Author                   = {{Advantech Wireless}},
+
+  Address                  = {http://www.advantechwireless.com/wp-content/uploads/PB-MILL-HUB-14027.pdf},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.02.02}
+}
+
+@Article{advsan_05,
+  Title                    = {{R}eliability-{A}ware {M}icroarchitecture},
+  Author                   = {S.V. Adve and Pia Sanda},
+  Journal                  = {IEEE Micro},
+  Year                     = {2005},
+
+  Month                    = nov # {--} # dec,
+  Number                   = {6},
+  Pages                    = {8--9},
+  Volume                   = {25},
+
+  File                     = {advsan_05.pdf:advsan_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Organization             = {IEEE micro},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Type                     = {Magazine}
+}
+
+@InProceedings{afibal_14,
+  Title                    = {{A} low-complexity improved successive cancellation decoder for polar codes},
+  Author                   = {O. Afisiadis and A. Balatsoukas-Stimming and A. Burg},
+  Booktitle                = {Signals, Systems and Computers, 2014 48th Asilomar Conference on},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {2116-2120},
+
+  Doi                      = {10.1109/ACSSC.2014.7094848},
+  Keywords                 = {computational complexity;decoding;error statistics;signal processing;average computational complexity;frame error rate;low-complexity improved SC flip decoder;polar codes;signal quality;successive cancellation decoding;Computational complexity;Decoding;Error analysis;Memory management;Signal to noise ratio},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Misc{afpgoogle15,
+  Title                    = {{G}oogle {I}s {T}urning {S}martphones {I}nto {R}eal-{T}ime {T}ranslators},
+
+  Author                   = {AFP},
+  HowPublished             = {Business Insider UK, \url{http://uk.businessinsider.com/afp-google-turns-smartphones-into-real-time-translators-2015-1}},
+  Month                    = jan,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.31}
+}
+
+@InProceedings{agabal_08,
+  Title                    = {{O}ptimized {C}ircuit {F}ailure {P}rediction for {A}ging: {P}racticality and {P}romise},
+  Author                   = {Agarwal, M. and Balakrishnan, V. and Bhuyan, A. and Kyunglok Kim and Paul, B. C. and Wenping Wang and Bo Yang and Yu Cao and Mitra, S.},
+  Booktitle                = {Proc. IEEE International Test Conference ITC 2008},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {1--10},
+
+  Doi                      = {10.1109/TEST.2008.4700619},
+  File                     = {agabal_08.pdf:agabal_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.23}
+}
+
+@InProceedings{agapau_07,
+  Title                    = {{C}ircuit {F}ailure {P}rediction and {I}ts {A}pplication to {T}ransistor {A}ging},
+  Author                   = {Agarwal, M. and Paul, B. C. and Ming Zhang and Mitra, S.},
+  Booktitle                = {Proc. 25th IEEE VLSI Test Symposium},
+  Year                     = {2007},
+  Month                    = may,
+  Pages                    = {277--286},
+
+  Doi                      = {10.1109/VTS.2007.22},
+  File                     = {agapau_07.pdf:agapau_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.23}
+}
+
+@Article{agaand_02,
+  Title                    = {{A 600-MHz VLIW DSP}},
+  Author                   = {S. Agarwala and T. Anderson and A. Hill and M.D. Ales and R. Damodaran and P. Wiley and T.T. Elappuparackal},
+  Journal                  = {IEEE Journal of Silid-State Circuits},
+  Year                     = {2002},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {1532--1544},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{agefly_73,
+  Title                    = {{C}omments on {C}apabilities, {L}imitations and {C}orrectness of {P}etri {N}ets},
+  Author                   = {Agerwala, Tilak and Flynn, Mike},
+  Booktitle                = {Proceedings of the 1st Annual Symposium on Computer Architecture},
+  Year                     = {1973},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {81--86},
+  Publisher                = {ACM},
+  Series                   = {ISCA '73},
+
+  Acmid                    = {803973},
+  Doi                      = {10.1145/800123.803973},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-27},
+  Url                      = {http://doi.acm.org/10.1145/800123.803973}
+}
+
+@Article{aghmey_91,
+  Title                    = {{A} new method for phase synchronization and automatic gain control of linearly modulated signals on frequency-flat fading channels},
+  Author                   = {Aghamohammadi, A. and Meyr, H. and Ascheid, G.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1991},
+  Number                   = {1},
+  Pages                    = {25--29},
+  Volume                   = {39},
+
+  Abstract                 = {An optimal phase synchronization and automatic gain control (AGC) scheme for coherent reception of linearly modulated signals on frequency-flat mobile fading channels is presented. The channel model and receiver performance are described. It is shown that using the technique allows the irreducible error floors (due to random FM) known from the noncoherent methods to be practically eliminated. Depending on the fastness of the fading, large power gains over the noncoherent methods are achieved. Unfavorable analog signal processing and/or the high bandwidth inefficiency of the FDM-pilot coherent methods are also avoided},
+  Doi                      = {10.1109/26.68273},
+  File                     = {aghmey_91.pdf:aghmey_91.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {0090-6778},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@InProceedings{agohic_05,
+  Title                    = {{E}rratic fluctuations of sram cache vmin at the 90nm process technology node},
+  Author                   = {Agostinelli, M. and Hicks, J. and Xu, J. and Woolery, B. and Mistry, K. and Zhang, K. and Jacobs, S. and Jopling, J. and Yang, W. and Lee, B. and Raz, T. and Mehalel, M. and Kolar, P. and Wang, Y. and Sandford, J. and Pivin, D. and Peterson, C. and DiBattista, M. and Pae, S. and Jones, M. and Johnson, S. and Subramanian, G. },
+  Booktitle                = {Proc. IEDM Technical Digest Electron Devices Meeting IEEE International},
+  Year                     = {2005},
+  Month                    = dec,
+  Pages                    = {655--658},
+
+  Doi                      = {10.1109/IEDM.2005.1609436},
+  File                     = {agohic_05.pdf:agohic_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.22}
+}
+
+@InProceedings{agrfoh_17,
+  Title                    = {{DRAM}-related {C}hallenges in {T}ask {S}cheduling with {T}iming {P}redictability on {COTS} {M}ulti-cores for {S}afety-critical {S}ystems},
+  Author                   = {Agrawal, Ankit and Fohler, Gerhard},
+  Booktitle                = {Proceedings of the International Symposium on Memory Systems},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {265--267},
+  Publisher                = {ACM},
+  Series                   = {MEMSYS '17},
+
+  Acmid                    = {3132417},
+  Doi                      = {10.1145/3132402.3132417},
+  ISBN                     = {978-1-4503-5335-9},
+  Keywords                 = {COTS DRAM controller, COTS multi-cores, inter-core interference, safety-critical systems, timing predictability},
+  Location                 = {Alexandria, Virginia},
+  Numpages                 = {3},
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-18},
+  Url                      = {http://doi.acm.org/10.1145/3132402.3132417}
+}
+
+@InProceedings{agroc_16,
+  Title                    = {{CLARA}: {C}ircular {L}inked-{L}ist {A}uto and {S}elf {R}efresh {A}rchitecture},
+  Author                   = {Agrawal, Aditya and O'Connor, Mike and Bolotin, Evgeny and Chatterjee, Niladrish and Emer, Joel and Keckler, Stephen},
+  Booktitle                = {Proceedings of the Second International Symposium on Memory Systems},
+  Year                     = {2016},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {338--349},
+  Publisher                = {ACM},
+  Series                   = {MEMSYS '16},
+
+  Acmid                    = {2989084},
+  Doi                      = {10.1145/2989081.2989084},
+  ISBN                     = {978-1-4503-4305-3},
+  Keywords                 = {Auto refresh, DRAM, Self refresh},
+  Location                 = {Alexandria, VA, USA},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2015.08.11},
+  Url                      = {http://doi.acm.org/10.1145/2989081.2989084}
+}
+
+@Article{ahlnel_99,
+  Title                    = {{O}ptimal {F}inite {F}ield {M}ultipliers for {FPGA}s},
+  Author                   = {Ahlquist, G.C. and Nelson, B. and Rice, M.},
+  Journal                  = {Lecture notes in computer science, Vol. 1673},
+  Year                     = {1999},
+  Pages                    = {51--60},
+  Volume                   = {1673},
+
+  Abstract                 = {With the end goal of implementing optimal Reed-Solomon
+error control decoders on FPGAs, we characterize the FPGA performance
+of several nite eld multiplier designs reported in the literature.
+We discover that nite eld multipliers optimized for VLSI implementation
+are not optimized for FPGA implementation. Based on this observation,
+we discuss the relative merits of each multiplier design and
+show why each does not perform well on FPGAs. We then suggest how
+to improve the performance of many nite eld multiplier designs1.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Galois field multiplier, FFM, FPGA},
+  File                     = {ahlnel_99.pdf:ahlnel_99.pdf:PDF},
+  Owner                    = {CdS},
+  Publisher                = {Springer},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{ahmawa_11,
+  Title                    = {{A} high throughput turbo decoder {VLSI} architecture for 3{GPP} {LTE} standard},
+  Author                   = {Ahmed, A. and Awais, M. and ur Rehman, A. and Maurizio, M. and Masera, G.},
+  Booktitle                = {Multitopic Conference (INMIC), 2011 IEEE 14th International},
+  Year                     = {2011},
+  Month                    = {Dec},
+  Pages                    = {340-346},
+
+  Doi                      = {10.1109/INMIC.2011.6151500},
+  Keywords                 = {3G mobile communication;Long Term Evolution;VLSI;decoding;network coding;turbo codes;3GPP LTE standard;backward state metrics;batcher-sorting-based permutation network;bit rate 285 Mbit/s;computational cost;frequency 200 MHz;high parallel turbo decoding architecture;high throughput turbo decoder VLSI architecture;size 90 nm;standard cell ASIC technology;Standards;3GPP LTE;VLSI architecture;iterative decoding;parallel turbo decoder},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@Article{ahmkoe_11,
+  Title                    = {{VLSI} {A}rchitectures for {S}oft-{D}ecision {D}ecoding of {R}eed--{S}olomon {C}odes},
+  Author                   = {Ahmed, A. and Koetter, R. and Shanbhag, N. R.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2011},
+  Number                   = {2},
+  Pages                    = {648--667},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TIT.2010.2095210},
+  File                     = {ahmkoe_11.pdf:ahmkoe_11.pdf:PDF},
+  Keywords                 = {ASD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.27}
+}
+
+@InProceedings{ahmkoe_04a,
+  Title                    = {{P}erformance analysis of the adaptive parity check matrix based soft-decision decoding algorithm},
+  Author                   = {Ahmed, A. and Koetter, R. and Shanbhag, N. R.},
+  Booktitle                = {Proc. Conf Signals, Systems and Computers Record of the Thirty-Eighth Asilomar Conf},
+  Year                     = {2004},
+  Pages                    = {1995--1999},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/ACSSC.2004.1399514},
+  File                     = {ahmkoe_04a.pdf:ahmkoe_04a.pdf:PDF},
+  Keywords                 = {ABP, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {Analyse des ABP (RS Codes) & neuer Algorithmus, der mit dem Syndrom, bzw. dem Syndromgewicht arbeitet},
+  Timestamp                = {2011.06.21}
+}
+
+@InProceedings{ahmsha_06,
+  Title                    = {{A}n {A}rchitectural {C}omparison of {R}eed-{S}olomon {S}oft-{D}ecoding {A}lgorithms},
+  Author                   = {Ahmed, A. and Shanbhag, N. R. and Koetter, R.},
+  Booktitle                = {Proc. Fortieth Asilomar Conf. Signals, Systems and Computers ACSSC '06},
+  Year                     = {2006},
+  Pages                    = {912--916},
+
+  Doi                      = {10.1109/ACSSC.2006.354883},
+  File                     = {ahmsha_06.pdf:ahmsha_06.pdf:PDF},
+  Keywords                 = {OSD, ASD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {Vergleich zw GMD, OSD und ASD für RS Soft-Decoder},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{ahmahm_16,
+  Title                    = {{O}perating {W}ireless {S}ensor {N}odes without {E}nergy {S}torage: {E}xperimental {R}esults with {T}ransient {C}omputing},
+  Author                   = {Ahmed, Faisal and Ahmed, Tauseef and Muhammad, Yar and Le Moullec, Yannick and Annus, Paul},
+  Journal                  = {Electronics},
+  Year                     = {2016},
+  Number                   = {4},
+  Volume                   = {5},
+
+  Article-number           = {89},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {electronics5040089},
+  Ccr_keywords             = {not accessible due to new license issue},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.3390/electronics5040089},
+  ISSN                     = {2079-9292},
+  Keywords                 = {TCS},
+  Owner                    = {CCR},
+  Url                      = {http://www.mdpi.com/2079-9292/5/4/89}
+}
+
+@Article{ahmker_18,
+  Title                    = {{Autonomous Wireless Sensor Networks: Implementation of Transient Computing and Energy Prediction for Improved Node Performance and Link Quality}},
+  Author                   = {Ahmed, Faisal and Kervadec, Corentin and Le Moullec, Yannick and Tamberg, Gert and Annus, Paul},
+  Journal                  = {The Computer Journal},
+  Year                     = {2018},
+
+  Month                    = {10},
+  Number                   = {6},
+  Pages                    = {820-837},
+  Volume                   = {62},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {ok},
+  Ccr_key_original         = {10.1093/comjnl/bxy101},
+  Ccr_keywords             = {PN, solar EH, predicting energy availability in the near future},
+  Ccr_relevance            = {high},
+  Ccr_topic                = {ATC, PCP},
+  Doi                      = {10.1093/comjnl/bxy101},
+  Eprint                   = {http://oup.prod.sis.lan/comjnl/article-pdf/62/6/820/28680876/bxy101.pdf},
+  ISSN                     = {0010-4620},
+  Keywords                 = {TCS},
+  Owner                    = {CCR},
+  Url                      = {https://doi.org/10.1093/comjnl/bxy101}
+}
+
+@InProceedings{ahmars_07,
+  Title                    = {{VLSI} {D}esign of {M}ulti {S}tandard {T}urbo {D}ecoder for 3{G} and {B}eyond},
+  Author                   = {Imran Ahmed and Tughrul Arslan},
+  Booktitle                = {Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific},
+  Year                     = {2007},
+  Month                    = {jan.},
+  Pages                    = {589 -594},
+
+  Doi                      = {10.1109/ASPDAC.2007.358050},
+  Keywords                 = {3G mobile communication;Computer architecture;Decoding;Error correctioncodes;Kernel;Multiaccess communication;Switches;Turbo codes;Very large scaleintegration;Viterbi algorithm;3G mobile communication;VLSI;Viterbidecoding;codecs;integrated circuit design;logic design;turbo codes;180 nm;4G concept;UMCprocess technology;VLSI design;Viterbi components;Viterbi decoder;error correctingcapability;multistandard turbo decoder;normalization scheme;reconfigurablemappings;turbo codes;turbo component;turbo decoding architectures;}
+}
+
+@InProceedings{ahmali_18,
+  Title                    = {{P}oster {A}bstract: {T}owards {S}maller {C}heckpoints for {B}etter {I}ntermittent {C}omputing},
+  Author                   = {S. {Ahmed} and M. H. {Alizai} and J. H. {Siddiqui} and N. A. {Bhatti} and L. {Mottola}},
+  Booktitle                = {2018 17th ACM/IEEE International Conference on Information Processing in Sensor Networks (IPSN)},
+  Year                     = {2018},
+  Month                    = {April},
+  Pages                    = {132-133},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8480052},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/IPSN.2018.00029},
+  Keywords                 = {TCS},
+  Keywords_original        = {checkpointing;embedded systems;energy conservation;power aware computing;random-access storage;differential techniques;embedded devices;nonvolatile memory;energy unavailability;energy budget;energy efficiency;intermittent computing;checkpoint;Nonvolatile memory;Systems support;Energy harvesting;Instruments;Measurement;Checkpointing;Energy efficiency;Sensor Networks;Embedded Systems},
+  Owner                    = {CCR}
+}
+
+@InProceedings{ahm_01,
+  Title                    = {{Block-Size Estimation and Application to BTFD for 3GPP UMTS}},
+  Author                   = {W. K. M. Ahmed},
+  Booktitle                = {Proc. 2001 Global Telecommunications Conference (GLOBECOM '01)},
+  Year                     = {2001},
+  Pages                    = {3045--3049},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{ahnjeo_06,
+  Title                    = {{Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications}},
+  Author                   = {J.-H. Ahn and Bong-Hwa Jeong and Saeng-Hwan Kim and Shin-Ho Chu and Sung-Kwon Cho and Han-Jin Lee and Min-Ho Kim and Sang-Il Park and Sung-Won Shin and Jun-Ho Lee and Bong-Seok Han and Jae-Keun Hong and Moran, P.B. and Yong-Tak Kim},
+  Booktitle                = {ASSCC. IEEE Asian},
+  Year                     = {2006},
+  Month                    = {Nov},
+
+  Doi                      = {10.1109/ASSCC.2006.357915},
+  Keywords                 = {DRAM chips;circuit testing;mobile handsets;transistors;adaptive self refresh scheme;battery operated high-density mobile DRAM applications;capacitor charge uniformity;cell transistor;dual period based refresh;internal refresh test circuits;power dissipation;row register information;Automatic speech recognition;Automatic testing;Batteries;Capacitors;Circuit testing;Power dissipation;Random access memory;Registers;SDRAM;Semiconductor devices}
+}
+
+@Article{ahrdie_88,
+  Title                    = {{E}fficient table-free sampling methods for the exponential, {C}auchy, and normal distributions},
+  Author                   = {Ahrens, Joachim H. and Dieter, Ulrich},
+  Journal                  = {Commun. ACM},
+  Year                     = {1988},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {1330--1337},
+  Volume                   = {31},
+
+  Acmid                    = {50094},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation},
+  Doi                      = {10.1145/50087.50094},
+  ISSN                     = {0001-0782},
+  Issue_date               = {Nov. 1988},
+  Keywords                 = {finance},
+  Numpages                 = {8},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2012.03.22},
+  Url                      = {http://doi.acm.org/10.1145/50087.50094}
+}
+
+@InCollection{aicbin_11,
+  Title                    = {{A} {F}ast and {S}table {H}eston {M}odel {C}alibration on the {GPU}},
+  Author                   = {Aichinger, Michael and Binder, Andreas and Fürst, Johannes and Kletzmayr, Christian},
+  Booktitle                = {Euro-Par 2010 Parallel Processing Workshops},
+  Publisher                = {Springer Berlin / Heidelberg},
+  Year                     = {2011},
+  Editor                   = {Guarracino, Mario and Vivien, Frédéric and Träff, Jesper and Cannatoro, Mario and Danelutto, Marco and Hast, Anders and Perla, Francesca and Knüpfer, Andreas and Di Martino, Beniamino and Alexander, Michael},
+  Pages                    = {431--438},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {6586},
+
+  Abstract                 = {For the analysis of many exotic financial derivatives, the Heston model, a stochastic volatility model, is widely used. Its specific parameters have to be identified from sets of options market data with different strike prices and maturities, leading to a minimization problem for the least square error between the model prices and the market prices. It is intrinsic to the Heston model that this error functional typically exhibits a large number of local minima, therefore techniques from global optimization have to be applied or combined with local optimization techniques to deliver a trustworthy optimum. To achieve results in reasonable time, we approach as follows: (1) For the evaluation of the objective function, we use a Fourier cosine method, optimized for parallelization, and (2) the local/global optimization scheme is carried out on parallel architectures. Results are reported for a multi GPU server and a multicore SGI Altix 4700.},
+  Affiliation              = {Johann Radon Institute for Computational and Applied Mathematics (RICAM), Austrian Academy of Sciences, Altenberger Strasse 69, A-4040 Linz, Austria},
+  Cds_grade                = {4},
+  Cds_keywords             = {Heston, calibration, GPU, comparison},
+  Cds_read                 = {2014-08-11},
+  Cds_review               = {combines global optimization with LM
+special treatment of cases that do not fulfil the Feller condition},
+  Doi                      = {10.1007/978-3-642-21878-1},
+  File                     = {aicbin_11.pdf:aicbin_11.pdf:PDF},
+  ISBN                     = {978-3-642-21877-4},
+  Keyword                  = {Computer Science},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.08.29}
+}
+
+@Article{akebic_01,
+  Title                    = {{S}ci{F}inance: {A} {P}rogram {S}ynthesis {T}ool for {F}inancial {M}odeling},
+  Author                   = {Robert L. Akers and Ion Bica and Elaine Kant and Curt Randall and Robert L. Young},
+  Journal                  = {AI Magazine},
+  Year                     = {2001},
+  Number                   = {2},
+  Pages                    = {27},
+  Volume                   = {22},
+
+  Abstract                 = {The SciFinance software synthesis system, licensed to major investment banks, automates programming for financial risk-management activities -- from algorithms research to production pricing to risk control. SciFinance's high-level, extensible specification language, aspen, lets quantitative analysts generate code from concise model descriptions written in application-specific and mathematical terminology; typically, a page or less produces thousands of lines of c. aspen's abstractions help analysts focus on their primary tasks -- model description, validation, and analysis -- rather than on programming details. Compared with manual programming, automation produces codes that are more sophisticated, accurate, and consistent. Analysts develop models within a day that previously took weeks or were not even attempted. SciFinance extends a system that generates scientific computing codes in a variety of target languages. The implementation integrates an object-oriented knowledge base, refinement and optimization rules, computer algebra, and a planning system. The shared knowledge base is used by the specification checker, synthesis system, and information portal.},
+  Cds_grade                = {0},
+  File                     = {akebic_01.pdf:akebic_01.pdf:PDF},
+  ISSN                     = {0738-4602},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.25}
+}
+
+@InProceedings{akegoo_07,
+  Title                    = {{P}redator: {A} predictable {SDRAM} memory controller},
+  Author                   = {B. Akesson and K. Goossens and M. Ringhofer},
+  Booktitle                = {2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)},
+  Year                     = {2007},
+  Month                    = {Sept},
+  Pages                    = {251-256},
+
+  Doi                      = {10.1145/1289816.1289877},
+  Keywords                 = {CMOS memory circuits;DRAM chips;industrial property;integrated circuit design;microprocessor chips;multiprocessing systems;network interfaces;network-on-chip;CMOS technology;Predator;frequency 200 MHz;high-speed external memories;intellectual property component;memory access group;memory controller design;multiprocessor systems-on-chip;network interface;network-on-chip;predictable SDRAM memory controller;size 0.13 mum;Bandwidth;Clocks;Delay;Memory management;SDRAM;Switches;System-on-a-chip;Memory Controller;Predictability;SDRAM;System-on-Chip},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-29}
+}
+
+@InProceedings{akejrh_11,
+  Title                    = {{A}utomatic {G}eneration of {E}fficient {P}redictable {M}emory {P}atterns},
+  Author                   = {B. Akesson and W. Hayes Jr. and K. Goossens},
+  Booktitle                = {2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications},
+  Year                     = {2011},
+  Month                    = {Aug},
+  Pages                    = {177-184},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/RTCSA.2011.33},
+  ISSN                     = {2325-1271},
+  Keywords                 = {DRAM chips;automatic test pattern generation;embedded systems;formal verification;storage management chips;DDR2-DDR3 memory;SDRAM command;SDRAM controller;automatic generation;efficient predictable memory pattern;embedded system;error-prone process;formal verification;hardware component;real-time requirement;software component;Algorithm design and analysis;Bandwidth;Clocks;Memory management;SDRAM;Time factors;Timing;SDRAM;memory controller;memory efficiency;memory patterns;pattern generation;predictability;real-time},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-29}
+}
+
+@InProceedings{akihoe_14,
+  Title                    = {{HAML}e{T}: {H}ardware accelerated memory layout transform within 3{D}-stacked {DRAM}},
+  Author                   = {B. Akin and J. C. Hoe and F. Franchetti},
+  Booktitle                = {High Performance Extreme Computing Conference (HPEC), 2014 IEEE},
+  Year                     = {2014},
+  Month                    = {Sept},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/HPEC.2014.7040954},
+  Keywords                 = {DRAM chips;3D stacked DRAM layers;CPU memory subsystems;GPU memory subsystems;HAMLeT system;data intensive applications;data reorganization;energy efficiency potentials;hardware accelerated memory layout transform;layout transform algorithms;logic layer;magnitude performance improvement;matrix layout transform operations;memory hierarchy;memory layout transformations;parallelism;peak system utilization;performance optimization;roundtrip data movement;Bandwidth;Hardware;Layout;Parallel processing;Random access memory;Through-silicon vias;Transforms},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11}
+}
+
+@InProceedings{alaber_12,
+  Title                    = {{A} {V}ersatile {UDP}/{IP} based {PC} - {FPGA} {C}ommunication {P}latform},
+  Author                   = {Alachiotis, N. and Berger, S.A. and Stamatakis, A.},
+  Booktitle                = {Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on},
+  Year                     = {2012},
+  Month                    = dec,
+  Pages                    = {1--6},
+
+  Abstract                 = {We present a substantially improved version of our popular UDP/IP core for simple and fast PC ↔ FPGA communication over Gigabit Ethernet. We provide a novel feature to automatically configure (previously hard-coded) internal settings on the FPGA. Thereby, we substantially reduce the installation overhead when a FPGA shall communicate with several different PCs. The UDP/IP core is designed to occupy a minimum amount of hardware resources on the FPGA. On the PC side, this new automatic configuration protocol can be used and invoked via a C software interface which provides convenient functions for setting up the connection to the FPGA device and sending/retrieving arrays of common C data types to/from the UDP/IP core on the FPGA. The initial UDP/IP core version is available under the LGPL license at http://opencores.org/project, udp_ip__core while the improved version of the core, including the C software interface (also under LGPL), is available at http://opencores.org/project, pc_fpga_com.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ReConFig.2012.6416725},
+  File                     = {alaber_12.pdf:alaber_12.pdf:PDF}
+}
+
+@InProceedings{alaber_10,
+  Title                    = {{E}fficient {PC}-{FPGA} {C}ommunication over {G}igabit {E}thernet},
+  Author                   = {Alachiotis, N. and Berger, S.A. and Stamatakis, A.},
+  Booktitle                = {Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on},
+  Year                     = {2010},
+  Month                    = jun,
+  Pages                    = {1727-1734},
+
+  Abstract                 = {As FPGAs become larger and more powerful, they are increasingly used as accelerator devices for compute-intensive functions. Input/Output (I/O) speeds can become a bottleneck and directly affect the performance of a reconfigurable accelerator since the chip will idle when there are no data available. While PCI Express represents the currently fastest and most expensive solution to connect a FPGA to a general purpose CPU, there exist several applications with I/O requirements for which Gigabit Ethernet is sufficient. To this end, we present the design of an efficient UDP/IP core for PC-FPGA communication that has been designed to occupy a minimum amount of hardware resources on the FPGA. An observation regarding the internet checksum algorithm, allows us to reduce the hardware requirements for computing the checksum. Furthermore, this property also allows for initiating packet transmission immediately, i.e., the UDP/IP core can start a transmission without the requirement of receiving, storing, and processing user data beforehand. The UDP/IP core is available as open-source code. A comparison with related work on UDP/IP core implementations shows that our implementation is significantly more efficient in terms of resource utilization and performance. The experimental results were obtained on a real-world system and we also make available the PC software test application that is used for performance assessment to allow for reproduction of our results.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Loopy, FPGA, interface, ethernet},
+  Doi                      = {10.1109/CIT.2010.302},
+  File                     = {alaber_10.pdf:alaber_10.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Patent{Alagha2009,
+  Title                    = {{H}ybrid frequency offset estimator},
+  Year                     = {2009},
+  Author                   = {Alagha, N.S.},
+  Month                    = {sep},
+  Note                     = {US Patent 7,590,199},
+  Url                      = {http://www.google.tl/patents/US7590199},
+
+  Owner                    = {ali},
+  Publisher                = {Google Patents},
+  Timestamp                = {2015.04.30}
+}
+
+@Article{ala_98,
+  Title                    = {{A} simple transmit diversity technique for wireless communications},
+  Author                   = {Alamouti, S. M.},
+  Journal                  = {Selected Areas in Communications, IEEE Journal on},
+  Year                     = {1998},
+  Number                   = {8},
+  Pages                    = {1451--1458},
+  Volume                   = {16},
+
+  File                     = {ala_98a.pdf:ala_98a.pdf:PDF},
+  Grade                    = {5},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{Albanese2015,
+  Title                    = {{Callable Swaps, Snowballs, and Videogames}},
+  Author                   = {Claudio Albanese},
+  Journal                  = {Wilmott Magazine},
+  Year                     = {2015},
+
+  Month                    = {Aug.},
+  Note                     = {Online: \url{https://www.wilmott.com/tag/games/} Last access 21 Jan 2018},
+  Pages                    = {82--93}
+}
+
+@Article{albrin_03,
+  Title                    = {{A}nalysis, implementation and application of an ordered statistics decoder for the se{RS}(16,14) code},
+  Author                   = {Albanese, M. and Rinaldi, I. and Spalvieri, A.},
+  Journal                  = {IEE Proceedings-Communications},
+  Year                     = {2003},
+  Number                   = {4},
+  Pages                    = {249--252},
+  Volume                   = {150},
+
+  Doi                      = {10.1049/ip-com:20030412},
+  File                     = {albrin_03.pdf:albrin_03.pdf:PDF},
+  Keywords                 = {OSD, Implementation},
+  Owner                    = {Scholl},
+  Review                   = {Hardware Implementatierung eines OSD Decoders},
+  Timestamp                = {2011.07.14}
+}
+
+@TechReport{albmay_06,
+  Title                    = {{T}he {L}ittle {H}eston {T}rap},
+  Author                   = {Hansjörg Albrecher and Philipp Mayer and Wim Schoutens and Jurgen Tistaert},
+  Institution              = {K.U.Leuven Section of Statistics},
+  Year                     = {2006},
+  Month                    = sep,
+  Note                     = {issue 05},
+  Number                   = {06},
+
+  Abstract                 = {The role of characteristic functions in finance has been strongly amplified by the development of the general option pricing formula by Carr and Madan. As these functions are defined and operating in the complex plane, they potentially encompass a few well known numerical
+
+issues due to ”branching”. A number of elegant publications have emerged tackling these effects specifically for the Heston model. For the latter however we have two specifications for the characteristic function as they are the solutions to a Riccati equation. In this article 
+we put the i’s and cross the t’s by formally pointing out the properties of and relations between both versions. For the first specification we show that for nearly any parameter choice, instabilities will occur for large enough maturities. We subsequently establish - under an additional parameter restriction - the existence of a “threshold” maturity from which the complex operations become a spoil-sport. For the second specification of the characteristic function it is proved that stability is guaranteed under the full dimensional and unrestricted parameter space. We blend the theoretical results with a few examples.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Feller condition},
+  Cds_read                 = {2014-08-01},
+  Cds_review               = {compares two different classical Heston formulas --> different regarding treating complex log --> branch cut
+also mentions FFT --> not further investigated},
+  File                     = {albmay_06.pdf:albmay_06.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.15}
+}
+
+@InProceedings{A–lcer2003,
+  Title                    = {{Decoder Architecture for Array-Code-Based LDPC Codes}},
+  Author                   = {Ölcer, S.},
+  Booktitle                = {Proc. 2003 Global Telecommunications Conference (GLOBECOM '03)},
+  Year                     = {2003},
+
+  Address                  = {San Francisco, USA},
+  Month                    = dec,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{ald_10,
+  Title                    = {{H}igh-{F}requency {T}rading: {A} {P}ractical {G}uide to {A}lgorithmic {S}trategies and {T}rading {S}ystems},
+  Author                   = {Irene Aldridge},
+  Publisher                = {John Wiley \& Sons},
+  Year                     = {2010},
+
+  Address                  = {Hoboken, NJ, USA},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.24}
+}
+
+@Book{ale_08,
+  Title                    = {{V}alue-at-{R}isk {M}odels},
+  Author                   = {Carol Alexander},
+  Publisher                = {John Wiley \& Sons Ltd},
+  Year                     = {2008},
+
+  Address                  = {Chichester, West Sussex, England},
+  Series                   = {Market Risk Analysis},
+  Volume                   = {IV},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.04}
+}
+
+@Article{alf_12,
+  Title                    = {{S}trong convergence of some drift implicit {E}uler scheme. {A}pplication to the {CIR} process},
+  Author                   = {Alfonsi, Aur{\'e}lien},
+  Journal                  = {arXiv preprint arXiv:1206.3855},
+  Year                     = {2012},
+
+  Keywords                 = {finance},
+  Owner                    = {Brugger},
+  Timestamp                = {2013.10.25}
+}
+
+@InProceedings{Ali2012,
+  Title                    = {{Code-Aided Synchronization IP Core for Iterative Channel Decoders}},
+  Author                   = {Ali, I. and Wasenm\"{u}ller, U.},
+  Booktitle                = {Proc. Kleinheubacher Tagung},
+  Year                     = {2012},
+
+  Address                  = {Miltenberg, Germany},
+  Month                    = sep,
+
+  Owner                    = {scholl},
+  Timestamp                = {2015.06.11}
+}
+
+@Article{aliwas_15,
+  Title                    = {{A High Throughput Architecture for a Low Complexity Soft-Output Demapper}},
+  Author                   = {Imran Ali and Uwe Wasenm\"{u}ller and Norbert Wehn},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2015},
+
+  Month                    = {Mar},
+  Pages                    = {in press},
+  Volume                   = {13},
+
+  Address                  = {Miltenberg, Germany},
+  Booktitle                = {Proc. Kleinheubacher Tagung},
+  Owner                    = {Imran},
+  Timestamp                = {2013.30.07}
+}
+
+@InProceedings{aliwas_14,
+  Title                    = {{H}ardware {I}mplementation {I}ssues of {C}arrier {S}ynchronization for {P}ilot-{S}ymbol {A}ssisted {B}ursts: {A} {C}ase {S}tudy for {DVB}-{RCS}2},
+  Author                   = {Ali, Imran and Wasenm\"{u}ller, Uwe and Wehn, Norbert},
+  Booktitle                = {8th IEEE International Conference on Signal Processing and Communication Systems},
+  Year                     = {2014},
+
+  Address                  = {Gold Coast, Australia},
+  Month                    = {Dec},
+  Pages                    = {in press},
+
+  Doi                      = {10.1109/SPC.2013.6735092},
+  Keywords                 = {chemical engineering computing;learning (artificial intelligence);oils;pattern classification;α-agarofuran;β-agarofuran;10-epi-H-eudesmol;Forest Research Institute Malaysia;H-eudesmol;agarwood oil quality grading;eudesmol;hexadecanol;k- nearest neighbor;k-NN;longifolol;oxo-agarospirol;Accuracy;Chemical compounds;Conferences;Oils;Sensitivity;Testing;Training;agarwood oil;agarwood oil quality and chemical compounds;grading;k-Nearest Neighbor(k-NN)}
+}
+
+@InProceedings{aliwas_14a,
+  Title                    = {{F}eedforward {C}arrier {S}ynchronization for {P}ilotless {B}ursts of {DVB}-{RCS}2},
+  Author                   = {Ali, I. and Wasenm\"{u}ller, Uwe. and Wehn, N.},
+  Booktitle                = {9th IEEE International Symposium on Communication Systems, Networks Digital Signal Processing},
+  Year                     = {2014},
+
+  Address                  = {Manchester, UK},
+  Month                    = {July},
+  Pages                    = {342-347},
+
+  Doi                      = {10.1109/CSNDSP.2014.6923851},
+  Keywords                 = {decoding;digital video broadcasting;field programmable gate arrays;satellite communication;synchronisation;turbo codes;DVB-RCS2;Xilinx FPGA;digital video broadcasting;feedforward carrier synchronization;frequency-phase synchronization methods;pilotless bursts;return channel via satellite;turbo code decoder;Decoding;Digital video broadcasting;Frequency estimation;Hardware;Standards;Synchronization;Turbo codes;Digital video broadcasting;field programmable gate arrays;frequency estimation;iterative methods;phase estimation}
+}
+
+@Article{aliwas_13,
+  Title                    = {{A Code-Aided Synchronization IP Core for Iterative Channel Decoders}},
+  Author                   = {Imran Ali and Uwe Wasenm\"{u}ller and Norbert Wehn},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2013},
+
+  Month                    = {Sep},
+  Pages                    = {137-142},
+  Volume                   = {11},
+
+  Address                  = {Miltenberg, Germany},
+  Booktitle                = {Proc. Kleinheubacher Tagung},
+  Owner                    = {Imran},
+  Timestamp                = {2013.30.07}
+}
+
+@InProceedings{aliwas_13a,
+  Title                    = {{C}ode-aided {S}ynchronization with {QPSK}, 8-{PSK} and 16-{QAM} {M}odulations},
+  Author                   = {Ali, I. and Wasenm\"{u}ller, Uwe. and Wehn, N.},
+  Booktitle                = {19th IEEE Asia-Pacific Conference on Communications},
+  Year                     = {2013},
+
+  Address                  = {Bali, Indonesia},
+  Month                    = {Aug},
+  Pages                    = {561-566},
+
+  Doi                      = {10.1109/APCC.2013.6766011},
+  Keywords                 = {channel coding;decoding;iterative methods;parameter estimation;quadrature amplitude modulation;quadrature phase shift keying;quantisation (signal);synchronisation;turbo codes;16-QAM;8-PSK;QPSK;channel decoding;code-aided turbo synchronization;fixed-point representation;frequency offset;hardware implementation;parameter estimation;phase offset;pilot symbols;quadrature amplitude modulation;quadrature phase shift keying;quantization losses;signal-to-noise ratio;synchronization quality;turbo decoder;Decoding;Frequency modulation;Iterative decoding;Signal to noise ratio;Standards;Synchronization}
+}
+
+@InProceedings{alifar_08,
+  Title                    = {{A} single-{FPGA} multipath {MIMO} fading channel simulator},
+  Author                   = {Alimohammad, A. and Fard, S.F. and Cockburn, B.F. and Schlegel, C.},
+  Booktitle                = {Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on},
+  Year                     = {2008},
+  Month                    = may,
+  Pages                    = {308--311},
+
+  Abstract                 = {We present an accurate model for compact implementations of Rayleigh and Rician fading channels. Verification of the proposed fading simulator is performed by comparing the simulated statistics with those of the ideal reference models. A parameterizable field-programmable gate array (FPGA) implementation of the channel simulator is presented. The design is readily scalable to support multipath fading channels and multiple-input multiple-output (MIMO) systems. A 16-path fading channel, providing either Rician or Rayleigh fading, uses 41% of the configurable slices, 33% of the dedicated multipliers, and 32% of the on-chip block memories of a Xilinx Virtex-II Pro XC2VP100-6 FPGA while generating over 200 million complex- valued fading coefficients per second.},
+  Doi                      = {10.1109/ISCAS.2008.4541416},
+  File                     = {alifar_08.pdf:alifar_08.pdf:PDF},
+  Keywords                 = {MIMO},
+  Owner                    = {CdS},
+  Timestamp                = {2012.06.20}
+}
+
+@InProceedings{al-bag_12,
+  Title                    = {{A}rchitecture efficiency of application-specific processors: {A} 170{M}bit/s 0.644mm2 multi-standard turbo decoder},
+  Author                   = {Al-Khayat, R. and Baghdadi, A. and Jezequel, M.},
+  Booktitle                = {System on Chip (SoC), 2012 International Symposium on},
+  Year                     = {2012},
+  Month                    = {oct.},
+  Pages                    = {1 -7},
+
+  Doi                      = {10.1109/ISSoC.2012.6376368},
+  File                     = {al-bag_12.pdf:al-bag_12.pdf:PDF},
+  Keywords                 = {Digital video broadcasting;Logicgates;Slag;Standards;Throughput;WiMAX;3G mobile communication;CMOSintegrated circuits;WiMax;application specific integratedcircuits;decoding;instruction sets;microprocessor chips;turbocodes;3GPP LTE;ASIP-based turbo decoder;CMOS technology;DVB-RCS turbocodes;WiMAX;application-specific instruction-set processors;bit rate170 Mbit/s;extrinsic information exchange;instructionset;instruction-set based processors;multistandard turbodecoder;pipeline stages usage;rapid reconfiguration;turbo decodingapplication;ARP interleaver;ASIP;Architectureefficiency;DVB-RCS;LTE;Pipeline;QPP interleaver;SoC design;Turbocodes;WiMAX; }
+}
+
+@InProceedings{al-mur_11,
+  Title                    = {{A}rea and throughput optimized {ASIP} for multi-standard turbo decoding},
+  Author                   = {Al-Khayat, Rachid and Murugappa, Purushotham and Baghdadi, Amer and Jezequel, Michel},
+  Booktitle                = {Proc. 22nd IEEE Int Rapid System Prototyping (RSP) Symp},
+  Year                     = {2011},
+  Pages                    = {79--84},
+
+  Doi                      = {10.1109/RSP.2011.5929979},
+  File                     = {al-mur_11.pdf:al-mur_11.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@PhdThesis{Phdalles10,
+  Title                    = {{I}mplementation {A}spects of {A}dvanced {C}hannel {D}ecoding},
+  Author                   = {Matthias Alles},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2010},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.03.04}
+}
+
+@MastersThesis{MTalles06,
+  Title                    = {{Synthesisable IP Cores for Irregular LDPC Code Decoding Based on Highly Flexible Architecture Templates}},
+  Author                   = {M. Alles},
+  School                   = {Microelectronic Systems Design Reseach Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2006},
+  Month                    = mar,
+
+  File                     = {MTalles06.pdf:MTalles06.pdf:PDF},
+  Optnote                  = {Diplomarbeit},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{allber_09,
+  Title                    = {{A Synthesizable IP Core for WiMedia 1.5 UWB LDPC Code Decoding}},
+  Author                   = {Matthias Alles and Friedbert Berens and Norbert Wehn},
+  Booktitle                = {Proc. IEEE International Conference on Ultra-Wideband ICUWB 2009},
+  Year                     = {2009},
+
+  Address                  = {Vancouver, Canada},
+  Month                    = sep,
+  Pages                    = {597--601},
+
+  File                     = {allber_09.pdf:allber_09.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.27}
+}
+
+@InProceedings{allbra_07,
+  Title                    = {{A} {R}eliability-{A}ware {LDPC} {C}ode {D}ecoding {A}lgorithm},
+  Author                   = {M. Alles and T. Brack and N. Wehn},
+  Booktitle                = {Proc. VTC2007-Spring Vehicular Technology Conference IEEE 65th},
+  Year                     = {2007},
+
+  Address                  = {Dublin, Ireland},
+  Month                    = apr,
+  Pages                    = {1544--1548},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- LDPC, AIS, AG},
+  File                     = {allbra_07.pdf:allbra_07.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{allleh_09,
+  Title                    = {{A} {R}apid {P}rototyping {E}nvironment for {ASIP} {V}alidation in {W}ireless {S}ystems},
+  Author                   = {Matthias Alles and Timo Lehnigk-Emden and Christian Brehm and Norbert Wehn},
+  Booktitle                = {Proc. edaWorkshop 09},
+  Year                     = {2009},
+
+  Address                  = {Dresden, Germany},
+  Month                    = may,
+  Pages                    = {43--48},
+
+  File                     = {allleh_09.pdf:allleh_09.pdf:PDF},
+  Keywords                 = {ASIP Turbo LDPC Validation AGWehn},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InProceedings{allleh_07,
+  Title                    = {{I}mplementation {I}ssues of {T}urbo {S}ynchronization with {D}uo-{B}inary {T}urbo {D}ecoding},
+  Author                   = {Alles, M. and Lehnigk-Emden, T. and Wasenmüller, U. and Wehn, N.},
+  Booktitle                = {Proc. IEEE 18th International Symposium on Personal, Indoor and Mobile Radio Communications PIMRC 2007},
+  Year                     = {2007},
+
+  Address                  = {Athens, Greece},
+  Month                    = sep,
+
+  Doi                      = {10.1109/PIMRC.2007.4394127},
+  File                     = {allleh_07.pdf:allleh_07.pdf:PDF},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.01.08}
+}
+
+@InProceedings{allvog_08,
+  Title                    = {{FlexiChaP: A Reconfigurable ASIP for Convolutional, Turbo, and LDPC Code Decoding}},
+  Author                   = {Matthias Alles and Timo Vogt and Norbert Wehn},
+  Booktitle                = {Proc. 5th International Symposium on Turbo Codes and Related Topics},
+  Year                     = {2008},
+
+  Address                  = {Lausanne, Switzerland},
+  Month                    = sep,
+  Pages                    = {84--89},
+
+  File                     = {allvog_08.pdf:allvog_08.pdf:PDF},
+  Keywords                 = {ASIP Turbo LDPC AGWehn},
+  Owner                    = {alles},
+  Timestamp                = {2008.09.25}
+}
+
+@InProceedings{al-elm_04a,
+  Title                    = {{L}ow-energy design of a 3{G}-compliant turbo decoder},
+  Author                   = {Al-Mohandes, I. A. and Elmasry, M. I. },
+  Booktitle                = {Proc. 2nd Annual IEEE Northeast Workshop on Circuits and Systems NEWCAS 2004},
+  Year                     = {2004},
+  Month                    = jun,
+  Pages                    = {153--156},
+
+  Doi                      = {10.1109/NEWCAS.2004.1359045},
+  File                     = {al-elm_04a.pdf:al-elm_04a.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{al-elm_04,
+  Title                    = {{A} low-power 5 {M}b/s turbo decoder for third-generation wireless terminals},
+  Author                   = {Al-Mohandes, I. and Elmasry, M.},
+  Booktitle                = {Proc. Canadian Conference on Electrical and Computer Engineering},
+  Year                     = {2004},
+  Month                    = may,
+  Pages                    = {2387--2390},
+  Volume                   = {4},
+
+  File                     = {al-elm_04.pdf:al-elm_04.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{al-cio_01,
+  Title                    = {{A Highly Efficient Domain-Programmable Parallel Architecture for Iterative LDPCC Decoding}},
+  Author                   = {G. Al-Rawi and J. Cioffi},
+  Booktitle                = {Proc. (ITCC '01)},
+  Year                     = {2001},
+
+  Address                  = {Las Vegas, USA},
+  Month                    = apr,
+  Pages                    = {569--577},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{al-cio_01a,
+  Title                    = {{Optimizing the mapping of Low-Density Parity-Check Codes on parallel decoding architectures}},
+  Author                   = {G. Al-Rawi and J. Cioffi and M. Horowitz},
+  Booktitle                = {Proc. (ITCC '01)},
+  Year                     = {2001},
+
+  Address                  = {Las Vegas, USA},
+  Month                    = apr,
+  Pages                    = {578--586},
+
+  File                     = {al-cio_01a.pdf:al-cio_01a.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{al-cio_01b,
+  Title                    = {{Optimizing Iterative Decoding of Low-Density Parity-Check Codes on Programmable Pipelined Parallel Architectures}},
+  Author                   = {G. Al-Rawi and J. Cioffi and R. Motwani and M. Horowitz},
+  Booktitle                = {Proc. 2001 Global Telecommunications Conference (GLOBECOM '01)},
+  Year                     = {2001},
+  Pages                    = {3012--3018},
+
+  File                     = {al-cio_01b.pdf:al-cio_01b.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{alsbha_11,
+  Title                    = {{T}he {T}ao of {S}ystems: {D}oing {N}othing {W}ell},
+  Author                   = {Sara Alspaugh and Arka Bhattacharya and David Culler and Randy Katz},
+  Year                     = {2011},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-17}
+}
+
+@TechReport{alt_07,
+  Title                    = {{C}onstellation {M}apper and {D}emapper for {W}i{MAX}},
+  Author                   = {Altera},
+  Year                     = {2007},
+
+  Address                  = {http://www.altera.com/literature/an/an439.pdf},
+  Month                    = {May},
+
+  Owner                    = {Imran},
+  Timestamp                = {2014.11.05}
+}
+
+@Article{alutse_16,
+  Title                    = {{O}verview of {S}elector {D}evices for 3-{D} {S}tackable {C}ross {P}oint {RRAM} {A}rrays},
+  Author                   = {R. Aluguri and T. Tseng},
+  Journal                  = {IEEE Journal of the Electron Devices Society},
+  Year                     = {2016},
+
+  Month                    = {Sept},
+  Number                   = {5},
+  Pages                    = {294-306},
+  Volume                   = {4},
+
+  Doi                      = {10.1109/JEDS.2016.2594190},
+  ISSN                     = {2168-6734},
+  Keywords                 = {resistive RAM;three-dimensional integrated circuits;cross point memory devices;mixed ionic-electronic conduction selector;threshold switch selector;metal-oxide based selector;silicon-based selector;1S1R devices;low program-erase voltages;sneak path problem;tunneling barrier;nonlinear resistive memory;valence modulated conductive oxide RRAM;hybrid RRAM cell;self-rectifying cells;complementary resistive cell;3D stackable cross point RRAM arrays;selector devices;Three-dimensional displays;Electrodes;Switches;Memory management;Leakage currents;Resistance;Cross bar RRAM;self-rectifying cells;selector devices},
+  Timestamp                = {2018-08-29}
+}
+
+@InProceedings{alvnep_09,
+  Title                    = {{D}etecting errors using multi-cycle invariance information},
+  Author                   = {Alves, N. and Nepal, K. and Dworak, J. and Bahar, R. I.},
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conference \& Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {791--796},
+
+  File                     = {alvnep_09.pdf:alvnep_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.01}
+}
+
+@InProceedings{amakno_10,
+  Title                    = {{H}ybrid {I}teration {C}ontrol on {LDPC} {D}ecoders},
+  Author                   = {Amador, E. and Knopp, R. and Rezard, V. and Pacalet, R.},
+  Booktitle                = {Wireless and Mobile Communications (ICWMC), 2010 6th International Conference on},
+  Year                     = {2010},
+  Pages                    = {102--106},
+
+  Doi                      = {10.1109/ICWMC.2010.45},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.11.24},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5629114}
+}
+
+@MastersThesis{MTamank15,
+  Title                    = {{A}ccelerating {B}ig {D}ata {S}elf-tuning {A}lgorithm to {F}ind {S}imilarity in {G}raphs},
+  Author                   = {De-Joy Amankwah},
+  School                   = {University of Kaiserslautern, Supervisor: N. Wehn, C. Brugger, C. De Schryver},
+  Year                     = {2015},
+  Month                    = Aug,
+  Type                     = {Master Thesis},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.23}
+}
+
+@InProceedings{amagom_17,
+  Title                    = {{M}itigating {R}ow {H}ammer attacks based on dummy cells in {DRAM}},
+  Author                   = {A. Amaya and H. Gomez and E. Roa},
+  Booktitle                = {2017 IEEE International Conference on Consumer Electronics (ICCE)},
+  Year                     = {2017},
+  Month                    = {Jan},
+  Pages                    = {442-443},
+
+  Doi                      = {10.1109/ICCE.2017.7889389},
+  Keywords                 = {CMOS memory circuits;DRAM chips;security;CMOS 64×64 memory array;DRAM memories;Row Hammer attacks;coupling noise;data corruption;dummy cells;Capacitors;Couplings;Discharges (electric);Leakage currents;Random access memory;Semiconductor device modeling;Standards},
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-03}
+}
+
+@Misc{awsaws18,
+  Title                    = {{AWS} {P}ricing: {H}ow does {AWS} pricing work?},
+
+  Author                   = {{Amazon Web Services (AWS)}},
+  HowPublished             = {Online: \url{https://aws.amazon.com/pricing/}},
+  Note                     = {Last access: 04 Jan. 2018},
+  Year                     = {2018},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.04},
+  Url                      = {https://aws.amazon.com/pricing/}
+}
+
+@Misc{awsamazon17,
+  Title                    = {{A}mazon {EC}2 {I}nstance {T}ypes},
+
+  Author                   = {{Amazon Web Services (AWS)}},
+  HowPublished             = {Online: \url{https://aws.amazon.com/ec2/instance-types/}},
+  Note                     = {last access: 15 Dec. 2017},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.11.02},
+  Url                      = {https://aws.amazon.com/ec2/instance-types/}
+}
+
+@Misc{awsofficial17,
+  Title                    = {{Official repository of the AWS EC2 FPGA Hardware and Software Development Kit (github repository)}},
+
+  Author                   = {{Amazon Web Services (AWS)}},
+  HowPublished             = {Online: \url{https://github.com/aws/aws-fpga}},
+  Note                     = {Last access: 05 Jan 2018},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.05}
+}
+
+@Article{amumas_09,
+  Title                    = {{M}itigation {T}echniques for {S}ingle-{E}vent-{I}nduced {C}harge {S}haring in a 90-nm {B}ulk {CMOS} {P}rocess},
+  Author                   = {Amusan, O. A. and Massengill, L. W. and Baze, M. P. and Bhuva, B. L. and Witulski, A. F. and Black, J. D. and Balasubramanian, A. and Casey, M. C. and Black, D. A. and Ahlbin, J. R. and Reed, R. A. and McCurdy, M. W. },
+  Journal                  = {Device and Materials Reliability, IEEE Transactions on},
+  Year                     = {2009},
+  Number                   = {2},
+  Pages                    = {311--317},
+  Volume                   = {9},
+
+  Doi                      = {10.1109/TDMR.2009.2019963},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{amumas_08,
+  Title                    = {{M}itigation techniques for single event induced charge sharing in a 90 nm bulk {CMOS} process},
+  Author                   = {Amusan, O. A. and Massengill, L. W. and Baze, M. P. and Bhuva, B. L. and Witulski, A. F. and Black, J. D. and Balasubramanian, A. and Casey, M. C. and Black, D. A. and Ahlbin, J. R. and Reed, R. A. and McCurdy, M. W. },
+  Booktitle                = {Proc. IEEE Int. Reliability Physics Symp. IRPS 2008},
+  Year                     = {2008},
+  Pages                    = {468--472},
+
+  Doi                      = {10.1109/RELPHY.2008.4558930},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@PhdThesis{an_10,
+  Title                    = {{C}omplete {VLSI} {I}mplementation of {I}mproved {L}ow {C}omplexity {C}hase {R}eed-{S}olomon {D}ecoders},
+  Author                   = {Wei An},
+  School                   = {Massachusetts Institute of Technology},
+  Year                     = {2010},
+  Month                    = {September},
+
+  File                     = {an_10.pdf:an_10.pdf:PDF},
+  Keywords                 = {ASD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {PhD zum Thema Implementeriung LCC auf ASIC, keine Paper von diesem Typ gefunden, nur diese Diss},
+  Timestamp                = {2011.07.27}
+}
+
+@Article{Anastasopoulos2001,
+  Title                    = {{A}daptive iterative detection for phase tracking in turbo-coded systems},
+  Author                   = {Anastasopoulos, A. and Chugg, K.M.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2001},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {2135-2144},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/26.974260},
+  ISSN                     = {0090-6778},
+  Keywords                 = {adaptive signal detection;concatenated codes;convolutional codes;decoding;demodulators;inverse problems;iterative methods;tracking;turbo codes;AID receivers;adaptive iterative detection;adaptive soft demodulator;adaptive soft inverse algorithms;adaptive soft-input soft-output demodulator;carrier-phase uncertainty;channel state information;decoding;parallel concatenated convolutional codes;parametric uncertainty;phase tracking;serial concatenated convolutional codes;turbo codes;Channel state information;Concatenated codes;Convolutional codes;Demodulation;Iterative algorithms;Iterative decoding;Maximum likelihood decoding;Phase detection;Turbo codes;Uncertainty},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.23}
+}
+
+@InProceedings{andmat_07,
+  Title                    = {{A} 1.9{G}b/s 358m{W} 16-to-256 {S}tate {R}econfigurable {V}iterbi {A}ccelerator in 90nm {CMOS}},
+  Author                   = {Anders, M. and Mathew, S. and Hsu, S. and Krishnamurthy, R. and Borkar, S.},
+  Booktitle                = {Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International},
+  Year                     = {2007},
+  Month                    = {feb.},
+  Pages                    = {256 -600},
+
+  Doi                      = {10.1109/ISSCC.2007.373391},
+  ISSN                     = {0193-6530},
+  Keywords                 = {CMOS process;CMOS technology;Counting circuits;Decoding;Flexible printed circuits;Polynomials;Power generation;Powermeasurement;Read-write memory;Viterbi algorithm;CMOS integrated circuits;Viterbi decoding;carry logic;coprocessors;microwaveintegrated circuits;1.3 V;1.9 Gbit/s;17 V;2.35 Gbit/s;3.8 GHz;358 mW;50 C;90 nm;dual-threshold voltage CMOS technology;programmable ring-buffer decoders;radix-4ripple-carry ACS circuits;reconfigurable Viterbi accelerator;reconfigurable path metric read/write control;tree-bitline traceback memory circuits;}
+}
+
+@InBook{andjaec_10,
+  Title                    = {{S}imulation of {S}quare-{R}oot {P}rocesses},
+  Author                   = {Andersen, Leif B.G. and Jäckel, Peter and Kahl, Christian},
+  Publisher                = {John Wiley \& Sons, Ltd},
+  Year                     = {2010},
+
+  Abstract                 = {We discuss methods for time discretization and simulation of square-root stochastic differential equations (SDEs), both in isolation (CIR (Cox–Ingersoll–Ross) process) and as part of vector SDEs modeling stochastic volatility (Heston model). Both exact and biased discretization methods are covered.},
+  Booktitle                = {Encyclopedia of Quantitative Finance},
+  Cds_grade                = {0},
+  Cds_keywords             = {Feller condition},
+  Doi                      = {10.1002/9780470061602.eqf13009},
+  File                     = {andjaec_10.pdf:andjaec_10.pdf:PDF},
+  ISBN                     = {9780470061602},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.11},
+  Url                      = {http://dx.doi.org/10.1002/9780470061602.eqf13009}
+}
+
+@InProceedings{andbai_90,
+  Title                    = {{LAPACK}: {A} portable linear algebra library for high-performance computers},
+  Author                   = {Anderson, Edward and Bai, Zhaojun and Dongarra, Jack and Greenbaum, A and McKenney, A and Du Croz, Jeremy and Hammerling, S and Demmel, James and Bischof, C and Sorensen, Danny},
+  Booktitle                = {Proceedings of the 1990 ACM/IEEE conference on Supercomputing},
+  Year                     = {1990},
+  Organization             = {IEEE Computer Society Press},
+  Pages                    = {2--11},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.24},
+  Url                      = {http://www.netlib.org/lapack}
+}
+
+@Article{andhla_98,
+  Title                    = {{Tailbiting MAP Decoders}},
+  Author                   = {Anderson, J. B. and Hladik, S. M.},
+  Journal                  = {IEEE Journal on Selected Areas in Communiations},
+  Year                     = {1998},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {297--302},
+  Volume                   = {16},
+
+  File                     = {andhla_98.pdf:andhla_98.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{andwid_03,
+  Title                    = {{U}niversal {O}ption {V}aluation {U}sing {Q}uadrature {M}ethods},
+  Author                   = {Andricopoulos, A.D. and Widdicks, M. and Duck, P.W. and Newton, D.P.},
+  Journal                  = {Journal of Financial Economics},
+  Year                     = {2003},
+  Number                   = {3},
+  Pages                    = {447--471},
+  Volume                   = {67},
+
+  Cds_grade                = {0},
+  File                     = {andwid_03.pdf:andwid_03.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Elsevier},
+  Timestamp                = {2012.02.14}
+}
+
+@InProceedings{angnic_00,
+  Title                    = {{C}ost reduction and evaluation of a temporary faults detecting technique},
+  Author                   = {Anghel, L. and Nicolaidis, M.},
+  Booktitle                = {Proc. Design Automation and Test in Europe Conference and Exhibition 2000},
+  Year                     = {2000},
+  Month                    = mar,
+  Pages                    = {591--598},
+
+  Doi                      = {10.1109/DATE.2000.840845},
+  File                     = {angnic_00.pdf:angnic_00.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{anigra_10a,
+  Title                    = {{U}ltra {L}ow {P}ower {RF} {T}ransceiver {A}rchitecture for {I}n-body {C}ommunication {S}ystem},
+  Author                   = {M. Anis and G. Grau and N. Wehn},
+  Booktitle                = {In Proc. IEEE 2010 Radio and Wireless Symposium},
+  Year                     = {2010},
+
+  Address                  = {New Orleans, USA},
+  Month                    = jan,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@InProceedings{anigra_10,
+  Title                    = {{L}ow {P}ower {S}elf-quenched {S}uper-regenerative {I}mpulse-{FM}-{UWB} {T}ransceiver for {WBAN}},
+  Author                   = {M. Anis and G. Grau and N. Wehn.},
+  Booktitle                = {In Proc. IEEE 2010 Radio and Wireless Symposium},
+  Year                     = {2010},
+
+  Address                  = {New Orleans, USA},
+  Month                    = jan,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@InProceedings{aniiln_08,
+  Title                    = {{3.1 GHz to 6GHz UWB Pulse radio transceiver front end based on super-regeneration approach}},
+  Author                   = {M. Anis and T. Ilnseher and R. Tielert and N. Wehn},
+  Booktitle                = {Proc. Digest of Technical Papers. International Conference on Consumer Electronics ICCE 2008},
+  Year                     = {2008},
+
+  Address                  = {Las Vegas, USA},
+  Month                    = jan,
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.31}
+}
+
+@InProceedings{aniort_10,
+  Title                    = {{UWB} {I}mpulse {T}ransmitter and 402-to-405{MH}z {S}uper-{R}egenerative {R}eceiver for {M}edical {I}mplant {D}evices},
+  Author                   = {M. Anis and M. Ortmanns and N. Wehn},
+  Booktitle                = {In Proc. IEEE International Symposium on Circuits and Systems},
+  Year                     = {2010},
+
+  Address                  = {Paris, France},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@InProceedings{aniort_10a,
+  Title                    = {3.6-to-4.4 {GH}z {UWB} {I}mpulse {T}ransmitter and 402-to-405{MH}z {S}uper-regenerative {R}eceiver for {M}edical {I}mplant {D}evices},
+  Author                   = {M. Anis and M. Ortmanns and N. Wehn},
+  Booktitle                = {In Proc. 11th annual IEEE Wireless and Microwave Technology (WAMI) Conference},
+  Year                     = {2010},
+
+  Address                  = {Melbourne Beach , Florida, USA},
+  Month                    = apr,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@InProceedings{aniort_10b,
+  Title                    = {{L}ow {P}ower {S}uper-regenerative {I}mpulse-{FM}-{UWB} {T}ransceiver for {WBAN}},
+  Author                   = {M. Anis and M. Ortmanns and N. Wehn},
+  Booktitle                = {In Proc. 11th annual IEEE Wireless and Microwave Technology (WAMI) Conference},
+  Year                     = {2010},
+
+  Address                  = {Melbourne Beach , Florida, USA},
+  Month                    = apr,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@InProceedings{aniort_10c,
+  Title                    = {{L}ow {P}ower {S}elf-{Q}uenched {S}uper-{R}egenerative {I}mpulse-{FM}-{UWB} {T}ransceiver for {WBAN}},
+  Author                   = {M. Anis and M. Ortmanns and N. Wehn},
+  Booktitle                = {In Proc. IEEE International Symposium on VLSI Design, Automation \& Test (VLSI-DAT)},
+  Year                     = {2010},
+
+  Address                  = {Hsinchu, Taiwan},
+  Month                    = apr,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@InProceedings{anitie_08,
+  Title                    = {{3.1-to-7GHz UWB Impulse Radio Transceiver Front-End Based on Statistical Correlation Technique}},
+  Author                   = {Muhammad Anis and Reinhard Tielert and Norbert Wehn},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2008},
+  Year                     = {2008},
+
+  Address                  = {Seattle, USA},
+  Month                    = may,
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.31}
+}
+
+@InProceedings{anitie_08a,
+  Title                    = {{Fully Integrated Super-Regenerative Bandpass Filters For 3.1-to-7GHz Multiband UWB System}},
+  Author                   = {M. Anis and R. Tielert and N. Wehn},
+  Booktitle                = {Proc. IEEE International Symposium on VLSI Design, Automation and Test VLSI-DAT 2008},
+  Year                     = {2008},
+
+  Address                  = {Hsinchu, Taiwan},
+  Month                    = apr,
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.31}
+}
+
+@InProceedings{anitie_08b,
+  Title                    = {{F}ully integrated self-quenched super-regenerative {UWB} impulse detector},
+  Author                   = {Anis, M. and Tielert, R. and Wehn, N. },
+  Booktitle                = {Proc. 3rd International Symposium on Wireless Pervasive Computing ISWPC 2008},
+  Year                     = {2008},
+  Month                    = may,
+  Pages                    = {773--775},
+
+  Doi                      = {10.1109/ISWPC.2008.4556315},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{anitie_08c,
+  Title                    = {{S}uper-regenerative {UWB} impulse detector with synchronized quenching mechanism},
+  Author                   = {Anis, M. and Tielert, R. and Wehn, N.},
+  Booktitle                = {Proc. 34th European Solid-State Circuits Conference ESSCIRC 2008},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {390--393},
+
+  Doi                      = {10.1109/ESSCIRC.2008.4681874},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{anitie_08d,
+  Title                    = {{L}ow power complementary-colpitts self-quenched super-regenerative ultra-wideband ({UWB}) bandpass filter in {CMOS} technology},
+  Author                   = {Anis, M. and Tielert, R. and Wehn, N.},
+  Booktitle                = {Proc. IEEE MTT-S International Microwave Symposium Digest},
+  Year                     = {2008},
+  Month                    = jun,
+  Pages                    = {1047--1049},
+
+  Doi                      = {10.1109/MWSYM.2008.4633015},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{anitie_08e,
+  Title                    = {{A} 400u{W} 10{M}bits/s {CMOS} {UWB} impulse radio transmitter for wireless sensor networks},
+  Author                   = {Anis, M. and Tielert, R. and Wehn, N.},
+  Booktitle                = {Proc. IEEE International Conference on Ultra-Wideband ICUWB 2008},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {33--35},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/ICUWB.2008.4653345},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{anitie_08f,
+  Title                    = {{A} 10{M}b/s 2.6m{W} 6-to-10{GH}z {UWB} impulse transceiver},
+  Author                   = {Anis, M. and Tielert, R. and Wehn, N.},
+  Booktitle                = {Proc. IEEE International Conference on Ultra-Wideband ICUWB 2008},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {129--132},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ICUWB.2008.4653301},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{anitie_08g,
+  Title                    = {{F}ully integrated super-regenerative bandpass filters for 3.1-to-7{GH}z multiband {UWB} system},
+  Author                   = {Anis, M. and Tielert, R. and Wehn, N.},
+  Booktitle                = {Proc. IEEE International Symposium on VLSI Design, Automation and Test VLSI-DAT 2008},
+  Year                     = {2008},
+  Month                    = apr,
+  Pages                    = {204--207},
+
+  Doi                      = {10.1109/VDAT.2008.4542448},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{anitie_07,
+  Title                    = {{Low Power Ultra-Wide-Bandpass Super-regenerative Filter}},
+  Author                   = {Muhammad Anis and Reinhard Tielert and Norbert Wehn},
+  Booktitle                = {Proc. 14th IEEE Symposium on Communications and Vehicular Technology in the Benelux},
+  Year                     = {2007},
+
+  Address                  = {Delft, Netherlands},
+  Month                    = nov,
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.30}
+}
+
+@InProceedings{aniton_08,
+  Title                    = {{A} 3m{W} 1{GH}z ultra-wide-bandpass super-regenerative filter},
+  Author                   = {Anis, M. and Tontisirin, S. and Tielert, R. and Wehn, N. },
+  Booktitle                = {Proc. IEEE Radio and Wireless Symposium},
+  Year                     = {2008},
+  Month                    = jan,
+  Pages                    = {455--458},
+
+  Doi                      = {10.1109/RWS.2008.4463527},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@Conference{aniweh_08,
+  Title                    = {{F}ully {I}ntegrated {M}ulti-channel {UWB} {I}mpulse {G}enerator and {D}etector},
+  Author                   = {M. Anis and N. Wehn},
+  Booktitle                = {International Solid-State Circuits Conference (ISSCC 2008) Student Forum},
+  Year                     = {2008},
+
+  Address                  = {San Francisco, USA},
+  Month                    = feb,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@InProceedings{aniort_11,
+  Title                    = {{A} 2.5m{W} 2{M}b/s {F}ully {I}ntegrated {I}mpulse-{FM}-{UWB} {T}ransceiver in 0.18$\mu$m {CMOS}},
+  Author                   = {S. Anis and M. Ortmanns and N. Wehn},
+  Booktitle                = {Proc. International Microwave Symposium for 2011},
+  Year                     = {2011},
+
+  Address                  = {Baltimore, Maryland},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.05.16}
+}
+
+@Unpublished{Anson2012,
+  Title                    = {{D}esign {E}xploration of {Q}uadrature {M}ethods in {O}ption {P}ricing},
+  Author                   = {H. T. Tse Anson and David Thomas and Wayne Luk},
+  Note                     = {Accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2012},
+
+  Cds_grade                = {0},
+  File                     = {anstho_12unpublished.pdf:anstho_12unpublished.pdf:PDF},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.14}
+}
+
+@InProceedings{olijun_18,
+  Title                    = {{E}nabling {C}ontinuous {S}oftware {E}ngineering for {E}mbedded {S}ystems {A}rchitectures with {V}irtual {P}rototypes},
+  Author                   = {Antonino, Pablo Oliveira and Jung, Matthias and Morgenstern, Andreas and Fa{\ss}nacht, Florian and Bauer, Thomas and Bachorek, Adam and Kuhn, Thomas and Nakagawa, Elisa Yumi},
+  Booktitle                = {Software Architecture},
+  Year                     = {2018},
+
+  Address                  = {Cham},
+  Editor                   = {Cuesta, Carlos E.
+and Garlan, David
+and P{\'e}rez, Jennifer},
+  Pages                    = {115--130},
+  Publisher                = {Springer International Publishing},
+
+  Abstract                 = {Continuous software engineering aims at orchestrating engineering knowledge from various disciplines in order to deal with the rapid changes within the ecosystems of which software-based systems are part of. The literature claims that one means to ensure these prompt responses is to incorporate virtual prototypes of the system as early as possible in the development process, such that requirements and architecture decisions are verified early and continuously by means of simulations. Despite the maturity of practices for designing and assessing architectures, as well as for virtual prototyping, it is still not clear how to jointly consider the practices from these disciplines within development processes, in order to address the dynamics imposed by continuous software engineering. In this regard, we discuss in this paper how to orchestrate architecture drivers and design specification techniques with virtual prototypes, to address the demands of continuous software engineering in development processes. Our proposals are based on experiences from research and industry projects in various domains such as automotive, agriculture, construction, and medical devices.},
+  ISBN                     = {978-3-030-00761-4},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-24}
+}
+
+@TechReport{AntwerpSpace,
+  Title                    = {{Bandwidth Efficient Burst Mode Demodulator: BMD-V2}},
+  Author                   = {{Antwerp Space}},
+
+  Address                  = {http://www.antwerpspace.be/sites/default/files/products/as-spe-110154-01-01-bmd.pdf},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.02.02}
+}
+
+@Article{app_13,
+  Title                    = {{P}seudorandom {G}enerators with {L}ong {S}tretch and {L}ow {L}ocality from {R}andom {L}ocal {O}ne-{W}ay {F}unctions},
+  Author                   = {Applebaum, Benny},
+  Journal                  = {SIAM Journal on Computing},
+  Year                     = {2013},
+  Number                   = {5},
+  Pages                    = {2008-2037},
+  Volume                   = {42},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-25}
+}
+
+@Article{arakas_76,
+  Title                    = {{S}ome decision problems related to the reachability problem for {P}etri nets},
+  Author                   = {Toshiro Araki and Tadao Kasami},
+  Journal                  = {Theoretical Computer Science},
+  Year                     = {1976},
+  Number                   = {1},
+  Pages                    = {85 - 104},
+  Volume                   = {3},
+
+  Doi                      = {http://dx.doi.org/10.1016/0304-3975(76)90067-0},
+  ISSN                     = {0304-3975},
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-27},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/0304397576900670}
+}
+
+@Article{araamo_07,
+  Title                    = {{S}implified {LLR}s for the {D}ecoding of {S}ingle {P}arity {C}heck {T}urbo {P}roduct {C}odes {T}ransmitted {U}sing 16{QAM}},
+  Author                   = {Maher Arar and Claude D Amours and Abbas Yongacoglu},
+  Journal                  = {Research Letters in Communications},
+  Year                     = {2007},
+  Number                   = {53517},
+  Pages                    = {4},
+
+  Doi                      = {10.1155/2007/53517},
+  Owner                    = {Imran},
+  Timestamp                = {2014.11.13}
+}
+
+@Article{aranic_15,
+  Title                    = {{E}lectromagnetic harvester for lateral vibration in rotating machines},
+  Author                   = {Marcus Vinícius Vitoratti de Araujo and Rodrigo Nicoletti},
+  Journal                  = {Mechanical Systems and Signal Processing},
+  Year                     = {2015},
+  Pages                    = {685 - 699},
+  Volume                   = {52-53},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {DEARAUJO2015685},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {https://doi.org/10.1016/j.ymssp.2014.07.025},
+  ISSN                     = {0888-3270},
+  Keywords                 = {TCS},
+  Keywords_original        = {Energy harvesting, Rotor dynamics, Electromagnetics, Lateral vibration},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S088832701400315X}
+}
+
+@Electronic{ardbri_10,
+  Title                    = {“{M}ore-than-{M}oore” {W}hite {P}aper},
+  Author                   = {Arden, Wolfgang and Brillou{\"e}t, Michel and Cogez, Patrick and Graef, Mart and Huizing, Bert and Mahnkopf, Reinhard},
+  HowPublished             = {\url{http://public.itrs.net/Links/2010ITRS/IRC-ITRS-MtM-v2%203.pdf}},
+  Language                 = {en},
+  Note                     = {last access 2014-06-27},
+  Url                      = {\url{http://public.itrs.net/Links/2010ITRS/IRC-ITRS-MtM-v2%203.pdf}},
+  Year                     = {2010},
+
+  Cds_grade                = {0},
+  File                     = {ardbri_10.pdf:ardbri_10.pdf:PDF},
+  Journal                  = {International Technical Roadmap for Semiconductors (ITRS)},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.27}
+}
+
+@Article{arddav_11,
+  Title                    = {{J}ump-{D}iffusion {C}alibration {U}sing {D}ifferential {E}volution},
+  Author                   = {Ardia, David and David, Juan and Arango, Ospina and G{\'o}mez, Norman Diego Giraldo},
+  Journal                  = {Wilmott},
+  Year                     = {2011},
+  Number                   = {55},
+  Pages                    = {76--79},
+  Volume                   = {2011},
+
+  Owner                    = {Brugger},
+  Publisher                = {Wiley Online Library},
+  Timestamp                = {2014.12.30}
+}
+
+@Article{ari_11,
+  Title                    = {{S}ystematic {P}olar {C}oding},
+  Author                   = {E. Arikan},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2011},
+
+  Month                    = {August},
+  Number                   = {8},
+  Pages                    = {860-862},
+  Volume                   = {15},
+
+  Doi                      = {10.1109/LCOMM.2011.061611.110862},
+  ISSN                     = {1089-7798},
+  Keywords                 = {binary codes;decoding;error statistics;linear codes;bit error rate performance;decoding methods;encoding methods;frame error rate;nonsystematic linear block codes;nonsystematic polar coding;systematic polar coding;Binary phase shift keying;Bit error rate;Channel coding;Complexity theory;Decoding;Systematics;Polar codes;error propagation;successive cancellation decoding;systematic polar codes},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{ari_09,
+  Title                    = {{C}hannel {P}olarization: {A} {M}ethod for {C}onstructing {C}apacity-{A}chieving {C}odes for {S}ymmetric {B}inary-{I}nput {M}emoryless {C}hannels},
+  Author                   = {E. Arikan},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2009},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {3051-3073},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TIT.2009.2021379},
+  File                     = {ari_09.pdf:ari_09.pdf:PDF},
+  ISSN                     = {0018-9448},
+  Keywords                 = {binary codes;channel capacity;channel coding;decoding;memoryless systems;probability;channel capacity;channel coding;channel polarization;code sequence;polar codes;probability;successive cancellation decoding algorithm;symmetric binary-input memoryless channel;Capacity planning;Channel capacity;Channel coding;Codes;Councils;Decoding;Information theory;Memoryless systems;Noise cancellation;Polarization;Capacity-achieving codes;Plotkin construction;Reed– Muller (RM) codes;channel capacity;channel polarization;polar codes;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2017-03-28}
+}
+
+@InProceedings{ari_08,
+  Title                    = {{C}hannel polarization: {A} method for constructing capacity-achieving codes},
+  Author                   = {E. Arikan},
+  Booktitle                = {Information Theory, 2008. ISIT 2008. IEEE International Symposium on},
+  Year                     = {2008},
+  Month                    = {July},
+  Pages                    = {1173-1177},
+
+  Doi                      = {10.1109/ISIT.2008.4595172},
+  Keywords                 = {binary codes;binary sequences;block codes;channel capacity;channel coding;computational complexity;decoding;discrete systems;memoryless systems;probability;set theory;symmetry;binary-input discrete memoryless channel coding;block decoding error;channel polarization;code sequence;computational complexity;polar codes;probability;symmetric capacity;Channel capacity;Channel coding;Codes;Decoding;Memoryless systems;Polarization},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Misc{aramba,
+  Title                    = {{AMBA} {S}pecification, rev. 2.0, {M}ay 1999},
+
+  Author                   = {{ARM}},
+  HowPublished             = {{{http://www.arm.com}}},
+
+  Key                      = {ARM},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{ARM,
+  Title                    = {{AMBA} {S}pecification, rev. 2.0, {M}ay 1999},
+
+  Author                   = {{ARM}},
+  HowPublished             = {{{http://www.arm.com}}},
+
+  Key                      = {ARM},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{ARMa,
+  Title                    = {{AMBA} {O}pen {S}pecifications {R}evision 4},
+
+  Author                   = {ARM},
+  HowPublished             = {http://www.arm.com/products/system-ip/amba/amba-open-specifications.php},
+
+  Key                      = {ARM},
+  Owner                    = {CdS},
+  Timestamp                = {2012.09.12}
+}
+
+@Misc{axi4,
+  Title                    = {{AMBA} {O}pen {S}pecifications {R}evision 4},
+
+  Author                   = {ARM},
+  HowPublished             = {\url{http://www.arm.com/products/system-ip/amba/amba-open-specifications.php}},
+  Note                     = {last access 2014-07-02},
+
+  Key                      = {ARM},
+  Owner                    = {CdS},
+  Timestamp                = {2012.09.12}
+}
+
+@Misc{aramba12,
+  Title                    = {{AMBA AXI4-Stream Protocol Specification}},
+
+  Author                   = {{ARM Ltd.}},
+  Year                     = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.10.04},
+  Url                      = {http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022d/index.html}
+}
+
+@Misc{ARM2012,
+  Title                    = {{AMBA AXI4-Stream Protocol Specification}},
+
+  Author                   = {{ARM Ltd.}},
+  Year                     = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.10.04},
+  Url                      = {http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022d/index.html}
+}
+
+@InProceedings{armbae_06,
+  Title                    = {{HPC} benchmarking and performance evaluation with realistic applications},
+  Author                   = {Armstrong, Brian and Bae, Hansang and Eigenmann, Rudolf and Saied, Faisal and Sayeed, Mohamed and Zheng, Yili},
+  Booktitle                = {SPEC benchmarking workshop},
+  Year                     = {2006},
+
+  Address                  = {University of Texas, Austin, USA},
+  Month                    = jan,
+
+  Cds_grade                = {0},
+  Cds_keywords             = {HPC, benchmarking},
+  File                     = {armbae_06.pdf:armbae_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2015-04-22}
+}
+
+@InProceedings{arnfet_10,
+  Title                    = {{P}ower {A}ware {H}eterogeneous {MPS}o{C} with {D}ynamic {T}ask {S}cheduling and {I}ncreased {D}ata {L}ocality for {M}ultiple {A}pplications},
+  Author                   = {Oliver Arnold and Gerhard Fettweis},
+  Booktitle                = {Embedded Computer Systems (SAMOS), 2010 International Conference on},
+  Year                     = {2010},
+  Month                    = jul,
+  Pages                    = {110 -117},
+
+  Abstract                 = {A new heterogeneous multiprocessor system with dynamic memory and power management for improved performance and power consumption is presented. Increased data locality is automatically revealed leading to enhanced memory access capabilities. Several applications can run in parallel sharing processing elements, memories as well as the interconnection network. Real time constraints are regarded by prioritization of processing element allocation, scheduling and data transfers. Scheduling and allocation is done dynamically according to runtime data dependency checking. We are able to show that execution times, bandwidth demands and power consumption are decreased. A tool flow is introduced for an easy generation of the hardware platform and software binaries for cycle accurate simulations. Further newly developed tools are available for power analysis, data transfer observation and task execution visualization.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ICSAMOS.2010.5642075},
+  File                     = {arnfet_10.pdf:arnfet_10.pdf:PDF},
+  Keywords                 = {MPSoC},
+  Owner                    = {CdS},
+  Timestamp                = {2010.12.01}
+}
+
+@Article{arorav_06,
+  Title                    = {{H}ardware-assisted run-time monitoring for secure program execution on embedded processors},
+  Author                   = {Arora, D. and Ravi, S. and Raghunathan, A. and Jha, N. K.},
+  Journal                  = {IEEE Transactions on VLSI Systems},
+  Year                     = {2006},
+  Number                   = {12},
+  Pages                    = {1295--1308},
+  Volume                   = {14},
+
+  Address                  = {Washington, DC, USA},
+  Publisher                = {IEEE Computer Society}
+}
+
+@InProceedings{asatah_05,
+  Title                    = {{S}oft error mitigation for {SRAM}-based {FPGA}s},
+  Author                   = {Asadi, G.-H. and Tahoori, M. B. },
+  Booktitle                = {Proc. 23rd IEEE VLSI Test Symp},
+  Year                     = {2005},
+  Pages                    = {207--212},
+
+  Doi                      = {10.1109/VTS.2005.75},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{asatah_07,
+  Title                    = {{A}nalytical {T}echniques for {S}oft {E}rror {R}ate {M}odeling and {M}itigation of {FPGA}-{B}ased {D}esigns},
+  Author                   = {Asadi, H. and Tahoori, M. B. },
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2007},
+  Number                   = {12},
+  Pages                    = {1320--1331},
+  Volume                   = {15},
+
+  Doi                      = {10.1109/TVLSI.2007.909795},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@TechReport{asabod_06,
+  Title                    = {{T}he {L}andscape of {P}arallel {C}omputing {R}esearch: {A} {V}iew from {B}erkeley},
+  Author                   = {Krste Asanovíc and Rastislav Bodik and Bryan Catanzaro and Joseph Gebis and Parry Husbands and Kurt Keutzer and David Patterson and William Plishker and John Shalf and Samuel Williams and Katherine Yelick},
+  Institution              = {Technical Report UCB/EECS-2006-183, EECS Department, University of California, Berkeley},
+  Year                     = {2006},
+  Month                    = dec,
+
+  Abstract                 = {The recent switch to parallel microprocessors is a milestone in the history of computing.
+Industry has laid out a roadmap for multicore designs that preserves the programming
+paradigm of the past via binary compatibility and cache coherence. Conventional wisdom
+is now to double the number of cores on a chip with each silicon generation.
+A multidisciplinary group of Berkeley researchers met nearly two years to discuss this
+change. Our view is that this evolutionary approach to parallel hardware and software
+may work from 2 or 8 processor systems, but is likely to face diminishing returns as 16
+and 32 processor systems are realized, just as returns fell with greater instruction-level
+parallelism.
+We believe that much can be learned by examining the success of parallelism at the
+extremes of the computing spectrum, namely embedded computing and high performance
+computing. This led us to frame the parallel landscape with seven questions, and to
+recommend the following:
+· The overarching goal should be to make it easy to write programs that execute
+efficiently on highly parallel computing systems
+· The target should be 1000s of cores per chip, as these chips are built from
+processing elements that are the most efficient in MIPS (Million Instructions per
+Second) per watt, MIPS per area of silicon, and MIPS per development dollar.
+· Instead of traditional benchmarks, use 13 “Dwarfs” to design and evaluate parallel
+programming models and architectures. (A dwarf is an algorithmic method that
+captures a pattern of computation and communication.)
+· “Autotuners” should play a larger role than conventional compilers in translating
+parallel programs.
+· To maximize programmer productivity, future programming models must be
+more human-centric than the conventional focus on hardware or applications.
+· To be successful, programming models should be independent of the number of
+processors.
+· To maximize application efficiency, programming models should support a wide
+range of data types and successful models of parallelism: task-level parallelism,
+word-level parallelism, and bit-level parallelism.
+The Landscape of Parallel Computing Research: A View From Berkeley
+2
+· Architects should not include features that significantly affect performance or
+energy if programmers cannot accurately measure their impact via performance
+counters and energy counters.
+· Traditional operating systems will be deconstructed and operating system
+functionality will be orchestrated using libraries and virtual machines.
+· To explore the design space rapidly, use system emulators based on Field
+Programmable Gate Arrays (FPGAs) that are highly scalable and low cost.
+Since real world applications are naturally parallel and hardware is naturally parallel,
+what we need is a programming model, system software, and a supporting architecture
+that are naturally parallel. Researchers have the rare opportunity to re-invent these
+cornerstones of computing, provided they simplify the efficient programming of highly
+parallel systems.},
+  Cds_grade                = {4},
+  Cds_keywords             = {computer architecture, Berkeley, methodology, Golden-Gate-Bridge model, dwarfs},
+  File                     = {asabod_06.pdf:asabod_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24},
+  Url                      = {\url{http://www.cs.berkeley.edu/~krste/papers/BerkeleyView.pdf}}
+}
+
+@Article{asabod_09,
+  Title                    = {{A} {V}iew of the {P}arallel {C}omputing {L}andscape},
+  Author                   = {Krste Asanovic and Rastislav Bodik and James Demmel and Tony Keaveny and Kurt Keutzer and John Kubiatowicz and Nelson Morgan and David Patterson and Koushik Sen and John Wawrzynek and David Wessel and Katherine Yelick},
+  Journal                  = {Commun. ACM},
+  Year                     = {2009},
+
+  Month                    = {Oct.},
+  Number                   = {10},
+  Pages                    = {56--67},
+  Volume                   = {52},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.04}
+}
+
+@Book{asc_89,
+  Title                    = {{G}eschichte der {N}achrichtentechnik},
+  Author                   = {Volker Aschoff},
+  Publisher                = {Springer Verlag},
+  Year                     = {1989},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.07.27}
+}
+
+@InProceedings{asgliu_08,
+  Title                    = {{D}ual standard re-configurable hardware interleaver for turbo decoding},
+  Author                   = {Asghar, R. and Liu, D. },
+  Booktitle                = {Proc. 3rd International Symposium on Wireless Pervasive Computing ISWPC 2008},
+  Year                     = {2008},
+  Month                    = may,
+  Pages                    = {768--772},
+
+  Doi                      = {10.1109/ISWPC.2008.4556314},
+  File                     = {asgliu_08.pdf:asgliu_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.12}
+}
+
+@Article{asgwu_10,
+  Title                    = {{M}emory {C}onflict {A}nalysis and {I}mplementation of a {R}e-configurable {I}nterleaver {A}rchitecture {S}upporting {U}nified {P}arallel {T}urbo {D}ecoding},
+  Author                   = {Rizwan Asghar and Di Wu and Johan Eilert and Dake Liu},
+  Journal                  = {Journal of Signal Processing Systems},
+  Year                     = {2010},
+  Pages                    = {15-29},
+  Volume                   = {60},
+
+  File                     = {asgwu_10.pdf:asgwu_10.pdf:PDF},
+  ISSN                     = {1939-8018},
+  Issue                    = {1},
+  Keyword                  = {Electrical Engineering},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Publisher                = {Springer New York},
+  Timestamp                = {2010.11.11}
+}
+
+@Book{ash_02,
+  Title                    = {{T}he {D}esigner's {G}uide {T}o {VHDL}},
+  Author                   = {Peter J. Ashenden},
+  Publisher                = {Morgan Kaufmann Publishers Inc.},
+  Year                     = {2002},
+  Edition                  = {2nd},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {VHDL, programming, design, Implementation},
+  Cds_read                 = {2008-10},
+  Date-added               = {2007-12-10 13:08:25 +0100},
+  Date-modified            = {2008-07-10 10:26:36 +0200},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Article{ashkra_04,
+  Title                    = {{E}xtrinsic information transfer functions: model and erasure channel properties},
+  Author                   = {Ashikhmin, A. and Kramer, G. and ten Brink, S.},
+  Journal                  = {Information Theory, IEEE Transactions on},
+  Year                     = {2004},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {2657--2673},
+  Volume                   = {50},
+
+  Doi                      = {10.1109/TIT.2004.836693},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{ashkra_02,
+  Title                    = {{C}ode rate and the area under extrinsic information transfer curves},
+  Author                   = {Ashikhmin, A. and Kramer, G. and ten Brink, S.},
+  Booktitle                = {Information Theory, 2002. Proceedings. 2002 IEEE International Symposium on},
+  Year                     = {2002},
+  Pages                    = {115},
+
+  Doi                      = {10.1109/ISIT.2002.1023387},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Electronic{ita_14,
+  Title                    = {{I}nfiniband},
+  Author                   = {I.T. Association},
+  Url                      = {http://www.infinibandta.org},
+  Year                     = {2014},
+
+  Owner                    = {Schlaefer},
+  Timestamp                = {2014.05.22}
+}
+
+@InProceedings{atlkum_05,
+  Title                    = {{E}nergy efficient architectures for the log-{MAP} decoder through intelligent memory usage},
+  Author                   = {Indrajit Atluri and Kumaraswamy, A. K. and Chouliaras, V. A.},
+  Booktitle                = {Proc. IEEE Computer Society Annual Symp. VLSI},
+  Year                     = {2005},
+  Pages                    = {263--265},
+
+  Doi                      = {10.1109/ISVLSI.2005.29},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@Misc{atmel,
+  Title                    = {http://www.atmel.com/},
+
+  Author                   = {Atmel},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://www.atmel.com/}
+}
+
+@Book{Attaway2009,
+  Title                    = {{Matlab: A Practical Introduction to Programming and Problem Solving}},
+  Author                   = {Stormy Attaway},
+  Publisher                = {Elsevier},
+  Year                     = {2009}
+}
+
+@InProceedings{auebac_12,
+  Title                    = {{A} {C}ompiler and {R}untime for {H}eterogeneous {C}omputing},
+  Author                   = {Auerbach, Joshua and Bacon, David F. and Burcea, Ioana and Cheng, Perry and Fink, Stephen J. and Rabbah, Rodric and Shukla, Sunil},
+  Booktitle                = {Proceedings of the 49th Annual Design Automation Conference},
+  Year                     = {2012},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {271--276},
+  Publisher                = {ACM},
+  Series                   = {DAC '12},
+
+  Acmid                    = {2228411},
+  Doi                      = {10.1145/2228360.2228411},
+  ISBN                     = {978-1-4503-1199-1},
+  Keywords                 = {FPGA, GPU, Java, heterogeneous, streaming},
+  Location                 = {San Francisco, California},
+  Numpages                 = {6},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://doi.acm.org/10.1145/2228360.2228411}
+}
+
+@InProceedings{auscha_12,
+  Title                    = {{S}taged {M}emory {S}cheduling: {A}chieving {H}igh {P}erformance and {S}calability in {H}eterogeneous {S}ystems},
+  Author                   = {Ausavarungnirun, Rachata and Chang, Kevin Kai-Wei and Subramanian, Lavanya and Loh, Gabriel H. and Mutlu, Onur},
+  Booktitle                = {Proceedings of the 39th Annual International Symposium on Computer Architecture},
+  Year                     = {2012},
+
+  Address                  = {Washington, DC, USA},
+  Pages                    = {416--427},
+  Publisher                = {IEEE Computer Society},
+  Series                   = {ISCA '12},
+
+  Acmid                    = {2337207},
+  ISBN                     = {978-1-4503-1642-2},
+  Location                 = {Portland, Oregon},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20},
+  Url                      = {http://dl.acm.org/citation.cfm?id=2337159.2337207}
+}
+
+@InProceedings{aus_99,
+  Title                    = {{DIVA}: a reliable substrate for deep submicron microarchitecture design},
+  Author                   = {Austin, T. M. },
+  Booktitle                = {Proc. 32nd Annual International Symposium on MICRO-32 Microarchitecture},
+  Year                     = {1999},
+  Month                    = nov,
+  Pages                    = {196--207},
+
+  Doi                      = {10.1109/MICRO.1999.809458},
+  File                     = {aus_99.pdf:aus_99.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{autroc_08,
+  Title                    = {{A}ltitude and {U}nderground {R}eal-{T}ime {SER} {C}haracterization of {CMOS} 65nm {SRAM}},
+  Author                   = {Autran, J. L. and Roche, P. and Sauze, S. and Gasiot, G. and Munteanu, D. and Loaiza, P. and Zampaolo, M. and Borel, J.},
+  Booktitle                = {Proc. European Conf. Radiation and Its Effects Components and Systems (RADECS)},
+  Year                     = {2008},
+  Pages                    = {519--524},
+
+  Cb_grade                 = {- gelesen 11/10/18
+- Reliability
+- soft error rate measurement, technology},
+  Doi                      = {10.1109/RADECS.2008.5782774},
+  File                     = {autroc_08.pdf:autroc_08.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{avikri_08,
+  Title                    = {{A} {N}ovel {E}ncoding {S}cheme for {D}elay and {E}nergy {M}inimization in {VLSI} {I}nterconnects with {B}uilt-{I}n {E}rror {D}etection},
+  Author                   = {Avinash, L. and Krishna, M. K. and Srinivas, M. B.},
+  Booktitle                = {Proc. IEEE Computer Society Annual Symposium on VLSI ISVLSI '08},
+  Year                     = {2008},
+  Month                    = apr,
+  Pages                    = {128--133},
+
+  Doi                      = {10.1109/ISVLSI.2008.51},
+  File                     = {avikri_08.pdf:avikri_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{avisom_11,
+  Title                    = {{L}ow {O}verhead {S}oft {E}rror {M}itigation {T}echniques for {H}igh-{P}erformance and {A}ggressive {D}esigns},
+  Author                   = {Avirneni, N. and Somani, A.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {2011},
+  Note                     = {Early Access},
+  Number                   = {99},
+
+  Doi                      = {10.1109/TC.2011.31},
+  File                     = {avisom_11.pdf:avisom_11.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{avisub_09,
+  Title                    = {{L}ow overhead {S}oft {E}rror {M}itigation techniques for high-performance and aggressive systems},
+  Author                   = {Avirneni, N. D. P. and Subramanian, V. and Somani, A. K.},
+  Booktitle                = {Proc. IEEE/IFIP Int. Conf. Dependable Systems \& Networks DSN '09},
+  Year                     = {2009},
+  Pages                    = {185--194},
+
+  Doi                      = {10.1109/DSN.2009.5270340},
+  File                     = {avisub_09.pdf:avisub_09.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{avilap_04,
+  Title                    = {{B}asic {C}oncepts and {T}axonomy of {D}ependable and {S}ecure {C}omputing},
+  Author                   = {Avizienis, Algirdas and Laprie, Jean-Claude and Randell, Brian and Landwehr, Carl},
+  Journal                  = {IEEE Trans. Dependable Secur. Comput.},
+  Year                     = {2004},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {11--33},
+  Volume                   = {1},
+
+  Acmid                    = {1026492},
+  Address                  = {Los Alamitos, CA, USA},
+  Doi                      = {10.1109/TDSC.2004.2},
+  ISSN                     = {1545-5971},
+  Issue_date               = {January 2004},
+  Keywords                 = {65, Index Terms- Dependability, Index Terms- Dependability, security, trust, faults, errors, failures, vulnerabilities, attacks, fault tolerance, fault removal, fault forecasting., attacks, errors, failures, fault forecasting., fault removal, fault tolerance, faults, security, trust, vulnerabilities},
+  Numpages                 = {23},
+  Owner                    = {MJ},
+  Publisher                = {IEEE Computer Society Press},
+  Timestamp                = {2018-05-03},
+  Url                      = {http://dx.doi.org/10.1109/TDSC.2004.2}
+}
+
+@Unpublished{_fpl09awad,
+  Title                    = {{FPGA} {S}upercomputing {P}latforms: {A} {S}urvey},
+  Author                   = {Mariette Awad},
+  Note                     = {Review FPL 09},
+
+  Month                    = apr,
+  Year                     = {2009},
+
+  Abstract                 = {Field Programmable Gate Arrays (FPGAs) inherent reconfigurable nature and their low power consumption have made them so complementary to microprocessors that many are advocating their inclusion in all supercomputing clusters. Just as versatile as a microprocessor, FPGA are more customizable for specific applications and can still be well suited for the small supercomputer markets that do not require high volume production. Today FPGAs are included in few mainstream computer systems for accelerating application specific performance. Among the numerous areas in reconfigurable computing FPGA have been encroaching into, we focus our literature review mainly on the area of high performance computing. Moving from FPGA general features to the evolution of FPGA supercomputing architecture, its roadmap, we reference selected applications lately developed for accelerating large simulation tasks using FPGA based supercomputers before presenting concluding remarks on challenges yet to be overcome.},
+  Cds_grade                = {4},
+  Cds_keywords             = {FPGA, Supercomputing, Application, Overview},
+  Cds_read                 = {2009-04-09},
+  Cds_review               = {When it comes to the content, the paper provides a good overview of FPGA use in supercomputing with application examples. For readers not familiar with FPGAs on the one or supercomputing concepts on the other hand, it is easy to understand the advantages of FPGAs being used in supercomputing platforms. State-of-the-art of supercomputer structure is presented and important application examples are given. The low power consumption is mentioned several times in the text; in my opinion this point should be documented more detailed, e.g. by giving some relative or absolute values of a power consumption comparison for different architectures.
+
+Some linguistic weaknesses should be removed before finally publishing the paper, e.g. in section 2.1 two following sentences start with "And..." and throughout the whole paper, several commas are missing, which make long sentences hard to understand.
+
+All in all, a good summary of FPGA supercomputing status and a good starting point for readers wanting to get familiar with the topic. I would really like to see this paper on FPL.},
+  File                     = {_fpl09awad.pdf:_fpl09awad.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.04.29}
+}
+
+@InProceedings{ayasam_16,
+  Title                    = {{N}onlinear model predictive control hardware implementation with custom-precision floating point operations},
+  Author                   = {H. Ayala and R. Sampaio and D. M. Mu{\~{n}}oz and C. Llanos and L. Coelho and R. Jacobi},
+  Booktitle                = {2016 24th Mediterranean Conference on Control and Automation (MED)},
+  Year                     = {2016},
+  Month                    = {June},
+  Pages                    = {135-140},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [53]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/MED.2016.7535908},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {field programmable gate arrays;floating point arithmetic;manipulators;neural nets;nonlinear control systems;optimisation;predictive control;sampling methods;nonlinear model predictive control hardware implementation;custom-precision floating point operations;{MPC} based techniques;sampling interval;real-time {MPC} solution;artificial neural network;{FPGA};field programmable gate array;radial basis function artificial neural network;custom precision floating point operations;single-link robotic manipulator;Hardware;Field programmable gate arrays;Optimization;Real-time systems;Neurons;Predictive control;Neural networks},
+  Owner                    = {CCR}
+}
+
+@Conference{ayatie_08b,
+  Title                    = {{Low Power electrocardiogram QRS Detection in real-time}},
+  Author                   = {E. Ayari and R. Tielert and N. Wehn},
+  Booktitle                = {The 13th International Conference on Biomedical Engineering},
+  Year                     = {2008},
+
+  Address                  = {Singapore, Singapore},
+  Month                    = dec,
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{ayatie_08a,
+  Title                    = {{A} new fitting approach for online electrocardiogram component waves delineation},
+  Author                   = {Ayari, E. P. and Tielert, R. and Wehn, N.},
+  Booktitle                = {Proc. Computers in Cardiology},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {861--864},
+
+  Doi                      = {10.1109/CIC.2008.4749178},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{ayatie_09,
+  Title                    = {{A} {N}oise {T}olerant {M}ethod for {ECG} {S}ignals {F}eature {E}xtraction and {N}oise {R}eduction},
+  Author                   = {Ayari, Emna Zoghlami and Tielert, Reinhard and Wehn, Norbert},
+  Booktitle                = {Proc. 3rd International Conference on Bioinformatics and Biomedical Engineering ICBBE 2009},
+  Year                     = {2009},
+  Month                    = jun,
+  Pages                    = {1--4},
+
+  Doi                      = {10.1109/ICBBE.2009.5162207},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{ayatie_08,
+  Title                    = {{T}emplate-based compression of {ECG} signals},
+  Author                   = {Ayari, Emna Zoghlami and Tielert, Rheinhardt and Wehn, Norbert},
+  Booktitle                = {Proc. 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society EMBS 2008},
+  Year                     = {2008},
+  Month                    = aug,
+  Pages                    = {283--286},
+
+  Doi                      = {10.1109/IEMBS.2008.4649145},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@Conference{ayn_09,
+  Title                    = {{TLM}-2.0 in {A}ction: {A}n {E}xample-based {A}pproach to {T}ransaction-level {M}odeling and the {N}ew {W}orld of {M}odel {I}nteroperability},
+  Author                   = {John Aynsley},
+  Year                     = {2009},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {Transaction-Level-Modeling, TLM, OSCI, Tutorial},
+  Cds_read                 = {2009-10-23},
+  Cds_review               = {good and quick introduction into OSCI TLM 2.0},
+  File                     = {ayn_09.pdf:ayn_09.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.10.23},
+  Url                      = {http://www.opensystemc.org/tlm20tutorial/John_Aynsley_1/player.html}
+}
+
+@InProceedings{ayoind_10,
+  Title                    = {{E}nergy {E}fficient {P}roactive {T}hermal {M}anagement in {M}emory {S}ubsystem},
+  Author                   = {Ayoub, Raid Zuhair and Indukuri, Krishnam Raju and Rosing, Tajana Simunic},
+  Booktitle                = {Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design},
+  Year                     = {2010},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {195--200},
+  Publisher                = {ACM},
+  Series                   = {ISLPED '10},
+
+  Acmid                    = {1840884},
+  Doi                      = {10.1145/1840845.1840884},
+  ISBN                     = {978-1-4503-0146-6},
+  Keywords                 = {energy, memory subsystem, performance, proactive, thermal management},
+  Location                 = {Austin, Texas, USA},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-22},
+  Url                      = {http://doi.acm.org/10.1145/1840845.1840884}
+}
+
+@InProceedings{aytkan_06,
+  Title                    = {{A} {F}ully {I}ntegrated {UWB} {PHY} in 0.13/spl mu/m {CMOS}},
+  Author                   = {Aytur, T. and Han-Chang Kang and Mahadevappa, R. and Altintas, M. and ten Brink, S. and Thanh Diep and Cheng-Chung Hsu and Feng Shi and Fei-Ran Yang and Chao-Cheng Lee and Ran-Hong Yan and Razavi, B.},
+  Booktitle                = {Solid-State Circuits, 2006 IEEE International Conference Digest of Technical Papers},
+  Year                     = {2006},
+  Month                    = feb,
+  Pages                    = {418--427},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{azapfi_16,
+  Title                    = {{L}ogic-{B}ase {I}nterconnect {D}esign for {N}ear {M}emory {C}omputing in the {S}mart {M}emory {C}ube},
+  Author                   = {E. Azarkhish and C. Pfister and D. Rossi and I. Loi and L. Benini},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2016},
+  Number                   = {99},
+  Pages                    = {1-14},
+  Volume                   = {PP},
+
+  Doi                      = {10.1109/TVLSI.2016.2570283},
+  ISSN                     = {1063-8210},
+  Keywords                 = {Bandwidth;Memory management;Program processors;Random access memory;Robustness;Standards;3-D integration;address scrambling;cycle accurate (CA) model;interconnect design;smart memory cube (SMC).},
+  Owner                    = {MJ},
+  Timestamp                = {2016-07-20}
+}
+
+@InProceedings{azeiss_02,
+  Title                    = {{Profile-based Dynamic Voltage SCheduling using Program Checkpoints}},
+  Author                   = {A. Azevedo and I. Issenin and R. Cornea and R. Gupta and N. Dutt and A. Veidenbaum and A. Nicolau},
+  Booktitle                = {Proc. 2002 Design, Automation and Test in Europe (DATE '02)},
+  Year                     = {2002},
+
+  Address                  = {Paris, France},
+  Month                    = mar,
+  Pages                    = {168--175},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{azzaya_08,
+  Title                    = {{R}eduction of {ML} decoding complexity for {MIMO} {S}phere {D}ecoding, {QOSTBC}, and {OSTBC}},
+  Author                   = {Azzam, L. and Ayanoglu, E.},
+  Booktitle                = {Proc. Information Theory and Applications Workshop},
+  Year                     = {2008},
+  Pages                    = {18--25},
+
+  Abstract                 = {In this paper, we discuss three applications of the QR decomposition algorithm to decoding in a number of Multi-Input Multi-Output (MIMO) systems. In the first application, we propose a new structure for MIMO Sphere Decoding (SD). We show that the new approach achieves 80% reduction in the overall complexity compared to conventional SD for a 2 times 2 system, and almost 50% reduction for the 4 times 4 and 6 times 6 cases. In the second application, we propose a low complexity Maximum Likelihood Decoding (MLD) algorithm for quasi-orthogonal space-time block codes (QOSTBCs). We show that for N = 8 transmit antennas and 16-QAM modulation scheme, the new approach achieves &gt; 97% reduction in the overall complexity compared to conventional MLD, and &gt; 89% reduction compared to the most competitive reported algorithms in the literature. This complexity gain becomes greater when the number of transmit antennas (N) or the constellation size (L) becomes larger. In the third application, we propose a low complexity Maximum Likelihood Decoding (MLD) algorithm for orthogonal space-time block codes (OSTBCs) based on the real-valued lattice representation and QR decomposition. For a system employing the well-known Alamouti OSTBC and 16-QAM modulation scheme, the new approach achieves &gt; 87% reduction in the overall complexity compared to conventional MLD. Moreover, we show that for square L-QAM constellations, the proposed algorithm reduces the decoding computational complexity from O(L<sup>N/2</sup>) for conventional MLD to O(L) for systems employing QOSTBCs and from O(L) for conventional MLD to O(radicL) for those employing OSTBCs without sacrificing the performance.},
+  Doi                      = {10.1109/ITA.2008.4601014},
+  File                     = {azzaya_08.pdf:azzaya_08.pdf:PDF},
+  Grade                    = {0},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@InProceedings{bac_14,
+  Title                    = {{C}haracterization of {D}ata {R}etention {F}aults in {DRAM} {D}evices},
+  Author                   = {Bacchini,Angelo},
+  Year                     = {2014},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-21}
+}
+
+@InProceedings{bacsmi_06,
+  Title                    = {{B}uilding a common {ESL} design and verification methodology - is it just a dream?},
+  Author                   = {Bacchini, F. and Smith, G. and Hosseini, A. and Parikh, A. and Chin, H. T. and Urard, P. and Girczyc, E. and Bloch, S. },
+  Booktitle                = {Proc. 43rd ACM/IEEE Design Automation Conference},
+  Year                     = {2006},
+  Pages                    = {370--371},
+
+  Doi                      = {10.1109/DAC.2006.229302},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@Article{bacgun_07,
+  Title                    = {{The long term evolution towards a new 3GPP* air interface standard}},
+  Author                   = {Rainer Bachl and Peter Gunreben and Suman Das and Said Tatesh},
+  Journal                  = {Bell Labs Technical Journal},
+  Year                     = {2007},
+  Pages                    = {25--51},
+  Volume                   = {11},
+
+  Doi                      = {10.1002/bltj.20195},
+  Issue                    = {4},
+  Masid                    = {4360198},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.01.16}
+}
+
+@Article{baelee_19,
+  Title                    = {{S}mart{P}atch: {A} {S}elf-{P}owered and {P}atchable {C}umulative {UV} {I}rradiance {M}eter},
+  Author                   = {D. {Baek} and H. G. {Lee} and N. {Chang}},
+  Journal                  = {IEEE Design Test},
+  Year                     = {2019},
+
+  Month                    = {Feb},
+  Number                   = {1},
+  Pages                    = {57-64},
+  Volume                   = {36},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8550715},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/MDAT.2018.2883717},
+  ISSN                     = {2168-2356},
+  Keywords                 = {TCS},
+  Keywords_original        = {Intelligent sensors;Radiation effects;Meters;Radiation monitoring;Radiation detectors;Batteries;Ultraviolet sources;Ultraviolet;skin damage;UV irradiance meter;dynamic power management},
+  Owner                    = {CCR}
+}
+
+@InProceedings{baekim_15,
+  Title                    = {{A} {R}eliable {C}ross-{P}oint {MLC} {R}e{RAM} with {S}neak {C}urrent {C}ompensation},
+  Author                   = {J. Baek and S. Kim and J. Park and J. Park and K. Kwon},
+  Booktitle                = {2015 IEEE International Memory Workshop (IMW)},
+  Year                     = {2015},
+  Month                    = {May},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/IMW.2015.7150272},
+  ISSN                     = {2159-483X},
+  Keywords                 = {CMOS memory circuits;multivalued logic circuits;resistive RAM;cross-point MLC ReRAM;sneak current compensation;CMOS technology;self-termination scheme;write failure;compliance current offset;current 300 muA;size 350 nm;Resistance;Arrays;Microprocessors;Switches;Current measurement;Reliability},
+  Timestamp                = {2018-08-29}
+}
+
+@Article{baecho_14,
+  Title                    = {{R}efresh now and then},
+  Author                   = {Baek, Sanghoon and Cho, Sangyeun and Melhem, Rami},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2014},
+  Number                   = {12},
+  Pages                    = {3114--3126},
+  Volume                   = {63},
+
+  Owner                    = {MJ},
+  Publisher                = {IEEE},
+  Timestamp                = {2015.07.10}
+}
+
+@Article{bahcoc_74,
+  Title                    = {{Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate}},
+  Author                   = {L. Bahl and J. Cocke and F. Jelinek and J. Raviv},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {1974},
+
+  Month                    = mar,
+  Pages                    = {284--287},
+  Volume                   = {IT-20},
+
+  File                     = {bahcoc_74.pdf:bahcoc_74.pdf:PDF},
+  Optnote                  = {Original description of the MAP algorithm},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{baiswa_91,
+  Title                    = {{T}he fractional {F}ourier transform and applications},
+  Author                   = {Bailey, David H and Swarztrauber, Paul N},
+  Journal                  = {SIAM review},
+  Year                     = {1991},
+  Number                   = {3},
+  Pages                    = {389--404},
+  Volume                   = {33},
+
+  Owner                    = {Brugger},
+  Publisher                = {SIAM},
+  Timestamp                = {2014.08.21}
+}
+
+@Article{balsha_01,
+  Title                    = {{T}he twin-transistor noise-tolerant dynamic circuit technique},
+  Author                   = {Balamurugan, G. and Shanbhag, N.R.},
+  Journal                  = {Solid-State Circuits, IEEE Journal of},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {273--280},
+  Volume                   = {36},
+
+  Doi                      = {10.1109/4.902768},
+  File                     = {balsha_01.pdf:balsha_01.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@Article{balwat_03,
+  Title                    = {{M}etropolis: an integrated electronic system design environment},
+  Author                   = {Balarin, F. and Watanabe, Y. and Hsieh, H. and Lavagno, L. and Passerone, C. and Sangiovanni-Vincentelli, A.},
+  Journal                  = {Computer},
+  Year                     = {2003},
+
+  Month                    = {April},
+  Number                   = {4},
+  Pages                    = {45-52},
+  Volume                   = {36},
+
+  Doi                      = {10.1109/MC.2003.1193228},
+  ISSN                     = {0018-9162},
+  Keywords                 = {electronic design automation;embedded systems;Metropolis;embedded software design;formal analysis;formal semantics;integrated electronic system design environment;metamodel;programmable platforms;simulation;synthesis;Algorithm design and analysis;Analytical models;Computational modeling;Computer architecture;Embedded software;Formal verification;Hardware;Software design;Solids;Uncertainty},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.27}
+}
+
+@Article{balgia_17,
+  Title                    = {{C}omparison of {P}olar {D}ecoders with {E}xisting {L}ow-{D}ensity {P}arity-{C}heck and {T}urbo {D}ecoders},
+  Author                   = {{Balatsoukas-Stimming}, A. and {Giard}, P. and {Burg}, A.},
+  Journal                  = {ArXiv e-prints},
+  Year                     = {2017},
+
+  Month                    = feb,
+
+  Adsnote                  = {Provided by the SAO/NASA Astrophysics Data System},
+  Adsurl                   = {http://adsabs.harvard.edu/abs/2017arXiv170204707B},
+  Archiveprefix            = {arXiv},
+  Eprint                   = {1702.04707},
+  File                     = {balgia_17.pdf:balgia_17.pdf:PDF},
+  Keywords                 = {Computer Science - Information Theory},
+  Owner                    = {CK},
+  Primaryclass             = {cs.IT},
+  Timestamp                = {2017-03-30}
+}
+
+@Article{balmei_15,
+  Title                    = {{A} {F}ully-{U}nrolled {LDPC} {D}ecoder {B}ased on {Q}uantized {M}essage {P}assing},
+  Author                   = {Balatsoukas-Stimming, Alexios and Meidlinger, Michael and Ghanaatian, Reza and Matz, Gerald and Burg, Andreas},
+  Journal                  = {arXiv preprint arXiv:1510.04589},
+  Year                     = {2015},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.10.20}
+}
+
+@InProceedings{balmei_15a,
+  Title                    = {{A} fully-unrolled {LDPC} decoder based on quantized message passing},
+  Author                   = {A. Balatsoukas-Stimming and M. Meidlinger and R. Ghanaatian and G. Matz and A. Burg},
+  Booktitle                = {Signal Processing Systems (SiPS), 2015 IEEE Workshop on},
+  Year                     = {2015},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/SiPS.2015.7345024},
+  File                     = {balmei_15a.pdf:balmei_15a.pdf:PDF},
+  Keywords                 = {message passing;parity check codes;table lookup;LDPC codes;LDPC decoder hardware architecture;codeword bits;decoder messages;finite alphabet message passing algorithm;fully unrolled LDPC decoder;generic look-up tables;mutual information;quantized message passing;standard minsum variable node;Algorithm design and analysis;Decoding;Hardware;Iterative decoding;Quantization (signal);Table lookup},
+  Owner                    = {StW},
+  Timestamp                = {2016.06.22}
+}
+
+@InProceedings{balpar_15,
+  Title                    = {{O}n metric sorting for successive cancellation list decoding of polar codes},
+  Author                   = {A. Balatsoukas-Stimming and M. Bastani Parizi and A. Burg},
+  Booktitle                = {Circuits and Systems (ISCAS), 2015 IEEE International Symposium on},
+  Year                     = {2015},
+  Month                    = {May},
+  Pages                    = {1993-1996},
+
+  Doi                      = {10.1109/ISCAS.2015.7169066},
+  Keywords                 = {channel coding;maximum likelihood decoding;log-likelihood ratio;metric sorter unit architecture;path metrics;polar codes;successive cancellation list decoder;successive cancellation list decoding;Computer architecture;Decoding;Delays;Hardware;Indexes;Sorting},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{balpar_14,
+  Title                    = {{LLR}-based successive cancellation list decoding of polar codes},
+  Author                   = {A. Balatsoukas-Stimming and M. Bastani Parizi and A. Burg},
+  Booktitle                = {Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on},
+  Year                     = {2014},
+  Month                    = {May},
+  Pages                    = {3903-3907},
+
+  Doi                      = {10.1109/ICASSP.2014.6854333},
+  Keywords                 = {channel coding;decoding;LLR-based successive cancellation list decoding;SCL decoder;block-length;channel LLR;log-likelihood based implementation;log-likelihood ratios;monotone function;path likelihood;polar codes;Clocks;Decoding;Hardware;Memory management;Signal processing;Hardware Implementation;Polar Codes;Successive Cancellation List Decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{balpar_14a,
+  Title                    = {{LLR}-based successive cancellation list decoding of polar codes},
+  Author                   = {A. Balatsoukas-Stimming and M. Bastani Parizi and A. Burg},
+  Booktitle                = {Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on},
+  Year                     = {2014},
+  Month                    = {May},
+  Pages                    = {3903-3907},
+
+  Doi                      = {10.1109/ICASSP.2014.6854333},
+  Keywords                 = {channel coding;decoding;LLR-based successive cancellation list decoding;SCL decoder;block-length;channel LLR;log-likelihood based implementation;log-likelihood ratios;monotone function;path likelihood;polar codes;Clocks;Decoding;Hardware;Memory management;Signal processing;Hardware Implementation;Polar Codes;Successive Cancellation List Decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{balray_14,
+  Title                    = {{H}ardware {A}rchitecture for {L}ist {S}uccessive {C}ancellation {D}ecoding of {P}olar {C}odes},
+  Author                   = {A. Balatsoukas-Stimming and A. J. Raymond and W. J. Gross and A. Burg},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2014},
+
+  Month                    = {Aug},
+  Number                   = {8},
+  Pages                    = {609-613},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCSII.2014.2327336},
+  ISSN                     = {1549-7747},
+  Keywords                 = {VLSI;block codes;decoding;error correction codes;linear codes;UMC 90 nm VLSI technology;bit rate 181 Mbit/s;block length;frequency 459 MHz;hardware architecture;list SC decoding;list sizes;list successive cancellation decoding;polar codes;Circuits and systems;Computer architecture;Decoding;Hardware;Indexes;Measurement;Quantization (signal);List successive cancellation (SC) decoding;polar codes;very-large-scale integration (VLSI)},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{balars_06,
+  Title                    = {{D}esign of a novel soft error mitigation technique for reconfigurable architectures},
+  Author                   = {Baloch, S. and Arslan, T. and Stoica, A. },
+  Booktitle                = {Proc. IEEE Aerospace Conf},
+  Year                     = {2006},
+
+  Doi                      = {10.1109/AERO.2006.1655970},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{baldas_16,
+  Title                    = {{G}raceful {P}erformance {M}odulation for {P}ower-{N}eutral {T}ransient {C}omputing {S}ystems},
+  Author                   = {D. Balsamo and A. Das and A. S. Weddell and D. Brunelli and B. M. Al-Hashimi and G. V. Merrett and L. Benini},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2016},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {738-749},
+  Volume                   = {35},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7403941},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/TCAD.2016.2527713},
+  ISSN                     = {0278-0070},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy conservation;microcontrollers;power aware computing;control algorithm;dynamic frequency scaling;energy harvesting;energy storage;microcontroller;power-neutral operation;power-neutral transient computing systems;voltage threshold-based interrupts;Batteries;Energy harvesting;Frequency modulation;Heuristic algorithms;Microcontrollers;Sensors;Transient analysis;Dynamic Frequency Scaling;Dynamic frequency scaling (DFS);Energy Harvesting;Graceful Performance Modulation;Transient Computing;energy harvesting;graceful performance modulation;transient computing},
+  Owner                    = {CCR}
+}
+
+@Article{balfle_19,
+  Title                    = {{M}omentum: {P}ower-neutral {P}erformance {S}caling with {I}ntrinsic {MPPT} for {E}nergy {H}arvesting {C}omputing {S}ystems},
+  Author                   = {Balsamo, Domenico and Fletcher, Benjamin J. and Weddell, Alex S. and Karatziolas, Giorgos and Al-Hashimi, Bashir M. and Merrett, Geoff V.},
+  Journal                  = {ACM Trans. Embed. Comput. Syst.},
+  Year                     = {2019},
+
+  Month                    = jan,
+  Number                   = {6},
+  Pages                    = {93:1--93:25},
+  Volume                   = {17},
+
+  Acmid                    = {3281300},
+  Address                  = {New York, NY, USA},
+  Articleno                = {93},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Balsamo:2019:MPP:3299750.3281300},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3281300},
+  ISSN                     = {1539-9087},
+  Issue_date               = {January 2019},
+  Keywords                 = {TCS},
+  Keywords_original        = {Energy harvesting, embedded computing systems, maximum power point tracking, performance adaptation, power neutrality, transient computing},
+  Numpages                 = {25},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/3281300}
+}
+
+@InProceedings{balmag_19,
+  Title                    = {{E}nergy {H}arvesting {M}eets {I}o{T}: {F}uelling {A}doption of {T}ransient {C}omputing in {E}mbedded {S}ystems},
+  Author                   = {D. {Balsamo} and M. {Magno} and K. {Kubara} and B. {Lazarescu} and G. V. {Merrett}},
+  Booktitle                = {2019 IEEE 5th World Forum on Internet of Things (WF-IoT)},
+  Year                     = {2019},
+  Month                    = {April},
+  Pages                    = {413-417},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8767302},
+  Ccr_keywords             = {todo},
+  Ccr_relevance            = {in general},
+  Ccr_topic                = {CP},
+  Doi                      = {10.1109/WF-IoT.2019.8767302},
+  Keywords                 = {TCS},
+  Keywords_original        = {application program interfaces;embedded systems;energy harvesting;flash memories;Internet of Things;operating systems (computers);portable hardware-independent software;lightweight operating systems;embedded IoT applications;open-source IoT code availability;system state;embedded systems;transient computing systems;IoT devices;energy harvesting;OS API;capacitance 4.9 mF;capacitance 4.7 mF;Transient analysis;Random access memory;Nonvolatile memory;Software;Internet of Things;Hardware;Standards;Energy harvesting;Transient computing;Internet of Things;Arm mbed programming framework},
+  Owner                    = {CCR}
+}
+
+@Article{balwed_16,
+  Title                    = {{H}ibernus++: {A} {S}elf-{C}alibrating and {A}daptive {S}ystem for {T}ransiently-{P}owered {E}mbedded {D}evices},
+  Author                   = {D. Balsamo and A. S. Weddell and A. Das and A. R. Arreola and D. Brunelli and B. M. Al-Hashimi and G. V. Merrett and L. Benini},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2016},
+  Number                   = {12},
+  Pages                    = {1968-1980},
+  Volume                   = {35},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7442814},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/TCAD.2016.2547919},
+  ISSN                     = {0278-0070},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy consumption;energy harvesting;microcontrollers;power engineering computing;secondary cells;supercapacitors;Hibernus++;adaptive system;autonomous systems;batteries;energy consumption;energy harvesters;energy storage devices;energy supply;microcontroller hardware;power outage;self-calibrating system;supercapacitors;transiently-powered embedded devices;Batteries;Checkpointing;Circuit faults;Microcontrollers;Nonvolatile memory;Transient analysis;Embedded systems;energy harvesting;intermittent supply;low-power design;transient computing},
+  Owner                    = {CCR}
+}
+
+@Article{balwed_15,
+  Title                    = {{H}ibernus: {S}ustaining {C}omputation {D}uring {I}ntermittent {S}upply for {E}nergy-{H}arvesting {S}ystems},
+  Author                   = {D. Balsamo and A. S. Weddell and G. V. Merrett and B. M. Al-Hashimi and D. Brunelli and L. Benini},
+  Journal                  = {IEEE Embedded Systems Letters},
+  Year                     = {2015},
+
+  Month                    = {March},
+  Number                   = {1},
+  Pages                    = {15-18},
+  Volume                   = {7},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {6960060},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/LES.2014.2371494},
+  ISSN                     = {1943-0663},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;ferroelectric storage;power engineering computing;random-access storage;FRAM nonvolatile memory;Hibernus;decoupling capacitance;discontinuous power supply;energy overhead reduction;energy-harvesting systems;intermittent supply;processor time reduction;Capacitance;Energy harvesting;Ferroelectric films;Microcontrollers;Nonvolatile memory;Random access memory;Registers;Checkpointing;embedded software;energy harvesting},
+  Owner                    = {CCR}
+}
+
+@InProceedings{bambha_01,
+  Title                    = {{Hybrid Global/Local Search Strategies for Dynamic Voltage Scaling in Embedded Multiprocessors}},
+  Author                   = {N. K. Bambha and S. S. Bhattacharyya and J. Teich and E. Zitzler},
+  Booktitle                = {Proc. 2001 International Workshop on Hardware/Software Co-Design (CODES '01)},
+  Year                     = {2001},
+
+  Address                  = {Copenhagen, Denmark},
+  Month                    = apr,
+  Pages                    = {243--248},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bankar_09,
+  Title                    = {{D}esign {M}ethodology for {L}ow {P}ower and {P}arametric {R}obustness {T}hrough {O}utput-{Q}uality {M}odulation: {A}pplication to {C}olor-{I}nterpolation {F}iltering},
+  Author                   = {Banerjee, N. and Karakonstantis, G. and Jung Hwan Choi and Chakrabarti, C. and Roy, K.},
+  Journal                  = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
+  Year                     = {2009},
+  Number                   = {8},
+  Pages                    = {1127--1137},
+  Volume                   = {28},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/TCAD.2009.2022197},
+  File                     = {bankar_09.pdf:bankar_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.26}
+}
+
+@Book{bangut_01,
+  Title                    = {{Digraphs - Theory, Algorithms and Applications}},
+  Author                   = {J. Bang-Jensen and G. Gutin},
+  Publisher                = {Springer-Verlag},
+  Year                     = {2001},
+
+  Address                  = {London/Berlin/Heidelberg},
+
+  Optnote                  = {ISBN 1-85233-611-0},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{banbea_08,
+  Title                    = {{FPGA} {I}mplementation of {P}seudo {R}andom {N}umber {G}enerators for {M}onte {C}arlo {M}ethods in {Q}uantitative {F}inance},
+  Author                   = {Simon Banks and Philip Beadling and Andras Ferencz},
+  Booktitle                = {Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on},
+  Year                     = {2008},
+  Month                    = {dec.},
+  Pages                    = {271 -276},
+
+  Abstract                 = {FPGA based implementations of two classes of pseudo random number(PRN) generator, intended for use in Monte Carlo methods for finance, are presented. FPGA implementations potentially offer reduced cost and improved performance compared to general purpose processor (GPP) systems such as PCs or mainframes. The first class of PRN generator, which includes the mersenne twister, uses generalized feedback shift registers (GFSRs). The second class is based on multiplication of fixed precision integers (with overflow). In both cases we compare a high quality generator and a generator with minimal resource usage. Comparisons of FPGA resource usage, data throughput and the quality of the generated series are given with a view to applications in high performance computing (HPC) for computational finance. The two classes of generator are shown to be complementary in their use of FPGA resources.},
+  Cds_grade                = {0},
+  Cds_keywords             = {random numbers, FPGA, Mersenne Twister},
+  Doi                      = {10.1109/ReConFig.2008.38},
+  File                     = {banbea_08.pdf:banbea_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@Article{baralb_99,
+  Title                    = {{E}mergence of {S}caling in {R}andom {N}etworks},
+  Author                   = {Albert-L{\' a}szl{\'o} Barab{\'a}si and R\'eka Albert},
+  Journal                  = {Science},
+  Year                     = {1999},
+  Number                   = {5439},
+  Pages                    = {509-512},
+  Volume                   = {286},
+
+  Owner                    = {lehmannk},
+  Timestamp                = {2014.11.28}
+}
+
+@Article{bartho_08a,
+  Title                    = {{E}xtending a {F}ixed-{C}omplexity {S}phere {D}ecoder to {O}btain {L}ikelihood {I}nformation for {T}urbo-{MIMO} {S}ystems},
+  Author                   = {Barbero, L.G. and Thompson, J.S.},
+  Journal                  = {Vehicular Technology, IEEE Transactions on},
+  Year                     = {2008},
+  Number                   = {5},
+  Pages                    = {2804-2814},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TVT.2007.914064},
+  ISSN                     = {0018-9545},
+  Keywords                 = {MIMO communication;channel coding;iterative decoding;matrix algebra;tree searching;turbo codes;channel matrix;fixed-complexity sphere decoder;hardware implementation;iterative decoding;iterative detection;tree search;turbo-MIMO system;Iterative decoding;Multiple input-multiple output (MIMO);iterative decoding;list sphere decoder (LSD);multiple input-multiple output (MIMO);turbo decoding;wireless communications},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.10}
+}
+
+@Article{bartho_08,
+  Title                    = {{F}ixing the {C}omplexity of the {S}phere {D}ecoder for {MIMO} {D}etection},
+  Author                   = {Barbero, L. G. and Thompson, J. S. },
+  Journal                  = {IEEE Transactions on Wireless Communications},
+  Year                     = {2008},
+  Number                   = {6},
+  Pages                    = {2131--2142},
+  Volume                   = {7},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.07.23}
+}
+
+@Article{barpie_95a,
+  Title                    = {{R}ate compatible turbo codes},
+  Author                   = {Barbulescu, Adrien Sorin and Pietrobon, SS},
+  Journal                  = {Electronics letters},
+  Year                     = {1995},
+  Number                   = {7},
+  Pages                    = {535--536},
+  Volume                   = {31},
+
+  Owner                    = {StW},
+  Publisher                = {IET},
+  Timestamp                = {2017.03.01}
+}
+
+@Article{barpie_99,
+  Title                    = {{Turbo Codes: A Tutorial on a New Class of Powerful Error Correcting Coding Schemes, Part 2: Decoder Design and Performance}},
+  Author                   = {Barbulescu, A. S. and Pietrobon, S. S.},
+  Journal                  = {Journal of Electrical and Electronics Engineering, Australia},
+  Year                     = {1999},
+
+  Month                    = sep,
+  Number                   = {3},
+  Pages                    = {143--152},
+  Volume                   = {19},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{barpie_99b,
+  Title                    = {{Turbo Codes: A Tutorial on a New Class of Powerful Error Correcting Coding Schemes}},
+  Author                   = {Barbulescu, A. S. and Pietrobon, S. S.},
+  Journal                  = {Journal of Electrical and Electronics Engineering, Australia},
+  Year                     = {1999},
+
+  Month                    = sep,
+  Number                   = {3},
+  Pages                    = {129--152},
+  Volume                   = {19},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{barpie_95,
+  Title                    = {{Terminating the Trellis of Turbo-Codes in the Same State}},
+  Author                   = {Barbulescu, A. S. and Pietrobon, S. S.},
+  Journal                  = {Electronics Letters},
+  Year                     = {1995},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {22--23},
+  Volume                   = {31},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{Phdbarbu96,
+  Title                    = {{Iterative Decoding of Turbo Codes and Other Concatenated Codes}},
+  Author                   = {Barbulescu, S. A.},
+  School                   = {University of South Australia},
+  Year                     = {1996},
+  Month                    = feb,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{barbra_48,
+  Title                    = {{T}he {T}ransistor, {A} {S}emi-{C}onductor {T}riode},
+  Author                   = {Bardeen, J. and Brattain, W. H.},
+  Journal                  = {Phys. Rev.},
+  Year                     = {1948},
+
+  Month                    = jul,
+  Note                     = {Invention of transistor},
+  Number                   = {2},
+  Pages                    = {230--231},
+  Volume                   = {74},
+
+  Doi                      = {10.1103/PhysRev.74.230},
+  Numpages                 = {1},
+  Publisher                = {American Physical Society}
+}
+
+@Article{barliu_13,
+  Title                    = {{D}ecomposition {M}ethods for {L}arge {S}cale {LP} {D}ecoding},
+  Author                   = {Barman, S. and Liu, X. and Draper, S. and Recht, B.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2013},
+  Number                   = {12},
+  Pages                    = {7870--7886},
+  Volume                   = {59},
+
+  Doi                      = {10.1109/TIT.2013.2281372},
+  File                     = {barliu_13.pdf:barliu_13.pdf:PDF},
+  Keywords                 = {LPDecoding, ADMM},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.08},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6595057}
+}
+
+@InProceedings{bardec_03,
+  Title                    = {{F}ast decoding algorithm for {LDPC} over {GF}(2q)},
+  Author                   = {Barnault, L. and Declercq, D. },
+  Booktitle                = {Proc. IEEE Information Theory Workshop},
+  Year                     = {2003},
+  Month                    = mar # {--} # apr,
+  Pages                    = {70--73},
+
+  File                     = {bardec_03.pdf:bardec_03.pdf:PDF},
+  Owner                    = {lehnigk},
+  Timestamp                = {2009.08.18}
+}
+
+@Article{barbau_00,
+  Title                    = {{I}mproved codes for space-time trellis-coded modulation},
+  Author                   = {Baro, S. and Bauch, G. and Hansmann, A.},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2000},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {20--22},
+  Volume                   = {4},
+
+  Doi                      = {10.1109/4234.823537},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.09.16}
+}
+
+@InProceedings{barhag_03,
+  Title                    = {{I}terative detection of {MIMO} transmission using a list-sequential ({LISS}) detector},
+  Author                   = {Baro, S. and Hagenauer, J. and Witzke, M.},
+  Year                     = {2003},
+  Month                    = {may},
+  Pages                    = { 2653 - 2657 vol.4},
+  Volume                   = {4},
+
+  Abstract                 = { For iterative detection in systems employing multiple antennas with an outer code we need a MIMO detector delivering a-posteriori capabilities (APP) about the code bits. Full-APP detection would lead to prohibitive complexity; therefore we extend for high-level signals the concept of the sphere decoder using an approach from sequential decoding instead of geometrical considerations. We show how a priori information can be incorporated into the metric, which is then optimized by systematic tree search. Furthermore, we show how the reliability of the resulting L-values can be improved by augmenting the complete search tree. Simulation results show an improved performance over the list sphere decoder.},
+  Doi                      = {10.1109/ICC.2003.1204433},
+  File                     = {barhag_03.pdf:barhag_03.pdf:PDF},
+  Journal                  = {Communications, 2003. ICC '03. IEEE International Conference on},
+  Keywords                 = { MIMO detection; a-posteriori capabilities; iterative detection; list sphere decoder; list-sequential detector; sequential decoding; tree search; MIMO systems; antenna arrays; iterative methods; receivers; signal detection;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.03.03}
+}
+
+@Electronic{bar_16,
+  Title                    = {{Developer Preview - EC2 Instances (F1) with Programmable Hardware}},
+  Author                   = {Jeff Barr},
+  HowPublished             = {https://aws.amazon.com/de/blogs/aws/developer-preview-ec2-instances-f1-with-programmable-hardware/},
+  Month                    = {Nov},
+  Note                     = {last access 2016-12-22},
+  Organization             = {{Amazon Web Services}},
+  Year                     = {2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.12.22}
+}
+
+@Book{barlee_04,
+  Title                    = {{Digital Communication}},
+  Author                   = {J. R. Barry and E. A. Lee and D. G. Messerschmitt},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {2004},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{barcar_02,
+  Title                    = {{I}mplementation of {DVB}-{RCS} turbo decoder for satellite on-board processing},
+  Author                   = {Bartolazzi, A. and Cardarilli, G. and Del Re, A. and Giancristofaro, D. and Re, M.},
+  Booktitle                = {Proc. 1st IEEE International Conference on Circuits and Systems for Communications ICCSC '02},
+  Year                     = {2002},
+  Month                    = jun,
+  Pages                    = {142--145},
+
+  Doi                      = {10.1109/OCCSC.2002.1029065},
+  File                     = {barcar_02.pdf:barcar_02.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.11.03}
+}
+
+@Article{basgra_82,
+  Title                    = {{T}raining in creative problem solving: {E}ffects on ideation and problem finding and solving in an industrial research organization},
+  Author                   = {Basadur, Min and Graen, George B and Green, Stephen G},
+  Journal                  = {Organizational Behavior and Human Performance},
+  Year                     = {1982},
+  Number                   = {1},
+  Pages                    = {41--70},
+  Volume                   = {30},
+
+  Owner                    = {Brugger},
+  Publisher                = {Elsevier},
+  Timestamp                = {2015.06.22}
+}
+
+@Article{bascas_06,
+  Title                    = {{Baseband Analog Front-End and Digital Back-End for Reconfigurable Multi-Standard Terminals}},
+  Author                   = {Baschirotto, A. and Castello, R. and Campi, F. and Cesura, G. and Toma, M. and Guerrieri, R. and Lodi, R. and Lavagno, L. and Malcovati, P.},
+  Journal                  = {Circuits and Systems Magazine, IEEE},
+  Year                     = {2006},
+
+  Month                    = jan # {--} # mar,
+  Number                   = {1},
+  Pages                    = {8--28},
+  Volume                   = {6},
+
+  Doi                      = {10.1109/MCAS.2006.1607635},
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.01}
+}
+
+@TechReport{bcb_16,
+  Title                    = {{M}inimum capital requirements for market risk},
+  Author                   = {{Basel Committee on Banking Supervision}},
+  Institution              = {Bank for International Settlements},
+  Year                     = {2016},
+  Month                    = {Jan},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.04},
+  Url                      = {http://www.bis.org/bcbs/publ/d352.pdf}
+}
+
+@TechReport{ban_10,
+  Title                    = {{B}asel {III}: {A} global regulatory framework for more resilient banks and banking systems},
+  Author                   = {{Basel Committee on Banking Supervision}},
+  Institution              = {Bank for International Settlements},
+  Year                     = {2010},
+  Month                    = {Dec},
+  Note                     = {(rev June 2011)},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.01.30},
+  Url                      = {http://www.bis.org/publ/bcbs189.pdf}
+}
+
+@InProceedings{basroe_15,
+  Title                    = {{P}erformance and {P}roductivity of {P}arallel {P}ython {P}rogramming: {A} {S}tudy with a {CFD} {T}est {C}ase},
+  Author                   = {Achim Basermann and Melven R\"{o}hrig-Z\"{o}llner and Joachim Illner},
+  Booktitle                = {Proceedings of the 5th Workshop on Python for High-Performance and Scientific Computing},
+  Year                     = {2015},
+  Month                    = {Nov},
+  Pages                    = {2:1--2:10},
+  Publisher                = {ACM},
+  Series                   = {PyHPC '15},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.16}
+}
+
+@Article{bat_67,
+  Title                    = {{Ponderation des symboles decodes par l'agorithem de Viterbi}},
+  Author                   = {G. Battail},
+  Journal                  = {Ann. Telecommun.},
+  Year                     = {1967},
+
+  Month                    = jan,
+  Pages                    = {31--38},
+  Volume                   = {42},
+
+  Optnumber                = {N 1-2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{baujac_07,
+  Title                    = {{Error Resilient System Architecture (ERSA) for Probabilistic Applications}},
+  Author                   = {J. Bau and Q. Jacobson and R. Hankins and B. Saha and A. Tabatabai and S. Mitra},
+  Booktitle                = {IEEE Intl. Workshop on Silicon Errors in Logic -- System Effects},
+  Year                     = {2007},
+  Month                    = apr,
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Mitra
+- ERSA},
+  File                     = {baujac_07.pdf:baujac_07.pdf:PDF},
+  Keywords                 = {Reliability, LDPC},
+  Owner                    = {Brehm, may},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{baufra_98,
+  Title                    = {{A Comparison of Soft-In/Soft-Out Algorithms for ''Turbo-Detection''}},
+  Author                   = {Gerhard Bauch and Volker Franz},
+  Booktitle                = {Proc. International Conference on Telecommunications (ICT)},
+  Year                     = {1998},
+
+  Address                  = {Porto Carras, Greece},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bauhag_00,
+  Title                    = {{Turbo-TCM and Transmit Antenna Diversity in Multipath Fading Channels}},
+  Author                   = {G. Bauch and J. Hagenauer and N. Seshadri},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {189--192},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{baureu_12,
+  Title                    = {{On the Calculation of the Solvency Capital Requirement Based on Nested Simulations}},
+  Author                   = {Daniel Bauer and Andreas Reuss and Daniela Singer},
+  Journal                  = {ASTIN Bulletin},
+  Year                     = {2012},
+  Note                     = {{Cambridge University Press}},
+  Number                   = {2},
+  Pages                    = {453–499},
+  Volume                   = {42},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.08}
+}
+
+@MastersThesis{MTbauer12,
+  Title                    = {{F}ast {C}alibration in the {H}eston {M}odel},
+  Author                   = {Rudolf Bauer},
+  School                   = {Vienna University of Technology},
+  Year                     = {2012},
+  Month                    = feb,
+
+  Cds_grade                = {0},
+  Cds_keywords             = {finance, calibration, Heston},
+  File                     = {MTbauer12.pdf:MTbauer12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24},
+  Url                      = {\url{http://www.fam.tuwien.ac.at/~sgerhold/pub_files/theses/bauer.pdf}}
+}
+
+@InProceedings{Bayliss2006,
+  Title                    = {{A}n {FPGA} implementation of the simplex algorithm},
+  Author                   = {Bayliss, S. and Bouganis, C.-S. and Constantinides, G.A. and Luk, W.},
+  Booktitle                = {Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on},
+  Year                     = {2006},
+  Pages                    = {49-56},
+
+  Doi                      = {10.1109/FPT.2006.270294},
+  File                     = {baybou_06.pdf:baybou_06.pdf:PDF},
+  Keywords                 = {field programmable gate arrays;integer programming;linear programming;logic design;microprocessor chips;3.4 GHz;FPGA;Pentium 4 processor;Simplex algorithm;bounding engine;industrial optimization problems;integer linear programming framework;scientific computing applications;Application software;Computer industry;Engines;Field programmable gate arrays;Integer linear programming;Linear programming;Robustness;Scalability;Scientific computing;Software algorithms},
+  Owner                    = {Scholl},
+  Timestamp                = {2013.07.12}
+}
+
+@InProceedings{baycon_11,
+  Title                    = {{A}pplication {S}pecific {M}emory {A}ccess, {R}euse and {R}eordering for {SDRAM}},
+  Author                   = {Bayliss, Samuel and Constantinides, George A.},
+  Booktitle                = {Proceedings of the 7th International Conference on Reconfigurable Computing: Architectures, Tools and Applications},
+  Year                     = {2011},
+
+  Address                  = {Berlin, Heidelberg},
+  Pages                    = {41--52},
+  Publisher                = {Springer-Verlag},
+  Series                   = {ARC'11},
+
+  Acmid                    = {1987544},
+  ISBN                     = {978-3-642-19474-0},
+  Location                 = {Belfast, UK},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-07},
+  Url                      = {http://dl.acm.org/citation.cfm?id=1987535.1987544}
+}
+
+@Article{becmoy_16,
+  Title                    = {{Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study}},
+  Author                   = {Becker, Denis and Moy, Matthieu and Cornet, J{\'e}r{\^o}me},
+  Journal                  = {{Electronics}},
+  Year                     = {2016},
+
+  Month                    = May,
+  Number                   = {2},
+  Pages                    = {22},
+  Volume                   = {5},
+
+  Doi                      = {10.3390/electronics5020022},
+  File                     = {electronics-05-00022.pdf:https\://hal.archives-ouvertes.fr/hal-01321055/file/electronics-05-00022.pdf:PDF},
+  Hal_id                   = {hal-01321055},
+  Hal_version              = {v1},
+  Keywords                 = {hardware modeling ; parallelization ; simulation ; loose timing ; TLM ; SystemC},
+  Owner                    = {MJ},
+  Publisher                = {{MDPI}},
+  Timestamp                = {2018-09-11},
+  Url                      = {https://hal.archives-ouvertes.fr/hal-01321055}
+}
+
+@InProceedings{bec_08,
+  Title                    = {{A}daptive {R}eliable {C}hips - {R}econfigurable {C}omputing in the {N}ano {E}ra},
+  Author                   = {Becker, J.},
+  Booktitle                = {Proc. IEEE Computer Society Annual Symposium on VLSI ISVLSI '08},
+  Year                     = {2008},
+  Month                    = apr,
+  Pages                    = {1--2},
+
+  Doi                      = {10.1109/ISVLSI.2008.96},
+  File                     = {bec_08.pdf:bec_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{bechueb_07,
+  Title                    = {{D}ynamic and {P}artial {FPGA} {E}xploitation},
+  Author                   = {Jürgen Becker and Michael Hübner and Hettich, G. and Constapel, R. and Eisenmann, J. and Luka, J.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2007},
+
+  Month                    = {feb. },
+  Number                   = {2},
+  Pages                    = {438 -452},
+  Volume                   = {95},
+
+  Abstract                 = {Today's field programmable gate array (FPGA) architectures, like Xilinx's Virtex-II series, enable partial and dynamic run-time self-reconfiguration. This feature allows the substitution of parts of a hardware design implemented on this reconfigurable hardware, and therefore, a system can be adapted to the actual demands of applications running on the chip. Exploiting this possibility enables the development of adaptive hardware for a huge variety of applications. A novel method for communication interfaces using look up table (LUT)-based communication primitives enables an exact separation of reconfigurable parts and a fast and intelligent bus-system. A new adaptive software/hardware reconfigurable system is presented in this paper, using a real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA to present results},
+  Doi                      = {10.1109/JPROC.2006.888404},
+  ISSN                     = {0018-9219},
+  Owner                    = {CdS},
+  Timestamp                = {2011.09.27}
+}
+
+@InProceedings{becjin_11,
+  Title                    = {{D}ynamic {C}onstant {R}econfiguration for {E}xplicit {F}inite {D}ifference {O}ption {P}ricing},
+  Author                   = {Tobias Becker and Qiwei Jin and Wayne Luk and Weston, S.},
+  Booktitle                = {Reconfigurable Computing and FPGAs (ReConFig), 2011 International Conference on},
+  Year                     = {2011},
+  Month                    = dec,
+  Pages                    = {176--181},
+
+  Abstract                 = {This paper explores the reconfiguration of slowly changing constants in an explicit finite difference solver for option pricing. Numerical methods for option pricing, such as finite difference, are computationally very complex and can be aided by hardware acceleration. Such hardware implementations can be further improved by specialising the circuit for constants, and reconfiguring the circuit when the constants change. In this paper we demonstrate how this concept can be applied to the pricing of European and American options. We present an analytical optimisation approach that explores the benefit of specialised designs over a static one. The key to this approach is the performance and area estimation of kernels that is based on the parameters of arithmetic operators inside the kernel. This allows us to quickly explore several design options without building full designs. Our experimental results on a Xilinx XC6VLX760 FPGA show that with a partially reconfigurable design performance can be improved by a factor of 4.7 over a design without reconfiguration.},
+  Cds_grade                = {4},
+  Cds_keywords             = {option pricing, finite difference method, reconfiguration},
+  Doi                      = {10.1109/ReConFig.2011.29},
+  File                     = {becjin_11.pdf:becjin_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.28}
+}
+
+@InCollection{beebar_01,
+  Title                    = {{CRISP}: {A} {T}emplate for {R}econfigurable {I}nstruction {S}et {P}rocessors},
+  Author                   = {de Beeck, PieterOp and Barat, Francisco and Jayapala, Murali and Lauwereins, Rudy},
+  Booktitle                = {Field-Programmable Logic and Applications},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2001},
+  Editor                   = {Brebner, Gordon and Woods, Roger},
+  Pages                    = {296-305},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {2147},
+
+  Doi                      = {10.1007/3-540-44687-7_31},
+  ISBN                     = {978-3-540-42499-4},
+  Language                 = {English},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://dx.doi.org/10.1007/3-540-44687-7_31}
+}
+
+@InProceedings{bekdie_01,
+  Title                    = {{P}ower-efficient application-specific {VLIW} processor for turbo decoding},
+  Author                   = {Bekooij, M. and Dielissen, J. and Harmsze, F. and Sawitzki, S. and Huisken, J. and van der Weri, A. and van Meerbergen, J. },
+  Booktitle                = {Proc. Digest of Technical Papers Solid-State Circuits Conf. ISSCC. 2001 IEEE Int},
+  Year                     = {2001},
+  Pages                    = {180--181},
+
+  Doi                      = {10.1109/ISSCC.2001.912594},
+  File                     = {bekdie_01.pdf:bekdie_01.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.03.10}
+}
+
+@InProceedings{bel_01,
+  Title                    = {{Cooling and Power Considerations for Semiconductors Into the Next Century (Invited Talk)}},
+  Author                   = {C. Belady},
+  Booktitle                = {Proc. 2001 International Symposium on Low Power Electronics and Design (ISLPED '01)},
+  Year                     = {2001},
+
+  Address                  = {Huntington Beach, California, USA},
+  Month                    = aug,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{belnun_14,
+  Title                    = {{A}ccurate power control and monitoring in {ZYNQ} boards},
+  Author                   = {A. F. {Beldachi} and J. L. {Nunez-Yanez}},
+  Booktitle                = {2014 24th International Conference on Field Programmable Logic and Applications ({FPL})},
+  Year                     = {2014},
+  Month                    = {Sep.},
+  Pages                    = {1-4},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/FPL.2014.6927415},
+  ISSN                     = {1946-147X},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {field programmable gate arrays;microprocessor chips;power aware computing;power control;ZYNQ boards;dual-core ARM Cortex A9 processor;power scaling capabilities;of-the-shelf boards;fine-grained power control;monitoring techniques;power consumption;area overhead;FPGA device;voltage scaling techniques;processor domain;hybrid energy proportional computing platforms;Monitoring;Field programmable gate arrays;Voltage control;IP networks;Software;Process control;Hardware;Adaptive Voltage Scaling;Power analysis;FPGA;Xilinx;ZYNQ board},
+  Owner                    = {CCR}
+}
+
+@InProceedings{belrot_13,
+  Title                    = {{A} 1{G}bps {LTE}-advanced turbo-decoder {ASIC} in 65nm {CMOS}},
+  Author                   = {Belfanti, S. and Roth, C. and Gautschi, M. and Benkeser, C. and Qiuting Huang},
+  Booktitle                = {VLSI Circuits (VLSIC), 2013 Symposium on},
+  Year                     = {2013},
+  Month                    = {June},
+  Pages                    = {C284-C285},
+
+  Abstract                 = {This paper presents a turbo-decoder ASIC for 3GPP LTE-Advanced supporting all specified code rates and block sizes. The highly parallelized architecture employs 16 SISO decoders with an optimized state-metric initialization scheme that reduces SISO-decoder latency, which is key for achieving very-high throughput. A novel CRC implementation for parallel turbo decoding prevents the decoder from performing redundant turbo iterations. The 65nm ASIC achieves a record data throughput of 1.013Gbps at 5.5 iterations with unprecedented energy efficiency of 0.17nJ/bit/iter.},
+  File                     = {belrot_13.pdf:belrot_13.pdf:PDF},
+  Keywords                 = {3G mobile communication;Long Term Evolution;decoding;3GPP LTE advanced;CMOS;LTE advanced turbo decoder ASIC;SISO decoder latency;optimized state metric initialization scheme;parallel turbo decoding;redundant turbo iterations;size 65 nm;unprecedented energy efficiency;Application specific integrated circuits;Bit error rate;Decoding;Iterative decoding;Long Term Evolution;Throughput;ASIC implementation;CRC;LTE-Advanced;early termination;mobile communications;turbo decoder},
+  Owner                    = {StW},
+  Timestamp                = {2015.01.06}
+}
+
+@Article{bel_68,
+  Title                    = {{A}lgorithm 334: {N}ormal random deviates},
+  Author                   = {Bell, James R.},
+  Journal                  = {Commun. ACM},
+  Year                     = {1968},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {498--},
+  Volume                   = {11},
+
+  Acmid                    = {363547},
+  Address                  = {New York, NY, USA},
+  Cds_keywords             = {random number generation},
+  Doi                      = {10.1145/363397.363547},
+  File                     = {bel_68.pdf:bel_68.pdf:PDF},
+  ISSN                     = {0001-0782},
+  Issue_date               = {July 1968},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2012.03.22},
+  Url                      = {http://doi.acm.org/10.1145/363397.363547}
+}
+
+@InProceedings{belcha_06,
+  Title                    = {{FPGA} implementation of a license plate recognition {S}o{C} using automatically generated streaming accelerators},
+  Author                   = {Bellas, N. and Chai, S.M. and Dwyer, M. and Linzmeier, D.},
+  Booktitle                = {Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006)},
+  Year                     = {2006},
+  Month                    = {April},
+
+  Abstract                 = {Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based system on chip (SoC) that meet the applications requirements. The designer can customize the hardware by selecting from a large number of pre-defined peripherals and fixed IP functions and by providing new hardware, typically expressed using RTL. Hardware accelerators that provide application-specific extensions to the computational capabilities of a system is an efficient mechanism to enhance the performance and reduce the power dissipation. What is missing is an integrated approach to identify the computationally critical parts of the application and to create accelerators starting from a high level representation with a minimal design effort. In this paper, we present an automation methodology and a tool that generates accelerators. We apply the methodology on an FPGA-based license plate recognition (LPR) system used in law enforcement. The accelerators process streaming data and support a programming model which can naturally express a large number of embedded applications resulting in efficient hardware implementations. We show that we can achieve an overall LPR application speed up from 1.2times to 2.6times, thus enabling real-time functionality under realistic road scenes},
+  Cds_keywords             = {morphological filter, FPGA},
+  Cds_read                 = {2014-07-15},
+  Doi                      = {10.1109/IPDPS.2006.1639437},
+  File                     = {belcha_06.pdf:belcha_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.07.15}
+}
+
+@Article{belkav_10,
+  Title                    = {{L}ow-{C}omplexity {S}oft-{D}ecoding {A}lgorithms for {R}eed--{S}olomon {C}odes---{P}art {I}: {A}n {A}lgebraic {S}oft-{I}n {H}ard-{O}ut {C}hase {D}ecoder},
+  Author                   = {Bellorado, J. and Kavcic, A. },
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2010},
+  Number                   = {3},
+  Pages                    = {945--959},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TIT.2009.2039073},
+  File                     = {belkav_10.pdf:belkav_10.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{belkav_06,
+  Title                    = {{A} {L}ow-{C}omplexity {M}ethod for {C}hase-{T}ype {D}ecoding of {R}eed-{S}olomon {C}odes},
+  Author                   = {Bellorado, J. and Kavcic, A.},
+  Booktitle                = {Proc. IEEE Int Information Theory Symp},
+  Year                     = {2006},
+  Pages                    = {2037--2041},
+
+  Doi                      = {10.1109/ISIT.2006.261907},
+  File                     = {belkav_06.pdf:belkav_06.pdf:PDF},
+  Keywords                 = {Reed-Solomon, Chase, LCC, Soft},
+  Owner                    = {Scholl},
+  Review                   = {LCC (low compleyity chase) Algorithmus},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{belkav_10a,
+  Title                    = {{L}ow-{C}omplexity {S}oft-{D}ecoding {A}lgorithms for {R}eed--{S}olomon {C}odes---{P}art {II}: {S}oft-{I}nput {S}oft-{O}utput {I}terative {D}ecoding},
+  Author                   = {Bellorado, J. and Kavcic, A. and Marrow, M. and Li Ping},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2010},
+  Number                   = {3},
+  Pages                    = {960--967},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TIT.2009.2039091},
+  File                     = {belkav_10a.pdf:belkav_10a.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{belkav_07,
+  Title                    = {{S}oft-{I}nput, {I}terative, {R}eed-{S}olomon {D}ecoding using {R}edundant {P}arity-{C}heck {E}quations},
+  Author                   = {Bellorado, J. and Kavcic, A. and Li Ping},
+  Booktitle                = {Proc. IEEE Information Theory Workshop ITW '07},
+  Year                     = {2007},
+  Pages                    = {138--143},
+
+  Doi                      = {10.1109/ITW.2007.4313063},
+  File                     = {belkav_07.pdf:belkav_07.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{ben_00,
+  Title                    = {{Concatenated Codes with Interleavers: From Theoretical Understanding to Applications}},
+  Author                   = {S. Benedetto},
+  Booktitle                = {Alcatel Internal Workshop on Coding},
+  Year                     = {2000},
+
+  Address                  = {Antwerp, Belgium},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bendin_06,
+  Title                    = {{Design Issues on the Parallel implementation of Versatile, High speed iterative decoders}},
+  Author                   = {S. Benedetto and L. Dinoi and G. Montorsi and A. Tarable},
+  Booktitle                = {4th International Symposium on Turbo Codes},
+  Year                     = {2006},
+
+  Address                  = {Munich, Germany},
+  Month                    = apr,
+
+  File                     = {bendin_06.pdf:bendin_06.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bendiv_96b,
+  Title                    = {{Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding}},
+  Author                   = {S. Benedetto and D. Divsalar and G. Montorsi and F. Pollara},
+  Journal                  = {Information Theory, IEEE Transactions on},
+  Year                     = {1998},
+
+  Month                    = aug,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {909--926},
+  Volume                   = {44},
+
+  Optannote                = {SCCC},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bendiv_98,
+  Title                    = {{Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding}},
+  Author                   = {S. Benedetto and D. Divsalar and G. Montorsi and F. Pollara},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1998},
+
+  Month                    = may,
+  Number                   = {3},
+  Pages                    = {909--926},
+  Volume                   = {44},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bendiv_97,
+  Title                    = {{A Soft-Input Soft-Output APP Module for Iterative Decoding of Concatenated Codes}},
+  Author                   = {S. Benedetto and D. Divsalar and G. Montorsi and F. Pollara},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {1997},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {22--24},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bendiv_96,
+  Title                    = {{A Soft-Input Soft-Output Maximum A Posteriori (MAP) Module to Decode Parallel and Serial Concatenated Codes}},
+  Author                   = {S. Benedetto and D. Divsalar and G. Montorsi and F. Pollara},
+  Journal                  = {The Telecommunications and Data Acquisition Progress Report 42--127},
+  Year                     = {1996},
+
+  Month                    = nov,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {1--20},
+  Volume                   = {127},
+
+  Optannote                = {SISO module},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bendiv_96a,
+  Title                    = {{Algorithm for Continuous Decoding of Turbo Codes}},
+  Author                   = {S. Benedetto and D. Divsalar and G. Montorsi and F. Pollara},
+  Journal                  = {Electronics Letters},
+  Year                     = {1996},
+
+  Month                    = feb,
+  Number                   = {4},
+  Pages                    = {314--315},
+  Volume                   = {32},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bendiv_96c,
+  Title                    = {{Soft-Output Decoding Algorithms in Iterative Decoding of Turbo Codes}},
+  Author                   = {S. Benedetto and D. Divsalar and G. Montorsi and F. Pollara},
+  Journal                  = {The Telecommunications and Data Acquisition Progress Report 42--124},
+  Year                     = {1996},
+
+  Month                    = feb,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {63--87},
+  Volume                   = {124},
+
+  Optannote                = {sliding windwos etc., Log-MAP, Max-Log-MAP},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bendiv_96d,
+  Title                    = {{Parallel concatenated trellis coded modulation}},
+  Author                   = {S. Benedetto and D. Divsalar and G. Montorsi and F. Pollara},
+  Booktitle                = {Proc. 1996 International Conference on Communications (ICC '96)},
+  Year                     = {1996},
+  Month                    = jun,
+  Pages                    = {974--978},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{benmon_97,
+  Title                    = {{Performance of Continuous and Blockwise Decoded Turbo Codes}},
+  Author                   = {S. Benedetto and G. Montorsi},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {1997},
+
+  Month                    = may,
+  Number                   = {3},
+  Pages                    = {77--79},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{benmon_96,
+  Title                    = {{Design of Parallel Concatenated Convolutional Codes}},
+  Author                   = {S. Benedetto and G. Montorsi},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1996},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {591--600},
+  Volume                   = {44},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{benmon_96a,
+  Title                    = {{Unveiling Turbo Codes: Some Results on Parallel Concatenated Coding Schemes}},
+  Author                   = {S. Benedetto and G. Montorsi},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1996},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {409--428},
+  Volume                   = {42},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{benmon_95,
+  Title                    = {{Role of Recursive Convolutional Codes in Turbo Codes}},
+  Author                   = {S. Benedetto and G. Montorsi},
+  Journal                  = {Electronics Letters},
+  Year                     = {1995},
+
+  Month                    = may,
+  Number                   = {11},
+  Pages                    = {858--859},
+  Volume                   = {31},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{benmon_98,
+  Title                    = {{Soft-Input Soft-Output Modules for the Construction and Distributed Iterative Decoding of Code Networks}},
+  Author                   = {S. Benedetto and G. Montorsi and D. Divsalar and F. Pollara},
+  Journal                  = {European Transactions on Telecommunications (ETT)},
+  Year                     = {1998},
+
+  Month                    = mar # {--} # apr,
+  Number                   = {2},
+  Pages                    = {155--172},
+  Volume                   = {9},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{Benes1964,
+  Title                    = {{O}ptimal {R}earrangeable {M}ultistage {C}onnecting {N}etworks},
+  Author                   = {V. E. Benes},
+  Journal                  = {The Bell System Technical Journal},
+  Year                     = {1964},
+  Volume                   = {4},
+
+  Annote                   = {vorh.1x,},
+  By_date                  = {GKn},
+  By_rev                   = {Le},
+  Country                  = {USA},
+  Date                     = {13/06/89},
+  Descriptors              = {Link system;},
+  Enum                     = {5437},
+  Language                 = {English},
+  Location                 = {TE-TN-S},
+  Owner                    = {Scholl},
+  References               = {0},
+  Revision                 = {19/12/93},
+  Timestamp                = {2013.12.12}
+}
+
+@InProceedings{ben_06,
+  Title                    = {{A}pplication {S}pecific {N}o{C} {D}esign},
+  Author                   = {Luca Benini},
+  Booktitle                = {Design, Automation and Test in Europe, 2006. DATE '06. Proceedings},
+  Year                     = {2006},
+  Month                    = mar,
+  Pages                    = {1 -5},
+  Publisher                = {IEEE Computer Society},
+  Volume                   = {1},
+
+  Abstract                 = {Scalable networks on chips (NoCs) are needed to match the ever-increasing communication demands of large-scale multi-processor systems-on-chip (MPSoCs) for high-end wireless communications applications. The heterogeneous nature of on-chip cores and the energy efficiency requirements typical of wireless communications call for application-specific NoCs which eliminate much of the overheads connected with general-purpose communication architectures. However, application-specific NoCs must be supported by adequate design flows to reduce design time and effort. In this paper we survey the main challenges in application-specific NoC design, and we outline a complete NoC design flow and methodology. A case study on a high complexity SoC demonstrates that it is indeed possible to generate an application-specific NoC from a high level specification in a few hours. Comparison with a hand-tuned solution shows that the automatically generated one is very competitive from the area, performance and power viewpoint, while design time is reduced from days to hours},
+  Cds_grade                = {0},
+  Cds_keywords             = {NoC},
+  Doi                      = {10.1109/DATE.2006.243857},
+  File                     = {ben_06.pdf:ben_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2011.02.07}
+}
+
+@Article{benmic_02,
+  Title                    = {{Networks on Chips: A New SoC Paradigm}},
+  Author                   = {Benini, L. and De Micheli, G.},
+  Journal                  = {IEEE Computer},
+  Year                     = {2002},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {70--78},
+  Volume                   = {35},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{benmic_01,
+  Title                    = {{Powering Networks on Chips}},
+  Author                   = {Benini, L. and De Micheli, G.},
+  Booktitle                = {Proceedings of the 14th International Symposium on System Synthesis, 2001},
+  Year                     = {2001},
+  Pages                    = {33--38},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{benmic_98,
+  Title                    = {{Dynamic Power Management Design Techniques and CAD Tools}},
+  Author                   = {Benini, L. and De Micheli, G.},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {1998},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{benmic_98a,
+  Title                    = {{Address Bus Encoding Techniques for System-Level Power Optimization}},
+  Author                   = {L. Benini and De Micheli, G. and E. Macii and D. Sciuto and C. Silvano},
+  Booktitle                = {{Proc. 1998 Design, Automation and Test in Europe (DATE '98)}},
+  Year                     = {1998},
+
+  Address                  = {Paris, France},
+  Month                    = feb,
+  Pages                    = {861--866},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{benbur_09,
+  Title                    = {{D}esign and {O}ptimization of an {HSDPA} {T}urbo {D}ecoder {ASIC}},
+  Author                   = {Benkeser, C. and Burg, A. and Cupaiuolo, T. and Qiuting Huang},
+  Journal                  = {IEEE Journal of Silid-State Circuits},
+  Year                     = {2009},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {98--106},
+  Volume                   = {44},
+
+  Doi                      = {10.1109/JSSC.2008.2007166},
+  File                     = {benbur_09.pdf:benbur_09.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.16}
+}
+
+@InProceedings{benbur_08,
+  Title                    = {{A} 58m{W} 1.2mm$^2$ {HSDPA} {T}urbo {D}ecoder {ASIC} in 0.13$\mu$m {CMOS}},
+  Author                   = {Benkeser, C. and Burg, A. and Cupaiuolo, T. and Qiuting Huang},
+  Booktitle                = {Proc. Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008},
+  Year                     = {2008},
+  Month                    = feb,
+  Pages                    = {264--612},
+
+  Doi                      = {10.1109/ISSCC.2008.4523158},
+  File                     = {benbur_08.pdf:benbur_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{benlan_07,
+  Title                    = {{T}he netflix prize},
+  Author                   = {Bennett, James and Lanning, Stan},
+  Booktitle                = {Proceedings of KDD cup and workshop},
+  Year                     = {2007},
+  Pages                    = {35},
+  Volume                   = {2007},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.12.01}
+}
+
+@InProceedings{berbin_99,
+  Title                    = {{Performance of Low Complexity Turbo-Codes in the UTRA-TDD-Mode}},
+  Author                   = {F. Berens and T. Bing and H. Michel and A. Worm and P. W. Baier},
+  Booktitle                = {Proc. 1999-Fall Vehicular Technology Conference (VTC Fall '99)},
+  Year                     = {1999},
+
+  Address                  = {Amsterdam, The Netherlands},
+  Month                    = sep,
+  Pages                    = {2621--2625},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Patent{ber_09a,
+  Title                    = {{M}ethod and device for decoding a received systematic code encoded block},
+  Nationality              = {Europe},
+  Number                   = {EP2066056},
+  Year                     = {2009},
+  Yearfiled                = {2010},
+  Author                   = {Berens, Friedbert AND Derdiyok, Cem AND Kienle, Frank AND Lehnigk-Emden, Timo AND Wehn, Norbert},
+  Month                    = jun,
+  Url                      = {http://www.freepatentsonline.com/EP2066056A1.html},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.18}
+}
+
+@InProceedings{berkre_04,
+  Title                    = {{C}hannel {D}ecoder {A}rchitecture for 3{G} {M}obile {W}ireless {T}erminals},
+  Author                   = {F. Berens and G. Kreiselmaier and N. Wehn},
+  Booktitle                = {Proc. 2004 Design, Automation and Test in Europe (DATE '04)},
+  Year                     = {2004},
+
+  Address                  = {Paris, France},
+  Month                    = feb,
+
+  File                     = {berkre_04.pdf:berkre_04.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{berdistributed02,
+  Title                    = {{Distributed device for concurrent interleaving}},
+
+  Author                   = {F. Berens and M. Thul and F. Gilbert and N. Wehn},
+  HowPublished             = {Patent Application},
+  Month                    = sep,
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{berelectronic02,
+  Title                    = {{Electronic Device Avoiding Write Access Conflicts in Interleaving, in Particular Optimized Concurrent Interleaving Architecture for High-Throughput Turbo-Decoding}},
+
+  Author                   = {F. Berens and M. Thul and F. Gilbert and N. Wehn},
+  HowPublished             = {US Patent Application},
+  Month                    = dec,
+  Year                     = {2002},
+
+  Optnote                  = {Larger claims than in the European Patent Application},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{berelectronic02a,
+  Title                    = {{Electronic Device Avoiding Write Access Conflicts in Interleaving, in Particular Optimized Concurrent Interleaving Architecture for High-Throughput Turbo-Decoding}},
+
+  Author                   = {F. Berens and M. Thul and F. Gilbert and N. Wehn},
+  HowPublished             = {European Patent Application No.02292244.7},
+  Month                    = sep,
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Berens2002,
+  Title                    = {{Distributed device for concurrent interleaving}},
+
+  Author                   = {F. Berens and M. Thul and F. Gilbert and N. Wehn},
+  HowPublished             = {Patent Application},
+  Month                    = sep,
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Berens2002a,
+  Title                    = {{Electronic Device Avoiding Write Access Conflicts in Interleaving, in Particular Optimized Concurrent Interleaving Architecture for High-Throughput Turbo-Decoding}},
+
+  Author                   = {F. Berens and M. Thul and F. Gilbert and N. Wehn},
+  HowPublished             = {US Patent Application},
+  Month                    = dec,
+  Year                     = {2002},
+
+  Optnote                  = {Larger claims than in the European Patent Application},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Berens2002b,
+  Title                    = {{Electronic Device Avoiding Write Access Conflicts in Interleaving, in Particular Optimized Concurrent Interleaving Architecture for High-Throughput Turbo-Decoding}},
+
+  Author                   = {F. Berens and M. Thul and F. Gilbert and N. Wehn},
+  HowPublished             = {European Patent Application No.02292244.7},
+  Month                    = sep,
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Berens2004a,
+  Title                    = {{Method and apparatus for turbo-encoding and turbo-decoding blocks of data with a controllable latency decoding, in particular for a wireless communication system of the WLAN or WPAN type}},
+
+  Author                   = {F. Berens and N. Wehn and F. Kienle and M. Thul and T. Vogt},
+  HowPublished             = {European Patent Application No.04 290 805.3},
+  Month                    = mar,
+  Year                     = {2004},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{bermethod04,
+  Title                    = {{Method and apparatus for turbo-encoding and turbo-decoding blocks of data with a controllable latency decoding, in particular for a wireless communication system of the WLAN or WPAN type}},
+
+  Author                   = {F. Berens and N. Wehn and F. Kienle and M. Thul and T. Vogt},
+  HowPublished             = {European Patent Application No.04 290 805.3},
+  Month                    = mar,
+  Year                     = {2004},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{berwor_99,
+  Title                    = {{Implementation Aspects of Turbo-Decoders for Future Radio Applications}},
+  Author                   = {Friedbert Berens and Alexander Worm and Heiko Michel and Norbert Wehn},
+  Booktitle                = {Proc. VTC 1999 - Fall Vehicular Technology Conference IEEE VTS 50th},
+  Year                     = {1999},
+  Month                    = sep,
+  Pages                    = {2601--2605},
+  Volume                   = {5},
+
+  Abstract                 = {Turbo-Codes will most likely be employed in future radio systems as a channel coding scheme for highrate data services. However, Turbo-Decoding is a comparatively complex task. To obtain efficient decoder implementations, the system design space has to be explored on multiple levels. In this paper, we span the system design space for Turbo-Codes and describe a method of exploration, while focusing on the implementation-dependent part. The design decisions taken during exploration are rated regarding complexity, throughput and power consumption. The second part of our paper evaluates sample software and hardware implementations of a 2Mbits Turbo-Decoder.},
+  Cds_grade                = {4},
+  Cds_read                 = {2008-11-28},
+  Cds_review               = {general overview over Turbo Decoder design space exploration
+very high level},
+  Doi                      = {10.1109/VETECF.1999.800257},
+  File                     = {berwor_99.pdf:berwor_99.pdf:PDF},
+  Grade                    = {4},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Review                   = {CG:
+Gelesen am: 22.10.2008
+Design Space Exploration of Turbo Decoders, Lehrstuhl-Paper},
+  Timestamp                = {2008.10.22}
+}
+
+@InProceedings{bermuel_10,
+  Title                    = {{U}niform sampling of digraphs with a fixed degree sequence},
+  Author                   = {Berger, Annabell and Müller-Hannemann, Matthias},
+  Booktitle                = {Graph theoretic concepts in computer science},
+  Year                     = {2010},
+  Organization             = {Springer},
+  Pages                    = {220--231},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.08.09}
+}
+
+@Article{ber_61,
+  Title                    = {{A} note on error detection codes for asymmetric channels},
+  Author                   = {Berger, J. M.},
+  Journal                  = {Information and Control},
+  Year                     = {1961},
+  Number                   = {1},
+  Pages                    = {68--73},
+  Volume                   = {4},
+
+  Publisher                = {Elsevier}
+}
+
+@InProceedings{berler_15,
+  Title                    = {{P}artial sums computation in polar codes decoding},
+  Author                   = {G. Berhault and C. Leroux and C. Jego and D. Dallet},
+  Booktitle                = {Circuits and Systems (ISCAS), 2015 IEEE International Symposium on},
+  Year                     = {2015},
+  Month                    = {May},
+  Pages                    = {826-829},
+
+  Doi                      = {10.1109/ISCAS.2015.7168761},
+  Keywords                 = {decoding;error correction codes;matrix algebra;channel capacity;decoder architectures;first error correcting codes;formalized architectures;generator matrix;infinite code lengths;matrix multiplication;partial sums computation unit;polar codes decoding;Computer architecture;Decoding;Error correction codes;Hardware;Indexes;Multiplexing;Signal processing;FEC;hardware architecture;polar codes;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{berler_15a,
+  Title                    = {{H}ardware implementation of a soft cancellation decoder for polar codes},
+  Author                   = {G. Berhault and C. Leroux and C. Jego and D. Dallet},
+  Booktitle                = {2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)},
+  Year                     = {2015},
+  Month                    = {Sept},
+  Pages                    = {1-8},
+
+  Abstract                 = {Polar Codes can provably achieve the capacity of discrete memoryless channels. In order to make practical, it is necessary to propose efficient hardware decoder architectures. In this paper, the first hardware decoder architecture implementing the Soft-output CANcellation (SCAN) decoding algorithm, is presented. This decoder was implemented on Field Programmable Gate Array (FPGA) devices. The proposed architecture is parametrizable for any number of iterations without adding hardware complexity. The SCAN decoder architecture is compared to another soft-output decoder that implements a Belief Propagation (BP) algorithm. The SCAN decoder can reach a higher throughput than a BP decoder, with a lower memory footprint. Moreover, only one iteration with the SCAN algorithm leads to better decoding performance than 50 iterations of the BP algorithm.},
+  Doi                      = {10.1109/DASIP.2015.7367252},
+  File                     = {berler_15a.pdf:berler_15a.pdf:PDF},
+  Keywords                 = {codecs;codes;decoding;field programmable gate arrays;iterative methods;logic design;BP algorithm;BP decoder;FPGA devices;SCAN decoder architecture;SCAN decoding algorithm;belief propagation;discrete memoryless channels;field programmable gate array;hardware decoder architectures;polar codes;soft cancellation decoder;soft-output cancellation;Computer architecture;Decoding;Encoding;Hardware;Iterative decoding;Logic gates;Systematics},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-30}
+}
+
+@InProceedings{ber_09,
+  Title                    = {{M}ulti-core for mobile phones},
+  Author                   = {van Berkel, C. H.},
+  Booktitle                = {Proc. DATE '09. Design, Automation. Test in Europe Conference. Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {1260--1265},
+
+  Owner                    = {Kienle},
+  Timestamp                = {2009.11.16}
+}
+
+@Article{bercab_18,
+  Title                    = {{A} modeling and distributed {MPC} approach for water distribution networks},
+  Author                   = {Felix Berkel and Sebastian Caba and Jonas Bleich and Steven Liu},
+  Journal                  = {Control Engineering Practice},
+  Year                     = {2018},
+  Pages                    = {199 - 206},
+  Volume                   = {81},
+
+  Ccr_grade                = {n.a.},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {https://doi.org/10.1016/j.conengprac.2018.09.017},
+  ISSN                     = {0967-0661},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {Model predictive control, Drinking water networks, Distributed control, Event-triggered communication, Economic model predictive control},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0967066118305641}
+}
+
+@Misc{Berkeley2002,
+  Title                    = {{MICA}2 platform: http://tinyos.net/scoop/special/hardware},
+
+  Author                   = {UC Berkeley},
+  Year                     = {2002},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://tinyos.net/scoop/special/hardware}
+}
+
+@Misc{Berkeley2002a,
+  Title                    = {{M}ica2{D}ot platform: http://tinyos.net/scoop/special/hardware},
+
+  Author                   = {UC Berkeley},
+  Year                     = {2002},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://tinyos.net/scoop/special/hardware}
+}
+
+@Misc{Berkeley2002b,
+  Title                    = {{MICA}z platform: http://docs.tinyos.net/index.php/{M}ica{Z}},
+
+  Author                   = {UC Berkeley},
+  Year                     = {2002},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://docs.tinyos.net/index.php/MicaZ}
+}
+
+@Misc{mica2,
+  Title                    = {{MICA}2 platform: http://tinyos.net/scoop/special/hardware},
+
+  Author                   = {UC Berkeley},
+  Year                     = {2002},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://tinyos.net/scoop/special/hardware}
+}
+
+@Misc{mica2dot,
+  Title                    = {{M}ica2{D}ot platform: http://tinyos.net/scoop/special/hardware},
+
+  Author                   = {UC Berkeley},
+  Year                     = {2002},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://tinyos.net/scoop/special/hardware}
+}
+
+@Misc{micaz,
+  Title                    = {{MICA}z platform: http://docs.tinyos.net/index.php/{M}ica{Z}},
+
+  Author                   = {UC Berkeley},
+  Year                     = {2002},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://docs.tinyos.net/index.php/MicaZ}
+}
+
+@Misc{Berkeley1999,
+  Title                    = {{T}iny{OS} wiki: http://tinyos.net/},
+
+  Author                   = {UC Berkeley},
+  Year                     = {1999},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://tinyos.net/}
+}
+
+@Misc{tinyos,
+  Title                    = {{T}iny{OS} wiki: http://tinyos.net/},
+
+  Author                   = {UC Berkeley},
+  Year                     = {1999},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://tinyos.net/}
+}
+
+@Article{ber_98,
+  Title                    = {{On turbo decoding of nonbinary codes}},
+  Author                   = {Jens Berkmann},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {1998},
+
+  Month                    = apr,
+  Pages                    = {94-96},
+  Volume                   = {2},
+
+  File                     = {ber_98.pdf:ber_98.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bercar_08,
+  Title                    = {{O}n 3{G} {LTE} {T}erminal {I}mplementation - {S}tandard, {A}lgorithms, {C}omplexities and {C}hallenges},
+  Author                   = {Berkmann, J. and Carbonelli, C. and Dietrich, F. and Drewes, C. and Wen Xu},
+  Booktitle                = {Proc. International Wireless Communications and Mobile Computing Conference IWCMC '08},
+  Year                     = {2008},
+  Month                    = aug,
+  Pages                    = {970--975},
+
+  Doi                      = {10.1109/IWCMC.2008.168},
+  File                     = {bercar_08.pdf:bercar_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.12}
+}
+
+@Article{bermce_78,
+  Title                    = {{O}n the inherent intractability of certain coding problems ({C}orresp.)},
+  Author                   = {Berlekamp, E. and McEliece, R. and van Tilborg, H. },
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1978},
+  Number                   = {3},
+  Pages                    = {384--386},
+  Volume                   = {24},
+
+  Doi                      = {10.1109/TIT.1978.1055873},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.02.07}
+}
+
+@Misc{Bernemann2011,
+  Title                    = {{A}ccelerating {E}xotic {O}ption {P}ricing and {M}odel {C}alibration {U}sing {GPU}s},
+
+  Author                   = {André Bernemann and Ralph Schreyer and Klaus Spanderen},
+  Month                    = feb,
+  Year                     = {2011},
+
+  Abstract                 = {Pricing and risk analysis for today's exotic structured equity products is computationally more and more demanding and time consuming. GPUs offer the possibility to significantly increase computing performance even at reduced costs. We applied this technology to replace a large amount of our CPU based computing grid by hybrid GPU/CPU pricing engines. 
+
+One GPU based pricing engine with two Tesla C1060 replaced 140 CPU cores in performing Monte Carlo based simulation of our productive structured equity portfolio with the local and stochastic volatility models. Instantaneous calibration of the piecewise timedependent Heston model on a single GPU is enabled.},
+  Address                  = {Herzogstrasse 17
+Düsseldorf 40217
+Germany},
+  Cds_grade                = {5},
+  Cds_keywords             = {Heston, GPU, calibration, exotic option pricing, quasi-random numbers, Sobol sequences},
+  Cds_read                 = {2012-03-05},
+  Cds_review               = {considers exotic option pricing and Heston model calibration; hybrid CPU-GPU approach on top of QuantLib; also considering multi-asset options; invesitgates different random number generators (Hybrid Taus, Mersenne Twister, Sobol sequences); compares against multi-threaded optimized C++ model with SSE2},
+  File                     = {bersch_11.pdf:bersch_11.pdf:PDF},
+  Keywords                 = {finance},
+  Language                 = {en},
+  Organization             = {WestLB et al.},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.26},
+  Url                      = {http://ssrn.com/abstract=1753596}
+}
+
+@Article{bersch_11,
+  Title                    = {{A}ccelerating {E}xotic {O}ption {P}ricing and {M}odel {C}alibration {U}sing {GPU}s},
+  Author                   = {Bernemann, Andr{\'e} and Schreyer, Ralph and Spanderen, Klaus},
+  Journal                  = {Available at SSRN 1753596},
+  Year                     = {2011},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.09.17}
+}
+
+@InProceedings{bersch_10,
+  Title                    = {{P}ricing {S}tructured {E}quity {P}roducts on {GPU}s},
+  Author                   = {André Bernemann and Ralph Schreyer and Klaus Spanderen},
+  Booktitle                = {High Performance Computational Finance (WHPCF), 2010 IEEE Workshop on},
+  Year                     = {2010},
+  Month                    = nov,
+  Pages                    = {1--7},
+
+  Abstract                 = {Pricing and risk analysis for today's structured equity products is computationally more and more demanding and time consuming. GPUs offer the possibility to significantly increase computing performance even at reduced costs. We applied this technology to replace a large amount of our CPU based computing grid by hybrid GPU/CPU pricing engines. One GPU based pricing engine with two Tesla C1060 replaced 140 CPU cores in performing Monte Carlo based simulation of our productive structured equity portfolio with the local and stochastic volatility model.},
+  Cds_grade                = {5},
+  Cds_keywords             = {GPU, Heston, speed comparison, CUDA},
+  Cds_read                 = {2011-11-11},
+  Cds_review               = {hybrid CPU-GPU approach on top of QuantLib, detailed implementations for Heston and Heston Hull-White with CUDA
+
++ detailed speed numbers
+- no numbers for energy},
+  Doi                      = {10.1109/WHPCF.2010.5671821},
+  File                     = {bersch_10.pdf:bersch_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.01.06}
+}
+
+@Article{ber_03,
+  Title                    = {{The Ten-Year-Old Turbo Codes are Entering into Service}},
+  Author                   = {C. Berrou},
+  Journal                  = {IEEE Communications Magazine},
+  Year                     = {2003},
+
+  Month                    = aug,
+  Pages                    = {110--116},
+  Volume                   = {41},
+
+  File                     = {ber_03.pdf:ber_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{beradd_93,
+  Title                    = {{A Low Complexity Soft-Output Viterbi Decoder Architecture}},
+  Author                   = {C. Berrou and P. Adde and E. Angui and S. Faudeil},
+  Booktitle                = {Proc. 1993 International Conference on Communications (ICC '93)},
+  Year                     = {1993},
+
+  Address                  = {Geneva, Switzerland},
+  Month                    = may,
+  Pages                    = {737--740},
+
+  Keywords                 = {Convolutional},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bercom_95,
+  Title                    = {{An IC for Turbo-Codes Encoding and Decoding}},
+  Author                   = {C. Berrou and P. Combelles and P. Pénard and B. Talibart},
+  Booktitle                = {Proc. 1995 International Solid-State Circuits Conference (ISSCC '95)},
+  Year                     = {1995},
+  Pages                    = {90--91},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bergla_96,
+  Title                    = {{Near Optimum Error Correcting Coding and Decoding}},
+  Author                   = {C. Berrou and A. Glavieux},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1996},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {1261--1271},
+  Volume                   = {44},
+
+  Optnote                  = {Slightly enhanced version of the ICC '93 paper},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bergla_93,
+  Title                    = {{Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes}},
+  Author                   = {C. Berrou and A. Glavieux and P. Thitimajshima},
+  Booktitle                = {Proc. 1993 International Conference on Communications (ICC '93)},
+  Year                     = {1993},
+
+  Address                  = {Geneva, Switzerland},
+  Month                    = may,
+  Pages                    = {1064--1070},
+
+  Abstract                 = {A new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed. The turbo-code encoder is built using a parallel concatenation of two recursive systematic convolutional codes, and the associated decoder, using a feedback decoding rule, is implemented as P pipelined identical elementary decoders},
+  File                     = {bergla_93.pdf:bergla_93.pdf:PDF},
+  Keywords                 = {Turbo},
+  Optnote                  = {Original Turbo-Code paper},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bergra_07,
+  Title                    = {{Adding a Rate-1 Third Dimension to Turbo Codes}},
+  Author                   = {Berrou, C. and Graell i Amat, A. and Ould Cheikh Mouhamedou, Y. and Douillard, C. and Saouter, Y.},
+  Booktitle                = {Proc. IEEE Information Theory Workshop ITW '07},
+  Year                     = {2007},
+  Month                    = sep,
+  Pages                    = {156--161},
+
+  Doi                      = {10.1109/ITW.2007.4313066},
+  File                     = {bergra_07.pdf:bergra_07.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.12.18}
+}
+
+@Article{berjez_99,
+  Title                    = {{Non-Binary Convolutional Codes for Turbo Coding}},
+  Author                   = {C. Berrou and M. J\'{e}z\'{e}quel},
+  Journal                  = {Electronic Letters},
+  Year                     = {1999},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {39-40},
+  Volume                   = {35},
+
+  File                     = {berjez_99.pdf:berjez_99.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{berjez_01,
+  Title                    = {{The Advantages of Non-Binary Turbo Codes}},
+  Author                   = {C. Berrou and M. J\'{e}z\'{e}quel and C. Doullard and S. Kerouedan},
+  Booktitle                = {Proceedings of Information Theory Workshop},
+  Year                     = {2001},
+
+  Address                  = {Cairns, Australia},
+  Month                    = sep,
+  Pages                    = {61-63},
+
+  File                     = {berjez_01.pdf:berjez_01.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bermau_03,
+  Title                    = {{Which Minimum Hamming Distance Do We Really Need}},
+  Author                   = {C. Berrou and E.A. Maury and H. Gonzalez},
+  Booktitle                = {Proc. 3rd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {141--148},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Berrou2004,
+  Title                    = {{D}esigning good permutations for turbo codes: towards a single model},
+  Author                   = {Berrou, C. and Saouter, Y. and Douillard, C. and Kerouedan, S. and J\'{e}z\'{e}quel, M.},
+  Booktitle                = {Proc. IEEE International Conference on Communications},
+  Year                     = {2004},
+  Month                    = jun,
+  Pages                    = {341--345},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ICC.2004.1312507},
+  Owner                    = {punekar},
+  Timestamp                = {2009.09.04}
+}
+
+@InProceedings{bersao_04,
+  Title                    = {{Designing good permutations for turbo codes: toward a single model}},
+  Author                   = {C. Berrou AND Y. Saouter AND C. Douillard AND S. Kerouedan AND M. J\'{e}z\'{e}quel},
+  Booktitle                = {Proceedings of ICC 2004},
+  Year                     = {2004},
+  Month                    = jun,
+  Pages                    = {341-345},
+  Volume                   = {1},
+
+  File                     = {bersao_04.pdf:bersao_04.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bervat_02,
+  Title                    = {{Computing the Minimum Distance of Linear Codes by the Error Impulse Method}},
+  Author                   = {C. Berrou and S. Vaton and M. J\'{e}z\'{e}quel and C. Douillard},
+  Booktitle                = {Proc. 2002 IEEE International Symposium on Information Theory (ISIT)},
+  Year                     = {2002},
+
+  Address                  = {Lausanne, Switzerland},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{berche_89,
+  Title                    = {{T}he {P}erfect {C}lub {B}enchmarks: {E}ffective {P}erformance {E}valuation of {S}upercomputers},
+  Author                   = {Berry, M. and Chen, D. and Koss, P. and Kuck, D. and Lo, S. and Pang, Y. and Pointer, L. and Roloff, R. and Sameh, A. and Clementi, E. and Chin, S. and Schneider, D. and Fox, G. and Messina, P. and Walker, D. and Hsiung, C. and Schwarzmeier, J. and Lue, K. and Orszag, S. and Seidl, F. and Johnson, O. and Goodrum, R. and Martin, J.},
+  Journal                  = {International Journal of High Performance Computing Applications},
+  Year                     = {1989},
+  Number                   = {3},
+  Pages                    = {5-40},
+  Volume                   = {3},
+
+  Abstract                 = {This report presents a methodology for measuring the performance of supercomputers. It includes 13 Fortran programs that total over 50,000 lines of source code. They represent applications in several areas of engi neering and scientific computing, and in many cases the codes are currently being used by computational re search and development groups. We also present the PERFECT Fortran standard, a set of guidelines that allow portability to several types of machines. Furthermore, we present some performance measures and a method ology for recording and sharing results among diverse users on different machines. The results presented in this paper should not be used to compare machines, except in a preliminary sense. Rather, they are presented to show how the methodology has been applied, and to encourage others to join us in this effort. The results should be regarded as the first step toward our objec tive, which is to develop a publicly accessible data base of performance information of this type.},
+  Cds_grade                = {0},
+  Cds_keywords             = {HPC, benchmarking},
+  Doi                      = {10.1177/109434208900300302},
+  Eprint                   = {http://hpc.sagepub.com/content/3/3/5.full.pdf+html},
+  File                     = {berche_89.pdf:berche_89.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.05.08},
+  Url                      = {http://hpc.sagepub.com/content/3/3/5.abstract}
+}
+
+@Article{bersim_10,
+  Title                    = {{HA}rtes: {H}ardware-software codesign for heterogeneous multicore platforms},
+  Author                   = {Bertels, Koen and Sima, Vlad-Mihai and Yankova, Yana and Kuzmanov, Georgi and Luk, Wayne and Coutinho, Gabriel and Ferrandi, Fabrizio and Pilato, Christian and Lattuada, Marco and Sciuto, Donatella and others},
+  Journal                  = {IEEE micro},
+  Year                     = {2010},
+  Number                   = {5},
+  Pages                    = {88--97},
+  Volume                   = {30},
+
+  Owner                    = {Brugger},
+  Publisher                = {Citeseer},
+  Timestamp                = {2015.04.30}
+}
+
+@Article{berdia_91,
+  Title                    = {{M}odeling and verification of time dependent systems using time {P}etri nets},
+  Author                   = {B. Berthomieu and M. Diaz},
+  Journal                  = {IEEE Transactions on Software Engineering},
+  Year                     = {1991},
+
+  Month                    = {Mar},
+  Number                   = {3},
+  Pages                    = {259-273},
+  Volume                   = {17},
+
+  Doi                      = {10.1109/32.75415},
+  ISSN                     = {0098-5589},
+  Keywords                 = {Petri nets;formal specification;parallel programming;program verification;protocols;alternating bit protocol;communication systems;concurrent systems;explicit values;formal verification;specification;time Petri nets;time dependent systems;time-dependent systems;verification;Fires;Petri nets;Protocols;Reachability analysis},
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-27}
+}
+
+@Article{berdel_19,
+  Title                    = {{S}ytare: {A} {L}ightweight {K}ernel for {NVRAM}-{B}ased {T}ransiently-{P}owered {S}ystems},
+  Author                   = {G. {Berthou} and T. {Delizy} and K. {Marquet} and T. {Risset} and G. {Salagnac}},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2019},
+
+  Month                    = {Sep.},
+  Number                   = {9},
+  Pages                    = {1390-1403},
+  Volume                   = {68},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {interesting},
+  Ccr_key_original         = {8585137},
+  Ccr_keywords             = {CP for (non-)trivial peripherals},
+  Ccr_topic                = {ATC, CP},
+  Doi                      = {10.1109/TC.2018.2889080},
+  ISSN                     = {0018-9340},
+  Keywords                 = {TCS},
+  Keywords_original        = {Nonvolatile memory;Random access memory;Checkpointing;Embedded systems;Batteries;Sensors;Kernel;Embedded systems;NVRAM;energy harvesting;low-power;wireless sensor networks;internet of things},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27}
+}
+
+@InProceedings{berdel_17,
+  Title                    = {{P}eripheral state persistence for transiently-powered systems},
+  Author                   = {G. Berthou and T. Delizy and K. Marquet and T. Risset and G. Salagnac},
+  Booktitle                = {2017 Global Internet of Things Summit (GIoTS)},
+  Year                     = {2017},
+  Month                    = {June},
+  Pages                    = {1-6},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8016243},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/GIOTS.2017.8016243},
+  Keywords                 = {TCS},
+  Keywords_original        = {analogue-digital conversion;checkpointing;embedded systems;energy harvesting;peripheral interfaces;power aware computing;random-access storage;analog-to-digital converters;checkpointing techniques;energy harvesting;nonvolatile memory;peripheral state;peripheral state persistence;power failures;program state checkpoints;radio devices;serial interfaces;tiny battery-less embedded systems;transiently-powered systems;Checkpointing;Data structures;Hardware;Kernel;Nonvolatile memory;Random access memory},
+  Owner                    = {CCR}
+}
+
+@Article{Bertossi1987,
+  Title                    = {{A} {VLSI} {I}mplementation of the {S}implex {A}lgorithm},
+  Author                   = {Bertossi, A. and Bonuccelli M.},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {1987},
+  Number                   = {2},
+  Pages                    = {241--247},
+  Volume                   = {C-36},
+
+  Doi                      = {10.1109/TC.1987.1676889},
+  File                     = {berbon_87.pdf:berbon_87.pdf:PDF},
+  Keywords                 = {LPDecoding},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.08},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1676889}
+}
+
+@Article{berben_05,
+  Title                    = {{Error Control Schemes for On-chip Communication Links: The Energy-Reliability Trade-Off}},
+  Author                   = {Bertozzi, D. and Benini, L. and De Micheli, G.},
+  Journal                  = {IEEE Transactions on CAD},
+  Year                     = {2005},
+  Number                   = {6},
+  Pages                    = {818--831},
+  Volume                   = {24},
+
+  File                     = {berben_05.pdf:berben_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.06.20}
+}
+
+@InProceedings{berben_02,
+  Title                    = {{L}ow power error resilient encoding for on-chip data buses},
+  Author                   = {Bertozzi, D. and Benini, L. and De Micheli, G.},
+  Booktitle                = {Proc. Design, Automation and Test in Europe Conference and Exhibition},
+  Year                     = {2002},
+  Month                    = mar,
+  Pages                    = {102--109},
+
+  Doi                      = {10.1109/DATE.2002.998256},
+  File                     = {berben_02.pdf:berben_02.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.06}
+}
+
+@Book{bertsi_97,
+  Title                    = {{P}arallel and {D}istributed {C}omputation: {N}umerical {M}ethods},
+  Author                   = {Dimitri P. Bertsekas and John N. Tsitsiklis},
+  Publisher                = {Athena Scientific},
+  Year                     = {1997},
+
+  Ccr_grade                = {n.a.},
+  Ccr_topic                = {NetControl Paper},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR},
+  Timestamp                = {2013.12.09}
+}
+
+@InProceedings{bettho_10,
+  Title                    = {{C}omparing performance and energy efficiency of {FPGA}s and {GPU}s for high productivity computing},
+  Author                   = {Betkaoui, B. and Thomas, D.B. and Luk, W.},
+  Booktitle                = {Field-Programmable Technology (FPT), 2010 International Conference on},
+  Year                     = {2010},
+  Month                    = dec,
+  Pages                    = {94-101},
+
+  Abstract                 = {This paper provides the first comparison of performance and energy efficiency of high productivity computing systems based on FPGA (Field-Programmable Gate Array) and GPU (Graphics Processing Unit) technologies. The search for higher performance compute solutions has recently led to great interest in heterogeneous systems containing FPGA and GPU accelerators. While these accelerators can provide significant performance improvements, they can also require much more design effort than a pure software solution, reducing programmer productivity. The CUDA system has provided a high productivity approach for programming GPUs. This paper evaluates the High-Productivity Reconfigurable Computer (HPRC) approach to FPGA programming, where a commodity CPU instruction set architecture is augmented with instructions which execute on a specialised FPGA co-processor, allowing the CPU and FPGA to co-operate closely while providing a programming model similar to that of traditional software. To compare the GPU and FPGA approaches, we select a set of established benchmarks with different memory access characteristics, and compare their performance and energy efficiency on an FPGA-based Hybrid-Core system with a GPU-based system. Our results show that while GPUs excel at streaming applications, high-productivity reconfigurable computing systems outperform GPUs in applications with poor locality characteristics and low memory bandwidth requirements.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPT.2010.5681761},
+  File                     = {bettho_10.pdf:bettho_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@InProceedings{bettho_11,
+  Title                    = {{A} framework for {FPGA} acceleration of large graph problems: {G}raphlet counting case study},
+  Author                   = {Betkaoui, B. and Thomas, D.B. and Luk, W. and Przulj, N.},
+  Booktitle                = {Proceedings of the 2011 International Conference on Field-Programmable Technology (FPT)},
+  Year                     = {2011},
+  Month                    = {Dec},
+  Pages                    = {1-8},
+
+  Abstract                 = {In many application domains, data are represented using large graphs involving millions of vertices and edges. Graph analysis algorithms, such as finding short paths and isomorphic subgraphs, are largely dominated by memory latency. Large cluster-based computing platforms can process graphs efficiently if the graph data can be partitioned, and on a smaller scale partitioning can be used to allocate graphs to low-latency on-chip RAMs in reconfigurable devices. However, there are many graph classes, such as scale-free social networks, which lack the locality to make partitioning graph data an efficient solution to the latency problem and are far too large to fit in on-chip RAMs and caches. In this paper, we present a framework for reconfigurable hardware acceleration of these large-scale graph problems that are difficult to partition and require high-latency off-chip memory storage. Our reconfigurable architecture tolerates off-chip memory latency by using a memory crossbar that connects many parallel identical processing elements to shared off-chip memory, without a traditional cached memory hierarchy. Quantitative comparison between the software and hardware performance of a graphlet counting case-study shows that our hardware implementation outperforms a quad-core software implementation by 10 times for large graphs. This speedup includes all software and IO overhead required, and reduces execution time for this common bioinformatics algorithm from about 2 hours to just 12 minutes. These results demonstrate that our methodology for accelerating graph algorithms is a promising approach for efficient parallel graph processing.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPT.2011.6132667},
+  File                     = {bettho_11.pdf:bettho_11.pdf:PDF},
+  Keywords                 = {graphs},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.28}
+}
+
+@InProceedings{beupfl_09,
+  Title                    = {{F}ully programmable decoder architecture for structured and unstructured {LDPC} codes},
+  Author                   = {Beuschel, C. and Pfleiderer, H.-J.},
+  Booktitle                = {Proc. 1st International Conference on Wireless Communication, Vehicular Technology, Information Theory and Aerospace. Electronic Systems Technology Wireless VITAE 2009},
+  Year                     = {2009},
+  Month                    = may,
+  Pages                    = {747--751},
+
+  Doi                      = {10.1109/WIRELESSVITAE.2009.5172542},
+  File                     = {beupfl_09.pdf:beupfl_09.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.16}
+}
+
+@Article{beupfl_08,
+  Title                    = {{FPGA implementation of a flexible decoder for long LDPC codes}},
+  Author                   = {Beuschel, C. and Pfleiderer, H.-J.},
+  Journal                  = {International Conference on Field Programmable Logic and Applications, FPL},
+  Year                     = {2008},
+
+  Month                    = sep,
+  Pages                    = {185-190},
+
+  Address                  = {Heidelberg, Germany},
+  File                     = {beupfl_08.pdf:beupfl_08.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{beudye_04,
+  Title                    = {{N}ext-generation prototyping of sensor networks},
+  Author                   = {Beutel, Jan and Dyer, Matthias and Hinz, Martin and Meier, Lennart and Ringwald, Matthias},
+  Booktitle                = {SenSys '04: Proceedings of the 2nd international conference on Embedded networked sensor systems},
+  Year                     = {2004},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {291--292},
+  Publisher                = {ACM},
+
+  Doi                      = {http://doi.acm.org/10.1145/1031495.1031541},
+  File                     = {beudye_04.pdf:beudye_04.pdf:PDF},
+  ISBN                     = {1-58113-879-2},
+  Location                 = {Baltimore, MD, USA},
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21}
+}
+
+@InProceedings{bhamue_10,
+  Title                    = {{M}aking {DRAM} {R}efresh {P}redictable},
+  Author                   = {Bhat, B. and Mueller, F.},
+  Booktitle                = {Real-Time Systems (ECRTS), 2010 22nd Euromicro Conference on},
+  Year                     = {2010},
+  Month                    = {July},
+  Pages                    = {145-154},
+
+  Doi                      = {10.1109/ECRTS.2010.23},
+  ISSN                     = {1068-3070},
+  Keywords                 = {DRAM chips;hardware-software codesign;program diagnostics;scheduling;task analysis;DRAM refresh predictable;caching;embedded control systems;pipelining;schedulability theory;static timing analysis;task execution times;worst-case execution times;Delay;Hardware;Real time systems;SDRAM;Software;DRAM;DRAM Refresh;Real-Time Systems;Timing Analysis;Timing Predictability;Worst-Case Execution Time},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.13}
+}
+
+@Misc{bhamm13,
+  Title                    = {mm: {L}inux {M}emory {P}ower {M}anagement},
+
+  Author                   = {Srivatsa S. Bhat},
+  HowPublished             = {\url{https://lwn.net/Articles/568369/}},
+  Year                     = {2013},
+
+  Owner                    = {EFZ},
+  Timestamp                = {2016-12-15},
+  Url                      = {https://lwn.net/Articles/568369/}
+}
+
+@Article{bhacha_16,
+  Title                    = {{DRAM} {R}efresh {M}echanisms, {P}enalties, and {T}rade-{O}ffs},
+  Author                   = {I. Bhati and M. T. Chang and Z. Chishti and S. L. Lu and B. Jacob},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2016},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {108-121},
+  Volume                   = {65},
+
+  Doi                      = {10.1109/TC.2015.2417540},
+  ISSN                     = {0018-9340},
+  Keywords                 = {DRAM chips;multiprocessing systems;performance evaluation;power aware computing;storage management;DRAM cell;DRAM chip speed;DRAM chips size;DRAM refresh mechanism;data footprint demand;data retention time;modern asynchronous DRAM;multicore processor;power dissipation;refresh operation;total memory capacity;Computer architecture;Performance evaluation;SDRAM;Temperature sensors;Timing;DRAM Refresh;Multicore processor;performance;power},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-17}
+}
+
+@Article{bhacha_15,
+  Title                    = {{DRAM} {R}efresh {M}echanisms, {T}rade-offs, and {P}enalties},
+  Author                   = {Bhati, Ishwar and Chang, Mu-Tien and Chishti, Z. and Lu, Shih-Lien and Jacob, B.},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2015},
+  Number                   = {99},
+  Pages                    = {1-1},
+  Volume                   = {PP},
+
+  Doi                      = {10.1109/TC.2015.2417540},
+  ISSN                     = {0018-9340},
+  Keywords                 = {Clocks;Computer architecture;Performance evaluation;SDRAM;Temperature sensors;Timing;DRAM Refresh;Multicore processor;performance;power},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.06}
+}
+
+@InProceedings{bhachi_13,
+  Title                    = {{C}oordinated {R}efresh: {E}nergy {E}fficient {T}echniques for {DRAM} {R}efresh {S}cheduling},
+  Author                   = {Bhati, Ishwar and Chishti, Zeshan and Jacob, Bruce},
+  Booktitle                = {Proceedings of the 2013 International Symposium on Low Power Electronics and Design},
+  Year                     = {2013},
+
+  Address                  = {Piscataway, NJ, USA},
+  Pages                    = {205--210},
+  Publisher                = {IEEE Press},
+  Series                   = {ISLPED '13},
+
+  Acmid                    = {2648720},
+  ISBN                     = {978-1-4799-1235-3},
+  Keywords                 = {DRAM refresh, energy efficiency, self refresh mode},
+  Location                 = {Beijing, China},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.13},
+  Url                      = {http://dl.acm.org/citation.cfm?id=2648668.2648720}
+}
+
+@InProceedings{bhachi_15,
+  Title                    = {{F}lexible auto-refresh: enabling scalable and energy-efficient {DRAM} refresh reductions},
+  Author                   = {Bhati, Ishwar and Chishti, Zeshan and Lu, Shih-Lien and Jacob, Bruce},
+  Booktitle                = {Proceedings of the 42nd Annual International Symposium on Computer Architecture},
+  Year                     = {2015},
+  Organization             = {ACM},
+  Pages                    = {235--246},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@InProceedings{bhamot_17,
+  Title                    = {{H}arv{OS}: {E}fficient {C}ode {I}nstrumentation for {T}ransiently-powered {E}mbedded {S}ensing},
+  Author                   = {Bhatti, Naveed Anwar and Mottola, Luca},
+  Booktitle                = {Proceedings of the 16th ACM/IEEE International Conference on Information Processing in Sensor Networks},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {209--219},
+  Publisher                = {ACM},
+  Series                   = {IPSN '17},
+
+  Acmid                    = {3055082},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Bhatti:2017:HEC:3055031.3055082},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3055031.3055082},
+  ISBN                     = {978-1-4503-4890-4},
+  Keywords                 = {TCS},
+  Keywords_original        = {checkpointing, embedded systems, sensor networks, transiently-powered computing},
+  Location                 = {Pittsburgh, Pennsylvania},
+  Numpages                 = {11},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/3055031.3055082}
+}
+
+@Article{bicgar_02,
+  Title                    = {{A Unified Turbo/Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18-$\mu$m CMOS}},
+  Author                   = {M. A. Bickerstaff and D. Garrett and T. Prokop and C. Thomas and B. Widdup and G. Zhou and L. M. Davis and G. Woodward and C. Nicol and R. Yan},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2002},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {1555--1564},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bicgar_02a,
+  Title                    = {{A Unified Turbo/Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18-$\mu$m CMOS}},
+  Author                   = {M. A. Bickerstaff and D. Garrett and T. Prokop and C. Thomas and B. Widdup and G. Zhou and C. Nicol and R. Yan},
+  Booktitle                = {Proc. IEEE International Solid-State Circuits Conference (ISSCC '02)},
+  Year                     = {2002},
+
+  Address                  = {San Francisco, CA, USA},
+  Month                    = feb,
+  Pages                    = {90--91},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bicdav_03,
+  Title                    = {{A 24Mb/s Radix-4 LogMAP Turbo Decoder for 3GPP-HSDPA Mobile Wireless}},
+  Author                   = {M. Bickerstaff and L. Davis and C. Thomas and D. Garrett and C. Nicol},
+  Booktitle                = {Proc. 2003 IEEE International Solid-State Circuits Conference (ISSCC '03)},
+  Year                     = {2003},
+
+  Address                  = {San Francisco, CA, USA},
+  Month                    = feb,
+  Pages                    = {150 -- 151,484},
+
+  File                     = {bicdav_03.pdf:bicdav_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bicgar_02c,
+  Title                    = {{A} unified turbo/viterbi channel decoder for 3{GPP} mobile wireless in 0.18 \&mu;m {CMOS}},
+  Author                   = {Bickerstaff, M. and Garrett, D. and Prokop, T. and Thomas, C. and Widdup, B. and Gongyu Zhou and Nicol, C. and Ran-Hong Yan},
+  Booktitle                = {Proc. Digest of Technical Papers Solid-State Circuits Conf. ISSCC. 2002 IEEE Int},
+  Year                     = {2002},
+  Pages                    = {124--451},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ISSCC.2002.992967},
+  File                     = {bicgar_02c.pdf:bicgar_02c.pdf:PDF},
+  Keywords                 = {Turbo Viterbi},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.08.22}
+}
+
+@InProceedings{bichug_00,
+  Title                    = {{DSP Systems for Next-Generation Mobile Wireless Infrastructure}},
+  Author                   = {M. Bickerstaff and G. Hughes and C. Nicol and Bing Xu and Ran-Hong Yan},
+  Booktitle                = {Proc. 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '00)},
+  Year                     = {2000},
+  Pages                    = {3710--3713},
+
+  Blabel                   = {{\bf bihuni:00}},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bidzim_15,
+  Title                    = {{S}ynchronization in wireless biomedical-sensor networks with {B}luetooth {L}ow {E}nergy},
+  Author                   = {Bideaux, A. and Zimmermann, B. and Hey, S. and Stork, W.},
+  Journal                  = {Current Directions in Biomedical Engineering},
+  Year                     = {2015},
+
+  Month                    = {September},
+  Pages                    = {73–76},
+
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {23645504},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1515/cdbme-2015-0019},
+  ISSN                     = {2364-5504},
+  Keywords                 = {BLE},
+  Owner                    = {CCR},
+  Publisher                = {De Gruyter},
+  Timestamp                = {2020-03-30},
+  Url                      = {//www.degruyter.com/view/j/cdbme.2015.1.issue-1/cdbme-2015-0019/cdbme-2015-0019.xml}
+}
+
+@Article{bie_93,
+  Title                    = {{The Siemens High-Level Synthesis System CALLAS}},
+  Author                   = {Biesenack, J. and Koster, M. and Langmaier, A. and Ledeux, S. and Marz, S. and Payer, M. and Pilsl, M. and Rumler, S. and Soukup, H. and Wehn, N. and Duzy, P.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {1993},
+
+  Month                    = nov,
+  Number                   = {2},
+  Pages                    = {244--253},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bieweh_92,
+  Title                    = {{ Data Part Optimization in the CALLAS Synthesis System}},
+  Author                   = { J.~Biesenack and N.~Wehn and A.~Stoll and M.~Payer},
+  Booktitle                = { IFIP Transactions A-22: Synthesis for Control Dominated Circuits},
+  Year                     = {1992},
+
+  Address                  = {Grenoble},
+  Pages                    = {263--274},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bimlen_10,
+  Title                    = {{P}erformance study of non-binary belief propagation for decoding {R}eed-{S}olomon codes},
+  Author                   = {Bimberg, M. and Lentmaier, M. and Fettweis, G. P.},
+  Booktitle                = {Proc. Int Source and Channel Coding (SCC) ITG Conf},
+  Year                     = {2010},
+  Pages                    = {1--6},
+
+  File                     = {bimlen_10.pdf:bimlen_10.pdf:PDF},
+  Keywords                 = {ABP, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {non binary belief propagation for ABP},
+  Timestamp                = {2011.06.21}
+}
+
+@InProceedings{bimmat_09,
+  Title                    = {{O}n {T}he {P}erformance {A}nd {N}umerical {S}tability of {S}oft-{D}ecision {R}eed-{S}olomon {D}ecoding},
+  Author                   = {Bimberg, M. and Matus, E. and Fettweis, G. P.},
+  Booktitle                = {Proc of 17th European Signal Processing Conference (EUSIPCO 2009)},
+  Year                     = {2009},
+
+  File                     = {bimmat_09.pdf:bimmat_09.pdf:PDF},
+  Keywords                 = {ABP, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {quantisierungsanalyse abp
+min sum vs optimale check nodes
+mit gauß und rayleigh},
+  Timestamp                = {2011.11.03}
+}
+
+@InProceedings{bimtav_07,
+  Title                    = {{A High-Throughput Programmable Decoder for LDPC Convolutional Codes}},
+  Author                   = {Marcel Bimberg and Marco B.S. Tavares and Emil Mati\'{u}\v{s} and Gerhard P. Fettweis},
+  Booktitle                = {Application-specific Systems, Architectures and Processors, 2007. ASAP '07. International Conference on},
+  Year                     = {2007},
+  Month                    = jul,
+  Pages                    = {239--246},
+
+  Doi                      = {10.1109/ASAP.2007.4429987},
+  File                     = {bimtav_07.pdf:bimtav_07.pdf:PDF},
+  Owner                    = {alles},
+  Timestamp                = {2008.06.27}
+}
+
+@MastersThesis{MTbin07,
+  Title                    = {{C}alibration of the {H}eston {M}odel with {A}pplication in {D}erivative {P}ricing and {H}edging},
+  Author                   = {Chen Bin},
+  School                   = {Delft University of Technology},
+  Year                     = {2007},
+  Month                    = dec,
+
+  Abstract                 = {Because of the complexity of the modern financial derivatives, like option contracts, practitioners
+heavily rely on mathematical models to price the derivatives. It is known that the
+classical Black-Scholes option pricing model is not capable of pricing without a significant
+bias. Numerous model extensions have been introduced in recent years and in this thesis we
+discuss several of them. To improve the understanding of the dynamics of the future uncertainty
+of asset prices, which is measured in volatility, and its impact on risk-free ‘hedged’
+portfolios, the stochastic volatility models have emerged in the last decade of the previous
+century. Within the big family of Stochastic volatility models, the Heston model (one of
+the many stochastic volatility models) has become a new industrial standard in the domain
+of exotic equity derivative. Its popularity comes from the fact that the Heston model can
+price European options highly efficiently by means of the so-called Fast Fourier Transform
+(FFT) algorithm.
+Advanced model requires equally sophisticated empirical implementation, in which stage
+the calibration problem comes in. Since the Heston model contains several undetermined
+parameters that need to be fitted to the present financial market data. This usually leads
+to an optimization problem, as calibration implies that the ‘distance’ between market and
+(Heston) mathematical model prices should be minimized. The major difficulty (the one
+we describe in detail in this thesis) is that the optimization problem is typically ill-posed:
+The commonly used methods may generate unstable parameters through time, or cannot
+produce a sufficient fit to the market prices. Here we propose a novel multilevel-structured
+global optimization procedure, called the Hybrid Stochastic Approximation Search. In this
+algorithm, we especially contribute with two distinct Markov processes: The first oneWang-
+Landau algorithm is capable of leaving local optima, in which common gradient-based
+optimization methods would stagnate in their convergence. At the same time, this algorithm
+is not as costly as common global optimization algorithms are; Secondly, we propose to
+i
+ii
+include a technique called ‘Partial resampling’ in order to reduce big fluctuations produced
+by the first level and steering the steps through the local dynamics of the optimization
+landscape.
+The optimization method is called a ‘Stochastic Approximation’ because the Wang-
+Landau is a controlled Markov Chain guided by the historical samples in the parameter
+space. These two processes are combined in a multi-level structure where level one, based on
+the Wang-Landau algorithm ensures a global search, and level two, the partial resampling,
+increases the efficiency by steering the algorithm with problem specific information.
+With the calibrated Heston model, we obtain a satisfactory low pricing error for basic
+‘plain vanilla’ options with parameters that are, to a large extent, stationary, i.e., not
+depending on time. A local enhancement of calibration can be made by allowing certain
+parameters to be mildly dependent on time.
+Next to this main contribution we considered it important to also present the typical use
+of these mathematical pricing models, and in particular the stochastic volatility models, in
+financial practice. Therefore, a chapter is reserved for the explanation of the pricing of exotic
+contract as well as for the hedging of a portfolio, as it occurs in practice. We focus here
+on the so-called ‘hedge ratios’ that are implied by the Heston model and derive analytical
+solutions for financial contracts that are considered to be volatility sensitive, like cliquets
+and variance swaps.},
+  Cds_grade                = {0},
+  Cds_keywords             = {finance, calibration, Heston},
+  File                     = {MTbin07.pdf:MTbin07.pdf:PDF},
+  Journal                  = {Master's thesis, Department of Mathematics, Technical University of Delft, Delft, The Netherlands},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24},
+  Url                      = {\url{http://ta.twi.tudelft.nl/mf/users/oosterle/oosterlee/chen.pdf}}
+}
+
+@Article{binbec_11,
+  Title                    = {{T}he gem5 simulator},
+  Author                   = {Binkert, Nathan and Beckmann, Bradford and Black, Gabriel and Reinhardt, Steven K. and Saidi, Ali and Basu, Arkaprava and Hestness, Joel and Hower, Derek R. and Krishna, Tushar and Sardashti, Somayeh and Sen, Rathijit and Sewell, Korey and Shoaib, Muhammad and Vaish, Nilay and Hill, Mark D. and Wood, David A.},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {2011},
+
+  Month                    = aug,
+  Number                   = {2},
+  Pages                    = {1--7},
+  Volume                   = {39},
+
+  Acmid                    = {2024718},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/2024716.2024718},
+  ISSN                     = {0163-5964},
+  Issue_date               = {May 2011},
+  Numpages                 = {7},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2015.01.20},
+  Url                      = {http://doi.acm.org/10.1145/2024716.2024718}
+}
+
+@Book{Bishop2006,
+  Title                    = {{P}attern {R}ecognition and {M}achine {L}earning ({I}nformation {S}cience and {S}tatistics)},
+  Author                   = {Christopher M. Bishop},
+  Editor                   = {ISBN-13: 978-0387310732},
+  Publisher                = {Springer},
+  Year                     = {2006},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.01.25}
+}
+
+@Article{bladas_09,
+  Title                    = {{CPU}, heal thyself},
+  Author                   = {Blaauw, D. and Das, S.},
+  Journal                  = {IEEE Spectrum},
+  Year                     = {2009},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {40--56},
+  Volume                   = {46},
+
+  Comment                  = {Razor},
+  Doi                      = {10.1109/MSPEC.2009.5186555},
+  File                     = {bladas_09.pdf:bladas_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.08.31}
+}
+
+@Book{bladon_09,
+  Title                    = {{S}ystem{C}: {F}rom the {G}round {U}p, {S}econd {E}dition},
+  Author                   = {Black, D.C. and Donovan, J. and Bunton, B. and Keist, A.},
+  Publisher                = {Springer US},
+  Year                     = {2009},
+
+  ISBN                     = {9780387699578},
+  Lccn                     = {2009933997},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.23}
+}
+
+@Article{blasch_73,
+  Title                    = {{T}he {P}ricing of {O}ptions and {C}orporate {L}iabilities},
+  Author                   = {Fischer Black and Myron Scholes},
+  Journal                  = {The Journal of Political Economy},
+  Year                     = {1973},
+
+  Month                    = mar # { -- } # jun,
+  Number                   = {3},
+  Pages                    = {637--654},
+  Volume                   = {81},
+
+  Abstract                 = {If options are correctly priced in the market, it should not be possible to make sure profits by creating portfolios of long and short positions in options and their underlying stocks. Using this principle, a theoretical valuation formula for options is derived. Since almost all corporate liabilities can be viewed as combinations of options, the formula and the analysis that led to it are also applicable to corporate liabilities such as common stock, corporate bonds, and warrants. In particular, the formula can be used to derive the discount that should be applied to a corporate bond because of the possibility of default.},
+  Cds_grade                = {0},
+  File                     = {blasch_73.pdf:blasch_73.pdf:PDF},
+  ISSN                     = {0022-3808},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {JSTOR},
+  Timestamp                = {2010.11.23}
+}
+
+@InProceedings{blamen_93,
+  Title                    = {{Hybrid Survivor Path Architectures for Viterbi Decoders}},
+  Author                   = {Black, P.J. and Meng, T.H.-Y.},
+  Booktitle                = {Acoustics, Speech, and Signal Processing, 1993. ICASSP-93., 1993 IEEE International Conference on},
+  Year                     = {1993},
+  Month                    = apr,
+  Pages                    = {433--436vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ICASSP.1993.319148},
+  Owner                    = {vogt},
+  Timestamp                = {2007.02.28}
+}
+
+@Article{blamen_92,
+  Title                    = {{A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder}},
+  Author                   = {Black, P. J. and Meng, T. H.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {1992},
+
+  Month                    = dec,
+  Number                   = {12},
+  Pages                    = {1877--1885},
+  Volume                   = {27},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{blahow_02,
+  Title                    = {{A 690-mW 1-Gb/s, Rate-1/2 Low-Density Parity-Check Code Decoder}},
+  Author                   = {A.J. Blanksby and C. J. Howland},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2002},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {404--412},
+  Volume                   = {37},
+
+  File                     = {blahow_02.pdf:blahow_02.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{blo_16,
+  Title                    = {{T}he {A}utomotive {S}hift to {S}oftware-{D}efined, {C}onsolidated {C}ontroller {A}rchitectures},
+
+  Author                   = {Bloor, Thomas},
+  Month                    = {October},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-03},
+  Url                      = {http://qnxauto.blogspot.de/2016/10/automotive-shifting-software-defined.html}
+}
+
+@Article{blufelnol_05,
+  Title                    = {{M}odel-{B}ased {E}xploration of the {D}esign {S}pace for {H}eterogeneous {S}ystems on {C}hip},
+  Author                   = {Blume, H. and Feldkaemper, H. T. and Noll, T. G.},
+  Journal                  = {Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on},
+  Year                     = {2002},
+  Number                   = {1},
+  Pages                    = {29--40},
+
+  Address                  = {Hingham, MA, USA},
+  Doi                      = {http://dx.doi.org/10.1007/s11265-005-4936-4},
+  File                     = {blufelnol_05.pdf:blufelnol_05.pdf:PDF},
+  ISSN                     = {0922-5773},
+  Publisher                = {Kluwer Academic Publishers}
+}
+
+@Book{bob_07,
+  Title                    = {{I}ntroduction to {R}econfigurable {C}omputing: {A}rchitectures, {A}lgorithms, and {A}pplications},
+  Author                   = {Bobda, C.},
+  Publisher                = {Springer},
+  Year                     = {2007},
+
+  ISBN                     = {9781402061004},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {https://books.google.de/books?id=\_cNSgjR32LkC}
+}
+
+@InProceedings{boe_04,
+  Title                    = {{F}undamental tradeoffs in {MIMO} wireless systems},
+  Author                   = {Boelcskei, H.},
+  Booktitle                = {Proc. IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication},
+  Year                     = {2004},
+  Pages                    = {I--10 Vol.1},
+  Volume                   = {1},
+
+  Abstract                 = {Summary form only given. The use of multiple-input multiple-output (MIMO) antenna systems leads to dramatic improvements in capacity and link reliability of wireless systems. Focusing on the coherent case where the channel is unknown at the transmitter and perfectly known at the receiver, the leverages offered by MIMO channels can be summarized as follows: 1) spatial multiplexing gain increases spectral efficiency by opening up multiple spatial data pipes in the frequency band of operation for no additional power expenditure; 2) diversity gain improves link reliability by providing multiple (ideally) independently fading signal paths between transmitter and receiver; 3) interference canceling gain reduces co-channel interference and hence increases cellular system capacity by using the spatial degrees of freedom to out undesired interfering signals; and 4) array gain improves coverage by improving the received signal-to-noise ratio (SNR) through coherent combining of the signals arriving at the receive antenna array. While there is a wide variety of space-time signaling techniques available realizing various combinations of the above mentioned MIMO gains, little is known about the underlying fundamental tradeoffs and relations between the different gains. Understanding these tradeoffs is paramount in the design of MIMO wireless transceiver algorithms. The purpose of this talk is to introduce a simple information-theoretic framework establishing the existence of fundamental tradeoffs and relations between MIMO gains and subsequently quantifying them. The resulting tradeoff curves provide valuable insights into the question of how much of each of the MIMO gains can be realized concurrently.},
+  Doi                      = {10.1109/CASSET.2004.1322893},
+  Keywords                 = {MIMO systems, antenna arrays, array signal processing, cellular radio, cochannel interference, diversity reception, fading channels, interference suppression, multiplexing, radio links, radio receivers, radio transmitters, receiving antennas, telecommunication network reliability, transceivers, MIMO channel, MIMO wireless system, MIMO wireless transceiver algorithm, SNR, cellular system capacity, cochannel interference, fading signal path, information-theoretic framework, interference canceling gain, multiple spatial data pipe, multiple-input multiple-output antenna system, receive antenna array, signal-to-noise ratio, space-time signaling technique, spatial degrees of freedom, spatial multiplexing gain},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.18}
+}
+
+@InProceedings{boe_01,
+  Title                    = {{D}igital signal processing challenges in {MIMO} wireless communications},
+  Author                   = {Boelcskei, H. },
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems},
+  Year                     = {2001},
+  Pages                    = {1--},
+
+  Abstract                 = {Summary form only given. The requirements on data rate and quality of service of future wireless communications systems call for new digital signal processing techniques to increase spectrum efficiency and improve link reliability. Deploying multiple antennas at both transmitter and receiver of a wireless link (MIMO technology) has the potential to achieve these ambitious goals. MIMO techniques are starting to find their way into standards, such as UMTS and IEEE 802.16. This article gives an overview of MIMO wireless covering issues such as propagation models, broadband transceivers, signaling techniques and coding and modulation. Special emphasis is put on the digital signal processing aspects},
+  Doi                      = {10.1109/SIPS.2001.957322},
+  Keywords                 = {MIMO systems, encoding, modulation, quality of service, radio links, radiowave propagation, receiving antennas, signal processing, telecommunication network reliability, telecommunication signalling, telecommunication standards, transceivers, transmitting antennas, DSP, IEEE 802.16 standard, MIMO wireless communications, QoS, UMTS standard, broadband transceivers, coding, data rate, digital signal processing, link reliability, modulation, multiple antennas, propagation models, quality of service, receiver, signaling techniques, spectrum efficiency, transmitter, wireless communications systems, wireless link},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.18}
+}
+
+@InProceedings{bogmer_06,
+  Title                    = {{A} {P}arallel {H}ardware {A}rchitecture for fast {G}aussian {E}limination over {GF}(2)},
+  Author                   = {Bogdanov, A. and Mertens, M.C. and Paar, C. and Pelzl, J. and Rupp, A.},
+  Booktitle                = {Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on},
+  Year                     = {2006},
+  Month                    = {april},
+  Pages                    = {237 -248},
+
+  Doi                      = {10.1109/FCCM.2006.12},
+  File                     = {bogmer_06.pdf:bogmer_06.pdf:PDF},
+  Owner                    = {Scholl},
+  Review                   = {SMITH Paper},
+  Timestamp                = {2013.02.04}
+}
+
+@InProceedings{bogde_14,
+  Title                    = {{A}n {I}nteger {P}rogramming {F}ormulation for the {M}aximum $k$-{S}ubset {I}ntersection {P}roblem},
+  Author                   = {Bogue, E.T. and {{de Souza}}, C.C. and Xavie, E.C. and Freire, A.S.},
+  Booktitle                = {Combinatorial Optimization},
+  Year                     = {2014},
+  Pages                    = {87--99},
+  Publisher                = {Springer International Publishing},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-25}
+}
+
+@Article{bohnou_15,
+  Title                    = {{O}n the {E}quivalence of {I}nterleavers for {T}urbo {C}odes},
+  Author                   = {R. Garzón Bohórquez and C. A. Nour and C. Douillard},
+  Journal                  = {IEEE Wireless Communications Letters},
+  Year                     = {2015},
+
+  Month                    = {Feb},
+  Number                   = {1},
+  Pages                    = {58-61},
+  Volume                   = {4},
+
+  Doi                      = {10.1109/LWC.2014.2367517},
+  ISSN                     = {2162-2337},
+  Keywords                 = {interleaved codes;turbo codes;almost regular permutation interleavers;dithered relative prime interleavers;long-term evolution standard;quadratic permutation polynomial interleavers;turbo codes;Conferences;Digital video broadcasting;Polynomials;Standards;Turbo codes;Vectors;Wireless communication;ARP interleaver;DRP interleaver;QPP interleaver;Turbo codes;almost regular permutation (ARP) interleavers;dithered relative prime (DRP) interleaver;equivalence;quadratic permutation polynomial (QPP) interleaver},
+  Owner                    = {StW},
+  Timestamp                = {2018.06.25}
+}
+
+@Article{bojipe_12,
+  Title                    = {{PARDIS}: {A} {P}rogrammable {M}emory {C}ontroller for the {DDR}x {I}nterfacing {S}tandards},
+  Author                   = {Bojnordi, Mahdi Nazm and Ipek, Engin},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {2012},
+
+  Month                    = jun,
+  Number                   = {3},
+  Pages                    = {13--24},
+  Volume                   = {40},
+
+  Acmid                    = {2337162},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/2366231.2337162},
+  File                     = {bojipe_12.pdf:bojipe_12.pdf:PDF},
+  ISSN                     = {0163-5964},
+  Issue_date               = {June 2012},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2015.02.12}
+}
+
+@InProceedings{bolcon_10,
+  Title                    = {{O}ptimising {M}emory {B}andwidth {U}se for {M}atrix-{V}ector {M}ultiplication in {I}terative {M}ethods},
+  Author                   = {Boland, David and Constantinides, George A.},
+  Booktitle                = {Reconfigurable Computing: Architectures, Tools and Applications},
+  Year                     = {2010},
+
+  Address                  = {Berlin, Heidelberg},
+  Editor                   = {Sirisuk, Phaophak and Morgan, Fearghal and El-Ghazawi, Tarek and Amano, Hideharu},
+  Pages                    = {169--181},
+  Publisher                = {Springer Berlin Heidelberg},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS},
+  Ccr_topic                = {NetControl Paper},
+  ISBN                     = {978-3-642-12133-3},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR}
+}
+
+@Article{bolmie_10,
+  Title                    = {{A} {N}ovel {D}esign {M}ethodology for {I}mplementing {R}eliability-{A}ware {S}ystems on {SRAM}-{B}ased {FPGA}s},
+  Author                   = {Bolchini, C. and Miele, A. and Sandionigi, C. },
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {2010},
+  Note                     = {Early Access},
+  Number                   = {99},
+
+  Doi                      = {10.1109/TC.2010.281},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{bol_06,
+  Title                    = {{MIMO}-{OFDM} wireless systems: basics, perspectives, and challenges},
+  Author                   = {Bolcskei, H.},
+  Journal                  = {IEEE Wireless Communications Magazine},
+  Year                     = {2006},
+  Number                   = {4},
+  Pages                    = {31--37},
+  Volume                   = {13},
+
+  Abstract                 = {Multiple-input multiple-output (MIMO) wireless technology in combination with orthogonal frequency division multiplexing (MIMO-OFDM) is an attractive air-interface solution for next-generation wireless local area networks (WLANs), wireless metropolitan area networks (WMANs), and fourth-generation mobile cellular wireless systems. This article provides an overview of the basics of MIMO-OFDM technology and focuses on space-frequency signaling, receiver design, multiuser systems, and hardware implementation aspects. We conclude with a discussion of relevant open areas for further research.},
+  Doi                      = {10.1109/MWC.2006.1678163},
+  File                     = {bol_06.pdf:bol_06.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {1536-1284},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.18}
+}
+
+@Article{BoleaAlamanac2010,
+  Title                    = {{DVB-RCS goes mobile: Challenges and technical solutions}},
+  Author                   = {Bolea Alamanac, Ana and Chan, Pauline ML and Duquerroy, Laurence and Hu, Y. Fun and Gallinaro, Gennaro and Guo, Wei and Mignolo, Domenico},
+  Journal                  = {International Journal of Satellite Communications and Networking},
+  Year                     = {2010},
+  Number                   = {3-4},
+  Pages                    = {137--155},
+  Volume                   = {28},
+
+  Doi                      = {10.1002/sat.946},
+  ISSN                     = {1542-0981},
+  Keywords                 = {DVB-RCS, mobile satellite services, satellite return link},
+  Publisher                = {John Wiley \& Sons, Ltd.},
+  Url                      = {http://dx.doi.org/10.1002/sat.946}
+}
+
+@Article{bol_86,
+  Title                    = {{G}eneralized {A}utoregressive {C}onditional {R}eteroskedasticity},
+  Author                   = {Bollerslev, Tim},
+  Journal                  = {Journal of Econometrics},
+  Year                     = {1986},
+  Number                   = {3},
+  Pages                    = {307--327},
+  Volume                   = {31},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {GARCH model},
+  File                     = {bol_86.pdf:bol_86.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Elsevier},
+  Timestamp                = {2014.06.12}
+}
+
+@Article{bolmag_17,
+  Title                    = {{K}inetic {AC/DC} {C}onverter for {E}lectromagnetic {E}nergy {H}arvesting in {A}utonomous {W}earable {D}evices},
+  Author                   = {R. {Bolt} and M. {Magno} and T. {Burger} and A. {Romani} and L. {Benini}},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2017},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {1422-1426},
+  Volume                   = {64},
+
+  Ccr_flags                = {unread, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8090900},
+  Ccr_keywords             = {MGS26.4},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/TCSII.2017.2768391},
+  Keywords                 = {TCS},
+  Keywords_original        = {AC-DC power convertors;choppers (circuits);CMOS integrated circuits;energy harvesting;low-power electronics;maximum power point trackers;rectifiers;electromagnetic energy harvesting;autonomous wearable devices;nanopower integrated circuit;electromagnetic microgenerator;wearable kinetic energy harvesting;usable power;energy conversion;kinetic energy harvester;transducer;zero-drop rectifier;optimal switching scheme;low power consumption;circuit simulations;AC output;maximum power point tracking efficiency;control circuit;kinetic AC-DC converter;AC-DC chopper;current 250.0 nA;voltage 3.5 V to 4.2 V;Wearable computers;Kinetic energy;AC-DC power converters;Electromagnetics;Low-power electronics;Energy harvesting;Wearable devices;energy harvesting;kinetic energy harvesting;low power design;AC-DC converter},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27}
+}
+
+@InProceedings{bonweh_86,
+  Title                    = {{Verfahren zur hierarchischen Layoutverifikation in der VLSI-Umgebung DAMOS}},
+  Author                   = {W.~Bonath and N.~Wehn and M.~Glesner},
+  Booktitle                = {2.\ E.I.S. Workshop, GMD-Studie Nr.110},
+  Year                     = {1986},
+
+  Address                  = {Bonn},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bonsom_09,
+  Title                    = {{C}ross-coupling in 65nm fully integrated {EDGE} {S}ystem {O}n {C}hip {D}esign and cross-coupling prevention of complex 65nm {S}o{C}},
+  Author                   = {Bonnaud, Pierre-Henri and Sommer, Grit},
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conference \& Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {1045--1050},
+
+  File                     = {bonsom_09.pdf:bonsom_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.01}
+}
+
+@MastersThesis{MTborja13,
+  Title                    = {{F}ramework {F}lexível para {P}rodutos {F}inanceiros de {A}lto {D}esempenho},
+  Author                   = {Francisco Gerdau de Borja},
+  School                   = {Universidade Federal do Rio Grande do Sul, Brazil},
+  Year                     = {2013},
+  Month                    = jan,
+  Note                     = {last access 2014-05-02},
+
+  Cds_grade                = {0},
+  File                     = {MTborja13.pdf:MTborja13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.05.02},
+  Url                      = {http://www.lume.ufrgs.br/bitstream/handle/10183/66360/000870878.pdf?sequence=1}
+}
+
+@InProceedings{bor_10,
+  Title                    = {{T}he {E}xascale challenge},
+  Author                   = {Borkar, S. },
+  Booktitle                = {Proc. Int VLSI Design Automation and Test (VLSI-DAT) Symp},
+  Year                     = {2010},
+  Pages                    = {2--3},
+
+  Doi                      = {10.1109/VDAT.2010.5496640},
+  File                     = {bor_10.pdf:bor_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2012.03.30}
+}
+
+@Article{bor_05,
+  Title                    = {{D}esigning {R}eliable {S}ystems from {U}nreliable {C}omponents: {T}he {C}hallenges of {T}ransistor {V}ariability and {D}egradation},
+  Author                   = {Borkar, S.},
+  Journal                  = {Micro, IEEE},
+  Year                     = {2005},
+
+  Month                    = nov # {--} # dec,
+  Number                   = {6},
+  Pages                    = {10--16},
+  Volume                   = {25},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Borkar
+- Basics},
+  Doi                      = {10.1109/MM.2005.110},
+  File                     = {bor_05.pdf:bor_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm, may},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{bor_99,
+  Title                    = {{D}esign challenges of technology scaling},
+  Author                   = {Borkar, S.},
+  Journal                  = {Micro, IEEE},
+  Year                     = {1999},
+  Number                   = {4},
+  Pages                    = {23--29},
+  Volume                   = {19},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Borkar
+- Basics},
+  Doi                      = {10.1109/40.782564},
+  File                     = {bor_99.pdf:bor_99.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{borkar_03,
+  Title                    = {{P}arameter variations and impact on circuits and microarchitecture},
+  Author                   = {Borkar, Shekhar and Karnik, Tanay and Narendra, Siva and Tschanz, Jim and Keshavarzi, Ali and De, Vivek},
+  Booktitle                = {Proceedings of the 40th annual Design Automation Conference},
+  Year                     = {2003},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {338--342},
+  Publisher                = {ACM},
+  Series                   = {DAC '03},
+
+  Acmid                    = {775920},
+  Doi                      = {10.1145/775832.775920},
+  ISBN                     = {1-58113-688-9},
+  Keywords                 = {body bias, high performance deisgn, parameter variation},
+  Location                 = {Anaheim, CA, USA},
+  Numpages                 = {5},
+  Url                      = {http://doi.acm.org/10.1145/775832.775920}
+}
+
+@InProceedings{borwit_11,
+  Title                    = {{A} 772{M}bit/s 8.81bit/n{J} 90nm {CMOS} soft-input soft-output sphere decoder},
+  Author                   = {Borlenghi, F. and Witte, E. M. and Ascheid, G. and Meyr, H. and Burg, A. },
+  Booktitle                = {Proc. IEEE Asian Solid State Circuits Conf. (A-SSCC)},
+  Year                     = {2011},
+  Pages                    = {297--300},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.07.23}
+}
+
+@Book{phdbor_09,
+  Title                    = {{V}ollständige funktionale {V}erifikation},
+  Author                   = {Bormann, Jörg},
+  Year                     = {2009},
+
+  File                     = {phdbor_09.pdf:phdbor_09.pdf:PDF},
+  Keywords                 = {Digitalschaltung Verifikation},
+  Owner                    = {Brehm},
+  Pages                    = {165 S. : graph. Darst.},
+  Timestamp                = {2010.10.21},
+  Url                      = {https://aleph.ub.uni-kl.de/F/F9NKJQ8JEB5B8FML895D9HRVV5Y4GNN26AJNCPIEF26VR4ALJY-16063?func=full-set-set&set_number=004099&set_entry=000001&format=999}
+}
+
+@Book{bos_14,
+  Title                    = {{C}ontinuous {S}oftware {E}ngineering},
+  Author                   = {Bosch, Jan},
+  Publisher                = {Springer Publishing Company, Incorporated},
+  Year                     = {2014},
+
+  ISBN                     = {3319112821, 9783319112824},
+  Owner                    = {MJ},
+  Timestamp                = {2020-02-09}
+}
+
+@Article{bos_06,
+  Title                    = {{D}esigning reliable systems with unreliable components},
+  Author                   = {Bose, P.},
+  Journal                  = {IEEE Micro},
+  Year                     = {2006},
+
+  Month                    = sep,
+  Number                   = {5},
+  Pages                    = {5--6},
+  Volume                   = {26},
+
+  Doi                      = {10.1109/MM.2006.87},
+  File                     = {bos_06.pdf:bos_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.20}
+}
+
+@Article{bosray_60,
+  Title                    = {{O}n a class of error correcting binary group codes},
+  Author                   = {Bose, R. C. and Ray-Chaudhuri, D. K.},
+  Journal                  = {Information and Control},
+  Year                     = {1960},
+
+  Month                    = {March},
+  Number                   = {1},
+  Pages                    = {68--79},
+  Volume                   = {3},
+
+  Abstract                 = {A general method of constructing error correcting binary group codes is obtained. A binary group code with n places, k of which are information places is called an (n,k) code. An explicit method of constructing t-error correcting (n,k) codes is given for n = 2m-1 and k = 2m-1-R(m,t) [greater-than over equal to] 2m-1-mt where R(m,t) is a function of m and t which cannot exceed mt. An example is worked out to illustrate the method of construction.},
+  Citeulike-article-id     = {2211986},
+  Citeulike-linkout-0      = {http://dx.doi.org/10.1016/S0019-9958(60)90287-4},
+  Citeulike-linkout-1      = {http://www.sciencedirect.com/science/article/B7MFM-4DX426C-F0/2/d9a23eb73f1795f641f55c71d2e08c0c},
+  Comment                  = {BCH Code Ursprungs Veröffentlichung},
+  Doi                      = {10.1016/S0019-9958(60)90287-4},
+  Posted-at                = {2009-05-12 12:51:33},
+  Priority                 = {2},
+  Url                      = {http://dx.doi.org/10.1016/S0019-9958(60)90287-4}
+}
+
+@InProceedings{bosana_19,
+  Title                    = {{A} 3.5m{V} {I}nput, 82% {P}eak {E}fficiency {B}oost {C}onverter with {L}oss-{O}ptimized {MPPT} and 50m{V} {I}ntegrated {C}old-{S}tart for {T}hermoelectric {E}nergy {H}arvesting},
+  Author                   = {S. {Bose} and T. {Anand} and M. L. {Johnston}},
+  Booktitle                = {2019 IEEE Custom Integrated Circuits Conference (CICC)},
+  Year                     = {2019},
+  Month                    = {April},
+  Pages                    = {1-4},
+
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8780352},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/CICC.2019.8780352},
+  Keywords                 = {TCS},
+  Keywords_original        = {CMOS integrated circuits;energy harvesting;maximum power point trackers;power convertors;thermoelectric conversion;loss-optimized MPPT;thermoelectric energy harvesting;thermal energy harvesting;human body heat;thermoelectric generators;TEG;loss-optimized maximum power point tracking scheme;end-to-end power efficiency;on-chip cold-start mechanism;fully-autonomous single inductor boost converter architecture;integrated cold-start;peak efficiency boost converter;voltage 3.5 mV;voltage 50.0 mV;voltage 15.0 mV to 100.0 mV;Switches;Maximum power point trackers;Charge pumps;Inductors;Voltage control;Zero current switching;Logic gates},
+  Owner                    = {CCR}
+}
+
+@Article{bosana_19a,
+  Title                    = {{I}ntegrated {C}old {S}tart of a {B}oost {C}onverter at 57 m{V} {U}sing {C}ross-{C}oupled {C}omplementary {C}harge {P}umps and {U}ltra-{L}ow-{V}oltage {R}ing {O}scillator},
+  Author                   = {S. {Bose} and T. {Anand} and M. L. {Johnston}},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2019},
+  Pages                    = {1-12},
+
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8792208},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/JSSC.2019.2930911},
+  Keywords                 = {TCS},
+  Keywords_original        = {Ring oscillators;Clocks;Charge pumps;Threshold voltage;System-on-chip;Voltage multipliers;Charge pump;dc-dc converter;integrated cold start;ring oscillator;thermoelectric energy harvesting.},
+  Owner                    = {CCR}
+}
+
+@InProceedings{bosana_18,
+  Title                    = {{F}ully-integrated 57 m{V} cold start of a thermoelectric energy harvester using a cross-coupled complementary charge pump},
+  Author                   = {S. {Bose} and T. {Anand} and M. L. {Johnston}},
+  Booktitle                = {2018 IEEE Custom Integrated Circuits Conference (CICC)},
+  Year                     = {2018},
+  Month                    = {April},
+  Pages                    = {1-4},
+
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8357081},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/CICC.2018.8357081},
+  Keywords                 = {TCS},
+  Keywords_original        = {charge pump circuits;clocks;CMOS analogue integrated circuits;coupled circuits;DC-DC power convertors;energy harvesting;low-power electronics;oscillators;starting;thermoelectric conversion;thermoelectric energy harvester;cold-start architecture;battery-less thermoelectric energy harvesters;fully-integrated design;ultra-low voltage ring oscillator;fast switching edge;inductive boost converter;autonomous harvester;harvesting source;CMOS process;cross-coupled complementary charge pump;voltage 57.0 mV;size 180.0 nm;time 135.0 ms;energy 90.0 nJ;Charge pumps;Logic gates;Ring oscillators;Clocks;Inverters;Boosting;Switches},
+  Owner                    = {CCR}
+}
+
+@InProceedings{bosjoh_18,
+  Title                    = {{A} {S}tacked-{I}nverter {R}ing {O}scillator for 50 m{V} {F}ully-{I}ntegrated {C}old-{S}tart of {E}nergy {H}arvesters},
+  Author                   = {S. {Bose} and M. L. {Johnston}},
+  Booktitle                = {2018 IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2018},
+  Month                    = {May},
+  Pages                    = {1-5},
+
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8351445},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/ISCAS.2018.8351445},
+  Keywords                 = {TCS},
+  Keywords_original        = {biomedical electronics;CMOS logic circuits;DC-DC power convertors;energy harvesting;logic gates;low-power electronics;oscillators;patient diagnosis;thermoelectric conversion;fully-integrated cold-start;stacked-inverter ring oscillator;CMOS process;start-up oscillator;millivolt-level thermoelectric generator;self-sustained oscillation;higher voltage DC-DC converter;low-voltage oscillator;energy harvesting circuit;healthcare diagnostics;battery-less wearable electronics;body temperature;energy harvesters;three-inverter delay element;size 0.18 mum;frequency 9.5 kHz;power 818.0 pW;Inverters;Delays;Ring oscillators;Clocks;MOSFET;Start-up oscillator;cold start;ring oscillator;energy harvester;thermoelectric generator;low-voltage cold start},
+  Owner                    = {CCR}
+}
+
+@Book{bos_98,
+  Title                    = {{K}analcodierung},
+  Author                   = {Martin Bossert},
+  Publisher                = {B.G.Teubner Stuttgart},
+  Year                     = {1998},
+  Edition                  = {2nd},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {Channel Code, BCH, Syndrome, Chien Search, Key Equation, Berlekamp-Massey, Euclidean Algorithm, Galois Fields, RS},
+  Cds_read                 = {2008-08},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bouzep_09,
+  Title                    = {{M}ulti-bit {S}oft- and {T}iming {E}rror {D}etection for {CPU} {P}ipeline},
+  Author                   = {Bouajila, Abdelmajid and Zeppenfeld, Johannes and Stechele, Walter and Herkersdorf, Andreas},
+  Booktitle                = {in Proc. Workshop 2009 - Electronic Design Automation (EDA)},
+  Year                     = {2009},
+  Month                    = jun,
+
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.14}
+}
+
+@InProceedings{bougiu_03,
+  Title                    = {{A Scalable 8.7nJ/bit 75.6Mb/s Parallel Concatenated Convolutional (Turbo-) CODEC}},
+  Author                   = {B. Bougard and A. Giulietti and V. Derudder and J.-W. Weijers and S. Dupont and L. Hollevoet and F. Catthoor and L. van der Perre and H. De Man and R. Lauwereins},
+  Booktitle                = {Proc. 2003 IEEE International Solid-State Circuits Conference (ISSCC '03)},
+  Year                     = {2003},
+
+  Address                  = {San Francisco, CA, USA},
+  Month                    = feb,
+  Pages                    = {152 -- 153,484},
+
+  File                     = {bougiu_03.pdf:bougiu_03.pdf:PDF},
+  Keywords                 = {Turbo, Convolutional},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bougiu_02,
+  Title                    = {{A class of power efficient VLSI architectures for high speed turbo-decoding}},
+  Author                   = {B. Bougard and A. Giulietti and L. van der Perre and F. Catthoor},
+  Booktitle                = {Proc. 2002 Global Telecommunications Conference (GLOBECOM '02)},
+  Year                     = {2002},
+  Month                    = nov,
+  Pages                    = {549--533},
+  Volume                   = {1},
+
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{bougiu_03a,
+  Title                    = {{A Low-Power High Speed Parallel Concatenated Turbo-Decoding Architecture}},
+  Author                   = {B. Bougard and A. Giulietti and L. Van der Perre and F. Catthoor},
+  Booktitle                = {Proc. 3rd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {511--514},
+
+  File                     = {bougiu_03a.pdf:bougiu_03a.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {may},
+  Timestamp                = {2007.02.07}
+}
+
+@InProceedings{boupri_08,
+  Title                    = {{Algorithm-Architecture Co-Design of a Multi-Standard FEC Decoder ASIP}},
+  Author                   = {Bruno Bougard and Robert Priewasser and Liesbet Van der Perre and Mario Huemer},
+  Booktitle                = {{ICT-MobileSummit 2008 Conference Proceedings}},
+  Year                     = {2008},
+
+  Address                  = {Stockholm, Sweden},
+  Month                    = jun,
+
+  Cb_grade                 = {Keine Daten!},
+  File                     = {boupri_08.pdf:boupri_08.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{boucas_00,
+  Title                    = {{Decoder-first code design}},
+  Author                   = {E. Boutillon and J. Castura and F.R. Kschischang},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {459--462},
+
+  File                     = {boucas_00.pdf:boucas_00.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{boucon_10,
+  Title                    = {{B}ubble check: a simplified algorithm for elementary check node processing in extended min-sum non-binary {LDPC} decoders},
+  Author                   = {Boutillon, E. and Conde-Canencia, L.},
+  Journal                  = {Electronics Letters},
+  Year                     = {2010},
+  Number                   = {9},
+  Pages                    = {633--634},
+  Volume                   = {46},
+
+  Doi                      = {10.1049/el.2010.0566},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5457396}
+}
+
+@Article{boucon_13,
+  Title                    = {{D}esign of a {GF}(64)-{LDPC} {D}ecoder {B}ased on the {EMS} {A}lgorithm},
+  Author                   = {Boutillon, E. and Conde-Canencia, L. and Al Ghouwayel, A.},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2013},
+  Number                   = {10},
+  Pages                    = {2644--2656},
+  Volume                   = {60},
+
+  Doi                      = {10.1109/TCSI.2013.2279186},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6595153}
+}
+
+@InProceedings{boudem_93,
+  Title                    = {{A Generalized Precompiling Scheme for Surviving Path Memory Management in Viterbi Decoders}},
+  Author                   = {E. Boutillon and N. Demassieux},
+  Booktitle                = {Proc. 1993 International Symposium on Circuits and Systems (ISCAS '93)},
+  Year                     = {1993},
+
+  Address                  = {Chicago, Illinois, USA},
+  Month                    = may,
+  Pages                    = {1579--1582},
+
+  Optvolume                = {3},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bougro_03,
+  Title                    = {{VLSI Architectures for the MAP Algorithm}},
+  Author                   = {E. Boutillon and W. J. Gross and P. G. Gulak},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2003},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {175--185},
+  Volume                   = {51},
+
+  File                     = {bougro_03.pdf:bougro_03.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{bousan_13,
+  Title                    = {{C}ompression of redundancy free trellis stages in turbo-decoder},
+  Author                   = {Boutillon, E. and Sanchez-Rojas, J. and Marchand, C.},
+  Journal                  = {Electronics Letters},
+  Year                     = {2013},
+
+  Month                    = {March},
+  Number                   = {7},
+  Pages                    = {460-462},
+  Volume                   = {49},
+
+  Abstract                 = {For turbo codes with a coding rate close to one, the high puncturing rate induces long sequences of trellis without a redundancy bit. A simplification technique to compute the final state of a sequence of redundancy free trellis stages (RFTSs) is presented. It compresses a sequence of RFTSs of length N into a sequence of RFTSs of length m - 1 + (N mod (m - 1)), where m is the number of states of the trellis. The computation is reduced accordingly.},
+  Doi                      = {10.1049/el.2012.4433},
+  File                     = {bousan_13.pdf:bousan_13.pdf:PDF},
+  ISSN                     = {0013-5194},
+  Keywords                 = {data compression;decoding;trellis codes;turbo codes;RFTS;coding rate;puncturing rate;redundancy free trellis stage sequence;sequence compression;simplification technique;turbo-decoder},
+  Owner                    = {StW},
+  Timestamp                = {2014.11.13}
+}
+
+@Article{bousan_14,
+  Title                    = {{S}implified {C}ompression of {R}edundancy {F}ree {T}rellis {S}ections in {T}urbo {D}ecoder},
+  Author                   = {Boutillon, E. and Sanchez-Rojas, J.-L. and Marchand, C.},
+  Journal                  = {Communications Letters, IEEE},
+  Year                     = {2014},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {941-944},
+  Volume                   = {18},
+
+  Abstract                 = {It has been recently shown that a sequence of R = q(M - 1) redundancy free trellis stages of a recursive convolutional decoder can be compressed in a sequence of L = M - 1 trellis stages, where M is the number of states of the trellis and q is a positive integer. In this paper, we show that for an M state Turbo decoder, among the L compressed trellis stages, only m = 3 or even m = 2 are necessary. The so-called m-min algorithm can either be used to increase the throughput for decoding a high rate turbo-code and/or to reduce its power consumption.},
+  Doi                      = {10.1109/LCOMM.2014.2319257},
+  File                     = {bousan_14.pdf:bousan_14.pdf:PDF},
+  ISSN                     = {1089-7798},
+  Keywords                 = {convolutional codes;decoding;optimisation;redundancy;trellis codes;turbo codes;compressed trellis stages;high rate turbo-code;m-min algorithm;positive integer;power consumption;recursive convolutional decoder;redundancy free trellis sections;turbo decoder;Complexity theory;Decoding;Measurement;Redundancy;Throughput;Turbo codes;Vectors;Turbo code;convolutional codes;digital circuits;trellis},
+  Owner                    = {StW},
+  Timestamp                = {2014.11.13}
+}
+
+@Patent{bousch_15,
+  Title                    = {{Method} {for} {controlling} {a} {check} {node} {of} {a} {NB}-{LDPC} {decoder} {and} {corresponding} {check} {node}},
+  Nationality              = {France},
+  Number                   = {15290110.4},
+  Year                     = {2015},
+  Yearfiled                = {2015},
+  Author                   = {Boutillon, Emmanuel and Schl{\"a}fer, Philipp and Lehnigk-Emden, Timo},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.10.14}
+}
+
+@InProceedings{boupot_99,
+  Title                    = {{G}eneralized low density ({T}anner) codes},
+  Author                   = {Boutros, J. and Pothier, O. and Zemor, G. },
+  Booktitle                = {Proc. IEEE International Conference on Communications ICC '99},
+  Year                     = {1999},
+  Month                    = jun,
+  Pages                    = {441--445},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ICC.1999.767979},
+  File                     = {boupot_99.pdf:boupot_99.pdf:PDF},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.08.03}
+}
+
+@Article{boxmul_58,
+  Title                    = {{A} note on the generation of random normal deviates},
+  Author                   = {Box, G.E.P. and Muller, M.E.},
+  Journal                  = {The Annals of Mathematical Statistics},
+  Year                     = {1958},
+  Number                   = {2},
+  Pages                    = {610--611},
+  Volume                   = {29},
+
+  Cds_grade                = {0},
+  File                     = {boxmul_58.pdf:boxmul_58.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Institute of Mathematical Statistics},
+  Timestamp                = {2010.07.23}
+}
+
+@Book{boyvan_04,
+  Title                    = {{C}onvex {O}ptimization},
+  Author                   = {Stephen Boyd and Lieven Vandenberghe},
+  Publisher                = {Cambridge University Press},
+  Year                     = {2004},
+
+  Ccr_grade                = {n.a.},
+  Ccr_topic                = {NetControl Paper},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR},
+  Timestamp                = {2013.12.08}
+}
+
+@PhdThesis{Phdbrack08,
+  Title                    = {{A}pplication and {S}tandard {D}riven {LDPC} {C}ode {D}ecoder {D}evelopment},
+  Author                   = {Torben Brack},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2008},
+  Note                     = {ISBN 978-3-939432-72-2},
+
+  File                     = {Phdbrack08.pdf:Phdbrack08.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.21}
+}
+
+@InProceedings{braall_06,
+  Title                    = {{A synthesizable IP Core for WiMax 802.16e LDPC Code Decoding}},
+  Author                   = {T. Brack and M. Alles and F. Kienle and N. Wehn},
+  Booktitle                = {Proc. IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications},
+  Year                     = {2006},
+
+  Address                  = {Helsinki, Finland},
+  Month                    = sep,
+
+  File                     = {braall_06.pdf:braall_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{braall_07,
+  Title                    = {{A} {S}urvey on {LDPC} {C}odes and {D}ecoders for {OFDM}-based {UWB} {S}ystems},
+  Author                   = {T. Brack and M. Alles and T. Lehnigk-Emden and F. Kienle and N. Wehn and F. Berens and A. Ruegg},
+  Booktitle                = {Proc. VTC2007-Spring Vehicular Technology Conference IEEE 65th},
+  Year                     = {2007},
+
+  Address                  = {Dublin, Ireland},
+  Month                    = apr,
+  Pages                    = {1549 -- 1553},
+
+  File                     = {braall_07.pdf:braall_07.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{braall_07a,
+  Title                    = {{L}ow {C}omplexity {LDPC} {C}ode {D}ecoders for {N}ext {G}eneration {S}tandards},
+  Author                   = {T. Brack and M. Alles and T. Lehnigk-Emden and F. Kienle and N. Wehn and N.E. Insalata and F. Rossi and M. Rovini and L. Fanucci},
+  Booktitle                = {Proc. Design, Automation. Test in Europe Conference. Exhibition DATE '07},
+  Year                     = {2007},
+
+  Address                  = {Nice, France},
+  Month                    = apr,
+
+  File                     = {braall_07a.pdf:braall_07a.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{brakie_06,
+  Title                    = {{E}nhanced {C}hannel {C}oding for {OFDM}-based {UWB} {S}ystems},
+  Author                   = {T. Brack and F. Kienle and T. Lehnigk-Emden and M. Alles and N. Wehn and F. Berens},
+  Booktitle                = {Proc. IEEE 2006 International Conference on Ultra-Wideband},
+  Year                     = {2006},
+
+  Address                  = {Waltham, Massachusetts},
+  Month                    = sep,
+  Pages                    = {255--260},
+
+  File                     = {brakie_06.pdf:brakie_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{brakie_06a,
+  Title                    = {{Disclosing the LDPC Code Decoder Design Space}},
+  Author                   = {T. Brack and F. Kienle and N. Wehn},
+  Booktitle                = {Proc. Design, Automation and Test in Europe DATE '06},
+  Year                     = {2006},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+  Pages                    = {200--205},
+
+  File                     = {brakie_06a.pdf:brakie_06a.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{brawas_05,
+  Title                    = {{D}esign {S}pace {E}xploration for {F}requency {S}ynchronisation of {BPSK/QPSK} {B}ursts},
+  Author                   = {T. Brack and U. Wasenmüller and D. Schmidt and N. Wehn},
+  Booktitle                = {Advances in Radio Science},
+  Year                     = {2005},
+
+  Address                  = {Miltenberg, Germany},
+  Month                    = mar,
+  Pages                    = {337--341},
+  Volume                   = {3},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{brawas_05a,
+  Title                    = {{A} configurable {IP} {C}ore for {C}ombined {B}lind {F}requency and {P}hase {S}ynchronization of {MPSK} {B}ursts},
+  Author                   = {Torben Brack and Uwe Wasenmüller and Norbert Wehn},
+  Booktitle                = {Proc. 2005 IST Mobile and Wireless Communication Summit},
+  Year                     = {2005},
+
+  Address                  = {Dresden, Germany},
+  Month                    = jun,
+
+  File                     = {brawas_05a.pdf:brawas_05a.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{bradu_11,
+  Title                    = {{P}arallelisation {T}echniques for {R}andom {N}umber {G}enerators},
+  Author                   = {Thomas Bradley and Jacques {du Toit} and Mike Giles and Robert Tong and Paul Woodhams},
+  Booktitle                = {GPU Computing Gems},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2011},
+  Chapter                  = {16},
+  Edition                  = {{Emerald}},
+  Editor                   = {Wen-Mei W. Hwu},
+  Pages                    = {231-246},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@Article{bra_00,
+  Title                    = {{T}he opencv library},
+  Author                   = {Bradski, Gary},
+  Journal                  = {Doctor Dobbs Journal},
+  Year                     = {2000},
+  Note                     = {last access 2015-01-13},
+  Number                   = {11},
+  Pages                    = {120--126},
+  Volume                   = {25},
+
+  Owner                    = {Brugger},
+  Publisher                = {M AND T PUBLISHING INC},
+  Timestamp                = {2014.07.24},
+  Url                      = {http://opencv.org/}
+}
+
+@InProceedings{bra_09,
+  Title                    = {{P}recise {S}imulation of {I}nterrupts {U}sing a {R}ollback {M}echanism},
+  Author                   = {Brandner, Florian},
+  Booktitle                = {Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems},
+  Year                     = {2009},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {71--80},
+  Publisher                = {ACM},
+  Series                   = {SCOPES '09},
+
+  Acmid                    = {1543833},
+  ISBN                     = {978-1-60558-696-0},
+  Location                 = {Nice, France},
+  Numpages                 = {10},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-11},
+  Url                      = {http://dl.acm.org/citation.cfm?id=1543820.1543833}
+}
+
+@InBook{brasch_10,
+  Title                    = {{D}ynamically {R}econfigurable {S}ystems {A}rchitectures, {D}esign {M}ethods and {A}pplications},
+  Author                   = {Lars Braun and T. Schwalb and P. Graf and Michael Hübner and M. Ullmann and K. D. Mueller-Glaser and Jürgen Becker},
+  Chapter                  = {Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies},
+  Publisher                = {Springer},
+  Year                     = {2010},
+
+  Address                  = {Heidelberg},
+  Month                    = feb,
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.09.27}
+}
+
+@PhdThesis{Phdbrehm13,
+  Title                    = {{D}issertation in preparation},
+  Author                   = {Christian Brehm},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2013},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.12}
+}
+
+@InProceedings{breiln_11,
+  Title                    = {{A} scalable multi-{ASIP} architecture for standard compliant trellis decoding},
+  Author                   = {Brehm, C. and Ilnseher, T. and Wehn, N.},
+  Booktitle                = {Proc. Int. SoC Design Conf. (ISOCC)},
+  Year                     = {2011},
+  Pages                    = {349--352},
+
+  Cb_grade                 = {see also bor_10},
+  Doi                      = {10.1109/ISOCC.2011.6138782},
+  File                     = {breiln_11.pdf:breiln_11.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Brehm},
+  Timestamp                = {2012.03.30}
+}
+
+@InProceedings{bremay_12,
+  Title                    = {{A} {C}ase {S}tudy on {E}rror {R}esilient {A}rchitectures for {W}ireless {C}ommunication},
+  Author                   = {C. Brehm and M. May and C. Gimmler and N. Wehn},
+  Booktitle                = {Proc. {A}rchitecture of {C}omputing {S}systems},
+  Year                     = {2012},
+  Pages                    = {13-24},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Ee                       = {http://dx.doi.org/10.1007/978-3-642-28293-5_2},
+  File                     = {bremay_12.pdf:bremay_12.pdf:PDF},
+  Keywords                 = {AGWehn, Reliability}
+}
+
+@InProceedings{breweh_11,
+  Title                    = {{V}alidation of channel decoding {ASIP}s -- {A} case study},
+  Author                   = {Brehm, C. and Wehn, N. and Loitz, S. and Kunz, W.},
+  Booktitle                = {Proc. 22nd IEEE Int Rapid System Prototyping (RSP) Symp},
+  Year                     = {2011},
+  Pages                    = {74--78},
+
+  Doi                      = {10.1109/RSP.2011.5929978},
+  File                     = {breweh_11.pdf:breweh_11.pdf:PDF},
+  Keywords                 = {ASIP Turbo AGWehn},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@Article{brebos_98,
+  Title                    = {{S}oft-decision decoding of linear block codes as optimization problem},
+  Author                   = {Breitbach, Markus and Bossert, Martin and Lucas, Rainer and Kempter, Christian},
+  Journal                  = {European Transactions on Telecommunications},
+  Year                     = {1998},
+  Number                   = {3},
+  Pages                    = {289--293},
+  Volume                   = {9},
+
+  Doi                      = {10.1002/ett.4460090308},
+  File                     = {brebos_98.pdf:brebos_98.pdf:PDF},
+  ISSN                     = {1541-8251},
+  Keywords                 = {LPDecoding},
+  Owner                    = {Scholl},
+  Publisher                = {Wiley Subscription Services, Inc., A Wiley Company},
+  Timestamp                = {2012.03.05},
+  Url                      = {http://dx.doi.org/10.1002/ett.4460090308}
+}
+
+@Article{breli_16,
+  Title                    = {20 {Y}ears of {T}urbo {C}oding and {E}nergy-{A}ware {D}esign {G}uidelines for {E}nergy-{C}onstrained {W}ireless {A}pplications},
+  Author                   = {M. F. Brejza and L. Li and R. G. Maunder and B. M. Al-Hashimi and C. Berrou and L. Hanzo},
+  Journal                  = {IEEE Communications Surveys Tutorials},
+  Year                     = {2016},
+
+  Month                    = {Firstquarter},
+  Number                   = {1},
+  Pages                    = {8-28},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/COMST.2015.2448692},
+  ISSN                     = {1553-877X},
+  Keywords                 = {Internet of Things;broadcast communication;cellular radio;error correction codes;error statistics;turbo codes;wireless LAN;ASIC;BER;Internet of Things;bit error ratio;broadcast systems;cellular telephony;energy-aware design guidelines;energy-constrained applications;energy-constrained wireless;energy-efficient TC decoder application-specific integrated circuit;near-capacity error-correcting codes;signal-processing-related EC;spectrum-constrained wireless communication;transmission energy consumption;turbo coding;wireless communication;wireless local area network;wireless sensor networks;Algorithm design and analysis;Binary phase shift keying;Bit error rate;Convolutional codes;Decoding;Iterative decoding;Wireless communication;BCJR algorithm;Turbo code;energy efficiency;holistic design;optimization;wireless sensor network},
+  Owner                    = {StW},
+  Timestamp                = {2017.02.20}
+}
+
+@Article{bre_74,
+  Title                    = {{A}lgorithm 488: {A} {G}aussian {P}seudo-{R}andom {N}umber {G}enerator},
+  Author                   = {Brent, R.P.},
+  Journal                  = {Communications of the ACM},
+  Year                     = {1974},
+  Number                   = {12},
+  Pages                    = {704--706},
+  Volume                   = {17},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation},
+  File                     = {bre_74.pdf:bre_74.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2012.03.22}
+}
+
+@InProceedings{bre_05,
+  Title                    = {{M}ulti-{M}edia {A}pplications and {I}mprecise {C}omputation},
+  Author                   = {Breuer, M. A.},
+  Booktitle                = {Proc. 8th Euromicro Conference on Digital System Design},
+  Year                     = {2005},
+  Month                    = aug # {--} # sep,
+  Pages                    = {2--7},
+
+  Doi                      = {10.1109/DSD.2005.58},
+  File                     = {bre_05.pdf:bre_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.20}
+}
+
+@InProceedings{brieck_15,
+  Title                    = {{T}he next generation of virtual prototyping: {U}ltra-fast yet accurate simulation of {HW}/{SW} systems},
+  Author                   = {O. Bringmann and W. Ecker and A. Gerstlauer and A. Goyal and D. Mueller-Gritschneder and P. Sasidharan and S. Singh},
+  Booktitle                = {2015 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2015},
+  Month                    = {March},
+  Pages                    = {1698-1707},
+
+  Doi                      = {10.7873/DATE.2015.1105},
+  ISSN                     = {1530-1591},
+  Keywords                 = {digital simulation;formal verification;hardware-software codesign;multiprocessing systems;operating systems (computers);software performance evaluation;system-on-chip;virtual prototyping;virtual prototyping methods;hardware-software system simulation;hardware-software coverification;hardware-software performance analysis;hardware-software architecture exploration;software functionality;design complexity;ultra-fast host-compiled software models;execution times;timing behavior;operating system;target processor;memory system;abstract TLM-based communication models;simulation speed;hardware peripheral models;industrial flow;model development;multiprocessor system-on-chip platforms;Timing;Accuracy;Computational modeling;Kernel;Hardware;Time-varying systems},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-11}
+}
+
+@Article{bri_01,
+  Title                    = {{C}onvergence behavior of iteratively decoded parallel concatenated codes},
+  Author                   = {ten Brink, S},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2001},
+  Number                   = {10},
+  Pages                    = {1727--1737},
+  Volume                   = {49},
+
+  Abstract                 = {Mutual information transfer characteristics of soft in/soft out decoders are proposed as a tool to better understand the convergence behavior of iterative decoding schemes. The exchange of extrinsic information is visualized as a decoding trajectory in the extrinsic information transfer chart (EXIT chart). This allows the prediction of turbo cliff position and bit error rate after an arbitrary number of iterations. The influence of code memory, code polynomials as well as different constituent codes on the convergence behavior is studied for parallel concatenated codes. A code search based on the EXIT chart technique has been performed yielding new recursive systematic convolutional constituent codes exhibiting turbo cliffs at lower signal-to-noise ratios than attainable by previously known constituent},
+  Doi                      = {10.1109/26.957394},
+  File                     = {bri_01d.pdf:bri_01d.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {0090-6778},
+  Keywords                 = {InfTheory},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.18}
+}
+
+@InProceedings{bri_01b,
+  Title                    = {{C}onvergence of multidimensional iterative decoding schemes},
+  Author                   = {ten Brink, S},
+  Booktitle                = {Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on},
+  Year                     = {2001},
+  Month                    = nov,
+  Pages                    = {270--274vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ACSSC.2001.986918},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{bri_01c,
+  Title                    = {{C}ode doping for triggering iterative decoding convergence},
+  Author                   = {ten Brink, S},
+  Booktitle                = {Information Theory, 2001. Proceedings. 2001 IEEE International Symposium on},
+  Year                     = {2001},
+  Month                    = jun,
+  Pages                    = {235},
+
+  Doi                      = {10.1109/ISIT.2001.936098},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{bri_00,
+  Title                    = {{R}ate one-half code for approaching the {S}hannon limit by 0.1 d{B}},
+  Author                   = {ten Brink, S},
+  Booktitle                = {Electronics Letters},
+  Year                     = {2000},
+  Month                    = jul,
+  Number                   = {15},
+  Pages                    = {1293--1294},
+  Volume                   = {36},
+
+  Doi                      = {10.1049/el:20000953},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{bri_99,
+  Title                    = {{I}terative decoding for multicode {CDMA}},
+  Author                   = {ten Brink, S},
+  Booktitle                = {Vehicular Technology Conference, 1999 IEEE 49th},
+  Year                     = {1999},
+  Month                    = may,
+  Pages                    = {1876--1880vol.3},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/VETEC.1999.778363},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{bri_99a,
+  Title                    = {{C}onvergence of iterative decoding},
+  Author                   = {ten Brink, S},
+  Booktitle                = {Electronics Letters},
+  Year                     = {1999},
+  Month                    = may,
+  Number                   = {10},
+  Pages                    = {806--808},
+  Volume                   = {35},
+
+  Doi                      = {10.1049/el:19990555},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{briere_04,
+  Title                    = {{A} close-to-capacity dirty paper coding scheme},
+  Author                   = {ten Brink, S and Erez, U.},
+  Booktitle                = {Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on},
+  Year                     = {2004},
+  Month                    = jun # {--} # jul,
+  Pages                    = {533},
+
+  Doi                      = {10.1109/ISIT.2004.1365573},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{brihoc_02,
+  Title                    = {{Detection thresholds of iterative MIMO processing}},
+  Author                   = {ten Brink, S and Hochwald, B.M.},
+  Booktitle                = {Information Theory, 2002. Proceedings. 2002 IEEE International Symposium on},
+  Year                     = {2002},
+  Pages                    = {22},
+
+  Doi                      = {10.1109/ISIT.2002.1023294},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{brikra_03,
+  Title                    = {{D}esign of repeat-accumulate codes for iterative detection and decoding},
+  Author                   = {ten Brink, S and Kramer, G.},
+  Journal                  = {Signal Processing, IEEE Transactions on [see also Acoustics, Speech, and Signal Processing, IEEE Transactions on]},
+  Year                     = {2003},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {2764--2772},
+  Volume                   = {51},
+
+  Doi                      = {10.1109/TSP.2003.818250},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{brikra_03a,
+  Title                    = {{Turbo Processing for Scalar and Vector Channels}},
+  Author                   = {ten Brink, S and G. Kramer},
+  Booktitle                = {Proc. 3nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {23--30},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{brikra_04,
+  Title                    = {{D}esign of low-density parity-check codes for modulation and detection},
+  Author                   = {ten Brink, S and Kramer, G. and Ashikhmin, A.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2004},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {670--678},
+  Volume                   = {52},
+
+  Doi                      = {10.1109/TCOMM.2004.826370},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{brimah_04,
+  Title                    = {{I}mplementation aspects of high-speed wireless {LAN} systems},
+  Author                   = {ten Brink, S and Mahadevappa, R.},
+  Booktitle                = {Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on},
+  Year                     = {2004},
+  Month                    = nov,
+  Pages                    = {789--793Vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ACSSC.2004.1399244},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{brisan_00,
+  Title                    = {{T}wo-dimensional iterative {APP} channel estimation and decoding for {OFDM} systems},
+  Author                   = {ten Brink, S and Sanzi, F. and Speidel, J.},
+  Booktitle                = {Global Telecommunications Conference, 2000. GLOBECOM '00. IEEE},
+  Year                     = {2000},
+  Month                    = nov # {--} # dec,
+  Pages                    = {741--745vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/GLOCOM.2000.891238},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{brispe_98,
+  Title                    = {{Iterative demapping for QPSK modulation}},
+  Author                   = {ten Brink, S and Speidel, J. and Han, R.-H.},
+  Booktitle                = {Electronics Letters},
+  Year                     = {1998},
+  Month                    = jul,
+  Number                   = {15},
+  Pages                    = {1459--1460},
+  Volume                   = {34},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{brispe_98a,
+  Title                    = {{I}terative demapping and decoding for multilevel modulation},
+  Author                   = {ten Brink, S and Speidel, J. and Ran-Hong Yan},
+  Booktitle                = {Global Telecommunications Conference, 1998. GLOBECOM 98. The Bridge to Global Integration. IEEE},
+  Year                     = {1998},
+  Month                    = nov,
+  Pages                    = {579--584vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/GLOCOM.1998.775793},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{brihag_97,
+  Title                    = {{A} history of the invention of the transistor and where it will lead us},
+  Author                   = {Brinkman, W. F. and Haggan, D. E. and Troutman, W. W.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {1997},
+  Number                   = {12},
+  Pages                    = {1858--1865},
+  Volume                   = {32},
+
+  Doi                      = {10.1109/4.643644},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.18}
+}
+
+@InCollection{brijoh_04,
+  Title                    = {{A}pplication of {P}roperty {C}hecking and {U}nderlying {T}echniques},
+  Author                   = {R. Brinkmann and P. Johannsen and K. Winkelmann},
+  Booktitle                = {Advanced Formal Verification},
+  Publisher                = {Springer US},
+  Year                     = {2005},
+  Editor                   = {R. Drechsler},
+  Pages                    = {125-166},
+
+  ISBN                     = {978-1-4020-2530-3},
+  Url                      = {http://dx.doi.org/10.1007/1-4020-2530-0_4}
+}
+
+@InProceedings{bri_16,
+  Title                    = {{T}rends in wireless communications towards 5{G} networks - {T}he influence of e-health and {I}o{T} applications},
+  Author                   = {J. M. C. Brito},
+  Booktitle                = {2016 International Multidisciplinary Conference on Computer and Energy Science (SpliTech)},
+  Year                     = {2016},
+  Month                    = {July},
+  Pages                    = {1-7},
+
+  Doi                      = {10.1109/SpliTech.2016.7555949},
+  Keywords                 = {5G mobile communication;Internet of Things;health care;5G networks;Internet of Things;IoT;e-health;fifth generation mobile networks;wireless communications;5G mobile communication;Internet of things;Market research;Medical services;Mobile computing;5G networks;e-health;internet of things;technological trends;wireless communications},
+  Owner                    = {StW},
+  Timestamp                = {2017.02.20}
+}
+
+@Article{brogla_97,
+  Title                    = {{A} continuity correction for discrete barrier options.},
+  Author                   = {Broadie, Mark and Glasserman, Paul and Kou, Steven},
+  Journal                  = {Math. Finance },
+  Year                     = {1997},
+  Number                   = {4},
+  Pages                    = {325-349},
+  Volume                   = {7},
+
+  Abstract                 = {Summary: The payoff of a barrier option depends on whether or not a specified asset price, index, or rate reaches a specified level during the life of the option. Most models for pricing barrier options assume continuous monitoring of the barrier; under this assumption, the option can often be priced in closed form. Many (if not most) real contracts with barrier provisions specify discrete monitoring instants; there are essentially no formulas for pricing these options, and even numerical pricing is difficult. We show, however, that discrete barrier options can be priced with remarkable accuracy using continuous barrier-formulas by applying a simple continuity correction to the barrier. The correction shifts the barrier away from the underlying by a factor of $\exp(\beta \sigma\sqrt {\Delta t})$, where $\beta\approx 0.5826$, $\sigma$ is the underlying valatility, and $\Delta t$ is the time between monitoring instants. The correction is justified both theoretically and experimentally.},
+  Classmath                = {{*91B28 (Finance etc.) 60K40 (Physical appl. of random processes) }},
+  Doi                      = {10.1111/1467-9965.00035},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Timestamp                = {2014.05.30}
+}
+
+@Article{brokay_06,
+  Title                    = {{E}xact {S}imulation of {S}tochastic {V}olatility and {O}ther {A}ffine {J}ump {D}iffusion {P}rocesses},
+  Author                   = {Mark Broadie and Özgür Kaya},
+  Journal                  = {Operations Research},
+  Year                     = {2006},
+  Number                   = {2},
+  Pages                    = {217-231},
+  Volume                   = {54},
+
+  Cds_grade                = {0},
+  Cds_review               = {exact volatility simulation in Heston model},
+  Doi                      = {10.1287/opre.1050.0247},
+  Eprint                   = { http://dx.doi.org/10.1287/opre.1050.0247 },
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.23},
+  Url                      = { http://dx.doi.org/10.1287/opre.1050.0247 
+}
+}
+
+@Article{bro_60,
+  Title                    = {{E}rror {D}etecting and {C}orrecting {B}inary {C}odes for {A}rithmetic {O}perations},
+  Author                   = {Brown, David T.},
+  Journal                  = {IRE Transactions on Electronic Computers},
+  Year                     = {1960},
+  Number                   = {3},
+  Pages                    = {333--337},
+
+  Doi                      = {10.1109/TEC.1960.5219855},
+  File                     = {bro_60.pdf:bro_60.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2011.08.04}
+}
+
+@Electronic{bro_11,
+  Title                    = {{D}ieharder: {A} {R}andom {N}umber {T}est {S}uite},
+  Author                   = {Robert G. Brown},
+  HowPublished             = {\url{http://www.phy.duke.edu/~rgb/General/dieharder.php}},
+  Language                 = {en},
+  Month                    = mar,
+  Note                     = {Version 3.31.0, last access 2014-07-02},
+  Url                      = {http://www.phy.duke.edu/~rgb/General/dieharder.php},
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@Electronic{Brown2011,
+  Title                    = {{D}ieharder: {A} {R}andom {N}umber {T}est {S}uite},
+  Author                   = {Robert G. Brown},
+  HowPublished             = {\url{http://www.phy.duke.edu/~rgb/General/dieharder.php}},
+  Language                 = {en},
+  Month                    = mar,
+  Note                     = {Version 3.31.0},
+  Url                      = {http://www.phy.duke.edu/~rgb/General/dieharder.php},
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@Article{bru_06,
+  Title                    = {{A}lgorithms for constructing (0,1)-matrices with prescribed row and column sum vectors},
+  Author                   = {Richard A. Brualdi},
+  Journal                  = {Discrete Mathematics},
+  Year                     = {2006},
+  Pages                    = {3054--3062},
+  Volume                   = {306},
+
+  Owner                    = {lehmannk},
+  Timestamp                = {2008.02.04}
+}
+
+@Article{bru_80,
+  Title                    = {{M}atrices of zeros and ones with fixed row and column sum vectors},
+  Author                   = {Brualdi, Richard A},
+  Journal                  = {Linear algebra and its applications},
+  Year                     = {1980},
+  Pages                    = {159--231},
+  Volume                   = {33},
+
+  Owner                    = {Brugger},
+  Publisher                = {Elsevier},
+  Timestamp                = {2015.08.09}
+}
+
+@Misc{brubeyond14,
+  Title                    = {{B}eyond the abstract machine model - {H}ow looking at real computing systems leads to new algorithmic insights and massive speedups: two case studies},
+
+  Author                   = {Christian Brugger},
+  HowPublished             = {Invited talk, Dagstuhl Seminar 14461 - High-performance Graph Algorithms and Applications in Computational Science},
+  Month                    = nov,
+  Year                     = {2014},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{brucustom14,
+  Title                    = {{C}ustom {C}omputing {S}ystems for {M}onte {C}arlo {O}ption {P}ricing in the {H}eston {M}odel},
+
+  Author                   = {Christian Brugger},
+  HowPublished             = {Invited Talk, Reconfigurable Architectures in Finance Tutorial, IEEE Field Programmable Logic and Applications (FPL)},
+  Month                    = sep,
+  Year                     = {2014},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Article{bruchi_16,
+  Title                    = {{I}ncreasing sampling efficiency for the fixed degree sequence model with phase transitions},
+  Author                   = {Brugger, Christian
+and Chinazzo, André Lucas
+and John, Alexandre Flores
+and De Schryver, Christian
+and Wehn, Norbert
+and Schlauch, Wolfgang
+and Zweig, Katharina Anna},
+  Journal                  = {Social Network Analysis and Mining (SNAM)},
+  Year                     = {2016},
+
+  Month                    = oct,
+  Number                   = {1},
+  Pages                    = {100},
+  Volume                   = {6},
+
+  Abstract                 = {Real-world network data is often very noisy and contains erroneous or missing edges. These superfluous and missing edges can be identified statistically by assessing the number of common neighbors of the two incident nodes. To evaluate whether this number of common neighbors, the so-called co-occurrence, is statistically significant, a comparison with the expected co-occurrence in a suitable random graph model is required. For networks with a skewed degree distribution, including most real-world networks, it is known that the fixed degree sequence model (FDSM), which maintains the degrees of nodes, is favorable over using simplified graph models that are based on an independence assumption. However, the use of a FDSM requires sampling from the space of all graphs with the given degree sequence and measuring the co-occurrence of each pair of nodes in each of the samples, since there is no known closed formula known for this statistic. While there exist log-linear approaches such as Markov chain Monte Carlo sampling, the computational complexity still depends on the length of the Markov chain and the number of samples, which is significant in large-scale networks. In this article, we show based on ground truth data for different data sets that there are various phase transition-like tipping points that enable us to choose a comparatively low number of samples and to reduce the length of the Markov chains without reducing the quality of the significance test. As a result, the computational effort can be reduced by an order of magnitudes. Furthermore, we present and evaluate practically usable strategies for speeding up the randomization process of input graphs and heuristics for phase transition-based computation stopping.},
+  Doi                      = {10.1007/s13278-016-0407-0},
+  File                     = {bruchi_16.pdf:bruchi_16.pdf:PDF},
+  ISSN                     = {1869-5469},
+  Keywords                 = {AG Wehn},
+  Owner                    = {CDS},
+  Timestamp                = {2016-10-24},
+  Url                      = {http://dx.doi.org/10.1007/s13278-016-0407-0}
+}
+
+@InProceedings{bruchi_15,
+  Title                    = {{E}xploiting {P}hase {T}ransitions for the {E}fficient {S}ampling of the {F}ixed {D}egree {S}equence {M}odel},
+  Author                   = {Brugger, Christian and Chinazzo, André Lucas and John, Alexandre Flores and De Schryver, Christian and Wehn, Norbert and Spitz, Andreas and Zweig, Katharina Anna},
+  Booktitle                = {Proceedings of the 2015 IEEE/ACM International Conference on Advances in Social Networks Analysis and Mining (ASONAM)},
+  Year                     = {2015},
+
+  Address                  = {Paris, France},
+  Month                    = aug,
+  Organization             = {IEEE},
+  Pages                    = {308--313},
+  Publisher                = {ACM},
+  Series                   = {ASONAM '15},
+
+  Abstract                 = {Real-world network data is often very noisy and contains erroneous or missing edges. These superfluous and missing edges can be identified statistically by assessing the number of common neighbors of the two incident nodes. To evaluate whether this number of common neighbors, the so called co-occurrence, is statistically significant, a comparison with the expected co-occurrence in a suitable random graph model is required. For networks with a skewed degree distribution, including most real-world networks, it is known that the fixed degree sequence model, which maintains the degrees of nodes, is favourable over using simplified graph models that are based on an independence assumption. However, the use of a fixed degree sequence model requires sampling from the space of all graphs with the given degree sequence and measuring the co-occurrence of each pair of nodes in each of the samples, since there is no known closed formula for this statistic. While there exist log-linear approaches such as Markov chain Monte Carlo sampling, the computational complexity still depends on the length of the Markov chain and the number of samples, which is significant in large-scale networks. In this article, we show based on ground truth data that there are various phase transition-like tipping points that enable us to choose a comparatively low number of samples and to reduce the length of the Markov chains without reducing the quality of the significance test. As a result, the computational effort can be reduced by an order of magnitudes.},
+  Acmid                    = {2809388},
+  Doi                      = {10.1145/2808797.2809388},
+  File                     = {bruchi_15.pdf:bruchi_15.pdf:PDF},
+  ISBN                     = {978-1-4503-3854-7},
+  Keywords                 = {AG Wehn},
+  Location                 = {Paris, France},
+  Numpages                 = {6},
+  Owner                    = {Brugger},
+  Timestamp                = {2016-01-26},
+  Url                      = {http://doi.acm.org/10.1145/2808797.2809388}
+}
+
+@InProceedings{bruchi_15_unpublished,
+  Title                    = {{E}xploiting {P}hase {T}ransitions for the {E}fficient {S}ampling of the {F}ixed {D}egree {S}equence {M}odel},
+  Author                   = {Brugger, Christian and Chinazzo, André Lucas and John, Alexandre Flores and De Schryver, Christian and Wehn, Norbert and Spitz, Andreas and Zweig, Katharina Anna},
+  Booktitle                = {Advances in Social Networks Analysis and Mining (ASONAM), 2015 IEEE/ACM International Conference on},
+  Year                     = {2015},
+  Organization             = {IEEE},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.16}
+}
+
+@InProceedings{brudal_15,
+  Title                    = {{A} {Q}uantitative {C}ross-{A}rchitecture {S}tudy of {M}orphological {I}mage {P}rocessing on {CPU}s, {GPU}s, and {FPGA}s},
+  Author                   = {Brugger, Christian and Dal'Aqua, Lorenzo and Varela, Javier Alejandro and De Schryver, Christian and Sadri, Mohammadsadegh and Wehn, Norbert and Klein, Martin and Siegrist, Michael},
+  Booktitle                = {Proceedings of the 2015 IEEE Symposium on Computer Applications \& Industrial Electronics (ISCAIE)},
+  Year                     = {2015},
+
+  Address                  = {Langkawi, Malaysia},
+  Month                    = apr,
+  Pages                    = {201--206},
+
+  Abstract                 = {The rapidly growing applications based on morphological operations in image processing and computer vision make efficient implementations of these key blocks an important topic of research. Nevertheless, a detailed comparison of the energy efficiency and performance of these implementations that covers all available major hardware platforms is still missing. In this paper we evaluate the performance and power consumption of the most efficient available morphological image processing algorithms for CPU, GPU, and FPGA platforms in detail. In addition, we study the suitability of available morphological library units for high-level synthesis and compare the results with an optimized hand-coded FPGA implementation. We demonstrate that even high-end GPUs cannot achieve the throughputs of modern CPUs and FPGAs by far. Our experimental results show that an FPGA implementation is 8???10 times more energy efficient for this application, being comparable in speed to CPUs for large kernels.},
+  Cds_grade                = {5},
+  Doi                      = {10.1109/ISCAIE.2015.7298356},
+  File                     = {brudal_15.pdf:brudal_15.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Brugger},
+  Timestamp                = {2016-01-26}
+}
+
+@InCollection{brude_15_unpublished,
+  Title                    = {{B}ringing {F}lexibility to {FPGA} {B}ased {P}ricing {S}ystems},
+  Author                   = {Brugger, Christian and De Schryver, Christian and Wehn, Norbert},
+  Booktitle                = {FPGA Based Accelerators for Financial Applications},
+  Publisher                = {Springer Book},
+  Year                     = {2015},
+  Editor                   = {Christian De Schryver},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2013.06.06}
+}
+
+@Article{brugri_17,
+  Title                    = {{A} {M}emory {C}entric {A}rchitecture of the {L}ink {A}ssessment {A}lgorithm in {L}arge {G}raphs},
+  Author                   = {Brugger, Christian and Grigorovici, Valentin and Jung, Matthias and De Schryver, Christian and Weis, Christian and Wehn, Norbert and Zweig, Katharina Anna},
+  Journal                  = {IEEE Design \& Test},
+  Year                     = {2018},
+
+  Month                    = {Feb},
+  Number                   = {1},
+  Pages                    = {7-15},
+  Volume                   = {35},
+
+  Doi                      = {10.1109/MDAT.2017.2750900},
+  ISSN                     = {2168-2356},
+  Keywords                 = {computer graphics;storage management;graph detection;hardware architecture;link assessment algorithm;memory centric architecture;Algorithm design and analysis;Hardware;Memory architecture;Optimization;Random access memory;Social network services;ASIC;Cluster;Graph Processing;Hardware Accelerator;Link Assessment;Network Motifs;Noisy Large-scale Data;Structural Node Similarity},
+  Owner                    = {MJ},
+  Timestamp                = {2018-02-20}
+}
+
+@Misc{bruamar15,
+  Title                    = {{A}mar {M}ukherjee {B}est {P}aper {A}ward},
+
+  Author                   = {Christian Brugger and Valentin Grigorovici and Matthias Jung and Christian Weis and Christian De Schryver and Katharina A. Zweig and Norbert Wehn},
+  HowPublished             = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France},
+  Month                    = jul,
+  Note                     = {For the Paper titled "A Custom Computing System for Finding Similarties in Complex Networks"},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.31}
+}
+
+@InProceedings{brugri_15,
+  Title                    = {{A} {C}ustom {C}omputing {S}ystem for {F}inding {S}imilarties in {C}omplex {N}etworks},
+  Author                   = {Christian Brugger and Valentin Grigorovici and Matthias Jung and Christian Weis and Christian De Schryver and Katharina A. Zweig and Norbert Wehn},
+  Booktitle                = {Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
+  Year                     = {2015},
+
+  Address                  = {Montpellier, France},
+  Month                    = jul,
+  Pages                    = {262--267},
+
+  Abstract                 = {Complex graphs are at the heart of today’s big data chal- lenges like recommendation systems, customer behavior mod- eling, or incident detection systems. One reoccurring task in these fields is the extraction of network motifs, reoccur- ring and statistically significant subgraphs. In this work we propose a precisely tailored embedded architecture for com- puting similarities based on one special network motif, the co-occurrence. It is based on efficient and scalable building blocks that exploit well-tuned algorithmic refinements and an optimized graph data representation approach. On chip, our solution features a customized cache design and a light- weight data path that allows the system to perform over 10,000 graph operations per cycle on each chip. We provide detailed area, energy, and timing results for a 28 nm ASIC process and DDR3 memory devices. Compared to an Intel cluster, our proposed solution uses 44x less memory and is 224x more energy efficient.},
+  Doi                      = {10.1109/ISVLSI.2015.78},
+  File                     = {brugri_15.pdf:brugri_15.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Brugger},
+  Timestamp                = {2015-07-13}
+}
+
+@Misc{bruoptimal15,
+  Title                    = {{A}n {O}ptimal {M}icroarchitecture for {F}inding {S}imilarities in {C}omplex {N}etworks {B}ased on {O}ptimal {M}emory {H}ierarchies},
+
+  Author                   = {Christian Brugger and Valentin Grigorovici and Matthias Jung and Christian Weis and Christian De Schryver and Katharina A. Zweig and Norbert Wehn},
+  HowPublished             = {WIP, IEEE/ACM Design Automation Conference (DAC)},
+  Month                    = jun,
+  Year                     = {2015},
+
+  Doi                      = {10.13140/RG.2.1.4296.5605},
+  File                     = {bruoptimal15.pdf:bruoptimal15.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Brugger},
+  Timestamp                = {2015-07-13}
+}
+
+@Article{bruhil_14,
+  Title                    = {{RIVER}: {R}econfigurable {F}low and {F}abric for {R}eal-{T}ime {S}ignal {P}rocessing on {FPGA}s},
+  Author                   = {Brugger, Christian and Hillenbrand, Dominic and Balzer, Matthias},
+  Journal                  = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
+  Year                     = {2014},
+  Number                   = {3},
+  Pages                    = {24},
+  Volume                   = {7},
+
+  Owner                    = {Brugger},
+  Publisher                = {ACM},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{brufirst13,
+  Title                    = {{F}irst {B}est {P}aper {A}ward, 1500 {EUR}},
+
+  Author                   = {Christian Brugger and Matthias Jung and Steffen Omland},
+  HowPublished             = {Young Researcher Symposium (YRS), Kaiserslautern, Germany},
+  Month                    = nov,
+  Note                     = {For the Paper titled "Virtual Platforms for Fast Exploration of Computing Systems in Finance"},
+  Year                     = {2013},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.31}
+}
+
+@InProceedings{brujun_13,
+  Title                    = {{V}irtual {P}latforms for {F}ast {E}xploration of {C}omputing {S}ystems in {F}inance},
+  Author                   = {Christian Brugger and Matthias Jung and Steffen Omland},
+  Booktitle                = {Young Researcher Symposium, YRS 2013. Proceedings},
+  Year                     = {2013},
+  Month                    = nov,
+  Note                     = {ISBN 978-3-8396-0628-5, \url{http://publica.fraunhofer.de/documents/N-266783.html}},
+  Pages                    = {18--23},
+  Publisher                = {Fraunhofer Verlag},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Article{bruliu_15,
+  Title                    = {{P}recision-tuning and hybrid pricer for closed-form solution-based {H}eston calibration},
+  Author                   = {Brugger, Christian and Liu, Gongda and De Schryver, Christian and Wehn, Norbert},
+  Journal                  = {Concurrency and Computation: Practice and Experience (JCCPE)},
+  Year                     = {2015},
+
+  Month                    = oct,
+
+  Abstract                 = {Calibration methods are the heart of modeling any financial process. While for the Heston model (semi) closed-form solutions exist for simple products, their evaluation involves complex functions and infinite integrals. So far, these integrals can only be solved with time-consuming numerical methods. For that reason, calibration consumes a large portion of available compute power in the daily finance business.However, more and more theoretical and practical subtleties have been discovered over the years, and today, a large number of calibration methods are available. Currently, there is no clear indication which numerical method should be used for a specific calibration purpose under given speed and accuracy constraints. With this publication, we aim at closing this gap. We derive a novel methodology for systematically finding the best methods for a well-defined accuracy target. For a practical setup, we study the available popular closed-form solutions and integration algorithms. In total, we compare 14 numerical methods, including adaptive quadrature and Fourier methods. For a target accuracy of 10−3, we show that adaptive Gauss–Kronrod methods are best on CPUs for the unrestricted parameter set. Furthermore, we introduce hybrid pricer methods that combine quadrature and fast Fourier transform pricers, what gives us another 2.4× speedup. Copyright © 2015 John Wiley & Sons, Ltd.},
+  Cds_grade                = {5},
+  Doi                      = {10.1002/cpe.3694},
+  File                     = {bruliu_15.pdf:bruliu_15.pdf:PDF},
+  ISSN                     = {1532-0634},
+  Keywords                 = {AGWehn},
+  Owner                    = {CDS},
+  Timestamp                = {2015-10-30},
+  Url                      = {http://dx.doi.org/10.1002/cpe.3694}
+}
+
+@Article{bruliu_15_unpublished,
+  Title                    = {{P}recision-{T}uning and {H}ybrid {P}ricer for {C}losed-{F}orm {S}olution based {H}eston {C}alibration},
+  Author                   = {Brugger, Christian and Liu, Gongda and De Schryver, Christian and Wehn, Norbert},
+  Journal                  = {Journal of Concurrency and Computation: Practice and Experience (JCCPE)},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Publisher                = {Wiley Online Library},
+  Timestamp                = {2015.07.25}
+}
+
+@InProceedings{bruliu_14,
+  Title                    = {{A} systematic {M}ethodology for {A}nalyzing {C}losed-{F}orm {H}eston {P}ricer regarding their {A}ccuracy and {R}untime},
+  Author                   = {Brugger, Christian and Liu, Gongda and de Schryver, Christian and Wehn, Norbert},
+  Booktitle                = {Proceedings of the 7th Workshop on High Performance Computational Finance},
+  Year                     = {2014},
+
+  Address                  = {Piscataway, NJ, USA},
+  Pages                    = {9--16},
+  Publisher                = {IEEE Press},
+  Series                   = {WHPCF '14},
+
+  Abstract                 = {Calibration methods are the heart of modeling any financial process. While for the Heston model (semi) closed-form solutions exist for calibrating to simple products, their evaluation involves complex functions and infinite integrals. So far these integrals can only be solved with time-consuming numerical methods. For that reason, calibration consumes a large portion of available compute power in the daily finance business and it is worth checking for the most optimal available methods with respect to runtime and accuracy.
+
+However, over the years more and more theoretical and practical subtleties have been revealed and today a large number of approaches are available, including different formulations of closed-formulas and various integration algorithms like quadrature or Fourier methods. Currently there is no clear indication which pricing method should be used for a specific calibration purpose with additional speed and accuracy constraints. With this publication we are closing this gap. We derive a novel methodology to systematically find the best methods for a well-defined accuracy target among a huge set of available methods. For a practical setup we study the available popular closed-form solutions and integration algorithms from literature. In total we compare 14 pricing methods, including adaptive quadrature and Fourier methods. For a target accuracy of 10-3 we show that static Gauss-Legendre are best on CPUs for the unrestricted parameter set. Further we show that for restricted Carr-Madan formulation the methods are 3.6x faster. We also show that Fourier methods are even better when pricing at least 10 options with the same maturity but different strikes.},
+  Acmid                    = {2688426},
+  Cds_grade                = {5},
+  Cds_keywords             = {calibration, FFT, Carr-Madan},
+  Doi                      = {10.1109/WHPCF.2014.13},
+  File                     = {bruliu_14.pdf:bruliu_14.pdf:PDF},
+  ISBN                     = {978-1-4799-7027-8},
+  Keywords                 = {AG Wehn, finance},
+  Location                 = {New Orleans, Louisiana},
+  Numpages                 = {8},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.18}
+}
+
+@Misc{bruhyper14,
+  Title                    = {{H}y{PER} -- {A} {P}latform based {M}ethodology to bring {F}lexibility to {H}ybrid {FPGA}/{CPU} {P}latforms in {F}inance},
+
+  Author                   = {Christian Brugger and Christian de Schryver and Norbert Wehn},
+  HowPublished             = {Demo at the 24th IEEE International Conference of Field Programmable Logic and Applications (FPL)},
+  Month                    = sep,
+  Year                     = {2014},
+
+  Booktitle                = {Demo, 24th IEEE International Conference of Field Programmable Logic and Applications (FPL)},
+  Cds_grade                = {5},
+  Doi                      = {10.1109/FPL.2014.6927458},
+  File                     = {brusch_14a.pdf:brusch_14a.pdf:PDF},
+  Keywords                 = {AG Wehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.15}
+}
+
+@InProceedings{brusch_14a,
+  Title                    = {{H}y{PER}: {A} {R}untime {R}econfigurable {A}rchitecture for {M}onte {C}arlo {O}ption {P}ricing in the {H}eston {M}odel},
+  Author                   = {Christian Brugger and Christian de Schryver and Norbert Wehn},
+  Booktitle                = {Proccedings of the 24th IEEE International Conference of Field Programmable Logic and Applications (FPL)},
+  Year                     = {2014},
+  Month                    = sep,
+  Pages                    = {1-8},
+
+  Abstract                 = {High-speed and energy-efficient computations are mandatory in the financial and insurance industry to survive in competition and meet the federal reporting requirements. On a hybrid CPU/FPGA system we propose a modular pricing engine and derive a novel algorithmic extension able to exploit online dynamic reconfiguration. The result is a high-performance and energy-efficient pricing system suitable for exotic option pricing in the state-of-the-art Heston market model. With the online reconfiguration extension our hybrid pricing system is nearly two orders of magnitude faster than high-end Intel CPUs, while consuming the same power.},
+  Cds_grade                = {5},
+  Doi                      = {10.1109/FPL.2014.6927458},
+  File                     = {brusch_14a.pdf:brusch_14a.pdf:PDF},
+  Keywords                 = {AG Wehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.15}
+}
+
+@Unpublished{brusch_14a_unpublished,
+  Title                    = {{H}y{PER}: {A} {R}untime {R}econfigurable {A}rchitecture for {M}onte {C}arlo {O}ption {P}ricing in the {H}eston {M}odel},
+  Author                   = {Christian Brugger and Christian de Schryver and Norbert Wehn},
+  Note                     = {Accepted for publication in Proccedings of the IEEE International Conference of Field Programmable Logic and Applications (FPL)},
+
+  Month                    = sep,
+  Year                     = {2014},
+
+  Keywords                 = {AG Wehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.15}
+}
+
+@Misc{brusch_14b,
+  Title                    = {{A} {R}untime {R}econfigurable {A}rchitecture for {M}onte {C}arlo {O}ption {P}ricing in the {H}eston {M}odel},
+
+  Author                   = {Christian Brugger and Christian de Schryver and Norbert Wehn},
+  HowPublished             = {WIP, IEEE/ACM Design Automation Conference (DAC)},
+  Month                    = jun,
+  Year                     = {2014},
+
+  Keywords                 = {AG Wehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.23}
+}
+
+@Conference{brusch_14c,
+  Title                    = {{H}y{PER}: {A} {R}untime {R}econfigurable {A}rchitecture for {M}onte {C}arlo {O}ption {P}ricing in the {H}eston {M}odel},
+  Author                   = {Christian Brugger and Christian de Schryver and Norbert Wehn},
+  Booktitle                = {WIP, IEEE/ACM Design Automation Conference (DAC)},
+  Year                     = {2014},
+  Month                    = jun,
+
+  Abstract                 = {High-speed and energy-ecient computations are mandatory in the financial and insurance industry to survive in competition and meet the federal reporting requirements. On a hybrid CPU/FPGA system we propose a modular pricing engine and derive a novel algorithmic extension able to exploit online dynamic reconfiguration. The result is a high-performance and energy-efficient pricing system suitable for exotic option pricing in the state-of-the-art Heston market model. With the extension our hybrid pricing system is nearly two orders of magnitude faster than high-end Intel CPUs, while consuming the same power.},
+  Cds_review               = {Poster for work-in-progress-session},
+  Doi                      = {10.13140/2.1.1005.4403},
+  File                     = {brusch_14c.pdf:brusch_14c.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.02}
+}
+
+@Conference{brusch_14d,
+  Title                    = {{H}eterogeneous {P}latforms for {B}ig {D}ata {A}pplications},
+  Author                   = {Christian Brugger and Christian de Schryver and Norbert Wehn},
+  Booktitle                = {International Workshop on Heterogeneous Computing Platforms (HCP)},
+  Year                     = {2014},
+  Month                    = nov,
+
+  Abstract                 = {Extracting value out of big data is all about predicting the future based on observations of the past. A more accurate algorithm means more value, and in the era of data deluge the only limit are in many cases the available computing resources. In the age of cloud computing, massive computing resources are right at our finger tips, promising near endless capabilities. However, the generated value by using more resources needs to be in balance with the additional costs. Furthermore, many big data applications scale very badly on such homogeneous computing systems, resulting in non-optimal utilization of the employed platforms.
+In contrast to homogeneous systems, heterogeneous systems adapt much better to the actual computing needs and come with a lower energy consumption. They are already emerging today with the wide adoption of accelerator cards like GPUs, FPGAs, or many-core architectures like the Xeon Phi extending standard CPUs nodes. However, heterogeneous systems come with unique challenges, i.e. first what is the right partitioning and mapping of different parts of the algorithm to the different subsystems and second how to efficiently explore those choices without having to create time-consuming implementations for all the choices.
+In this poster we tackle dedicated heterogeneous computing platforms for two big data applications: Financial Model Calibration and Graph Similarity Analysis. For both of them we present efficient hybrid architectures based on CPUs and FPGAs. First results show massive improvements in both runtime and energy-efficiency compared to homogeneous implementations on CPU clusters.
+Many financial applications such as derivative pricing or risk management rely on assumptions about the future evolvement of assets on financial markets. The behavior of such assets is in general described by (complex) market models that incorporate a number of tuning parameters. Calibrating those model parameters to the markets is crucial to achieve meaningful simulation results. Many institutes spend the whole night running those calibration tasks on their clusters to have the values ready on the next morning (typically up to >10k assets with up to 2k options / asset).
+While calibration tries to minimize the error between simulated and observed asset prices by varying the model parameters, more than 99% of compute time are spent in evaluating (semi-)closed-form solutions for standard products such as plain vanilla calls. By implementing accelerators with optimized data paths for computing those prices we show that we achieve a 4x faster system that only consumes 3% of energy on a hybrid Xilinx Zynq device compared to a multi-core Xeon CPU. 
+Finding similarities in complex networks is a classic big data problem and the core of every recommendation system. One example is the Netflix dataset containing 17k movies, 480k users and 200 million ratings, with the goal to find related movies for recommendations. The algorithm we have chosen extracts significant information by comparing the dataset with random graphs, generated without similarities. Generating the graphs involves in our example 1013 random accesses to memory and the results matrix has 1010 values, posing huge challenges for the memory hierarchy of standard CPU systems. We present a CPU/FPGA architecture that is 20x faster and 1000x more power efficient than a cluster implementation. It exploits custom data paths, and very high bit-level parallelism based on 1-4 bit operations. With a custom cache architecture the system is able to calculate more than 200 movies in parallel. Those optimizations are unique to FPGAs, while the outer part of the algorithm is handled by the CPU.},
+  Cds_grade                = {5},
+  Doi                      = {10.13140/2.1.1887.4568},
+  File                     = {brusch_14d.pdf:brusch_14d.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.12}
+}
+
+@InProceedings{brusch_14,
+  Title                    = {{M}ixed {P}recision {M}ultilevel {M}onte {C}arlo on {H}ybrid {C}omputing {S}ystems},
+  Author                   = {Brugger, C. and de Schryver, C. and Wehn, N. and Omland, S. and Hefter, M. and Ritter, K. and Kostiuk, A. and Korn, R.},
+  Booktitle                = {Proceedings of the 2014 IEEE Conference on Computational Intelligence for Financial Engineering Economics (CIFEr)},
+  Year                     = {2014},
+  Month                    = mar,
+  Pages                    = {215-222},
+
+  Abstract                 = {Nowadays, high-speed computations are mandatory for financial and insurance institutes to survive in competition and to fulfill the regulatory reporting requirements that have just toughened over the last years. A majority of these computations are carried out on huge computing clusters, which are an ever increasing cost burden for the financial industry. There, state-of-the-art CPU and GPU architectures execute arithmetic operations with pre-defined precisions only, that may not meet the actual requirements for a specific application. Reconfigurable architectures like field programmable gate arrays (FPGAs) have a huge potential to accelerate financial simulations while consuming only very low energy by exploiting dedicated precisions in optimal ways. In this work we present a novel methodology to speed up multilevel Monte Carlo (MLMC) simulations on reconfigurable architectures. The idea is to aggressively lower the precisions for different parts of the algorithm without loosing any accuracy at the end. For this, we have developed a novel heuristic for selecting an appropriate precision at each stage of the simulation that can be executed with low costs at runtime. Further, we introduce a cost model for reconfigurable architectures and minimize the cost of our algorithm without changing the overall error. We consider the showcase of pricing Asian options in the Heston model. For this setup we improve one of the most advanced simulation methods by a factor of 3-9x on the same platform.},
+  Doi                      = {10.1109/CIFEr.2014.6924076},
+  File                     = {brusch_14.pdf:brusch_14.pdf:PDF},
+  Keywords                 = {AG Wehn},
+  Owner                    = {Brugger},
+  Timestamp                = {2014.04.10}
+}
+
+@Misc{brutowards15,
+  Title                    = {{T}owards {P}ortable {L}ibraries for {H}ybrid {S}ystems},
+
+  Author                   = {Christian Brugger and Christian De Schryver},
+  HowPublished             = {Thematic Session at the HiPEAC Computer Systems Week, Spring 2015, \url{https://www.hipeac.org/events/activities/7229/towards-portable-libraries-for-hybrid-systems/}},
+  Month                    = may,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@InCollection{brusch_15,
+  Title                    = {{B}ringing {F}lexibility to {FPGA} {B}ased {P}ricing {S}ystems},
+  Author                   = {Christian Brugger and Christian De Schryver and Norbert Wehn},
+  Booktitle                = {FPGA Based Accelerators for Financial Applications},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2015},
+  Edition                  = {1st},
+  Editor                   = {De Schryver, Christian},
+  Month                    = jul,
+  Pages                    = {167--190},
+
+  Abstract                 = {High-speed and energy-efficient computations are mandatory in the financial and insurance industry to survive in competition and meet the federal reporting requirements. While FPGA based systems have demonstrated to provide huge speedups, they are perceived to be much harder to adapt to new products. In this chapter we introduce HyPER, a novel methodology for designing Monte Carlo based pricing engines for hybrid CPU/FPGA systems. Following this approach, we derive a high-performance and flexible system for exotic option pricing in the state-of-the-art Heston market model. Exemplarily, we show how to find an efficient implementation for barrier option pricing on the Xilinx Zynq 7020 All Programmable SoC with HyPER. The constructed system is nearly two orders of magnitude faster than high-end Intel CPUs, while consuming the same power.},
+  Doi                      = {10.1007/978-3-319-15407-7_8},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-08-21}
+}
+
+@Unpublished{bruvar_15,
+  Title                    = {{R}everse {L}ongstaff-{S}chwartz {A}merican {O}ption {P}ricing on hybrid {CPU/FPGA} {S}ystems},
+  Author                   = {Christian Brugger and Javier Alejandro Varela and Norbert Wehn and Songyin Tang and Ralf Korn},
+  Note                     = {{A}ccepted for publication, {IEEE} {C}onference {D}esign, {A}utomation and {T}est in {E}urope ({DATE}), {M}arch, 2015, {G}renoble, {F}rance},
+
+  Month                    = {mar},
+  Year                     = {2015},
+
+  Abstract                 = {Abstract—In today’s markets, high-speed and energy-efficient computations are mandatory in the financial and insurance industry. At the same time, the gradual convergence of highperformance computing with embedded systems is having a huge impact on the design methodologies, where dedicated accelerators are implemented to increase performance and energy efficiency. This paper follows this trend and presents a novel way to price high-dimensional American options using techniques of the embedded community. The proposed architecture targets heterogeneous CPU/FPGA systems, and it exploits the FPGA reconfiguration to deliver high-throughput. With a bit-true algorithmic transformation based on recomputation, it is possible to eliminate the memory bottleneck and access costs. The result is a pricing system that is 16x faster and 268x more energy-efficient than an optimized Intel CPU implementation.},
+  Owner                    = {varela},
+  Timestamp                = {2014.12.20}
+}
+
+@InProceedings{bruvar_15a,
+  Title                    = {{R}everse {L}ongstaff-{S}chwartz {A}merican {O}ption {P}ricing on hybrid {CPU/FPGA} {S}ystems},
+  Author                   = {Christian Brugger and Javier Alejandro Varela and Norbert Wehn and Songyin Tang and Ralf Korn},
+  Booktitle                = {Proceedings of the 2015 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
+  Year                     = {2015},
+  Month                    = {mar},
+  Pages                    = {1599-1602},
+
+  Abstract                 = {In today’s markets, high-speed and energy-efficient
+computations are mandatory in the financial and insurance
+industry. At the same time, the gradual convergence of highperformance
+computing with embedded systems is having a huge
+impact on the design methodologies, where dedicated accelerators
+are implemented to increase performance and energy efficiency.
+This paper follows this trend and presents a novel way to
+price high-dimensional American options using techniques of
+the embedded community. The proposed architecture targets
+heterogeneous CPU/FPGA systems, and it exploits the FPGA
+reconfiguration to deliver high-throughput. With a bit-true algorithmic
+transformation based on recomputation, it is possible to
+eliminate the memory bottleneck and access costs. The result is a
+pricing system that is 16x faster and 268x more energy-efficient
+than an optimized Intel CPU implementation.},
+  File                     = {bruvar_15a.pdf:bruvar_15a.pdf:PDF},
+  Owner                    = {varela},
+  Timestamp                = {2015-07-23}
+}
+
+@Misc{bruwinning15,
+  Title                    = {{W}inning {P}roject in the {C}ategory {H}igh {L}evel {S}ynthesis},
+
+  Author                   = {Christian Brugger and Norbert Wehn},
+  HowPublished             = {Xilinx OpenHardware 2015 Competition. Awarded at the 25th IEEE International Conference of Field Programmable Logic and Applications (FPL), London, UK},
+  Month                    = sep,
+  Note                     = {For the Project "Bringing Flexibility to FPGAs with HyPER: Exotic Derivative Pricing on Zynq"},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.31}
+}
+
+@InProceedings{brutowards14,
+  Title                    = {{T}owards {H}igh-{P}erformance {R}econfigurable {C}omputing: {C}urrent {C}hallenges of a {R}apid and {H}igh-{L}evel {D}esign {F}low},
+  Author                   = {Christian Brugger and Norbert Wehn},
+  Booktitle                = {ACACES 2014 Poster Abstracts},
+  Year                     = {2014},
+  Month                    = jul,
+  Note                     = {ISBN 978-88-905806-2-8},
+  Organization             = {Advanced Computer Architecture and Compilation for High-Performance Embedded Systems, ACACES 2014},
+  Pages                    = {13--16},
+  Publisher                = {HiPEAC the European Network of Exellence on High Performance and Embedded Architecture and Compilation},
+
+  HowPublished             = {ACACES 2014 Poster Abstracts, Advanced Computer Architecture and Compilation for High-Performance Embedded Systems},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{brumethodology13,
+  Title                    = {{M}ethodology for {R}apid {A}ccelerator {D}evelopment {A}pplied to {F}inancial {A}pplications},
+
+  Author                   = {Christian Brugger and Norbert Wehn},
+  HowPublished             = {Demo Night of the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancún},
+  Month                    = dec,
+  Year                     = {2013},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Article{bruwei_14,
+  Title                    = {{O}n parallel random number generation for accelerating simulations of communication systems},
+  Author                   = {Christian Brugger and Stefan Weithoffer and Christian de Schryver and Uwe Wasenmüller and Norbert Wehn},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2014},
+
+  Month                    = nov,
+  Pages                    = {75-81},
+  Volume                   = {12},
+
+  Abstract                 = {Powerful compute clusters and multi-core systems have become widely available in research and industry nowadays. This boost in utilizable computational power tempts people to run compute-intensive tasks on those clusters, either for speed or accuracy reasons. Especially Monte Carlo simulations with their inherent parallelism promise very high speedups. Nevertheless, the quality of Monte Carlo simulations strongly depends on the quality of the employed random numbers. In this work we present a comprehensive analysis of state-of-the-art pseudo random number generators like the MT19937 or the WELL generator used for parallel stream generation in different settings. These random number generators can be realized in hardware as well as in software and help to accelerate the analysis (or simulation) of communications systems. We show that it is possible to generate high-quality parallel random number streams with both generators, as long as some configuration constraints are met. We furthermore depict that distributed simulations with those generator types are viable even to very high degrees of parallelism.},
+  Cds_grade                = {5},
+  Doi                      = {10.5194/ars-12-75-2014},
+  File                     = {bruwei_14.pdf:bruwei_14.pdf:PDF},
+  Keywords                 = {random numbers, AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.12},
+  Url                      = {http://www.adv-radio-sci.net/12/75/2014/}
+}
+
+@Unpublished{bruwei_14_unpublished,
+  Title                    = {{O}n {P}arallel {R}andom {N}umber {G}eneration for {A}ccelerating {S}imulations of {C}ommunication {S}ystems},
+  Author                   = {Christian Brugger and Stefan Weithoffer and Christian de Schryver and Uwe Wasenmüller and Norbert Wehn},
+  Note                     = {Accepted for publication in Advances in Radio Science},
+  Year                     = {2014},
+
+  Keywords                 = {random numbers, AG Wehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.04.04}
+}
+
+@Article{raysec_02,
+  Title                    = {{P}rincipal component value at risk},
+  Author                   = {Raymond Brummelhuis and Antonio Cordoba and Maite Quintanilla and Luis A. Seco},
+  Journal                  = {Mathematical Finance},
+  Year                     = {2002},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {23-43},
+  Volume                   = {12},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@InProceedings{bucbur_96,
+  Title                    = {{To compress or not to compress?}},
+  Author                   = {G. Buch and F. Burkert and J. Hagenauer and B. Kukla},
+  Booktitle                = {Proc. 1996 Global Telecommunications Conference (GLOBECOM '96)},
+  Year                     = {1996},
+
+  Address                  = {London, United Kingdom},
+  Month                    = nov,
+  Pages                    = {198--203},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{bna_15,
+  Title                    = {{T\"atigkeitsbericht 2014/2015 Telekommunikation}},
+
+  Author                   = {Bundesnetzagentur},
+  Month                    = Nov,
+  Year                     = {2015},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.02.21}
+}
+
+@InProceedings{burbro_00,
+  Title                    = {{Design Issues for Dynamic Voltage Scaling}},
+  Author                   = {T. Burd and R. Brodersen},
+  Booktitle                = {Proc. 2000 International Symposium on Low Power Electronics and Design (ISLPED '00)},
+  Year                     = {2000},
+
+  Address                  = {Rapallo, Italy},
+  Month                    = aug,
+  Pages                    = {9--14},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{burper_00,
+  Title                    = {{A Dynamic Voltage Scaled Microprocessor System}},
+  Author                   = {T. Burd and T. Pering and A. Stratakos and R. Brodersen},
+  Booktitle                = {International Solid-State Circuits Conference Digest of Technical Papers},
+  Year                     = {2000},
+
+  Address                  = {San Francisco, California, USA},
+  Month                    = feb,
+  Pages                    = {294--295},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{burbro_02,
+  Title                    = {{Energy Efficient Microprocessor Design}},
+  Author                   = {T. D. Burd and R. W. Brodersen},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {2002},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{burfai_10,
+  Title                    = {{N}umerical {A}nalysis},
+  Author                   = {Richard L. Burden and J. Douglas Faires},
+  Publisher                = {Brooks Cole},
+  Year                     = {2010},
+  Edition                  = {9th},
+  Month                    = aug,
+
+  Cds_grade                = {0},
+  Cds_keywords             = {numerical analysis},
+  Cds_read                 = {2012-02-29},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.29}
+}
+
+@PhdThesis{Phdburg06,
+  Title                    = {{VLSI} {C}ircuits for {MIMO} {C}ommunication {S}ystems},
+  Author                   = {Andreas Burg},
+  School                   = {Swiss Federal Institute of Technology, Zurich},
+  Year                     = {2006},
+
+  File                     = {Phdburg06.pdf:Phdburg06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.01.30}
+}
+
+@Article{burbor_05,
+  Title                    = {{VLSI} implementation of {MIMO} detection using the sphere decoding algorithm},
+  Author                   = {Burg, A. and Borgmann, M. and Wenk, M. and Zellweger, M. and Fichtner, W. and Bolcskei, H.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2005},
+  Number                   = {7},
+  Pages                    = {1566--1577},
+  Volume                   = {40},
+
+  Abstract                 = {Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mb/s at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit-error-rate degradation and achieves a throughput of 170 Mb/s at the same SNR. The three key contributing factors to high throughput and low complexity are: depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the &#8467;<sup>&infin;</sup>-instead of &#8467;<sup>2</sup>-norm, and, finally, the efficient implementation of the enumeration approach recently proposed in . The resulting ASICs currently rank among the fastest reported MIMO detector implementations.},
+  Doi                      = {10.1109/JSSC.2005.847505},
+  File                     = {burbor_05.pdf:burbor_05.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {0018-9200},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.18}
+}
+
+@Article{buraus_97,
+  Title                    = {{T}he {S}imple{S}calar tool set, version 2.0},
+  Author                   = {Burger, Doug and Austin, Todd M.},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {1997},
+
+  Month                    = jun,
+  Number                   = {3},
+  Volume                   = {25},
+
+  Acmid                    = {268810},
+  Doi                      = {10.1145/268806.268810},
+  Issue_date               = {June 1997},
+  Numpages                 = {13},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20},
+  Url                      = {http://doi.acm.org/10.1145/268806.268810}
+}
+
+@Article{schhae_10,
+  Title                    = {{R}econfiguration {T}echniques for self-{X} {P}ower and {P}erformance {M}anagement on {X}ilinx {V}irtex-{II}/{V}irtex-{II}-{P}ro {FPGA}s},
+  Author                   = {C. Schuck, B. Haetzer, J. Becker},
+  Journal                  = {International Journal of Reconfigurable Computing},
+  Year                     = {2011},
+  Volume                   = {Vol. 2011},
+
+  Cb_grade                 = {- gelesen
+- Reliability
+- Karlsruhe, reconfiguration},
+  Doi                      = {doi:10.1155/2011/671546},
+  File                     = {schhae_10.pdf:schhae_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{caitar_98,
+  Title                    = {{B}it-interleaved coded modulation},
+  Author                   = {Caire, G. and Taricco, G. and Biglieri, E.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1998},
+  Number                   = {3},
+  Pages                    = {927--946},
+  Volume                   = {44},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.06}
+}
+
+@Article{calbro_10,
+  Title                    = {{C}an {S}ubthreshold and {N}ear-{T}hreshold {C}ircuits {G}o {M}ainstream?},
+  Author                   = {Calhoun, B.H. and Brooks, D.},
+  Journal                  = {Micro, IEEE},
+  Year                     = {2010},
+  Number                   = {4},
+  Pages                    = {80-85},
+  Volume                   = {30},
+
+  Doi                      = {10.1109/MM.2010.60},
+  ISSN                     = {0272-1732},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.03.25}
+}
+
+@InProceedings{cammod_01,
+  Title                    = {{Designing LDPC codes using bit-filling}},
+  Author                   = {J. Campello and D.S. Modha and S. Rajagopalan},
+  Booktitle                = {Proc. 2001 International Conference on Communications (ICC '01)},
+  Year                     = {2001},
+
+  Address                  = {Helsinki,Finland},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{camcap_03,
+  Title                    = {{A reconfigurable processor architecture and software development environment for embedded systems}},
+  Author                   = {F. Campi and A. Cappelli and R. Guerrieri and A. Lodi and M. Toma and A. La Rosa and L. Lavagno and C. Passerone and R. Canegallo},
+  Booktitle                = {{ Parallel and Distributed Processing Symposium, 2003. Proceedings. International}},
+  Year                     = {2003},
+
+  Address                  = {Nice, France},
+  Month                    = apr,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{cancho_13,
+  Title                    = {{F}rom {S}oftware to {A}ccelerators with {L}eg{U}p {H}igh-level {S}ynthesis},
+  Author                   = {Canis, Andrew and Choi, Jongsok and Fort, Blair and Lian, Ruolong and Huang, Qijing and Calagar, Nazanin and Gort, Marcel and Qin, Jia Jun and Aldham, Mark and Czajkowski, Tomasz and Brown, Stephen and Anderson, Jason},
+  Booktitle                = {Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems},
+  Year                     = {2013},
+
+  Address                  = {Piscataway, NJ, USA},
+  Pages                    = {18:1--18:9},
+  Publisher                = {IEEE Press},
+  Series                   = {CASES '13},
+
+  Acmid                    = {2555747},
+  Articleno                = {18},
+  ISBN                     = {978-1-4799-1400-5},
+  Keywords                 = {FPGA, hardware accelerators, high-level synthesis},
+  Location                 = {Montreal, Quebec, Canada},
+  Numpages                 = {9},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.27},
+  Url                      = {http://dl.acm.org/citation.cfm?id=2555729.2555747}
+}
+
+@Article{caocla_07,
+  Title                    = {{M}apping {S}tatistical {P}rocess {V}ariations {T}oward {C}ircuit {P}erformance {V}ariability: {A}n {A}nalytical {M}odeling {A}pproach},
+  Author                   = {Yu Cao and Clark, L. T.},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2007},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {1866--1873},
+  Volume                   = {26},
+
+  Doi                      = {10.1109/TCAD.2007.895613},
+  File                     = {caocla_07.pdf:caocla_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{carcar_12,
+  Title                    = {{LARA}: {A}n {A}spect-oriented {P}rogramming {L}anguage for {E}mbedded {S}ystems},
+  Author                   = {Cardoso, Jo\~{a}o M.P. and Carvalho, Tiago and Coutinho, Jos{\'e} G.F. and Luk, Wayne and Nobre, Ricardo and Diniz, Pedro and Petrov, Zlatko},
+  Booktitle                = {Proceedings of the 11th Annual International Conference on Aspect-oriented Software Development},
+  Year                     = {2012},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {179--190},
+  Publisher                = {ACM},
+  Series                   = {AOSD '12},
+
+  Acmid                    = {2162071},
+  Doi                      = {10.1145/2162049.2162071},
+  ISBN                     = {978-1-4503-1092-5},
+  Keywords                 = {FPGAs, aspect-oriented programming, compilers, domain-specific languages, embedded systems, reconfigurable computing},
+  Location                 = {Potsdam, Germany},
+  Numpages                 = {12},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://doi.acm.org/10.1145/2162049.2162071}
+}
+
+@Book{cardin_11a,
+  Title                    = {{C}ompilation {T}echniques for {R}econfigurable {A}rchitectures},
+  Author                   = {Cardoso, J.M.P. and Diniz, P.C.},
+  Publisher                = {Springer US},
+  Year                     = {2011},
+  Series                   = {Current Topics in Microbiology and Immunology},
+
+  ISBN                     = {9780387096711},
+  Lccn                     = {78016343},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {https://books.google.de/books?id=4xwWNCiF9CgC}
+}
+
+@InCollection{cardin_11,
+  Title                    = {{REFLECT}: {R}endering {FPGA}s to {M}ulti-core {E}mbedded {C}omputing},
+  Author                   = {Cardoso, JoãoM.P. and Diniz, PedroC. and Petrov, Zlatko and Bertels, Koen and Hübner, Michael and van Someren, Hans and Gonçalves, Fernando and de Coutinho, JoséGabrielF. and Constantinides, GeorgeA. and Olivier, Bryan and Luk, Wayne and Becker, Juergen and Kuzmanov, Georgi and Thoma, Florian and Braun, Lars and Kühnle, Matthias and Nane, Razvan and Sima, VladMihai and Krátký, Kamil and Alves, JoséCarlos and Ferreira, JoãoCanas},
+  Booktitle                = {Reconfigurable Computing},
+  Publisher                = {Springer New York},
+  Year                     = {2011},
+  Editor                   = {Cardoso, João M. P. and Hübner, Michael},
+  Pages                    = {261-289},
+
+  Doi                      = {10.1007/978-1-4614-0061-5_11},
+  ISBN                     = {978-1-4614-0060-8},
+  Language                 = {English},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://dx.doi.org/10.1007/978-1-4614-0061-5_11}
+}
+
+@Book{carhue_11,
+  Title                    = {{R}econfigurable {C}omputing: {F}rom {FPGA}s to {H}ardware/{S}oftware {C}odesign},
+  Author                   = {Cardoso, J. and H{\"u}bner, M.},
+  Publisher                = {Springer New York},
+  Year                     = {2011},
+  Series                   = {Electrical engineering},
+
+  ISBN                     = {9781461400615},
+  Lccn                     = {2011933471},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {https://books.google.de/books?id=ycjIkoHzVYsC}
+}
+
+@InProceedings{carfag_07,
+  Title                    = {{P}arallel {A}lgebraic {A}pproach of {BCH} {C}oding in {VHDL}},
+  Author                   = {Cargnini, L.V. and Fagundes, R.D.R. and Bezerra, E.A. and Almeida, G.M.},
+  Booktitle                = {Computing in the Global Information Technology, 2007. ICCGI 2007. International Multi-Conference on},
+  Year                     = {2007},
+  Month                    = mar,
+  Pages                    = {22},
+
+  Abstract                 = {This work introduces an algebraic approach, using a Hardware Description Language (HDL) and shows that nowadays microelectronics technology could solve algebraic problems that were considered unsolvable using traditional sequential implementation forms as Berlekamp-Massey. An algebraic approach to implement Error Correcting Codes (ECC) is proposed, and implemented using a Hardware Description Language, specifically VHDL. The ECC designed for HDL algebraic implementation is Bose-Chaudhuri-Hocquenghem (BCH), that is one of the most important cyclic block codes. In this research work, we adopted n=63 and k=57, BCH(63,57) an usual configuration in many scientific communication systems as CCSDS telecommand systems of European Space Agency (ESA) and Agenda Espacial Brasileira (AEB). The achieved results clearly shows the main idea in our approach: to prove that an algebraic implementation is a far better approach, leading to an impressive efficiency, and much more suitable than any other sequential algorithm, even then the ones in a hardware version.},
+  Cds_grade                = {0},
+  Cds_keywords             = {BCH, FPGA},
+  Doi                      = {10.1109/ICCGI.2007.47},
+  File                     = {carfag_07.pdf:carfag_07.pdf:PDF},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.22}
+}
+
+@Article{carmad_99,
+  Title                    = {{O}ption {V}aluation {U}sing the {F}ast {F}ourier {T}ransform},
+  Author                   = {Carr, Peter and Madan, Dilip},
+  Journal                  = {Journal of Computational Finance},
+  Year                     = {1999},
+  Number                   = {4},
+  Pages                    = {61--73},
+  Volume                   = {2},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {calibration, FFT},
+  Cds_read                 = {2014-08-13},
+  Cds_review               = {FFT method for calibration + CPU results},
+  File                     = {carmad_99.pdf:carmad_99.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.08.13}
+}
+
+@InProceedings{carhei_13,
+  Title                    = {{T}he {S}ystems {H}acker's {G}uide to the {G}alaxy {E}nergy {U}sage in a {M}odern {S}martphone},
+  Author                   = {Carroll, Aaron and Heiser, Gernot},
+  Booktitle                = {Proceedings of the 4th Asia-Pacific Workshop on Systems},
+  Year                     = {2013},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {5:1--5:7},
+  Publisher                = {ACM},
+  Series                   = {APSys '13},
+
+  Acmid                    = {2500734},
+  Articleno                = {5},
+  Doi                      = {10.1145/2500727.2500734},
+  ISBN                     = {978-1-4503-2316-1},
+  Location                 = {Singapore, Singapore},
+  Numpages                 = {7},
+  Owner                    = {MJ},
+  Timestamp                = {2016-05-09},
+  Url                      = {http://doi.acm.org/10.1145/2500727.2500734}
+}
+
+@InProceedings{carhei_13a,
+  Title                    = {{T}he {S}ystems {H}acker's {G}uide to the {G}alaxy {E}nergy {U}sage in a {M}odern {S}martphone},
+  Author                   = {Aaron Carroll and Gernot Heiser},
+  Booktitle                = {Proceedings of the 4th Asia-Pacific Workshop on Systems},
+  Year                     = {2013},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {5:1--5:7},
+  Publisher                = {ACM},
+  Series                   = {APSys '13},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.04}
+}
+
+@Article{car_90,
+  Title                    = {{T}wo fast implementations of the \“minimal standard\” random number generator},
+  Author                   = {David F. Carta},
+  Journal                  = {Commun. ACM},
+  Year                     = {1990},
+
+  Month                    = jan,
+  Pages                    = {87--88},
+  Volume                   = {33},
+
+  Acmid                    = {76379},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generator},
+  Doi                      = {http://doi.acm.org/10.1145/76372.76379},
+  File                     = {car_90.pdf:car_90.pdf:PDF},
+  ISSN                     = {0001-0782},
+  Issue                    = {1},
+  Numpages                 = {2},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2011.12.15},
+  Url                      = {http://doi.acm.org/10.1145/76372.76379}
+}
+
+@InProceedings{carhsi_99,
+  Title                    = {{I}mpulse: building a smarter memory controller},
+  Author                   = {Carter, John and Hsieh, Wilson and Stoller, Leigh and Swanson, Mark. and Zhang, Lixin and Brunvand, Erik. and Davis, Al. and Kuo, Chen-Chi and Kuramkote, Ravindra and Parker, Michael and Schaelicke, Lambert and Tateyama, Terry},
+  Booktitle                = {High-Performance Computer Architecture, 1999. Proceedings. Fifth International Symposium On},
+  Year                     = {1999},
+  Month                    = {Jan},
+  Pages                    = {70-79},
+
+  Doi                      = {10.1109/HPCA.1999.744334},
+  Keywords                 = {cache storage;conjugate gradient methods;database management systems;memory architecture;multimedia computing;DRAM access latency hiding;Impulse memory system architecture;NAS conjugate gradient benchmark;application-specific optimization;bus design;cache design;configurable physical address remapping;data access;data caching;database programs;memory controller;memory-bound program performance;multimedia programs;performance;prefetching;processor design;scientific applications;Bandwidth;Cities and towns;Computer science;Databases;Delay;Electronic switching systems;Microprocessors;Prefetching;Random access memory;Sparse matrices},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11}
+}
+
+@Article{cascas_17,
+  Title                    = {{Relevant applications of Monte Carlo simulation in Solvency II}},
+  Author                   = {Giuseppe Casarano and Gilberto Castellani and Luca Passalacqua and Francesca Perla and Paolo Zanetti},
+  Journal                  = {Soft Computing},
+  Year                     = {2017},
+
+  Month                    = {Mar},
+  Number                   = {5},
+  Pages                    = {1181--1192},
+  Volume                   = {21},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.08}
+}
+
+@InProceedings{casrov_06,
+  Title                    = {{Adaptive Single Phase Decoding of LDPC Codes}},
+  Author                   = {M. Castano and M. Rovini and N. E. Insalata and F. Rossi and R. Merlino and C. Ciofi and L. Fanucci},
+  Booktitle                = {Proc. 4th International Symposium on Turbo Codes and Related Topics},
+  Year                     = {2006},
+
+  Address                  = {Munich, Germany},
+  Month                    = apr,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{casvel_10,
+  Title                    = {{T}race-based {KPN} composability analysis for mapping simultaneous applications to {MPS}o{C} platforms},
+  Author                   = {Jeronimo Castrillon and Ricardo Velasquez and Anastasia Stulova and Weihua Sheng and Jianjiang Ceng and Rainer Leupers and Gerd Ascheid and Heinrich Meyr},
+  Booktitle                = {Design, Automation Test in Europe Conference Exhibition (DATE), 2010},
+  Year                     = {2010},
+  Month                    = {8-12},
+  Pages                    = {753 -758},
+
+  Abstract                 = {Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compiler-centric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.},
+  Cds_grade                = {0},
+  File                     = {casvel_10.pdf:casvel_10.pdf:PDF},
+  ISSN                     = {1530-1591},
+  Owner                    = {CdS},
+  Timestamp                = {2010.08.05}
+}
+
+@Book{Catthoor2010,
+  Title                    = {{U}ltra-{L}ow {E}nergy {D}omain-{S}pecific {I}nstruction-{S}et {P}rocessors},
+  Author                   = {Catthoor, F. and Raghavan, P. and Lambrechts, A. and Jayapala, M. and Kritikakou, A. and Absar, J.},
+  Publisher                = {Springer},
+  Year                     = {2010},
+
+  Address                  = {Netherlands},
+
+  Doi                      = {10.1007/978-90-481-9528-2},
+  Optnote                  = {ISBN 978-90-481-9528-2},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.02}
+}
+
+@InProceedings{catweh_91,
+  Title                    = {{Novel ASIC Architecture and Synthesis Methodologies for Future Multiplexed Datapath Designs}},
+  Author                   = {F.~Catthoor and N.~Wehn and B.~Courtois and H.~DeMan et al.},
+  Booktitle                = {Proc. Advanced Computer Technology 5th Annual European Computer Conference Reliable Systems and Applications CompEuro '91},
+  Year                     = {1991},
+  Pages                    = {506--511},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{catwuy_98,
+  Title                    = {{Custom Memory Management Methodology}},
+  Author                   = {F. Catthoor and S. Wuytack and E. De Greef and F. Balasa and L. Nachtergaele and A. Vandercappelle},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {1998},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{cavvay_03,
+  Title                    = {{Viturbo: A reconfigurable architecture for Viterbi and Turbo decoding}},
+  Author                   = {J. R. Cavallaro and M. Vaya},
+  Booktitle                = {{Proc. 2003 Conference on Acoustics, Speech, and Signal Processing (ICASSP '03)}},
+  Year                     = {2003},
+
+  Address                  = {Hong Kong, P.R.China},
+  Month                    = apr,
+  Pages                    = {497--500},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{ccsds2003synchronization,
+  Title                    = {{S}ynchronization and {C}hannel {C}oding},
+  Author                   = {CCSDS, TM},
+  Journal                  = {Blue Book},
+  Year                     = {2003},
+  Number                   = {1},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.03.02}
+}
+
+@InProceedings{cencas_08,
+  Title                    = {{MAPS}: {A}n integrated framework for {MPS}o{C} application parallelization},
+  Author                   = {Ceng, J. and Castrillon, J. and Sheng, W. and Scharwachter, H. and Leupers, R. and Ascheid, G. and Meyr, H. and Isshiki, T. and Kunieda, H.},
+  Booktitle                = {Proc. 45th ACM/IEEE Design Automation Conf. DAC 2008},
+  Year                     = {2008},
+  Pages                    = {754--759},
+
+  Abstract                 = {In the past few years, <span class='snippet'>MPSoC</span> has become the most popular solution <span class='snippet'>for</span> embedded computing. However, the challenge of programming MPSoCs also comes as the biggest side-effect of the solution. Especially, when designers have to face the legacy C code accumulated through the years, the tool support is mostly unsatisfactory. In this paper, we propose <span class='snippet'>an</span> <span class='snippet'>integrated</span> <span class='snippet'>framework</span>, <span class='snippet'>MAPS</span>, which aims at parallelizing C <span class='snippet'>applications</span> <span class='snippet'>for</span> <span class='snippet'>MPSoC</span> platforms. It extracts coarse-grained parallelism on a novel granularity level. A set of tools have been developed <span class='snippet'>for</span> the <span class='snippet'>framework</span>. We will introduce the major components and their functionalities. Two case studies will be given, which demonstrate the use of <span class='snippet'>MAPS</span> on two different kinds of <span class='snippet'>applications</span>. In both cases the proposed <span class='snippet'>framework</span> helps the programmer to extract parallelism efficiently.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Partitioning, MPSoC, Multicore, Mapping, Tool, Software},
+  Cds_read                 = {2010-05-07},
+  Cds_review               = {MAPS = MPSoC Application Programming Studio
+Framework and toolset for mapping software onto MPSoCs
+Programmer obtains proposals for partitioning the source code into Coupled Blocks (CB) that can be seen as tasks
+TCT (Tightly-Coupled Threading) backend allows efficiency considerations after partitioning},
+  File                     = {cencas_08.pdf:cencas_08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.05.07}
+}
+
+@Misc{cerare,
+  Title                    = {{A}re we too {H}ard for {A}gile?},
+
+  Author                   = {François Cerisier and Mike Bartley},
+  HowPublished             = {Design and Reuse, \url{http://www.design-reuse.com/articles/32442/are-we-too-hard-for-agile.html}},
+  Note                     = {last access 2015-06-26},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.26}
+}
+
+@Conference{ces_14,
+  Title                    = {{A} brief history of {FD}-{SOI}: a faster, cooler, simpler alternative technology for {I}o{T}, mobile and servers},
+  Author                   = {Giorgio Cesana},
+  Booktitle                = {Proc. nano-tera},
+  Year                     = {2014},
+
+  Address                  = {Lausanne, Switzerland},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.08.20}
+}
+
+@Article{cesboe_11,
+  Title                    = {{A}lgorithms for {I}nterpolation-{B}ased {QR} {D}ecomposition in {MIMO}-{OFDM} {S}ystems},
+  Author                   = {Cescato, D. and Boelcskei, H.},
+  Journal                  = {Signal Processing, IEEE Transactions on},
+  Year                     = {2011},
+
+  Month                    = {april },
+  Number                   = {4},
+  Pages                    = {1719 -1733},
+  Volume                   = {59},
+
+  Doi                      = {10.1109/TSP.2010.2104149},
+  File                     = {cesboe_11.pdf:cesboe_11.pdf:PDF},
+  ISSN                     = {1053-587X},
+  Keywords                 = {MIMO-OFDM system;channel matrices;computational complexity;in-depth complexity analysis;interpolation-based QR decomposition algorithms;multiple input multiple output wireless system;orthogonal frequency division multiplexing;polynomial matrix;very large scale integration;MIMO communication;OFDM modulation;VLSI;computational complexity;interpolation;polynomial matrices;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.12.18}
+}
+
+@InProceedings{cevleb_10,
+  Title                    = {{A} 5.35 mm2 10{GBASE}-{T} {E}thernet {LDPC} decoder chip in 90 nm {CMOS}},
+  Author                   = {A. Cevrero and Y. Leblebici and P. Ienne and A. Burg},
+  Booktitle                = {Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian},
+  Year                     = {2010},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/ASSCC.2010.5716619},
+  Keywords                 = {CMOS integrated circuits;energy conservation;message passing;parity check codes;telecommunication standards;100BASE-T Ethernet;CMOS;Ethernet LDPC decoder chip;IEEE 802.3an standard;energy efficiency;low density parity check decoder;message passing decoding algorithm;size 90 nm;voltage 1.2 V;Application specific integrated circuits;Clocks;Decoding;Parity check codes;Routing;Throughput;Wires},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.03.21}
+}
+
+@InProceedings{chapat_94,
+  Title                    = {{L}atch design for transient pulse tolerance},
+  Author                   = {Hungse Cha and Patel, J. H.},
+  Booktitle                = {Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors ICCD '94},
+  Year                     = {1994},
+  Month                    = oct,
+  Pages                    = {385--388},
+
+  Doi                      = {10.1109/ICCD.1994.331932},
+  File                     = {chapat_94.pdf:chapat_94.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{chawil_17,
+  Title                    = {{M}ulti-standard low-power {DDR} {I}/{O} circuit design in 7nm {CMOS} process},
+  Author                   = {M. {Chae} and T. {Wilson} and E. {Naviasky}},
+  Booktitle                = {2017 IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2017},
+  Month                    = {May},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/ISCAS.2017.8050331},
+  ISSN                     = {2379-447X},
+  Keywords                 = {CMOS memory circuits;DRAM chips;driver circuits;feedback amplifiers;integrated circuit design;interference suppression;intersymbol interference;low-power electronics;power aware computing;power consumption;receiver bandwidth;ISI suppression;intersymbol interference suppression;frequency peaking;replica feedback loop;first stage amplifier;power consumption;thick gate oxide devices;thin gate oxide devices;power gating switch;hybrid pull-up driver;CMOS FinFET process;multistandard low-power DDR I/O circuit deisgn;size 7 nm;Receivers;Logic gates;Simulation;Transistors;Standards;Power demand;MOS devices;LPDDR;output driver;level translation;input receiver;frequency peaking;active inductor}
+}
+
+@Article{chakor_07,
+  Title                    = {{P}robabilistic {S}ystem-on-a-{C}hip {A}rchitectures},
+  Author                   = {Chakrapani, L. N. and Korkmaz, P. and Akgul, B. E. S. and Palem, K. V.},
+  Journal                  = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
+  Year                     = {2007},
+  Number                   = {3},
+  Pages                    = {1--28},
+  Volume                   = {12},
+
+  Address                  = {New York, NY, USA},
+  Doi                      = {http://doi.acm.org/10.1145/1255456.1255466},
+  File                     = {chakor_07.pdf:chakor_07.pdf:PDF},
+  ISSN                     = {1084-4309},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Publisher                = {ACM},
+  Timestamp                = {2010.01.20}
+}
+
+@InBook{cha_98,
+  Title                    = {{E}ssays in {D}erivatives: {R}isk-{T}ransfer {T}ools and {T}opics {M}ade {E}asy},
+  Author                   = {Don M. Chance},
+  Chapter                  = {A Brief History of Derivatives},
+  Publisher                = {Wiley},
+  Year                     = {1998},
+  Edition                  = {1st},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {history, derivatives, introduction},
+  Cds_read                 = {2014-05-21},
+  File                     = {cha_98.pdf:cha_98.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.05.22}
+}
+
+@InBook{chabro_95,
+  Title                    = {{Low Power Digital CMOS Design}},
+  Author                   = {A. P. Chandrakasan and R. W. Brodersen},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {1995},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Optchapter               = {{Voltage Scaling Approaches}},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chashe_92,
+  Title                    = {{Low-Power CMOS Digital Design}},
+  Author                   = {Chandrakasan, A. P. and Sheng, S. and Brodersen, R. W.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {1992},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {473--484},
+  Volume                   = {27},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{cha_14,
+  Title                    = {{H}igh-level power estimation and optimization of {DRAM}s},
+  Author                   = {Chandrasekar, Karthik},
+  Year                     = {2014},
+
+  Owner                    = {MJ},
+  Publisher                = {Technische Universiteit Delft},
+  Timestamp                = {2020-04-15}
+}
+
+@InProceedings{chaake_12,
+  Title                    = {{R}un-time {P}ower-down {S}trategies for {R}eal-time {SDRAM} {M}emory {C}ontrollers},
+  Author                   = {Chandrasekar, Karthik and Akesson, Benny and Goossens, Kees},
+  Booktitle                = {Proceedings of the 49th Annual Design Automation Conference},
+  Year                     = {2012},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {988--993},
+  Publisher                = {ACM},
+  Series                   = {DAC '12},
+
+  Acmid                    = {2228538},
+  Doi                      = {10.1145/2228360.2228538},
+  ISBN                     = {978-1-4503-1199-1},
+  Keywords                 = {SDRAM, memory controller, power-down, real-time},
+  Location                 = {San Francisco, California},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-22},
+  Url                      = {http://doi.acm.org/10.1145/2228360.2228538}
+}
+
+@InProceedings{chaake_11,
+  Title                    = {{Improved Power Modeling of DDR SDRAMs}},
+  Author                   = {Chandrasekar, Karthik and Akesson, Benny and Goossens, Kees},
+  Booktitle                = {{proc. DSD'11}},
+  Year                     = {2011},
+
+  Acmid                    = {2056663},
+  Doi                      = {10.1109/DSD.2011.17},
+  Keywords                 = {DDR SDRAMs; Power Modeling; Power Estimation; State Transitions; Power-Down; Self-Refresh; Bank-Interleaving; Open-page; Close-page; SDRAM Command Trace},
+  Numpages                 = {10},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20},
+  Url                      = {http://dx.doi.org/10.1109/DSD.2011.17}
+}
+
+@InProceedings{chagoo_14,
+  Title                    = {{E}xploiting {E}xpendable {P}rocess-margins in {DRAM}s for {R}un-time {P}erformance {O}ptimization},
+  Author                   = {Chandrasekar, Karthik and Goossens, Sven and Weis, Christian and Koedam, Martijn and Akesson, Benny and Wehn, Norbert and Goossens, Kees},
+  Booktitle                = {Proceedings of the Conference on Design, Automation \& Test in Europe},
+  Year                     = {2014},
+
+  Address                  = {3001 Leuven, Belgium, Belgium},
+  Pages                    = {173:1--173:6},
+  Publisher                = {European Design and Automation Association},
+  Series                   = {DATE '14},
+
+  Acmid                    = {2616820},
+  Articleno                = {173},
+  ISBN                     = {978-3-9815370-2-4},
+  Location                 = {Dresden, Germany},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-14},
+  Url                      = {http://dl.acm.org/citation.cfm?id=2616606.2616820}
+}
+
+@InProceedings{chawei_13,
+  Title                    = {{T}owards {V}ariation-{A}ware {S}ystem-{L}evel {P}ower {E}stimation of {DRAM}s: {A}n {E}mpirical {A}pproach},
+  Author                   = {K. Chandrasekar and C. Weis and B. Akesson and N. Wehn and K.G.W. Goossens},
+  Booktitle                = {Proc. 50th Design Automation Conference},
+  Year                     = {2013},
+
+  Address                  = {Austin, USA},
+  Month                    = {June},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-02-19}
+}
+
+@InProceedings{chawei_13a,
+  Title                    = {{S}ystem and circuit level power modeling of energy-efficient 3{D}-stacked wide {I}/{O} {DRAM}s},
+  Author                   = {Chandrasekar, Karthik and Weis, Christian and Akesson, Benny and Wehn, Norbert and Goossens, Kees},
+  Booktitle                = {2013 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2013},
+  Pages                    = {236-241},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-04-15}
+}
+
+@Misc{kargoo_14,
+  Title                    = {{DRAMP}ower: {O}pen-source {DRAM} power \& energy estimation tool},
+
+  Author                   = {Karthik Chandrasekar and Christian Weis and Yonghui Li and Benny Akesson and Omar Naji and Matthias Jung and Norbert Wehn and Kees Goossens},
+  HowPublished             = {\url{ http://www.drampower.info}},
+  Year                     = {Last Access 15.08.2019},
+
+  Address                  = {http://www.drampower.info/},
+  Owner                    = {Brugger},
+  Timestamp                = {2019-08-15}
+}
+
+@InProceedings{chaami_08,
+  Title                    = {{H}igh {P}erformance {FPGA} {I}mplementation of the {M}ersenne {T}wister},
+  Author                   = {Shrutisagar Chandrasekaran and Abbes Amira},
+  Booktitle                = {Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on},
+  Year                     = {2008},
+  Month                    = {jan.},
+  Pages                    = {482 -485},
+
+  Abstract                 = {Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twister is presented. The proposed architecture has the smallest footprint of all published architectures to date and occupies only 330 FPGA slices. Partial pipelining and sub-expression simplification has been used to improve throughput per clock cycle. The proposed architecture is implemented on an RC1000 FPGA Development platform equipped with a Xilinx XCV2000E FPGA, and can generate 20 million 32 bit random numbers per second at a clock rate of 24.234 MHz. A through performance analysis has been performed, and it is observed that the proposed architecture clearly outperforms other existing implementations in key comparable performance metrics.},
+  Cds_grade                = {0},
+  Cds_keywords             = {FPGA, random numbers, generator, Mersenne Twister},
+  Doi                      = {10.1109/DELTA.2008.113},
+  File                     = {chaami_08.pdf:chaami_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@InProceedings{chadiv_12,
+  Title                    = {{N}on-binary protograph-based {LDPC} codes for short block-lengths},
+  Author                   = {Ben-Yue Chang and Divsalar, D. and Dolecek, L.},
+  Booktitle                = {Information Theory Workshop (ITW), 2012 IEEE},
+  Year                     = {2012},
+  Pages                    = {282--286},
+
+  Doi                      = {10.1109/ITW.2012.6404676},
+  Owner                    = {PS},
+  Timestamp                = {2014.10.08},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6404676}
+}
+
+@InProceedings{chacon_01,
+  Title                    = {{Power Model for Interconnect Planning}},
+  Author                   = {C.C. Chang and J. Cong and T. Uchino and X. Yuan},
+  Booktitle                = {Procedings of the Workshop on Synthesis And System Integration of Mixed Technologies, October 2001},
+  Year                     = {2001},
+  Pages                    = {234--241},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chamoh_11,
+  Title                    = {{A} {P}riority-{B}ased 6{T}/8{T} {H}ybrid {SRAM} {A}rchitecture for {A}ggressive {V}oltage {S}caling in {V}ideo {A}pplications},
+  Author                   = {Ik Joon Chang and Mohapatra, D. and Roy, K.},
+  Journal                  = {Circuits and Systems for Video Technology, IEEE Transactions on},
+  Year                     = {2011},
+  Number                   = {2},
+  Pages                    = {101--112},
+  Volume                   = {21},
+
+  Cb_grade                 = {- ungelesed
+- reliabilty},
+  Doi                      = {10.1109/TCSVT.2011.2105550},
+  File                     = {chamoh_11.pdf:chamoh_11.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2012.03.30}
+}
+
+@InProceedings{chakas_16,
+  Title                    = {{U}nderstanding {L}atency {V}ariation in {M}odern {DRAM} {C}hips: {E}xperimental {C}haracterization, {A}nalysis, and {O}ptimization},
+  Author                   = {Chang, Kevin K. and Kashyap, Abhijith and Hassan, Hasan and Ghose, Saugata and Hsieh, Kevin and Lee, Donghyuk and Li, Tianshi and Pekhimenko, Gennady and Khan, Samira and Mutlu, Onur},
+  Booktitle                = {Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science},
+  Year                     = {2016},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {323--336},
+  Publisher                = {ACM},
+  Series                   = {SIGMETRICS '16},
+
+  Acmid                    = {2901453},
+  Doi                      = {10.1145/2896377.2901453},
+  ISBN                     = {978-1-4503-4266-7},
+  Keywords                 = {dram, dram errors, memory latency, process variation},
+  Location                 = {Antibes Juan-les-Pins, France},
+  Numpages                 = {14},
+  Url                      = {http://doi.acm.org/10.1145/2896377.2901453}
+}
+
+@InProceedings{chalee_14,
+  Title                    = {{I}mproving {DRAM} performance by parallelizing refreshes with accesses},
+  Author                   = {Chang, Kevin Kai-Wei and Lee, Donghyuk and Chishti, Zeshan and Alameldeen, Alaa R and Wilkerson, Chris and Kim, Yoongu and Mutlu, Onur},
+  Booktitle                = {High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on},
+  Year                     = {2014},
+  Organization             = {IEEE},
+  Pages                    = {356--367},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@Article{cha_66,
+  Title                    = {{S}ynthesis of {B}and-{L}imited {O}rthogonal {S}ignals for {M}ultichannel {D}ata {T}ransmission},
+  Author                   = {Chang, Robert W.},
+  Journal                  = {Bell System Technical Journal},
+  Year                     = {1966},
+  Number                   = {10},
+  Pages                    = {1775--1796},
+  Volume                   = {45},
+
+  Doi                      = {10.1002/j.1538-7305.1966.tb02435.x},
+  ISSN                     = {1538-7305},
+  Publisher                = {Blackwell Publishing Ltd},
+  Url                      = {http://dx.doi.org/10.1002/j.1538-7305.1966.tb02435.x}
+}
+
+@Article{chahan_66,
+  Title                    = {{On Receiver Structures for Channels Having Memory}},
+  Author                   = {R. W. Chang and J. C. Hancock},
+  Journal                  = {IEEE Transcations on Information Theory},
+  Year                     = {1966},
+
+  Month                    = oct,
+  Pages                    = {463--468},
+  Volume                   = {IT-12},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chasuz_00,
+  Title                    = {{A 2-Mb/s 256-State 10-mW Rate-1/3 Viterbi Decoder}},
+  Author                   = {Chang, Y. and Suzuki, H. and Parhi, K. K.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2000},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {826--834},
+  Volume                   = {35},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{chajos_07,
+  Title                    = {{U}sing {O}pen{MP}: {P}ortable {S}hared {M}emory {P}arallel {P}rogramming ({S}cientific and {E}ngineering {C}omputation)},
+  Author                   = {Barbara Chapman and Gabriele Jost and Ruud van der Pas},
+  Publisher                = {The MIT Press},
+  Year                     = {2007},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22}
+}
+
+@Article{cha_72,
+  Title                    = {{C}lass of algorithms for decoding block codes with channel measurement information},
+  Author                   = {Chase, D.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1972},
+  Number                   = {1},
+  Pages                    = {170--182},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/TIT.1972.1054746},
+  File                     = {cha_72.pdf:cha_72.pdf:PDF},
+  Keywords                 = {BCH, Soft, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {chase algorithm for soft decoding of linear blockcodes},
+  Timestamp                = {2011.04.27}
+}
+
+@InProceedings{chanel_08,
+  Title                    = {{R}eal-{T}ime {O}ptical {F}low {C}alculations on {FPGA} and {GPU} {A}rchitectures: {A} {C}omparison {S}tudy},
+  Author                   = {Chase, J. and Nelson, B. and Bodily, J. and Zhaoyi Wei and Dah-Jye Lee},
+  Booktitle                = {Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on},
+  Year                     = {2008},
+  Pages                    = {173-182},
+
+  Abstract                 = {FPGA devices have often found use as higher-performance alternatives to programmable processors for implementing a variety of computations. Applications successfully implemented on FPGAs have typically contained high levels of parallelism and have often used simple statically-scheduled control and modest arithmetic. Recently introduced computing devices such as coarse grain reconfigurable arrays, multi-core processors, and graphical processing units (GPUs) promise to significantly change the computational landscape for the implementation of high-speed real-time computing tasks. One reason for this is that these architectures take advantage of many of the same application characteristics that fit well on FPGAs. One real-time computing task, optical flow, is difficult to apply in robotic vision applications in practice because of its high computational and data rate requirements, and so is a good candidate for implementation on FPGAs and other custom computing architectures. In this paper, a tensor-based optical flow algorithm is implemented on both an FPGA and a GPU and the two implementations discussed. The two implementations had similar performance, but with the FPGA implementation requiring 12× more development time. Other comparison data for these two technologies is then given for three additional applications taken from a MIMO digital communication system design, providing additional examples of the relative capabilities of these two technologies.},
+  Cds_grade                = {2},
+  Cds_read                 = {2011-11-11},
+  Cds_review               = {- no fitting applications
+- no real numbers},
+  Doi                      = {10.1109/FCCM.2008.24},
+  File                     = {chanel_08.pdf:chanel_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@InProceedings{chagub_00,
+  Title                    = {{On Performance/Complexity Analysis and SW Implementation of Turbo Decoding}},
+  Author                   = {A. Chass and A. Gubeskys},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {531--534},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chabal_12,
+  Title                    = {{USIMM}: the {U}tah {SI}mulated {M}emory {M}odule, {A} {S}imulation {I}nfrastructure for the {JWAC} {M}emory {S}cheduling {C}hampionship},
+  Author                   = {Chatterjee, Niladrish and Balasubramonian, Rajeev and Shevgoor, Manjunath and Pugsley, Seth and Udipi, Aniruddha and Shafiee, Ali and Sudan, Kshitij amd Awasthi, Manu and Chishti, Zeshan},
+  Journal                  = {Utah and Intel Corp.},
+  Year                     = {2012},
+
+  Month                    = {February},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.17}
+}
+
+@InProceedings{chabro_12,
+  Title                    = {{A}n {FPGA}-based {P}arallel {P}rocessor for {B}lack-{S}choles {O}ption {P}ricing {U}sing {F}inite {D}ifferences {S}chemes},
+  Author                   = {Georgios Chatziparaskevas and Andreas Brokalakis and Ioannis Papaefstathiou},
+  Booktitle                = {Proc. Design, Automation and Test in Europe, 2012 (DATE '12)},
+  Year                     = {2012},
+  Month                    = mar,
+
+  Cds_grade                = {3},
+  Cds_keywords             = {option pricing, FPGA, Black-Scholes, finite difference},
+  Cds_read                 = {2012-03-18},
+  Cds_review               = {general purpose finite difference solver implemented for specific application option pricing},
+  File                     = {chabro_12.pdf:chabro_12.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.21}
+}
+
+@InCollection{chaste_92,
+  Title                    = {{Scaling and Folding the Viterbi Algorithm Trellis}},
+  Author                   = {P. M. Chau and K. J. Stephen},
+  Booktitle                = {{VLSI Signal Processing V}},
+  Publisher                = {IEEE},
+  Year                     = {1992},
+  Pages                    = {479--489},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{chaand_07,
+  Title                    = {{A} design flow dedicated to multi-mode architectures for {DSP} applications},
+  Author                   = {Chavet, Cyrille and Andriamisaina, Caaliph and Coussy, Philippe and Casseau, Emmanuel and Juin, Emmanuel and Urard, Pascal and Martin, Eric},
+  Booktitle                = {Proc. IEEE/ACM International Conference on Computer-Aided Design ICCAD 2007},
+  Year                     = {2007},
+  Month                    = nov,
+  Pages                    = {604--611},
+
+  Doi                      = {10.1109/ICCAD.2007.4397331},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{chacou_07,
+  Title                    = {{A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver},
+  Author                   = {Chavet, C. and Coussy, P. and Urard, P. and Martin, E.},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2007},
+  Year                     = {2007},
+  Month                    = may,
+  Pages                    = {2946--2949},
+
+  Doi                      = {10.1109/ISCAS.2007.377867},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{cheli_08,
+  Title                    = {{A}ccelerating {C}ompute-{I}ntensive {A}pplications with {GPU}s and {FPGA}s},
+  Author                   = {Shuai Che and Jie Li and Sheaffer, J.W. and Skadron, K. and Lach, J.},
+  Booktitle                = {Application Specific Processors, 2008. SASP 2008. Symposium on},
+  Year                     = {2008},
+  Pages                    = {101-107},
+
+  Abstract                 = {Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are FPGAs and GPUs, which can often achieve better performance than CPUs on certain workloads. FPGAs are highly customizable, while GPUs provide massive parallel execution resources and high memory bandwidth. Applications typically exhibit vastly different performance characteristics depending on the accelerator. This is an inherent problem attributable to architectural design, middleware support and programming style of the target platform. For the best application-to-accelerator mapping, factors such as programmability, performance, programming cost and sources of overhead in the design flows must be all taken into consideration. In general, FPGAs provide the best expectation of performance, flexibility and low overhead, while GPUs tend to be easier to program and require less hardware resources. We present a performance study of three diverse applications - Gaussian elimination, data encryption standard (DES), and Needleman-Wunsch - on an FPGA, a GPU and a multicore CPU system. We perform a comparative study of application behavior on accelerators considering performance and code complexity. Based on our results, we present an application characteristic to accelerator platform mapping, which can aid developers in selecting an appropriate target architecture for their chosen application.},
+  Cds_grade                = {2},
+  Cds_read                 = {2011-11-11},
+  Cds_review               = {- no energy numbers
+- very generic
+- no fitting applications},
+  Doi                      = {10.1109/SASP.2008.4570793},
+  File                     = {cheli_08.pdf:cheli_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@Article{checro_07,
+  Title                    = {{I}mproving the {E}rror {R}ate {P}erformance of {T}urbo {C}odes using the {F}orced {S}ymbol {M}ethod},
+  Author                   = {Y. Ould-Cheikh-Mouhamedou and S. Crozier},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2007},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {616-618},
+  Volume                   = {11},
+
+  Doi                      = {10.1109/LCOMM.2007.070171},
+  ISSN                     = {1089-7798},
+  Keywords                 = {decoding;error correction codes;DVB-RCS 8-state;error flare;error rate performance;forced symbol method;repeated decoding;turbo codes;Computer errors;Cyclic redundancy check;Decoding;Digital video broadcasting;Error analysis;Protection;Reed-Solomon codes;Signal to noise ratio;Turbo codes;Viterbi algorithm},
+  Owner                    = {StW},
+  Timestamp                = {2016.11.15}
+}
+
+@InProceedings{moucro_06,
+  Title                    = {{A} {M}ethod for {L}owering {T}urbo {C}ode {E}rror {F}lare using {C}orrection {I}mpulses and {R}epeated {D}ecoding},
+  Author                   = {Y. Ould-Cheikh-Mouhamedou and S. Crozier and K. Gracie and P. Guinand and P. Kabal},
+  Booktitle                = {Turbo Codes Related Topics; 6th International ITG-Conference on Source and Channel Coding (TURBOCODING), 2006 4th International Symposium on},
+  Year                     = {2006},
+  Month                    = {April},
+  Pages                    = {1-6},
+
+  Owner                    = {StW},
+  Timestamp                = {2016.11.15}
+}
+
+@Article{che_17,
+  Title                    = {{M}emory selector devices and crossbar array design: a modeling-based assessment},
+  Author                   = {Chen, An},
+  Journal                  = {Journal of Computational Electronics},
+  Year                     = {2017},
+
+  Month                    = {Dec},
+  Number                   = {4},
+  Pages                    = {1186--1200},
+  Volume                   = {16},
+
+  Abstract                 = {Functional and scalable memory selector devices are essential for high-density memory and storage. This paper reviews the performance requirements and device options of two-terminal memory selectors for crossbar arrays. In a large crossbar array without appropriate selector devices, large number of sneak paths will significantly degrade the reading signal and writing conditions. Asymmetry and nonlinearity in selector device characteristics can both improve crossbar array operation by making sneak paths more resistive. Rectifying diodes, nonlinear devices, and volatile switches can provide basic selector functions; however, they also need to be balanced with memory elements and meet rigorous requirements in large arrays. Modeling plays an important role in the assessment of selector device function and crossbar array performance. This paper will review the selector device and crossbar array modeling approaches and summarize key observations. The design of large crossbar arrays with functional selector devices requires a comprehensive approach that incorporates device characteristics, array parameters, operation conditions, and application specifications.},
+  Day                      = {01},
+  Doi                      = {10.1007/s10825-017-1059-7},
+  ISSN                     = {1572-8137},
+  Timestamp                = {2018-09-03},
+  Url                      = {https://doi.org/10.1007/s10825-017-1059-7}
+}
+
+@InProceedings{chelin_11,
+  Title                    = {{V}ariability of resistive switching memories and its impact on crossbar array performance},
+  Author                   = {A. Chen and M. Lin},
+  Booktitle                = {2011 International Reliability Physics Symposium},
+  Year                     = {2011},
+  Month                    = {April},
+  Pages                    = {MY.7.1-MY.7.4},
+
+  Doi                      = {10.1109/IRPS.2011.5784590},
+  ISSN                     = {1938-1891},
+  Keywords                 = {random-access storage;resistive switching memories;crossbar array performance;metal oxide;RRAM;signal degradation;Arrays;Resistance;Switches;Sensors;Transistors;Mathematical model;Metals;Resistive switching memory;RRAM;variability;crossbar arrays},
+  Timestamp                = {2018-08-29}
+}
+
+@InProceedings{chezha_08,
+  Title                    = {{FPGA} implementation of a factorization processor for soft-decision reed-solomon decoding},
+  Author                   = {Bainan Chen and Xinmiao Zhang},
+  Booktitle                = {Proc. IEEE Int. Symp. Circuits and Systems ISCAS 2008},
+  Year                     = {2008},
+  Pages                    = {944--947},
+
+  Doi                      = {10.1109/ISCAS.2008.4541575},
+  File                     = {chezha_08.pdf:chezha_08.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ASD},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.27}
+}
+
+@Article{chedho_05,
+  Title                    = {{Reduced-Complexity Decoding of LDPC Codes}},
+  Author                   = {Chen, J. and Dholakia, A. and Eleftheriou, E. and Fossorier, M. P. C. and Hu, X.-Y.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2005},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {1288--1299},
+  Volume                   = {53},
+
+  File                     = {chedho_05.pdf:chedho_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chefos_02,
+  Title                    = {{Near optimum universal belief propagation based decoding of low-density parity check codes}},
+  Author                   = {J. Chen and M. Fossorier},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2002},
+
+  Month                    = mar,
+  Pages                    = {406--414},
+  Volume                   = {50},
+
+  File                     = {chefos_02.pdf:chefos_02.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chefos_00,
+  Title                    = {{Bi-Directional SOVA Decoding for Turbo-Codes}},
+  Author                   = {J. Chen and Fossorier, M. P. C. and S. Lin and C. Xu},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2000},
+
+  Month                    = dec,
+  Number                   = {4},
+  Pages                    = {405--407},
+  Volume                   = {12},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{chehu_10,
+  Title                    = {{H}ardware-efficient architecture for high throughput {T}urbo decoder},
+  Author                   = {Jienan Chen and Jianhao Hu},
+  Booktitle                = {Computer Application and System Modeling (ICCASM), 2010 International Conference on},
+  Year                     = {2010},
+  Month                    = {Oct},
+  Pages                    = {V4-207-V4-211},
+  Volume                   = {4},
+
+  Doi                      = {10.1109/ICCASM.2010.5619233},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@Article{chemoo_04,
+  Title                    = {{R}econfigurable {R}eadback-{S}ignal {G}enerator {B}ased on a {F}ield-{P}rogrammable {G}ate {A}rray},
+  Author                   = {Jinghuan Chen and Jaekyun Moon and Kia Bazargan Bazargan},
+  Journal                  = {Magnetics, IEEE Transactions on},
+  Year                     = {2004},
+
+  Month                    = {may},
+  Number                   = {3},
+  Pages                    = { 1744 - 1750},
+  Volume                   = {40},
+
+  Abstract                 = {We have designed a readback-signal generator to provide noise-corrupted signals to a read channel simulator. It is implemented in a Xilinx Virtex-E field-programmable gate array (FPGA) device. The generator simulates in hardware the noise processes and distortions observed in hard drives. It uses embedded nonuniform random number generators to simulate the random characteristics of various disturbances in the read/write process. The signal generator can simulate readback pulses, intersymbol interference, transition noise, electronics noise, head and media nonlinearity, intertrack interference, and write timing error according to the characteristics specified by the user. A sample implementation operates at a 70-MHz clock speed. The design can easily be scaled for different error rates. The generator can be reconfigured in real time to give the user flexibility and increase the capacity of the FPGA device. The readback-signal generator can be integrated into an FPGA read channel simulator or serve as a test bench for data-recovery circuits.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TMAG.2004.826913},
+  File                     = {chemoo_04.pdf:chemoo_04.pdf:PDF},
+  ISSN                     = {0018-9464},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.28}
+}
+
+@Article{cheniu_13,
+  Title                    = {{I}mproved {S}uccessive {C}ancellation {D}ecoding of {P}olar {C}odes},
+  Author                   = {K. Chen and K. Niu and J. Lin},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2013},
+
+  Month                    = {August},
+  Number                   = {8},
+  Pages                    = {3100-3107},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCOMM.2013.070213.120789},
+  ISSN                     = {0090-6778},
+  Keywords                 = {decoding;interference suppression;search problems;trees (mathematics);ML decoding;SC decoding;SCH;SCL decoding;SCS decoding;code tree;finite-length performance;maximum likelihood decoding;path search procedure;polar codes;pruning technique;signal-to-noise ratio regime;successive cancellation hybrid;successive cancellation list decoding;successive cancellation stack;Algorithm design and analysis;Complexity theory;Maximum likelihood decoding;Measurement;Signal to noise ratio;Vectors;Polar codes;code tree;successive cancellation decoding;tree pruning},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{cheniu_13a,
+  Title                    = {{A} {R}educed-{C}omplexity {S}uccessive {C}ancellation {L}ist {D}ecoding of {P}olar {C}odes},
+  Author                   = {Kai Chen and Kai Niu and Jiaru Lin},
+  Booktitle                = {Vehicular Technology Conference (VTC Spring), 2013 IEEE 77th},
+  Year                     = {2013},
+  Month                    = {June},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/VTCSpring.2013.6691844},
+  ISSN                     = {1550-2252},
+  Keywords                 = {computational complexity;maximum likelihood decoding;trees (mathematics);SCL decoding algorithm;code tree representation;computational complexity;finite code length;maximum-likelihood decoding;path searching procedure;polar codes;signal-to-noise ratio regime;successive cancellation list decoding algorithm;tree-pruning technique;Computational complexity;Maximum likelihood decoding;Measurement;Signal to noise ratio;Vectors},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{cheyu_19,
+  Title                    = {{A} {B}atteryless {S}ingle-{I}nductor {B}oost {C}onverter {W}ith 190 m{V} {S}elf-{S}tartup {V}oltage for {T}hermal {E}nergy {H}arvesting {O}ver a {W}ide {T}emperature {R}ange},
+  Author                   = {M. {Chen} and H. {Yu} and G. {Wang} and Y. {Lian}},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2019},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {889-893},
+  Volume                   = {66},
+
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8458174},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/TCSII.2018.2869328},
+  Keywords                 = {TCS},
+  Keywords_original        = {CMOS integrated circuits;energy harvesting;maximum power point trackers;power inductors;zero current switching;stepping-up architecture;input voltage;zero-current switching;power point tracking techniques;CMOS process;main converter;startup converter;inductor sharing technique;off-chip inductor;wide temperature range;thermal energy harvesting;190 mV self-startup voltage;batteryless single-inductor boost converter;voltage 190.0 mV;power 400.0 muW;voltage 50.0 mV;size 180.0 nm;temperature -30.0 degC to 80.0 degC;Switches;Inductors;Clocks;Zero current switching;Thermal energy;Inverters;Voltage control;Boost converter;maximum power point tracking (MPPT);self-startup;single inductor;thermal energy harvesting},
+  Owner                    = {CCR}
+}
+
+@InProceedings{chewan_07,
+  Title                    = {{FPGA} {I}mplementation of an {I}nterpolation {P}rocessor for {S}oft-{D}ecision {D}ecoding of {R}eed-{S}olomon {C}odes},
+  Author                   = {Qinqin Chen and Zhongfeng Wang and Jim Ma},
+  Booktitle                = {Proc. IEEE Int. Symp. Circuits and Systems ISCAS 2007},
+  Year                     = {2007},
+  Pages                    = {2100--2103},
+
+  Doi                      = {10.1109/ISCAS.2007.378513},
+  File                     = {chewan_07.pdf:chewan_07.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ASD},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.27}
+}
+
+@InProceedings{chepra_15,
+  Title                    = {{DRAM} {R}ow {A}ctivation {E}nergy {O}ptimization for {S}tride {M}emory {A}ccess on {FPGA}-{B}ased {S}ystems},
+  Author                   = {Ren Chen and Viktor K. Prasanna},
+  Booktitle                = {Applied Reconfigurable Computing - 11th International Symposium, {ARC} 2015, Bochum, Germany, April 13-17, 2015, Proceedings},
+  Year                     = {2015},
+  Pages                    = {349--356},
+
+  Bibsource                = {dblp computer science bibliography, http://dblp.org},
+  Doi                      = {10.1007/978-3-319-16214-0},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11},
+  Url                      = {http://dx.doi.org/10.1007/978-3-319-16214-0}
+}
+
+@InProceedings{cheho_14,
+  Title                    = {{A}n all-digital delay-locked loop for high-speed memory interface applications},
+  Author                   = {S. {Chen} and M. {Ho} and Y. {Sun} and M. W. {Lin} and J. {Lai}},
+  Booktitle                = {Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test},
+  Year                     = {2014},
+  Month                    = {April},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/VLSI-DAT.2014.6834900},
+  Keywords                 = {circuit tuning;CMOS digital integrated circuits;delay lines;delay lock loops;low-power electronics;SRAM chips;system-on-chip;all-digital delay-locked loop;high-speed memory interface;digital delay line;tuning linearity;DDR3 PHY;low-power CMOS process;system-on-chip;size 40 nm;bit rate 800 Mbit/s to 1600 Mbit/s;Delays;Delay lines;Tuning;Inverters;Jitter;CMOS process;System-on-chip;all-digital delay-locked loop (ADDLL);delay-locked loop (DLL);coarse delay line (CDL);fine delay line (FDL);double data rate (DDR);system-on-a-chip(SoC)}
+}
+
+@InProceedings{chezha_07,
+  Title                    = {{L}ow power soft-output signal detector design for wireless {MIMO} communication systems},
+  Author                   = {Sizhong Chen and Tong Zhang},
+  Booktitle                = {Proc. ACM/IEEE Int Low Power Electronics and Design (ISLPED) Symp},
+  Year                     = {2007},
+  Pages                    = {232--237},
+
+  Doi                      = {10.1145/1283780.1283831},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@InProceedings{chezha_05,
+  Title                    = {{B}readth-first tree search {MIMO} signal detector design and {VLSI} implementation},
+  Author                   = {Sizhong Chen and Tong Zhang and Yan Xin},
+  Booktitle                = {Military Communications Conference, 2005. MILCOM 2005. IEEE},
+  Year                     = {2005},
+  Pages                    = {1470-1476 Vol. 3},
+
+  Doi                      = {10.1109/MILCOM.2005.1605884},
+  File                     = {chezha_05.pdf:chezha_05.pdf:PDF},
+  Keywords                 = {CMOS integrated circuits;MIMO systems;VLSI;decoding;quadrature amplitude modulation;radiocommunication;search problems;signal detection;trees (mathematics);CMOS technology;K-best detector;MIMO signal detector;QAM;Synopsys;VLSI;breadth-first tree search;multiple-input multiple-output;nonlinear MIMO detector design;quadrature amplitude modulation;sphere decoding algorithm;CMOS technology;Decoding;Detectors;MIMO;Quadrature amplitude modulation;Signal design;Signal detection;Silicon;Throughput;Very large scale integration},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.09}
+}
+
+@InProceedings{chemin_12,
+  Title                    = {{FLEXDET}: {F}lexible, {E}fficient {M}ulti-{M}ode {MIMO} {D}etection {U}sing {R}econfigurable {ASIP}},
+  Author                   = {Xiaolin Chen and Minwegen, A. and Hassan, Y. and Kammler, D. and Shuai Li and Kempf, T. and Chattopadhyay, A. and Ascheid, G.},
+  Booktitle                = {Field-Programmable Custom Computing Machines (FCCM), 2012 IEEE 20th Annual International Symposium on},
+  Year                     = {2012},
+  Month                    = {29 2012-may 1},
+  Pages                    = {69 -76},
+
+  Doi                      = {10.1109/FCCM.2012.22},
+  Keywords                 = {ASIC implementation;CGRA-based multimode MIMO detection;FLEXDET;MMSE detection;MMSE successive interference cancellation;algorithm configurations;antenna configurations;architectural support;coarse-grained reconfigurable architecture;detection algorithms;linear minimum mean square error detection;matrix inversion algorithm;matrix operations;maximum ratio combining;modulation schemes;multimode MIMO detector;partially reconfigurable ASIP;rASIP;MIMO communication;antennas;application specific integrated circuits;diversity reception;error detection;interference suppression;matrix inversion;mean square error methods;reconfigurable architectures;signal detection;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.22}
+}
+
+@InProceedings{chehoc_03,
+  Title                    = {{A FPGA and ASIC Implementation of Rate 1/2, 8088-b Irregular Low Density Parity Check Decoder}},
+  Author                   = {Y. Chen and D. Hocevar},
+  Booktitle                = {Proc. 2003 Global Telecommunications Conference (GLOBECOM '03)},
+  Year                     = {2003},
+
+  Address                  = {San Francisco, USA},
+  Month                    = dec,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Chen2011,
+  Title                    = {{A}nalysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3{D} {IC} designs},
+  Author                   = {Yibo Chen and Kursun, E. and Motschman, D. and Johnson, C. and Yuan Xie},
+  Booktitle                = {Low Power Electronics and Design (ISLPED) 2011 International Symposium on},
+  Year                     = {2011},
+  Month                    = {Aug},
+  Pages                    = {397-402},
+
+  Doi                      = {10.1109/ISLPED.2011.5993673},
+  ISSN                     = {Pending},
+  Keywords                 = {circuit optimisation;integrated circuit design;integrated circuit interconnections;power aware computing;thermal conductivity;three-dimensional integrated circuits;3D IC design;lateral thermal blockage effect analysis;lateral thermal blockage effect mitigation;placement-aspect ratio optimization;signal bus connection;thermal aware via farm placement technique;thermal conductivity;three-dimensional integrated circuits;through-silicon-vias;Conductivity;Heating;Optimization;Silicon;Thermal conductivity;Three dimensional displays;Through-silicon vias},
+  Owner                    = {weis},
+  Timestamp                = {2015.04.14}
+}
+
+@Conference{chepar_04,
+  Title                    = {{A}rea {E}fficient {P}arallel {D}ecoder {A}rchitecture {F}or {L}ong {BCH}-{C}odes},
+  Author                   = {Yanni Chen and Keshab K. Parhi},
+  Year                     = {2004},
+  Organization             = {University of Minnesota, United States},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {Channel Code, BCH, Syndrome, Chien Search, FPGA, VLSI, Implementation},
+  Cds_read                 = {2008-05},
+  Date-added               = {2007-11-28 12:07:33 +0100},
+  Date-modified            = {2008-08-08 11:59:17 +0200},
+  File                     = {chepar_04.pdf:chepar_04.pdf:PDF},
+  Keywords                 = {Channel Code, BCH, Syndrome, Chien Search, FPGA, VLSI, Implementation},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{chezho_11,
+  Title                    = {{P}ricing {A}merican {O}ptions on {A}ssets with {D}ividends by {A} {B}rownian {B}ridge {S}imulation {M}ethod},
+  Author                   = {Yang Chen and Yanchun Zhou},
+  Booktitle                = {Proceedings of the 2011 International Conference on Computer Science and Network Technology (ICCSNT)},
+  Year                     = {2011},
+  Pages                    = {185 - 189},
+  Volume                   = {1},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.03.25}
+}
+
+@InProceedings{checon_13,
+  Title                    = {{A}ccelerator-{R}ich {CMP}s: {F}rom {C}oncept to {R}eal {H}ardware},
+  Author                   = {Yu-Ting Chen and Cong, J. and Ghodrat, M.A. and Huang, M. and Chunyue Liu and Bingjun Xiao and Yi Zou},
+  Booktitle                = {Proceedings of the 2013 IEEE 31st International Conference on Computer Design (ICCD)},
+  Year                     = {2013},
+  Month                    = oct,
+  Pages                    = {169-176},
+
+  Abstract                 = {Application-specific accelerators provide 10-100× improvement in power efficiency over general-purpose processors. The accelerator-rich architectures are especially promising. This work discusses a prototype of accelerator-rich CMPs (PARC). During our development of PARC in real hardware, we encountered a set of technical challenges and proposed corresponding solutions. First, we provided system IPs that serve a sea of accelerators to transfer data between userspace and accelerator memories without cache overhead. Second, we designed a dedicated interconnect between accelerators and memories to enable memory sharing. Third, we implemented an accelerator manager to virtualize accelerator resources for users. Finally, we developed an automated flow with a number of IP templates and customizable interfaces to a C-based synthesis flow to enable rapid design and update of PARC. We implemented PARC in a Virtex-6 FPGA chip with integration of platform-specific peripherals and booting of unmodified Linux. Experimental results show that PARC can fully exploit the energy benefits of accelerators at little system overhead.},
+  Doi                      = {10.1109/ICCD.2013.6657039},
+  Owner                    = {CDS},
+  Timestamp                = {2016-02-16}
+}
+
+@InProceedings{chepen_11,
+  Title                    = {{A} macro-layer level fully parallel layered {LDPC} decoder {SOC} for {IEEE} 802.15.3c application},
+  Author                   = {Zhixiang Chen and Xiao Peng and Xiongxin Zhao and Qian Xie and Okamura, L. and Dajiang Zhou and Goto, S.},
+  Booktitle                = {VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on},
+  Year                     = {2011},
+  Pages                    = {1--4},
+
+  Abstract                 = {In this paper, we propose an ultra high-throughput <span class='snippet'>LDPC</span> <span class='snippet'>decoder</span> <span class='snippet'>SOC</span> to fulfill the requirement of <span class='snippet'>IEEE</span> <span class='snippet'>802</span>.<span class='snippet'>15</span>.<span class='snippet'>3c</span> standard. By implementing <span class='snippet'>a</span> <span class='snippet'>macro</span>-<span class='snippet'>layer</span> <span class='snippet'>fully</span> <span class='snippet'>parallel</span> architecture, our proposed <span class='snippet'>decoder</span> takes only 4 clock cycles to finish one <span class='snippet'>layered</span> decoding iteration. Interconnection complexity problem introduced by high-<span class='snippet'>parallel</span> decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-<span class='snippet'>level</span> pipeline decoding. <span class='snippet'>A</span> 65 nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2 V, 400 MHz and 10 iterations the proposed <span class='snippet'>decoder</span> achieves <span class='snippet'>a</span> data throughput 6.72 Gb/s and consumes <span class='snippet'>a</span> power 537.6 mW with an energy efficiency 8.0 pJ/bit&#x00B7;iter.},
+  Doi                      = {10.1109/VDAT.2011.5783634},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.07.15}
+}
+
+@InProceedings{chezha_09,
+  Title                    = {{A}n {A}rea-{E}fficient and {D}egree-{C}omputationless {BCH} {D}ecoder for {DVB}-{S}2},
+  Author                   = {Zhou Chen and Yulong Zhang and Yan Ying and Chuan Wu and Xiaoyang Zeng},
+  Booktitle                = {ASIC, 2009. ASICON '09. IEEE 8th International Conference on},
+  Year                     = {2009},
+  Month                    = oct,
+  Pages                    = {489--492},
+
+  Abstract                 = {This paper presents an area-efficient BCH decoder for DVB-S2 system. The proposed architecture can support all 11 code rates in DVB-S2. Based on the modified Euclidean algorithm (MEA), The BCH decoder has a low hardware complexity with the folding and degree computationless architecture in key equation solver (KES) block. Further more, the multiplier in Galois Field is also optimized to reduce the hardware complexity. The proposed decoder requires at least 16% fewer gates than the conventional RS/BCH decoders and can work up to 277 MHz, which meets the speed requirements of the system.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ASICON.2009.5351625},
+  File                     = {chezha_09.pdf:chezha_09.pdf:PDF},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.22}
+}
+
+@InBook{cheede_14,
+  Title                    = {{U}sing {M}odels at {R}untime to {A}ddress {A}ssurance for {S}elf-{A}daptive {S}ystems},
+  Author                   = {Cheng, Betty H. C.
+and Eder, Kerstin I.
+and Gogolla, Martin
+and Grunske, Lars
+and Litoiu, Marin
+and M{\"u}ller, Hausi A.
+and Pelliccione, Patrizio
+and Perini, Anna
+and Qureshi, Nauman A.
+and Rumpe, Bernhard
+and Schneider, Daniel
+and Trollmann, Frank
+and Villegas, Norha M.},
+  Editor                   = {Bencomo, Nelly
+and France, Robert
+and Cheng, Betty H. C.
+and A{\ss}mann, Uwe},
+  Pages                    = {101--136},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2014},
+
+  Address                  = {Cham},
+
+  Abstract                 = {A self-adaptive software system modifies its behavior at runtime in response to changes within the system or in its execution environment. The fulfillment of the system requirements needs to be guaranteed even in the presence of adverse conditions and adaptations. Thus, a key challenge for self-adaptive software systems is assurance. Traditionally, confidence in the correctness of a system is gained through a variety of activities and processes performed at development time, such as design analysis and testing. In the presence of self-adaptation, however, some of the assurance tasks may need to be performed at runtime. This need calls for the development of techniques that enable continuous assurance throughout the software life cycle. Fundamental to the development of runtime assurance techniques is research into the use of models at runtime (M@RT). This chapter explores the state of the art for using M@RT to address the assurance of self-adaptive software systems. It defines what information can be captured by M@RT, specifically for the purpose of assurance, and puts this definition into the context of existing work. We then outline key research challenges for assurance at runtime and characterize assurance methods. The chapter concludes with an exploration of selected application areas where M@RT could provide significant benefits beyond existing assurance techniques for adaptive systems.},
+  Booktitle                = {Models@run.time: Foundations, Applications, and Roadmaps},
+  Doi                      = {10.1007/978-3-319-08915-7_4},
+  ISBN                     = {978-3-319-08915-7},
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-02},
+  Url                      = {https://doi.org/10.1007/978-3-319-08915-7_4}
+}
+
+@Article{chepar_06,
+  Title                    = {{H}igh-{S}peed {P}arallel {CRC} {I}mplementation {B}ased on {U}nfolding, {P}ipelining, and {R}etiming},
+  Author                   = {Chao Cheng and Parhi, K.K.},
+  Journal                  = {Circuits and Systems II: Express Briefs, IEEE Transactions on},
+  Year                     = {2006},
+
+  Month                    = {Oct},
+  Number                   = {10},
+  Pages                    = {1017-1021},
+  Volume                   = {53},
+
+  Abstract                 = {This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost},
+  Doi                      = {10.1109/TCSII.2006.882213},
+  File                     = {chepar_06.pdf:chepar_06.pdf:PDF},
+  ISSN                     = {1549-7747},
+  Keywords                 = {cyclic redundancy check codes;high-speed integrated circuits;integrated circuit design;pipeline processing;cyclic redundancy check;high-speed parallel circuits;iteration bound;linear feedback shift register;look-ahead pipelining;Algorithm design and analysis;Circuits;Clocks;Computer architecture;Costs;Cyclic redundancy check;Hardware;Parallel processing;Pipeline processing;Polynomials;Cyclic redundancy check (CRC);linear feedback shift register (LFSR);pipelining;retiming;unfolding},
+  Owner                    = {StW},
+  Timestamp                = {2014.11.17}
+}
+
+@Article{chepar_08,
+  Title                    = {{H}ardware {E}fficient {L}ow-{L}atency {A}rchitecture for {H}igh {T}hroughput {R}ate {V}iterbi {D}ecoders},
+  Author                   = {C. Cheng and K. K. Parhi},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2008},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {1254-1258},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCSII.2008.2008061},
+  File                     = {chepar_08.pdf:chepar_08.pdf:PDF},
+  ISSN                     = {1549-7747},
+  Keywords                 = {Viterbi decoding;add-compare-select computation;hardware complexity;hardware efficient low-latency architecture;high throughput rate Viterbi decoders;Chaotic communication;Computer architecture;Convolution;Costs;Decoding;Delay;Hardware;Throughput;Tree data structures;Viterbi algorithm;Add-Compare-Select (ACS);high-throughput rate Viterbi decoder;look-ahead implementation;low latency viterbi decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.18}
+}
+
+@InProceedings{che_08,
+  Title                    = {{T}wo-{L}evel {E}arly {S}topping {A}lgorithm for {LTE} {T}urbo {D}ecoding},
+  Author                   = {J. F. Cheng},
+  Booktitle                = {Vehicular Technology Conference, 2008. VTC 2008-Fall. IEEE 68th},
+  Year                     = {2008},
+  Month                    = {Sept},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/VETECF.2008.165},
+  File                     = {che_08.pdf:che_08.pdf:PDF},
+  ISSN                     = {1090-3038},
+  Keywords                 = {data structures;decoding;turbo codes;LTE turbo coding chain;LTE turbo decoding;analytical model;flexible parallel hardware implementation;hierarchical data structure;long term evolution;pipelined hardware implementation;two-level early stopping algorithm;Algorithm design and analysis;Analytical models;Cyclic redundancy check;Data structures;Energy consumption;Error analysis;Hardware;Iterative decoding;Runtime;Turbo codes},
+  Owner                    = {StW},
+  Timestamp                = {2016.06.28}
+}
+
+@InProceedings{chenim_08,
+  Title                    = {{A}nalysis of {C}ircular {B}uffer {R}ate {M}atching for {LTE} {T}urbo {C}ode},
+  Author                   = {J. F. Cheng and A. Nimbalker and Y. Blankenship and B. Classon and T. K. Blankenship},
+  Booktitle                = {Vehicular Technology Conference, 2008. VTC 2008-Fall. IEEE 68th},
+  Year                     = {2008},
+  Month                    = {Sept},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/VETECF.2008.162},
+  File                     = {chenim_08.pdf:chenim_08.pdf:PDF},
+  ISSN                     = {1090-3038},
+  Keywords                 = {broadband networks;code division multiple access;convolutional codes;turbo codes;8-state recursive systematic convolutional code;CBRM;LTE turbo code;QPP interleavers;WCDMA-based air interface;circular buffer rate matching;code division multiple access;long term evolution codes;Automatic repeat request;Channel coding;Convolutional codes;Delay;Long Term Evolution;Modulation coding;Multiaccess communication;OFDM modulation;Tail;Turbo codes},
+  Owner                    = {StW},
+  Timestamp                = {2016.02.25}
+}
+
+@InProceedings{chekoo_08,
+  Title                    = {{E}rror {D}etection {R}eliability of {LTE} {CRC} {C}oding},
+  Author                   = {Jung-Fu Cheng and Koorapaty, H.},
+  Booktitle                = {Proc. VTC 2008-Fall Vehicular Technology Conference IEEE 68th},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/VETECF.2008.163},
+  File                     = {chekoo_08.pdf:chekoo_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.11.16}
+}
+
+@InProceedings{cheott_00,
+  Title                    = {{Linearly Approximated Log-MAP Algorithms for Turbo Decoding}},
+  Author                   = {J.-F. Cheng and T. Ottoson},
+  Booktitle                = {Proc. 2000-Spring Vehicular Technology Confernce (VTC Spring '00)},
+  Year                     = {2000},
+
+  Address                  = {Tokyo, Japan},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{cheped_01,
+  Title                    = {{Low Power Techniques for Address Encoding and Memory Allocation}},
+  Author                   = {W. Cheng and M. Pedram},
+  Booktitle                = {Proc. 2001 Asia South Pacific Design Automation Conference (ASP-DAC '01)},
+  Year                     = {2001},
+
+  Address                  = {Yokohama, Japan},
+  Month                    = jan,
+  Pages                    = {245--250},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chelee_07,
+  Title                    = {{H}ardware {G}eneration of {A}rbitrary {R}andom {N}umber {D}istributions {F}rom {U}niform {D}istributions {V}ia the {I}nversion {M}ethod},
+  Author                   = {Cheung, R. C. C. and Dong-U Lee and Wayne Luk and Villasenor, J. D.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2007},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {952--962},
+  Volume                   = {15},
+
+  Abstract                 = {We present an automated methodology for producing hardware-based random number generator (RNG) designs for arbitrary distributions using the inverse cumulative distribution function (ICDF). The ICDF is evaluated via piecewise polynomial approximation with a hierarchical segmentation scheme that involves uniform segments and segments with size varying by powers of two which can adapt to local function nonlinearities. Analytical error analysis is used to guarantee accuracy to one unit in the last place (ulp). Compact and efficient RNGs that can reach arbitrary multiples of the standard deviationcan be generated. For instance, a Gaussian RNG based on our approach for a Xilinx Virtex-4 XC4VLX100-12 field-programmable gate array produces 16-bit random samples up to},
+  Cds_grade                = {4},
+  Cds_keywords             = {ICDF, inversion, normal distribution,},
+  Cds_read                 = {2010-07-26},
+  Doi                      = {10.1109/TVLSI.2007.900748},
+  File                     = {chelee_07.pdf:chelee_07.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.21},
+  Url                      = {http://dx.doi.org/10.1109/TVLSI.2007.900748}
+}
+
+@InProceedings{chicon_01,
+  Title                    = {{A} pragmatic approach to space-time coding},
+  Author                   = {Chiani, M. and Conti, A. and Tralli, V. },
+  Booktitle                = {Proc. IEEE International Conference on Communications ICC 2001},
+  Year                     = {2001},
+  Month                    = jun,
+  Pages                    = {2794--2799},
+  Volume                   = {9},
+
+  Doi                      = {10.1109/ICC.2001.936659},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.11.02}
+}
+
+@InProceedings{chikim_92,
+  Title                    = {{Planar-adaptive Routing: Low-cost Adaptive Networks for Multiprocessors}},
+  Author                   = {A.A. Chien and J.H. Kim},
+  Booktitle                = {Proc. 19th International Symposium on Computer Architecture},
+  Year                     = {1992},
+  Month                    = may,
+  Pages                    = {268--277},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{chi_01,
+  Title                    = {{Digital Systems On a Chip}},
+  Author                   = {C. Chien},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {2001},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chi_64,
+  Title                    = {{C}yclic decoding procedures for {B}ose- {C}haudhuri-{H}ocquenghem codes},
+  Author                   = {R. Chien},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1964},
+
+  Month                    = {Oct},
+  Number                   = {4},
+  Pages                    = {357-363},
+  Volume                   = {10},
+
+  Doi                      = {10.1109/TIT.1964.1053699},
+  ISSN                     = {0018-9448},
+  Keywords                 = {BCH codes;Decoding;Decoding;Delay;Electronic circuits;Equations;Error correction codes;Galois fields;Hardware;Instruments;Parity check codes;Polynomials}
+}
+
+@Misc{CCSA,
+  Title                    = {{CCSA home page}},
+
+  Author                   = {{China Communications Standard Association}},
+  HowPublished             = {{{www.cwts.org}}},
+
+  Key                      = {CWTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{chccsa,
+  Title                    = {{CCSA home page}},
+
+  Author                   = {{China Communications Standard Association}},
+  HowPublished             = {{{www.cwts.org}}},
+
+  Key                      = {CWTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{chinik_01,
+  Title                    = {{Achieving 550 MHz in an ASIC Methodology}},
+  Author                   = {D. G. Chinnery and B. Nikolic and K. Keutzer},
+  Booktitle                = {Proc. 2001 Design Automation Conference (DAC '01)},
+  Year                     = {2001},
+
+  Address                  = {Las Vegas, Nevada, USA},
+  Month                    = jun,
+  Pages                    = {420--425},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{chimoh_10,
+  Title                    = {{S}calable {E}ffort {H}ardware {D}esign: {E}xploiting {A}lgorithmic {R}esilience for {E}nergy {E}fficiency},
+  Author                   = {Chippa, V. K. and Mohapatra, D. and Raghunathan, A. and Roy, K. and Chakradhar, S. T.},
+  Booktitle                = {Proc. 47th ACM/IEEE Design Automation Conf. (DAC)},
+  Year                     = {2010},
+  Pages                    = {555--560},
+
+  Cb_grade                 = {SPP 1500},
+  File                     = {chimoh_10.pdf:chimoh_10.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.26}
+}
+
+@Article{chldin_18,
+  Title                    = {{T}he {D}ensest $k$-{S}ubhypergraph {P}roblem},
+  Author                   = {Chlamt\'{a}\v{c}, Eden and Dinitz, Michael and Konrad, Christian and Kortsarz, Guy and Rabanca, George},
+  Journal                  = {SIAM Journal on Discrete Math},
+  Year                     = {2018},
+  Number                   = {2},
+  Pages                    = {1458--1477},
+  Volume                   = {32},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-20}
+}
+
+@Conference{chldin_16,
+  Title                    = {{T}he {D}ensest $k$-{S}ubhypergraph {P}roblem},
+  Author                   = {Chlamt\'{a}\v{c}, Eden and Dinitz, Michael and Konrad, Christian and Kortsarz, Guy and Rabanca, George},
+  Booktitle                = {Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques (APPROX/RANDOM 2016)},
+  Year                     = {2016},
+  Pages                    = {6:1--6:19},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-25}
+}
+
+@InProceedings{chldin_17,
+  Title                    = {{M}inimizing the {U}nion: {T}ight {A}pproximations for {S}mall {S}et {B}ipartite {V}ertex {E}xpansion},
+  Author                   = {Chlamt\'{a}\v{c}, Eden and Dinitz, Michael and Makarychev, Yury},
+  Booktitle                = {SODA '17 Proceedings of the Twenty-Eighth Annual ACM-SIAM Symposium on Discrete Algorithms},
+  Year                     = {2017},
+  Pages                    = {881-899},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-25}
+}
+
+@Article{choche_15,
+  Title                    = {{U}nderstanding {S}oft {E}rrors in {U}ncore {C}omponents},
+  Author                   = {Hyungmin Cho and 
+ Chen{-}Yong Cher and
+ Thomas Shepherd and
+ Subhasish Mitra},
+  Journal                  = {CoRR},
+  Year                     = {2015},
+  Volume                   = {abs/1504.01381},
+
+  Bibsource                = {dblp computer science bibliography, http://dblp.org},
+  Biburl                   = {http://dblp.uni-trier.de/rec/bib/journals/corr/ChoCSM15},
+  Owner                    = {MJ},
+  Timestamp                = {Sat, 02 May 2015 17:50:32 +0200},
+  Url                      = {http://arxiv.org/abs/1504.01381}
+}
+
+@Article{chojun_05,
+  Title                    = {{Complexity-Reduced Algorithms for LDPC Decoder for DVB-S2 Systems}},
+  Author                   = {E. Choi and J. Jung and N. Kim and D. Oh},
+  Journal                  = {ETRI Journal},
+  Year                     = {2005},
+
+  Month                    = oct,
+  Number                   = {5},
+  Pages                    = {639--642},
+  Volume                   = {27},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{chokim_06,
+  Title                    = {{L}ow-power hybrid turbo decoding based on reverse calculation},
+  Author                   = {Hye-Mi Choi and Ji-Hoon Kim and In-Cheol Park},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2006},
+  Year                     = {2006},
+  Pages                    = {4pp.--2056},
+
+  Doi                      = {10.1109/ISCAS.2006.1693019},
+  File                     = {chokim_06.pdf:chokim_06.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{cholee_11,
+  Title                    = {{S}tudy on {H}igh {T}hroughput {T}urbo {D}ecoder},
+  Author                   = {Jaesung Choi and Jeong Woo Lee},
+  Booktitle                = {Vehicular Technology Conference (VTC Spring), 2011 IEEE 73rd},
+  Year                     = {2011},
+  Month                    = {May},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/VETECS.2011.5956697},
+  ISSN                     = {1550-2252},
+  Keywords                 = {error correction codes;error statistics;iterative decoding;maximum likelihood decoding;turbo codes;BER performance;error correction performance;high throughput turbo decoder;iterative turbo decoder;turbo codes;turbo decoding;Bit error rate;Decoding;Iterative decoding;Measurement;Memory management;Throughput;Tiles}
+}
+
+@Article{choban_09,
+  Title                    = {{V}ariation-{A}ware {L}ow-{P}ower {S}ynthesis {M}ethodology for {F}ixed-{P}oint {FIR} {F}ilters},
+  Author                   = {Choi, J. H. and Banerjee, N. and Roy, K.},
+  Journal                  = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
+  Year                     = {2009},
+  Number                   = {1},
+  Pages                    = {87--97},
+  Volume                   = {28},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/TCAD.2008.2009135},
+  File                     = {choban_09.pdf:choban_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.26}
+}
+
+@InProceedings{chonar_07,
+  Title                    = {{O}ptimizing {D}ata {M}ining {W}orkloads using {H}ardware {A}ccelerators},
+  Author                   = {Choudhary, Alok and Narayanan, Ramanathan and Iky{\i}lmaz, Berkin {\"O}z{\i}s and Memik, Gokhan and Zambreno, Joseph and Pisharath, Jayaprakash},
+  Booktitle                = {Proceedings of the Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW)},
+  Year                     = {2007},
+  Organization             = {Citeseer},
+
+  File                     = {chonar_07.pdf:chonar_07.pdf:PDF},
+  Owner                    = {CDS},
+  Timestamp                = {2016-02-04}
+}
+
+@InProceedings{chomoh_09,
+  Title                    = {{M}asking timing errors on speed-paths in logic circuits},
+  Author                   = {Choudhury, Mihir R. and Mohanram, Kartik},
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conference \& Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {87--92},
+
+  File                     = {chomoh_09.pdf:chomoh_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.01}
+}
+
+@Article{cho_04,
+  Title                    = {{O}ption pricing using the fractional {FFT}},
+  Author                   = {Chourdakis, Kyriakos},
+  Journal                  = {Journal of Computational Finance},
+  Year                     = {2004},
+  Number                   = {2},
+  Pages                    = {1--18},
+  Volume                   = {8},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.08.21}
+}
+
+@InProceedings{chokwo_11,
+  Title                    = {{M}ixed {P}recision {C}omparison in {R}econfigurable {S}ystems},
+  Author                   = {Chow, G.C.T. and Kwok, K. W. and Luk, W. and Leong, P.},
+  Booktitle                = {2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
+  Year                     = {2011},
+  Pages                    = {17--24},
+
+  Abstract                 = {Customisable data formats provide an opportunity for exploring trade-offs in accuracy and performance of reconfigurable systems. This paper introduces a novel methodology for mixed-precision comparison, which improves comparison performance by using reduced-precision data paths while maintaining accuracy by using high-precision data paths. Our methodology adopts reduced-precision data-paths for preliminary comparison, and high-precision data-paths when the accuracy for preliminary comparison is insufficient. We develop an analytical model for performance estimation of the proposed mixed-precision methodology. Optimisation based on integer linear programming is employed for determining the optimal precision and resource allocation for each of the data paths. The effectiveness of our approach is evaluated using a common collision detection problem. Performance gains of 4 to 7.3 times are obtained over baseline fixed-precision designs for the same FPGAs. With the help of the proposed mixed-precision methodology, our FPGA designs are 15.4 to 16.7 times faster than software running on multi-core CPUs with the same technology.},
+  Cds_keywords             = {mixed precision},
+  Doi                      = {10.1109/FCCM.2011.57},
+  File                     = {chokwo_11.pdf:chokwo_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@InProceedings{chotse_12,
+  Title                    = {{A} mixed precision {M}onte {C}arlo methodology for reconfigurable accelerator systems},
+  Author                   = {Chow, Gary Chun Tak and Tse, Anson Hong Tak and Jin, Qiwei and Luk, Wayne and Leong, Philip H.W. and Thomas, David B.},
+  Booktitle                = {Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays},
+  Year                     = {2012},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {57--66},
+  Publisher                = {ACM},
+  Series                   = {FPGA '12},
+
+  Acmid                    = {2145705},
+  Cds_grade                = {0},
+  Cds_keywords             = {Monte Carlo, mixed precision},
+  Doi                      = {10.1145/2145694.2145705},
+  File                     = {chotse_12.pdf:chotse_12.pdf:PDF},
+  ISBN                     = {978-1-4503-1155-7},
+  Keywords                 = {finance},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {10},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@InProceedings{chofai_00,
+  Title                    = {{Complexity-Performance Trade-offs in Turbo Codes for IMT-2000}},
+  Author                   = {L. F. Choy and I. J. Fair and W. A. Krzymien},
+  Booktitle                = {Proc. 2000-Fall Vehicular Technology Conference (VTC '00 Fall)},
+  Year                     = {2000},
+
+  Address                  = {Boston, Massachusetts, USA},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{chupia_15,
+  Title                    = {{D}esign of low area list successive cancellation decoder for polar codes},
+  Author                   = {J. G. Chung and Z. Piao},
+  Booktitle                = {2015 International SoC Design Conference (ISOCC)},
+  Year                     = {2015},
+  Month                    = {Nov},
+  Pages                    = {35-36},
+
+  Doi                      = {10.1109/ISOCC.2015.7401646},
+  Keywords                 = {maximum likelihood decoding;ML decoder;constructive capacity-achieving codes;low area SCL decoder architecture;low area list successive cancellation decoder design;maximum-likelihood decoder;merged processing elements;polar codes;provable capacity-achieving codes;Complexity theory;Decision support systems;Decoding;list SC decoder;low area;polar codes;pre-computation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{chufor_01,
+  Title                    = {{On the Design of Low-Density Parity-Check Codes Within 0.0045dB of the Shannon Limit}},
+  Author                   = {S.Y. Chung and G.D. Forney and T.J. Richardson and R. Urbanke},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {58--60},
+  Volume                   = {5},
+
+  File                     = {chufor_01.pdf:chufor_01.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{chugol_01,
+  Title                    = {{D}egrees of freedom in adaptive modulation: a unified view},
+  Author                   = {Chung, Seong Taek and Goldsmith, Andrea J},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2001},
+  Number                   = {9},
+  Pages                    = {1561--1571},
+  Volume                   = {49},
+
+  Publisher                = {IEEE}
+}
+
+@Book{chv_83,
+  Title                    = {{L}inear programming},
+  Author                   = {Chvátal, Vasek},
+  Publisher                = {Freeman},
+  Year                     = {1983},
+
+  Address                  = {New York (N. Y.)},
+  Note                     = {Réimpressions : 1999, 2000, 2002},
+  Series                   = {A Series of books in the mathematical sciences},
+
+  ISBN                     = {0-7167-1195-8},
+  Url                      = {http://opac.inria.fr/record=b1104676}
+}
+
+@Article{ciohem_13,
+  Title                    = {{A}daptive {M}ultiset {S}tochastic {D}ecoding of {N}on-{B}inary {LDPC} {C}odes},
+  Author                   = {Ciobanu, A. and Hemati, S. and Gross, W.J.},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2013},
+  Number                   = {16},
+  Pages                    = {4100--4113},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TSP.2013.2264813},
+  Owner                    = {PS},
+  Timestamp                = {2014.10.07},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6519310}
+}
+
+@InProceedings{ciojah_17,
+  Title                    = {{A}ccelerated {S}imulated {F}ault {I}njection {T}esting},
+  Author                   = {E. Cioroaica and J. Jahić and T. Kuhn and C. Peper and D. Uecker and C. Dropmann and P. Munk and A. Rakshith and E. Thaden},
+  Booktitle                = {2017 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)},
+  Year                     = {2017},
+  Month                    = {Oct},
+  Pages                    = {228-233},
+
+  Doi                      = {10.1109/ISSREW.2017.35},
+  Keywords                 = {embedded systems;middleware;operating systems (computers);program testing;safety-critical software;software fault tolerance;software behavior;platform software;embedded systems;operating systems;middleware platforms;accelerated simulated fault injection testing;fault injection testing approaches;critical software;software complexity;execution environments reliability;software components testing;Testing;Safety;Operating systems;Hardware;Computational modeling;Registers;simulated fault injection technique;accelerated fault injection;gem5;FERAL},
+  Owner                    = {MJ},
+  Timestamp                = {2018-12-18}
+}
+
+@InProceedings{cla_99,
+  Title                    = {{High Speed: Not the only way to exploit the intrinsic computational power of silicon}},
+  Author                   = {T. A. C. M. Claasen},
+  Booktitle                = {Proc. 1999 IEEE International Solid-State Circuits Conference (ISSCC)},
+  Year                     = {1999},
+
+  Address                  = {San Francisco, California, USA},
+  Month                    = feb,
+  Pages                    = {22--25},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{clabla_00,
+  Title                    = {{Turbo Decoding with the Constant-Log-MAP Algorithm}},
+  Author                   = {B. Classon and K. Blankenship and V. Desai},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {467--470},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{clazha_08,
+  Title                    = {{A} multi-platform controller allowing for maximum {D}ynamic {P}artial {R}econfiguration throughput},
+  Author                   = {Claus, C. and Zhang, B. and Stechele, W. and Braun, L. and Hubner, M. and Becker, J.},
+  Journal                  = {Field Programmable Logic and Applications, International Conference on},
+  Year                     = {2008},
+
+  Month                    = sep,
+  Pages                    = {535-538},
+
+  Abstract                 = {Dynamic and partial reconfiguration (DPR) is a special feature offered by Xilinx Field Programmable Gate Arrays (FPGAs), giving the designer the ability to reconfigure a certain portion of the FPGA during run-time without influencing the other parts. This feature allows the hardware to be adaptable to any potential situation. For some applications, such as video-based driver assistance, the time needed to exchange a certain portion of the device might be critical. This paper addresses problems, limitations and results of on-chip reconfiguration that enable the user to decide whether DPR is suitable for a certain design prior to its implementation. A method is therefore introduced to calculate the expected reconfiguration throughput and latency. In addition, an IP core is presented that enables fast on-chip DPR close to the maximum achievable speed. Compared to an alternative state-of-the art realization, an increase in speed by a factor of 58 can be obtained.},
+  Cds_grade                = {3},
+  Cds_keywords             = {FPGA, Xilinx, partial reconfiguration, ICAP, DPR},
+  Cds_read                 = {2009-02-13},
+  Cds_review               = {general overview only, not detailed
+claims speeup of 58 times, but no comparable values given},
+  Date-added               = {2008-12-09 09:51:49 +0100},
+  Date-modified            = {2008-12-09 09:52:50 +0100},
+  Doi                      = {10.1109/FPL.2008.4630002},
+  File                     = {clazha_08.pdf:clazha_08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{clakar_03,
+  Title                    = {{I}mproved max-log map turbo decoding using maximum mutual information combining},
+  Author                   = {Claussen, H. and Karimi, H. R. and Mulgrew, B. },
+  Booktitle                = {Proc. 14th IEEE Personal, Indoor and Mobile Radio Communications PIMRC 2003},
+  Year                     = {2003},
+  Pages                    = {424--428},
+  Volume                   = {1},
+
+  Doi                      = {.2003.1264307},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.10}
+}
+
+@InProceedings{cleber_10,
+  Title                    = {{A} 477m{W} {N}o{C}-{B}ased {D}igital {B}aseband for {MIMO} 4{G} {SDR}},
+  Author                   = {F. Clermidy and C. Bernard and R. Lemaire and J. Martin and I. Miro-Panades and Y. Thonnart and P. Vivet and N. Wehn},
+  Booktitle                = {Proc. IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2010. ISSCC 2010},
+  Year                     = {2010},
+
+  Address                  = {San Francisco, USA},
+  Month                    = feb,
+  Pages                    = {278--279},
+  Volume                   = {53},
+
+  File                     = {cleber_10.pdf:cleber_10.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.10}
+}
+
+@Article{clipop_11,
+  Title                    = {{M}aximum {S}ubset {I}ntersection},
+  Author                   = {Clifford, R. and Popa, A.},
+  Journal                  = {Information Processing Letters},
+  Year                     = {2011},
+  Number                   = {7},
+  Pages                    = {323--325},
+  Volume                   = {111},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-25}
+}
+
+@InProceedings{cmarij_99,
+  Title                    = {{A Methodology and Design Environment for DSP ASIC Fixed Point Refinement}},
+  Author                   = {R. Cmar and L. Rijnders and P. Schaumont and S. Vernalde and I. Bolsens},
+  Booktitle                = {Proc. 1999 Design, Automation and Test in Europe (DATE '99)},
+  Year                     = {1999},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+  Pages                    = {271--276},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{CMP,
+  Title                    = {{C}ircuits {M}ulti-{P}rojets},
+
+  Author                   = {CMP},
+
+  Owner                    = {Kienle},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://cmp.imag.fr/products/ic/}
+}
+
+@Misc{cmp_all,
+  Title                    = {{C}ircuits {M}ulti-{P}rojets},
+
+  Author                   = {CMP},
+
+  Owner                    = {Kienle},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://cmp.imag.fr/products/ic/}
+}
+
+@Article{cobche_03,
+  Title                    = {{A}n {A}pplication of {M}arkov {C}hain {M}onte {C}arlo to {C}ommunity {E}cology},
+  Author                   = {George W. Cobb and Yung-Pin Chen},
+  Journal                  = {The American Mathematical Monthly},
+  Year                     = {2003},
+  Pages                    = {265--288},
+  Volume                   = {110},
+
+  Owner                    = {Nina},
+  Timestamp                = {2007.10.05}
+}
+
+@InProceedings{cocdie_04,
+  Title                    = {{A Scalable Architecture for LDPC Decoding}},
+  Author                   = {M. Cocco and J. Dielissen and M. Heijligers and A. Hekstra and J. Huisken},
+  Booktitle                = {Proc. 2004 Design, Automation and Test in Europe (DATE '04)},
+  Year                     = {2004},
+
+  Address                  = {Paris, France},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{col_04,
+  Title                    = {{Design and Performance of Turbo Gallager Codes}},
+  Author                   = {G. Colavolpe},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2004},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {1901--1908},
+  Volume                   = {52},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{Colavolpe2000,
+  Title                    = {{N}oncoherent iterative (turbo) decoding},
+  Author                   = {Colavolpe, Giulio and Ferrari, Gianluigi and Raheli, Riccardo},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2000},
+  Number                   = {9},
+  Pages                    = {1488--1498},
+  Volume                   = {48},
+
+  Owner                    = {ali},
+  Publisher                = {IEEE},
+  Timestamp                = {2015.04.23}
+}
+
+@InProceedings{colluc_18,
+  Title                    = {{T}ermination {C}hecking and {T}ask {D}ecomposition for {T}ask-based {I}ntermittent {P}rograms},
+  Author                   = {Colin, Alexei and Lucia, Brandon},
+  Booktitle                = {Proceedings of the 27th International Conference on Compiler Construction},
+  Year                     = {2018},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {116--127},
+  Publisher                = {ACM},
+  Series                   = {CC 2018},
+
+  Acmid                    = {3179525},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Colin:2018:TCT:3178372.3179525},
+  Ccr_keywords             = {CleanCut},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3178372.3179525},
+  ISBN                     = {978-1-4503-5644-2},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy estimation, intermittent computing},
+  Location                 = {Vienna, Austria},
+  Numpages                 = {12},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/3178372.3179525}
+}
+
+@Article{colluc_16,
+  Title                    = {{C}hain: {T}asks and {C}hannels for {R}eliable {I}ntermittent {P}rograms},
+  Author                   = {Colin, Alexei and Lucia, Brandon},
+  Journal                  = {SIGPLAN Not.},
+  Year                     = {2016},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {514--530},
+  Volume                   = {51},
+
+  Acmid                    = {2983995},
+  Address                  = {New York, NY, USA},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Colin:2016:CTC:3022671.2983995},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3022671.2983995},
+  ISSN                     = {0362-1340},
+  Issue_date               = {October 2016},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy-harvesting, intermittent computing},
+  Numpages                 = {17},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/3022671.2983995}
+}
+
+@Article{colrup_18,
+  Title                    = {{A} {R}econfigurable {E}nergy {S}torage {A}rchitecture for {E}nergy-harvesting {D}evices},
+  Author                   = {Colin, Alexei and Ruppel, Emily and Lucia, Brandon},
+  Journal                  = {SIGPLAN Not.},
+  Year                     = {2018},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {767--781},
+  Volume                   = {53},
+
+  Acmid                    = {3173210},
+  Address                  = {New York, NY, USA},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Colin:2018:RES:3296957.3173210},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3296957.3173210},
+  ISSN                     = {0362-1340},
+  Issue_date               = {February 2018},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy burst, energy-harvesting power system, intermittent computing},
+  Numpages                 = {15},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/3296957.3173210}
+}
+
+@TechReport{col_08,
+  Title                    = {{T}esting, {S}election, and {I}mplementation of {R}andom {N}umber {G}enerators},
+  Author                   = {Joseph C. Collins},
+  Institution              = {Army Research Laboratory},
+  Year                     = {2008},
+
+  Address                  = {Aberdeen Proving Ground, MD 21005-5068},
+  Month                    = jul,
+
+  Cds_grade                = {0},
+  Cds_keywords             = {TestU01, tausworthe, random number generation},
+  File                     = {col_08.pdf:col_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.26}
+}
+
+@Article{colpol_88,
+  Title                    = {{Wiring Viterbi Decoders (Splitting deBruijn Graphs)}},
+  Author                   = {O. Collins and F. Pollara and S. Dolinar and J. Statman},
+  Journal                  = {The Telecommunications and Data Acquisition Progress Report 42--96},
+  Year                     = {1988},
+
+  Month                    = oct # {--} # dec,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {93-103},
+  Volume                   = {42},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{col_92,
+  Title                    = {{The Subtleties and Intricacies of Building a Constraint Length 15 Convolutional Decoder}},
+  Author                   = {Collins, O. M.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1992},
+
+  Month                    = dec,
+  Number                   = {12},
+  Pages                    = {1810--1819},
+  Volume                   = {40},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Comellas,
+  Title                    = {{Using Simulated Annealing to Design Interconnection Networks}},
+
+  Author                   = {F. Comellas and M. A. Fiol},
+  Note                     = {{\sf http://www-mat.upc.es/\symbol{126}comellas/anneal/anneal.html}, Departament de Matem\`atica Aplicada i Telem\`atica; Universitat Polit\`ecnica de Catalunya, DMAT Report 05-290, January 1991},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{comusing,
+  Title                    = {{Using Simulated Annealing to Design Interconnection Networks}},
+
+  Author                   = {F. Comellas and M. A. Fiol},
+  Note                     = {{\sf http://www-mat.upc.es/\symbol{126}comellas/anneal/anneal.html}, Departament de Matem\`atica Aplicada i Telem\`atica; Universitat Polit\`ecnica de Catalunya, DMAT Report 05-290, January 1991},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Booklet{com_13,
+  Title                    = {{T}rends in {C}loud {C}omputing - {F}ull {R}eport},
+  Author                   = {CompTIA},
+  Month                    = aug,
+  Year                     = {2013},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {cloud, HPC, finance},
+  Cds_read                 = {2014-01-30},
+  Cds_review               = {cloud computing study with status quo of cloud usage and predictions},
+  File                     = {com_13.pdf:com_13.pdf:PDF},
+  Keywords                 = {cloud},
+  LastChecked              = {2014-01-30},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.30},
+  Url                      = {\url{http://www.comptia.org/research/cloud.aspx}}
+}
+
+@Article{conmar_14,
+  Title                    = {{V}ariable {P}arallelism {C}yclic {R}edundancy {C}heck {C}ircuit for 3{GPP}-{LTE}/{LTE}-{A}dvanced},
+  Author                   = {Condo, C. and Martina, M. and Piccinini, G. and Masera, G.},
+  Journal                  = {Signal Processing Letters, IEEE},
+  Year                     = {2014},
+
+  Month                    = {Nov},
+  Number                   = {11},
+  Pages                    = {1380-1384},
+  Volume                   = {21},
+
+  Abstract                 = {Cyclic Redundancy Check (CRC) is often employed in data storage and communications to detect errors. The 3GPP-LTE wireless communication standard uses a 24-bit CRC with every turbo coded frame, thus, the CRC can be exploited to detect residual errors and to enable early stopping of iterations as well. The current state of the art lacks specific CRC implementations for this standard, and most current solutions adopt a fixed degree of parallelism, unsuitable for many turbo decoder architectures. This work proposes a variable parallelism circuit targeting the 3GPP-LTE/LTE-Advanced 24-bit CRC, that can adapt to input data of different sizes. Low complexity is achieved through careful functional sharing among the various parallelisms: comparison with the state of the art shows comparable or superior speed and extremely low complexity.},
+  Doi                      = {10.1109/LSP.2014.2334393},
+  File                     = {conmar_14.pdf:conmar_14.pdf:PDF},
+  ISSN                     = {1070-9908},
+  Keywords                 = {3G mobile communication;Long Term Evolution;cyclic redundancy check codes;decoding;turbo codes;3GPP-LTE-LTE-advanced;CRC;data communications;data storage;residual error detection;turbo coded frame;turbo decoder architectures;variable parallelism cyclic redundancy check circuit;wireless communication standard;word length 24 bit;Clocks;Decoding;Logic gates;Long Term Evolution;Parallel processing;Vectors;3GPP-LTE;CRC;LTE-advanced;turbo codes},
+  Owner                    = {StW},
+  Timestamp                = {2014.11.17}
+}
+
+@InProceedings{con_01,
+  Title                    = {{An Interconnect-Centric Design Flow for Nanometer Technologies}},
+  Author                   = {J. Cong},
+  Booktitle                = {Proceedings of the Workshop on Synthesis And System Integration of Mixed Technologies, October 2001},
+  Year                     = {2001},
+  Pages                    = {199--205},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{conhua_16,
+  Title                    = {{A} {S}calable {C}ommunication-{A}ware {C}ompilation {F}low for {P}rogrammable {A}ccelerators},
+  Author                   = {Jason Cong and Hui Huang and Mohammad Ali Ghodrat},
+  Booktitle                = {Proceedings of the 2016 21th Asia and South Pacific Design Automation Conference (ASP-DAC)},
+  Year                     = {2016},
+  Month                    = {Jan},
+  Pages                    = {503-510},
+
+  Abstract                 = {Due to the increased power density and lower thermal conductivity, 3D is faced with heat dissipation and temperature problem seriously. Previous researches show that leakage power and delay are both relevant to temperature. The timing-power-temperature dependence will potentially negate the performance improvement of 3D designs. TSV (Through-Silicon-Vias) has been shown as an effective way to help heat removal, but they create routing congestions. Therefore, how to reach the trade-off between temperature, via number and delay is required to be solved. Different from previous works on TSV planning which ignored the effects of leakage power, in this paper, we integrate temperature-leakage-timing dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering both performance and heat dissipation with resource constraint, is proposed to achieve the best balance among delay, via number and temperature. Experiment results show that, with leakage power and resource constraint considered the temperature and via number required can be quite different, and weighted TSV insertion approach can improve thermal via number, by about 5.6%.},
+  File                     = {conhua_16.pdf:conhua_16.pdf:PDF},
+  ISSN                     = {2153-6961},
+  Owner                    = {CDS},
+  Timestamp                = {2016-02-16}
+}
+
+@Article{conliu_11,
+  Title                    = {{H}igh-{L}evel {S}ynthesis for {FPGA}s: {F}rom {P}rototyping to {D}eployment},
+  Author                   = {Cong, J. and Bin Liu and Neuendorffer, S. and Noguera, J. and Vissers, K. and Zhiru Zhang},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2011},
+  Number                   = {4},
+  Pages                    = {473--491},
+  Volume                   = {30},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.08.03}
+}
+
+@InProceedings{conuch_01,
+  Title                    = {{An Interconnect Energy Model Considering Coupling Effects}},
+  Author                   = {J. Cong and T. Uchinko},
+  Booktitle                = {Proceedings of the 38th Design Automation Conference, June 2001},
+  Year                     = {2001},
+  Pages                    = {555--558},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Cong2005,
+  Title                    = {{T}hermal via planning for 3-{D} {IC}s},
+  Author                   = {Cong, J. and Yan Zhang},
+  Booktitle                = {Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on},
+  Year                     = {2005},
+  Month                    = {Nov},
+  Pages                    = {745-752},
+
+  Doi                      = {10.1109/ICCAD.2005.1560164},
+  Keywords                 = {circuit layout;circuit optimisation;convex programming;integrated circuit design;nonlinear programming;thermal analysis;thermal management (packaging);3D IC;circuit temperature;constrained nonlinear programming problem;convex programming;heat dissipation;heat propagation;m-ADVP;multilevel routing framework;path counting;thermal resistive model;thermal through-the-silicon vias;thermal via planning;Computer science;Cooling;Heat sinks;Optimization methods;Resistance heating;Routing;Speech synthesis;Temperature;Thermal conductivity;Three-dimensional integrated circuits},
+  Owner                    = {weis},
+  Timestamp                = {2015.04.14}
+}
+
+@Article{conxia_99,
+  Title                    = {{O}n {SOVA} for nonbinary codes},
+  Author                   = {Ling Cong and Wu Xiaofu and Yi Xiaoxin},
+  Journal                  = {IEEE_J_COML},
+  Year                     = {1999},
+  Number                   = {12},
+  Pages                    = {335--337},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/4234.809527},
+  Owner                    = {m.alles},
+  Timestamp                = {2010.08.12}
+}
+
+@Article{con_03,
+  Title                    = {{T}rends and challenges in {VLSI} circuit reliability},
+  Author                   = {Constantinescu, C.},
+  Journal                  = {IEEE Micro},
+  Year                     = {2003},
+
+  Month                    = jul,
+  Number                   = {4},
+  Pages                    = {14--19},
+  Volume                   = {23},
+
+  Doi                      = {10.1109/MM.2003.1225959},
+  File                     = {con_03.pdf:con_03.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{con_17,
+  Title                    = {{FPGA}s in the {C}loud},
+  Author                   = {George A. Constantinides},
+  Booktitle                = {Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {167--167},
+  Publisher                = {ACM},
+  Series                   = {FPGA '17},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.22}
+}
+
+@Misc{CCSDS1999,
+  Title                    = {{Recommendation for Space Data System Standards -- CCSDS 101.0-B-4}},
+
+  Author                   = {{Consultative Committee for Space Data Systems}},
+  HowPublished             = {{{www.ccsds.org}}},
+  Month                    = may,
+  Year                     = {1999},
+
+  Key                      = {ccsdsturbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{corecommendation99,
+  Title                    = {{Recommendation for Space Data System Standards -- CCSDS 101.0-B-4}},
+
+  Author                   = {{Consultative Committee for Space Data Systems}},
+  HowPublished             = {{{www.ccsds.org}}},
+  Month                    = may,
+  Year                     = {1999},
+
+  Key                      = {ccsdsturbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{con_01a,
+  Title                    = {{E}mpirical properties of asset returns: stylized facts and statistical issues},
+  Author                   = {Rama Cont},
+  Journal                  = {Quantitative Finance},
+  Year                     = {2001},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {223-236},
+  Volume                   = {1},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.30}
+}
+
+@InCollection{conbai_14,
+  Title                    = {{FPGA} {I}mplementation of {G}lobal {V}ision for {R}obot {S}occer as a {S}mart {C}amera},
+  Author                   = {Contreras, Miguel and Bailey, DonaldG. and Gupta, GourabSen},
+  Booktitle                = {Robot Intelligence Technology and Applications 2},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2014},
+  Editor                   = {Kim, Jong-Hwan and Matson, Eric T . and Myung, Hyun and Xu, Peter and Karray, Fakhri},
+  Pages                    = {657-665},
+  Series                   = {Advances in Intelligent Systems and Computing},
+  Volume                   = {274},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {morphological filter, FPGA},
+  Doi                      = {10.1007/978-3-319-05582-4_56},
+  ISBN                     = {978-3-319-05581-7},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Timestamp                = {2014.07.15},
+  Url                      = {http://dx.doi.org/10.1007/978-3-319-05582-4_56}
+}
+
+@Article{con_99,
+  Title                    = {{Implementation of high speed Viterbi detectors}},
+  Author                   = {T. Conway},
+  Journal                  = {Electronics Letters},
+  Year                     = {1999},
+
+  Month                    = nov,
+  Number                   = {24},
+  Pages                    = {2089--2090},
+  Volume                   = {35},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{cooros_12,
+  Title                    = {{B}uffer-on-board memory systems},
+  Author                   = {E. Cooper-Balis and P. Rosenfeld and B. Jacob},
+  Booktitle                = {Computer Architecture (ISCA), 2012 39th Annual International Symposium on},
+  Year                     = {2012},
+  Month                    = {June},
+  Pages                    = {392-403},
+
+  Doi                      = {10.1109/ISCA.2012.6237034},
+  ISSN                     = {1063-6897},
+  Keywords                 = {DRAM chips;buffer storage;logic circuits;memory architecture;queueing theory;system buses;CPU;DRAM;buffer-on-board memory systems;bus organization;capacity limitations;clock rates;commodity memory architecture;full system simulations;hardware-verified simulation suite;implementation costs;intermediate logic;mapping schemes;performance limitations;queue storage;signal integrity;simulated configurations;Bandwidth;Clocks;Protocols;SDRAM;Standards;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2016-08-19}
+}
+
+@InProceedings{copche_05,
+  Title                    = {{H}ave {GPU}s made {FPGA}s redundant in the field of {V}ideo {P}rocessing?},
+  Author                   = {Ben Cope and Peter Y.K. Cheung and Wayne Luk and Sarah Witt},
+  Booktitle                = {Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on},
+  Year                     = {2005},
+  Month                    = dec,
+  Pages                    = {111 -118},
+
+  Abstract                 = {Since the 1990s FPGAs have been popular for accelerating video processing applications. This paper presents GPUs (graphics processing units) as another viable solution, comparing their throughput with that of FPGAs. Previous work on using FPGAs and GPUs for video processing is analysed, grounds for comparison formulated and then exemplified through case studies of primary colour correction and 2D convolution. GPUs are seen to be advantageous in applications utilising their optimised instruction set and which have a low number of memory accesses. We found that for 2D convolution, the throughput of the GPUs exceeds that of FPGAs if the mask dimension is 2 times 2. For mask sizes greater than 4 times 4 and for primary colour correction FPGAs have higher throughput. The GPU implementation of primary colour correction is shown to be capable of a throughput of 63 MP/s (million pixels per second) enough for high definition video at 30 f/s (frames per second). For 2D convolution GPUs achieved the target throughput rate of 8MP/s (512 times 512 frames at 30 f/s) up to size 7 times 7. The Spartan 3 FPGA was capable of over 60 MP/s throughput and the Virtex II Pro over 110 MP/s at this size of convolution},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPT.2005.1568533},
+  File                     = {copche_05.pdf:copche_05.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.01.05}
+}
+
+@Misc{coqpasr12,
+  Title                    = {{PASR}: {P}artial {A}rray {S}elf-{R}efresh {F}ramework },
+
+  Author                   = {Maxime Coquelin},
+  HowPublished             = {\url{https://lwn.net/Articles/478049/}},
+  Year                     = {2012},
+
+  Owner                    = {EFZ},
+  Timestamp                = {2016-12-15},
+  Url                      = {https://lwn.net/Articles/478049/}
+}
+
+@Electronic{cor_17,
+  Title                    = {{NVIDIA OpenCL SDK Code Samples}},
+  Author                   = {Nvidia Corporation},
+  Note                     = {last access: 06 February 2017},
+  Url                      = {https://developer.nvidia.com/opencl},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.04.06}
+}
+
+@InProceedings{corhoa_12,
+  Title                    = {{HLS}-based fast design space exploration of ad hoc hardware accelerators: {A} key tool for {MPS}o{C} synthesis on {FPGA}},
+  Author                   = {Corre, Y. and Hoang, V.-T. and Diguet, J.-P. and Heller, D. and Lagadec, L.},
+  Booktitle                = {Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on},
+  Year                     = {2012},
+  Month                    = {Oct},
+  Pages                    = {1-8},
+
+  Keywords                 = {field programmable gate arrays;high level synthesis;multiprocessing systems;software architecture;system-on-chip;FPGA;HLS-based fast design space exploration;MPSoC synthesis;ad hoc hardware accelerators;heterogeneous multiprocessor synthesis framework;high level synthesis;larger design space exploration flow;model based software architecture;Computer architecture;Estimation;Field programmable gate arrays;Hardware;IP networks;Libraries;Software;Accelerator architectures;Field programmable gate arrays;High level synthesis;System-on-a-chip},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.27}
+}
+
+@Article{cosabu_19,
+  Title                    = {{R}econfigurable {S}ystem for {E}lectromagnetic {E}nergy {H}arvesting {W}ith {I}nherent {A}ctivity {S}ensing {C}apabilities for {W}earable {T}echnology},
+  Author                   = {A. {Costilla Reyes} and A. {Abuellil} and J. J. {Estrada-López} and S. {Carreon-Bautista} and E. {Sánchez-Sinencio}},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2019},
+
+  Month                    = {Aug},
+  Number                   = {8},
+  Pages                    = {1302-1306},
+  Volume                   = {66},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {good},
+  Ccr_key_original         = {8556033},
+  Ccr_keywords             = {wearable EH, rectifier for AC harvesters, utilizing harvester as sensor},
+  Ccr_relevance            = {high},
+  Ccr_topic                = {CS, TCW},
+  Doi                      = {10.1109/TCSII.2018.2884613},
+  Keywords                 = {TCS},
+  Keywords_original        = {CMOS integrated circuits;electromagnetic devices;energy harvesting;rectifiers;transducers;reconfigurable system;electromagnetic energy harvesting;wearable technology;power management system;electromagnetic transducer;front-end circuit;EM transducer;reconfigurable rectifier;power-efficient active topology;passive mode;negative voltage converter;active configuration;activity detection circuit;net-zero power consumption;EH front-end;peak power conversion efficiency;sensing capabilities;output storage capacitor;activity sensing capabilities;accelerometer;CMOS process;Fitbit charge HR;battery charge;voltage 1.8 V;size 130.0 nm;efficiency 92.04 percent;Transducers;Sensors;Electromagnetics;Power conversion;Transistors;Energy harvesting;Topology;Activity sensing;electromagnetic transducer;energy harvesting;human-motion sensing;wearable technology},
+  Owner                    = {CCR}
+}
+
+@InProceedings{Cote2006,
+  Title                    = {{Implementation Challenges and Synergistic Benefits of DVB-S2 and DVB-RCS}},
+  Author                   = {Cote, M. and Erup, L. and Lambert, M. and McSparron, N.},
+  Booktitle                = {The Institution of Engineering and Technology Seminar on Digital Video Broadcasting Over Satellite: Present and Future},
+  Year                     = {2006},
+
+  Address                  = {London, UK},
+  Month                    = {Nov},
+  Pages                    = {21-34},
+
+  ISSN                     = {0537-9989},
+  Keywords                 = {broadcast channels;digital video broadcasting;direct broadcasting by satellite;Advantech;DVB-RCS;DVB-S2;Ka band satellites;broadcast services;interactive services;optimisations;return channel}
+}
+
+@InProceedings{Coudrain2012,
+  Title                    = {{T}owards efficient and reliable 300mm 3{D} technology for wide {I}/{O} interconnects},
+  Author                   = {Coudrain, P. and Colonna, J.-P. and Aumont, C. and Garnier, G. and Chausse, P. and Segaud, R. and Vial, K. and Jouve, A. and Mourier, T. and Magis, T. and Besson, P. and Gabette, L. and Brunet-Manquat, C. and Allouti, N. and Laviron, C. and Cheramy, S. and Saugier, E. and Pruvost, J. and Farcy, A. and Hotellier, N.},
+  Booktitle                = {Electronics Packaging Technology Conference (EPTC), 2012 IEEE 14th},
+  Year                     = {2012},
+  Month                    = {Dec},
+  Pages                    = {330-335},
+
+  Doi                      = {10.1109/EPTC.2012.6507102},
+  Keywords                 = {CMOS integrated circuits;assembling;ball grid arrays;integrated circuit interconnections;integrated circuit reliability;integrated circuit testing;three-dimensional integrated circuits;3D assembly;3D circuit;BGA;CMOS node;bottom die realization;electrical tests;face-to-back integration;reliability tests;size 65 nm;wide I/O interconnects;Assembly;Etching;Nails;Reliability;Silicon;Stacking;Through-silicon vias},
+  Owner                    = {weis},
+  Timestamp                = {2015.04.14}
+}
+
+@Book{cou_13,
+  Title                    = {{D}esigning {S}cientific {A}pplications on {GPU}s},
+  Author                   = {Raphael Couturier},
+  Publisher                = {Chapman \& Hall/CRC},
+  Year                     = {2013},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.27}
+}
+
+@Misc{covdynamic97,
+  Title                    = {{Dynamic Logic Circuit with Noise-Immunity}},
+
+  Author                   = {J. J. Covino},
+  HowPublished             = {US Patent 5650733},
+  Year                     = {1997},
+
+  File                     = {covdynamic97.pdf:covdynamic97.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Publisher                = {Patent and Trademark Office},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Covino1997,
+  Title                    = {{Dynamic Logic Circuit with Noise-Immunity}},
+
+  Author                   = {J. J. Covino},
+  HowPublished             = {US Patent 5650733},
+  Year                     = {1997},
+
+  File                     = {covdynamic97.pdf:covdynamic97.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Publisher                = {Patent and Trademark Office},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{coxing_85,
+  Title                    = {{A} {T}heory of the {T}erm {S}tructure of {I}nterest {R}ates},
+  Author                   = {Cox, John C. and Ingersoll, Jonathan E., Jr. and Ross, Stephen A.},
+  Journal                  = {Econometrica},
+  Year                     = {1985},
+  Number                   = {2},
+  Pages                    = {385--407},
+  Volume                   = {53},
+
+  Abstract                 = {This paper uses an intertemporal general equilibrium asset pricing model to study the term structure of interest rates. In this model, anticipations, risk aversion, investment alternatives, and preferences about the timing of consumption all play a role in determining bond prices. Many of the factors traditionally mentioned as influencing the term structure are thus included in a way which is fully consistent with maximizing behavior and rational expectations. The model leads to specific formulas for bond prices which are well suited for empirical testing.},
+  Cds_grade                = {0},
+  Copyright                = {Copyright © 1985 The Econometric Society},
+  File                     = {coxing_85.pdf:coxing_85.pdf:PDF},
+  ISSN                     = {00129682},
+  Jstor_articletype        = {research-article},
+  Jstor_formatteddate      = {Mar., 1985},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Publisher                = {The Econometric Society},
+  Timestamp                = {2012.04.03},
+  Url                      = {http://www.jstor.org/stable/1911242}
+}
+
+@Book{Cramer1999,
+  Title                    = {{M}athematical {M}ethods of {S}tatistics},
+  Author                   = {Cram{\'e}r, H.},
+  Publisher                = {Princeton University Press},
+  Year                     = {1999},
+  Series                   = {Princeton Mathematical Series},
+
+  ISBN                     = {9780691005478},
+  Lccn                     = {lc99012156},
+  Owner                    = {ali},
+  Timestamp                = {2015.03.09},
+  Url                      = {http://books.google.com.pk/books?id=CRTKKaJO0DYC}
+}
+
+@InCollection{crasin_15,
+  Title                    = {{FiNS: A Framework for Accelerating Nested Simulations on Heterogeneous Platforms}},
+  Author                   = {Joris Cramwinckel and Stefan Singor and Ana Lucia Varbanescu},
+  Booktitle                = {Euro-Par 2015: Parallel Processing Workshops: Euro-Par 2015 International Workshops, Vienna, Austria, August 24-25, 2015, Revised Selected Papers},
+  Publisher                = {Springer, Cham},
+  Year                     = {2015},
+  Editor                   = {Sascha Hunold and Alexandru Costan and Domingo Gim{\'e}nez and Alexandru Iosup and Laura Ricci and Mar{\'i}a Engracia {G{\'o}mez Requena} and Vittorio Scarano and Ana Lucia Varbanescu and Stephen L. Scott and Stefan Lankes and Josef Weidendorfer and Michael Alexander},
+  Pages                    = {246--257},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {9523},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.10}
+}
+
+@TechReport{csf_97,
+  Title                    = {{CreditRisk+: A Credit Risk Management Framework}},
+  Author                   = {{Credit Suisse First Boston International}},
+  Year                     = {1997},
+  Note                     = {\url{http://www.csfb.com/institutional/research/assets/creditrisk.pdf}},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@Article{creder_09,
+  Title                    = {{I}nfinite-{D}imensional {Q}uadrature and {A}pproximation of {D}istributions},
+  Author                   = {Creutzig, Jakob and Dereich, Steffen and Müller-Gronbach, Thomas and Ritter, Klaus},
+  Journal                  = {Foundations of Computational Mathematics},
+  Year                     = {2009},
+  Number                   = {4},
+  Pages                    = {391-429},
+  Volume                   = {9},
+
+  Cds_grade                = {0},
+  Doi                      = {10.1007/s10208-008-9029-x},
+  ISSN                     = {1615-3375},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Publisher                = {Springer-Verlag},
+  Timestamp                = {2013.11.06}
+}
+
+@InProceedings{cro_00,
+  Title                    = {{New High-Spread High-Distance Interleavers for Turbo-Codes}},
+  Author                   = {S. Crozier},
+  Booktitle                = {Proc. 20-th biennal Symposium on Communications},
+  Year                     = {2000},
+
+  Address                  = {Kingston, Canada},
+  Month                    = may,
+  Pages                    = {3 -- 7},
+
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{crogra_08,
+  Title                    = {{I}mproving the flare performance of turbo codes using error detection and event flipping},
+  Author                   = {S. Crozier and K. Gracie},
+  Booktitle                = {2008 5th International Symposium on Turbo Codes and Related Topics},
+  Year                     = {2008},
+  Month                    = {Sept},
+  Pages                    = {266-271},
+
+  Doi                      = {10.1109/TURBOCODING.2008.4658709},
+  ISSN                     = {2165-4700},
+  Keywords                 = {algebra;error detection codes;turbo codes;algebraic cleanup codes;decoder complexity;error detection code;error rate performance;event flipping;flare performance;turbo codes;Cleaning;Cyclic redundancy check;Degradation;Error analysis;Event detection;Iterative algorithms;Iterative decoding;Protection;Turbo codes;Viterbi algorithm},
+  Owner                    = {StW},
+  Timestamp                = {2016.11.15}
+}
+
+@InProceedings{crogui_03,
+  Title                    = {{Distance Upper Bounds and True Minimum Distance Results for Turbo-Codes Designed with DRP Interleavers}},
+  Author                   = {S. Crozier and P. Guinand},
+  Booktitle                = {Proc. 3rd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{crogui_01,
+  Title                    = {{High-Performance Low-Memory Interleaver Banks for Turbo-Codes}},
+  Author                   = {S. Crozier and P. Guinand},
+  Booktitle                = {Proc. 2001-Fall Vehicular Technology Conference (VTC Fall 2001)},
+  Year                     = {2001},
+
+  Address                  = {Atlantic City, NJ, USA},
+  Month                    = oct,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{Crozier2005,
+  Title                    = {{E}stimating the minimum distance of turbo-codes using double and triple impulse methods},
+  Author                   = {Crozier, S. and Guinand, P. and Hunt, A.},
+  Journal                  = {Communications Letters, IEEE},
+  Year                     = {2005},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {631--633},
+  Volume                   = {9},
+
+  Doi                      = {10.1109/LCOMM.2005.1461687},
+  Owner                    = {punekar},
+  Timestamp                = {2009.09.04}
+}
+
+@InProceedings{crogui_04,
+  Title                    = {{Computing the Minimum Distance of Turbo-Codes Using Iterative Decoding Techniques}},
+  Author                   = {S. Crozier and P. Guinand and A. Hunt},
+  Booktitle                = {Proc. 22-th biennal Symposium on Communications},
+  Year                     = {2004},
+
+  Address                  = {Kingston, Canada},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{crolod_99,
+  Title                    = {{Performance of Turbo-Codes with Relative-Prime and Golden Interleaving Strategies}},
+  Author                   = {S. Crozier and J. Lodge and P. Guinand and A. Hunt},
+  Booktitle                = {Proc. 6th International Mobile Satellite Conference (IMSC'99)},
+  Year                     = {1999},
+
+  Address                  = {Ottawa, Canada},
+  Month                    = jun,
+  Pages                    = {268--275},
+
+  Optnote                  = {RP-Interleavers},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{css_11,
+  Title                    = {{C}ircular 11/512},
+  Author                   = {CSSF},
+  Institution              = {Commission de Surveillance du Secteur Financier},
+  Year                     = {2011},
+
+  Address                  = {Luxembourg},
+  Month                    = {May},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@MastersThesis{MTcuber14,
+  Title                    = {{V}irtual {P}latform {B}ased {D}esign of an {E}mbedded {O}ption {P}ricing {S}ystem on the {X}ilinx {Z}ynq-7000 {A}ll {P}rogrammable {S}o{C}},
+  Author                   = {Cubero Cascante, José},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+  Month                    = mar,
+
+  Cds_grade                = {3},
+  Cds_keywords             = {Heston, MLMC, option pricing, VP},
+  File                     = {MTcuber14.pdf:MTcuber14.pdf:PDF},
+  Keywords                 = {AG Wehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.21}
+}
+
+@InProceedings{cuimck_14,
+  Title                    = {{DT}ail: {A} {F}lexible {A}pproach to {DRAM} {R}efresh {M}anagement},
+  Author                   = {Cui, Zehan and McKee, Sally A. and Zha, Zhongbin and Bao, Yungang and Chen, Mingyu},
+  Booktitle                = {Proceedings of the 28th ACM International Conference on Supercomputing},
+  Year                     = {2014},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {43--52},
+  Publisher                = {ACM},
+  Series                   = {ICS '14},
+
+  Acmid                    = {2597663},
+  Doi                      = {10.1145/2597652.2597663},
+  ISBN                     = {978-1-4503-2642-1},
+  Keywords                 = {dram refresh, energy saving, refresh management},
+  Location                 = {Munich, Germany},
+  Numpages                 = {10},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10},
+  Url                      = {http://doi.acm.org/10.1145/2597652.2597663}
+}
+
+@InProceedings{cupjac_01,
+  Title                    = {{C}oncurrency, latency, or system overhead: {W}hich has the largest impact on uniprocessor {DRAM}-system performance?},
+  Author                   = {V. Cuppu and B. Jacob},
+  Booktitle                = {Proceedings 28th Annual International Symposium on Computer Architecture},
+  Year                     = {2001},
+  Pages                    = {62-71},
+
+  Doi                      = {10.1109/ISCA.2001.937433},
+  ISSN                     = {1063-6897},
+  Keywords                 = {parallel architectures;performance evaluation;processor scheduling;protocols;timing;SPEC CPU 2000 integer suite;application execution times;burst sizes;concurrency;fixed CPU architecture;fixed DRAM timing specification;ganged direct rambles organization;high-performance DRAM systems;latency;memory-controller page protocol;organizations;queue sizes;system overhead;uniprocessor DRAM-system performance;Bandwidth;Concurrent computing;Delay;Dynamic scheduling;Performance loss;Protocols;Random access memory;Read-write memory;Scheduling algorithm;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2017-04-06}
+}
+
+@InProceedings{cypshu_90,
+  Title                    = {{Generalized Trace Back Techniques for Survivor Memory Management in the Viterbi Algorithm}},
+  Author                   = {R. Cypher and C. B. Shung},
+  Booktitle                = {Proc. 1990 Global Telecommunications Conference (GLOBECOM '90)},
+  Year                     = {1990},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = dec,
+  Pages                    = {1318--1322},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{DAmico2001,
+  Title                    = {{E}fficient non-data-aided carrier and clock recovery for satellite {DVB} at very low signal-to-noise ratios},
+  Author                   = {D'Amico, A.A. and D'Andrea, A.N. and Regiannini, R.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2001},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {2320-2330},
+  Volume                   = {19},
+
+  Doi                      = {10.1109/49.974599},
+  ISSN                     = {0733-8716},
+  Keywords                 = {digital video broadcasting;direct broadcasting by satellite;noise;synchronisation;turbo codes;QPSK;SNR;clock/carrier recovery;clock/carrier synchronization;digital satellite communications;efficient algorithms;frequency/phase synchronization algorithms;lock-in delay;nondata-aided carrier recovery;nondata-aided clock recovery;power efficiency;quaternary phase-shift keying;satellite DVB;satellite digital video broadcasting systems;synchronization parameters acquisition;turbo-coding;very low signal-to-noise ratios;Algorithm design and analysis;Clocks;Delay;Digital video broadcasting;Frequency synchronization;Radio frequency;Satellite broadcasting;Signal design;Signal to noise ratio;Turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27}
+}
+
+@Article{DAndrea1994,
+  Title                    = {{T}he modified {Cramer-Rao} bound and its application to synchronization problems},
+  Author                   = {D'Andrea, A.N. and Mengali, U. and Reggiannini, R.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1994},
+
+  Month                    = {Feb},
+  Number                   = {234},
+  Pages                    = {1391-1399},
+  Volume                   = {42},
+
+  Doi                      = {10.1109/TCOMM.1994.580247},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Clocks;Continuous phase modulation;Cramer-Rao bounds;Detectors;Frequency estimation;Frequency synchronization;Parameter estimation;Phase estimation;Phase modulation;Timing},
+  Owner                    = {ali},
+  Timestamp                = {2015.03.09}
+}
+
+@Misc{dsodynamic96,
+  Title                    = {{Dynamic Logic Circuit with Reduced Charge Leakage}},
+
+  Author                   = {G. P. D'Souza},
+  HowPublished             = {US Patent 5483181},
+  Year                     = {1996},
+
+  File                     = {dsodynamic96.pdf:dsodynamic96.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Publisher                = {Patent and Trademark Office},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{DSouz1996,
+  Title                    = {{Dynamic Logic Circuit with Reduced Charge Leakage}},
+
+  Author                   = {G. P. D'Souza},
+  HowPublished             = {US Patent 5483181},
+  Year                     = {1996},
+
+  File                     = {dsodynamic96.pdf:dsodynamic96.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Publisher                = {Patent and Trademark Office},
+  Timestamp                = {2008.11.26}
+}
+
+@Conference{dah_09,
+  Title                    = {{T}echnological {T}rends, {D}esign {C}onstraints and {A}rchitectural {C}hallenges in {M}obile {P}hone {P}latforms},
+  Author                   = {F. Dahlgren},
+  Booktitle                = {9th International Forum on Embedded MPSoC and Multicore},
+  Year                     = {2009},
+
+  Address                  = {Savanna, USA},
+  Month                    = aug,
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.19}
+}
+
+@Book{dahpar_08,
+  Title                    = {3{G} {E}volution, {HSPA} and {LTE} for {M}obile {B}roadband},
+  Author                   = {Erik Dahlman and Stefan Parkvall and Johan Skoeld and Per Beming},
+  Publisher                = {Elsevier},
+  Year                     = {2008},
+
+  Owner                    = {Kienle},
+  Timestamp                = {2012.11.14}
+}
+
+@Book{dahpar_10,
+  Title                    = {3{G} evolution: {HSPA} and {LTE} for mobile broadband},
+  Author                   = {Dahlman, Erik and Parkvall, Stefan and Skold, Johan and Beming, Per},
+  Publisher                = {Academic press},
+  Year                     = {2010},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.02.23}
+}
+
+@InProceedings{dalste_08,
+  Title                    = {{A} {H}ardware {F}ramework for the {F}ast {G}eneration of {M}ultiple {L}ong-period {R}andom {N}umber {S}treams},
+  Author                   = {Ishaan L. Dalal and Deian Stefan},
+  Booktitle                = {Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays},
+  Year                     = {2008},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {245--254},
+  Publisher                = {ACM},
+  Series                   = {FPGA '08},
+
+  Abstract                 = {Stochastic simulations and other scientific applications that depend on random numbers are increasingly implemented in a parallelized manner in programmable logic. High-quality pseudo-random number generators (PRNG), such as the Mersenne Twister, are often based on binary linear recurrences and have extremely long periods (more than 21024. Many software implementations of such PRNGs exist, but hardware implementations are rare. We have developed an optimized, resource-efficient parallel framework for this class of random number generators that exploits the underlying algorithm as well as FPGA-specific architectural features. The framework also incorporates fast "jump-ahead" capability for these PRNGs, allowing simultaneous, independent sub-streams to be generated in parallel by partitioning one long-period pseudo-random sequence
+
+We demonstrate parallelized implementations of three types of PRNGs -- the 32-, 64- and 128-bit SIMD Mersenne Twister -- on Xilinx Virtex-II Pro FPGAs. Their area/throughput performance is impressive: for example, compared clock-for-clock with a previous FPGA implementation, a "two-parallelized" 32-bit Mersenne Twister uses 41% fewer resources. It can also scale to 350 MHz for a throughput of 22.4 Gbps, which is 5.5x faster than the older FPGA implementation and 7.1x faster than a dedicated software implementation. The quality of generated random numbers is verified with the standard statistical test batteries Diehard and TestU01. We also present two real-world application studies with multiple RNG streams: the Ziggurat method for generating normal random variables and a Monte Carlo photon-transport simulation.The availability of fast long-period random number generators with multiple streams accelerates hardware-based scientific simulations and allows them to scale to greater complexities},
+  Acmid                    = {1344707},
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generator, Mersenne Twister, FPGA},
+  Doi                      = {10.1145/1344671.1344707},
+  File                     = {dalste_08.pdf:dalste_08.pdf:PDF},
+  ISBN                     = {978-1-59593-934-0},
+  Keywords                 = {finance},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {10},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.14},
+  Url                      = {http://doi.acm.org/10.1145/1344671.1344707}
+}
+
+@Electronic{dal_10,
+  Title                    = {{GPU} {C}omputing {T}o {E}xascale and {B}eyond},
+  Author                   = {Bill Dally},
+  Language                 = {en},
+  Note                     = {last access 2014-02-07},
+  Organization             = {Nvidia Corporation},
+  Url                      = {\url{http://www.nvidia.com/content/PDF/sc_2010/theater/Dally_SC10.pdf}},
+  Year                     = {2010},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {power, scaling, HPC},
+  File                     = {dal_10.pdf:dal_10.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@InProceedings{dalsei_87,
+  Title                    = {{Deadlock-free Message Routing in Multiprocessor Interconnection Networks}},
+  Author                   = {W.J. Dally and C.L. Seitz},
+  Booktitle                = {IEEE Transactions on Computers},
+  Year                     = {1987},
+  Pages                    = {547--553},
+
+  Optvolume                = {C-36(5)},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{damgam_03,
+  Title                    = {{O}n maximum-likelihood detection and the search for the closest lattice point},
+  Author                   = {Damen, M. O. and El Gamal, H. and Caire, G.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2003},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {2389--2402},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/TIT.2003.817444}
+}
+
+@InProceedings{damgri_08,
+  Title                    = {{C}onnecting {S}ystem{C}-{AMS} models with {OSCI} {TLM} 2.0 models using temporal decoupling},
+  Author                   = {M. Damm and C. Grimm and J. Haas and A. Herrholz and W. Nebel},
+  Booktitle                = {2008 Forum on Specification, Verification and Design Languages},
+  Year                     = {2008},
+  Month                    = {Sept},
+  Pages                    = {25-30},
+
+  Doi                      = {10.1109/FDL.2008.4641416},
+  Keywords                 = {electronic engineering computing;embedded systems;simulation languages;SystemC-AMS models;OSCI TLM 2.0 models;temporal decoupling;system modelling language;embedded systems;computation models;Converters;Time domain analysis;Time varying systems;Computational modeling;Digital signal processing;Kernel;Synchronization},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-11}
+}
+
+@Article{MD_LDPC_FMM,
+  Title                    = {{A}n algorithm for the computation of the minimum distance of {LDPC} codes},
+  Author                   = {F. Daneshgaran and M. Laddomada and M. Mondin},
+  Journal                  = {European Transactions on Telecommunications},
+  Year                     = {2006},
+  Pages                    = {57 - 62},
+  Volume                   = {17},
+
+  Owner                    = {punekar},
+  Timestamp                = {2009.09.04}
+}
+
+@Article{danyeo_95,
+  Title                    = {{The iterative collapse algorithm: A novel approach for the design of long constraint length Viterbi decoders - Part I.}},
+  Author                   = {F. Daneshgaran and K. Yeo},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1995},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {1409--1418},
+  Volume                   = {43},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{dan_11,
+  Title                    = {{F}inancial {R}isk {F}orecasting},
+  Author                   = {Jon Danielsson},
+  Publisher                = {Wiley},
+  Year                     = {2011},
+  Series                   = {Wiley Finance Series},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.03.27}
+}
+
+@InProceedings{dansaw_08,
+  Title                    = {{R}econfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems},
+  Author                   = {Danilin, A. and Sawitzki, S. and Rijshouwer, E.},
+  Booktitle                = {Proc. Int. Conf. Field Programmable Logic and Applications FPL 2008},
+  Year                     = {2008},
+  Pages                    = {527--530},
+
+  Doi                      = {10.1109/FPL.2008.4630000},
+  File                     = {dansaw_08.pdf:dansaw_08.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2010.06.14}
+}
+
+@InProceedings{darcar_06,
+  Title                    = {{A bit-serial approximate min-sum LDPC decoder and FPGA implementationr}},
+  Author                   = {A. Darabiha and A.C. Carusone and F.R. Kaschischang},
+  Booktitle                = {Proceedings. 2006 IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2006},
+
+  Address                  = {Island of Kos, Greece},
+  Month                    = may,
+
+  File                     = {darcar_06.pdf:darcar_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{darcar_05,
+  Title                    = {{Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity}},
+  Author                   = {A. Darabiha and A.C. Carusone and F.R. Kschischang and S. Edward},
+  Booktitle                = {Proc. 2005 IEEE International Symposium on Circuits and Systems},
+  Year                     = {2005},
+  Month                    = may,
+  Pages                    = {5194-5197},
+
+  File                     = {darcar_05.pdf:darcar_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{darcar_07,
+  Title                    = {{A} 3.3-{Gb}ps bit-serial block-interlaced min-sum {LDPC} decoder in 0.13-$\mu$m {CMOS}},
+  Author                   = {Ahmad Darabiha and Anthony Chan Carusone and Frank R. Kschischang},
+  Booktitle                = {Custom Integrated Circuits Conference, 2007. CICC '07. IEEE},
+  Year                     = {2007},
+  Pages                    = {459--462},
+
+  Doi                      = {10.1109/CICC.2007.4405773},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.03.25},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4405773}
+}
+
+@Article{darcha_08,
+  Title                    = {{P}ower {R}eduction {T}echniques for {LDPC} {D}ecoders},
+  Author                   = {Darabiha, A. and Chan Carusone, A. and Kschischang, F. R.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2008},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {1835--1845},
+  Volume                   = {43},
+
+  Doi                      = {10.1109/JSSC.2008.925402},
+  File                     = {darcha_08.pdf:darcha_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@Article{dastok_09,
+  Title                    = {{R}azor{II}: {I}n {S}itu {E}rror {D}etection and {C}orrection for {PVT} and {SER} {T}olerance},
+  Author                   = {Das, S. and Tokunaga, C. and Pant, S. and Ma, W.-H. and Kalaiselvan, S. and Lai, K. and Bull, D. M. and Blaauw, D. T. },
+  Journal                  = {Solid-State Circuits, IEEE Journal of},
+  Year                     = {2009},
+  Number                   = {1},
+  Pages                    = {32--48},
+  Volume                   = {44},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Technology},
+  Doi                      = {10.1109/JSSC.2008.2007145},
+  File                     = {dastok_09.pdf:dastok_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{dasnar_00,
+  Title                    = {{Parallel Decoding of Turbo Codes Using Soft Output T-Algorithms}},
+  Author                   = {U. Dasgupta and K. R. Narayanan},
+  Booktitle                = {Proc. 2000-Fall Vehicular Technology Conference (VTC '00 Fall)},
+  Year                     = {2000},
+
+  Address                  = {Boston, Massachusetts, USA},
+  Month                    = sep,
+  Pages                    = {1204--1210},
+  Volume                   = {3},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{davden_07,
+  Title                    = {{A} next-generation design framework for platform-based design},
+  Author                   = {Davare, Abhijit and Densmore, Douglas and Meyerowitz, Trevor and Pinto, Alessandro and Sangiovanni-Vincentelli, Alberto and Yang, Guang and Zeng, Haibo and Zhu, Qi},
+  Booktitle                = {Conference on using hardware design and verification languages (DVCon)},
+  Year                     = {2007},
+  Volume                   = {152},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.27}
+}
+
+@PhdThesis{Phddavey99,
+  Title                    = {{Error-correction using Low-Density Parity-Check Codes}},
+  Author                   = {Davey, M.C.},
+  School                   = {University of Cambridge, England},
+  Year                     = {1999},
+  Month                    = dec,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{davmac_98,
+  Title                    = {{Low-Density Parity Check Codes over GF(q)}},
+  Author                   = {Davey, M.C. and MacKay, D.J.C.Fas},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {1998},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {165--167},
+  Volume                   = {2},
+
+  File                     = {davmac_98.pdf:davmac_98.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{davgm_18,
+  Title                    = {{GM} {W}ill {L}aunch {R}obocars {W}ithout {S}teering {W}heels {N}ext {Y}ear},
+
+  Author                   = {Davies, Alex},
+  HowPublished             = {https://www.wired.com/story/gm-cruise-self-driving-car-launch-2019/},
+  Month                    = {January},
+  Year                     = {2018},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-01}
+}
+
+@Misc{davandroid15,
+  Title                    = {{A}ndroid {A}uto: {T}he {F}irst {G}reat {I}n-{C}ar {I}nfotainment {S}ystem},
+
+  Author                   = {Alex Davies},
+  HowPublished             = {Wired, \url{http://www.wired.com/2015/05/android-auto-first-great-car-infotainment-system/}},
+  Month                    = may,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@InProceedings{davgar_03,
+  Title                    = {{S}ystem architecture and {ASIC}s for a {MIMO} 3{GPP}-{HSDPA} receiver},
+  Author                   = {Davis, L. M. and Garrett, D. C. and Woodward, G. K. and Bickerstaff, M. A. and Mullany, F. J. },
+  Booktitle                = {Proc. VTC 2003-Spring Vehicular Technology Conference The 57th IEEE Semiannual},
+  Year                     = {2003},
+  Month                    = apr,
+  Pages                    = {818--822},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/VETECS.2003.1207739},
+  File                     = {davgar_03.pdf:davgar_03.pdf:PDF},
+  Keywords                 = {MIMO, Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.15}
+}
+
+@Article{davzha_02,
+  Title                    = {{A Design Environment for High-Throughput Low-Power Dedicated Signal Processing Systems}},
+  Author                   = {Davis, W. R. and N. Zhang and K. Camera and D. Markovic and T. Smilkstein and Ammer, M. J. and E. Yeo and S. Augsburger and B. Nikolic and Brodersen, R. W.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2002},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {420--431},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{Phddawid96,
+  Title                    = {{Algorithmen und Schaltungsarchitekturen zur Maximum a Posteriori Faltungsdecodierung}},
+  Author                   = {H. Dawid},
+  School                   = {RWTH Aachen},
+  Year                     = {1996},
+
+  Address                  = {Shaker Verlag, Aachen, Germany},
+  Note                     = {In German},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{dawfet_96,
+  Title                    = {{A CMOS IC for Gb/s Viterbi Decoding: System Design and VLSI Implementation}},
+  Author                   = {H. Dawid and G. Fettweis and H. Meyr},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {1996},
+
+  Month                    = mar,
+  Number                   = {1},
+  Pages                    = {17--31},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{dawgeh_93,
+  Title                    = {{MAP Channel Decoding: Algorithm and VLSI Architecture}},
+  Author                   = {H. Dawid and G. Gehnen and H. Meyr},
+  Booktitle                = {{VLSI Signal Processing VI}},
+  Publisher                = {IEEE},
+  Year                     = {1993},
+  Pages                    = {141--149},
+
+  File                     = {dawgeh_93.pdf:dawgeh_93.pdf:PDF},
+  Opteditor                = {L. D. J. Eggermont and P. Dewilde and E. Deprettere and J. van Meerbergen},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{dawmey_95,
+  Title                    = {{Real-Time Algorithms and VLSI Architectures for Soft Output MAP Convolutional Decoding}},
+  Author                   = {H. Dawid and H. Meyr},
+  Booktitle                = {{Proc. 1995 International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC '95)}},
+  Year                     = {1995},
+
+  Address                  = {Toronto, Canada},
+  Month                    = sep,
+  Pages                    = {193--197},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{dawmey_94,
+  Title                    = {{Scalable Architectures for High Speed Channel Decoding}},
+  Author                   = {H. Dawid and H. Meyr},
+  Booktitle                = {VLSI Signal Processing VII},
+  Publisher                = {IEEE},
+  Year                     = {1994},
+  Pages                    = {226--235},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{de_caro13,
+  Title                    = {{G}litch-{F}ree {NAND}-{B}ased {D}igitally {C}ontrolled {D}elay-{L}ines},
+  Author                   = {D. {De Caro}},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2013},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {55-66},
+  Volume                   = {21},
+
+  Doi                      = {10.1109/TVLSI.2011.2181547},
+  ISSN                     = {1063-8210},
+  Keywords                 = {clocks;CMOS integrated circuits;delay lines;driver circuits;invertors;NAND circuits;glitch-free NAND;digitally controlled delay-lines;glitching problem;driving circuits;delay control-bits;CMOS technology;sizing strategy;all-digital spread-spectrum clock generator;peak-to-peak absolute output jitter;three-state inverter;size 90 nm;Delay;Switches;Logic gates;Topology;Clocks;Switching circuits;All-digital delay-locked loop (ADDLL);all-digital phase-locked loop (ADPLL);delay-line;digitally controlled oscillator (DCO);flip-flops;sense amplifier;spread-spectrum clock generator (SSCG)}
+}
+
+@Article{jonwil_05,
+  Title                    = {{I}terative tree search detection for {MIMO} wireless systems},
+  Author                   = {De Jong, Y. L C and Willink, T.J.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2005},
+  Number                   = {6},
+  Pages                    = {930-935},
+  Volume                   = {53},
+
+  Doi                      = {10.1109/TCOMM.2005.849638},
+  File                     = {jonwil_05.pdf:jonwil_05.pdf:PDF},
+  ISSN                     = {0090-6778},
+  Keywords                 = {MIMO systems;iterative decoding;quadrature amplitude modulation;radio receivers;signal detection;tree searching;turbo codes;MIMO wireless system;QAM signal;block partitionable label;complexity reduction;iterative decoding;iterative tree search detection;multiple-input multiple-output wireless communication system;radio receiver;soft-input soft-output detection scheme;transmit antenna;turbo processing;Detectors;Fading;Iterative decoding;MIMO;Object detection;Polynomials;Quadrature amplitude modulation;Receiving antennas;Turbo codes;Wireless communication;Complexity reduction;iterative detection/decoding;multiple-input multiple-output (MIMO) systems;tree searching},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.02}
+}
+
+@Misc{DeMicheli2005,
+  Title                    = {{R}eliability and {R}eliable {D}esign},
+
+  Author                   = {De Micheli, Giovanni},
+  HowPublished             = {5th International Forum on Application-Specific Multi-Processor SoC},
+  Month                    = jul,
+  Year                     = {2005},
+
+  File                     = {dereliability05.pdf:dereliability05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {scholl},
+  Timestamp                = {2015.06.11},
+  Url                      = {http://www.mpsoc-forum.org/2005/slides/De_Micheli.pdf}
+}
+
+@Misc{dereliability05,
+  Title                    = {{R}eliability and {R}eliable {D}esign},
+
+  Author                   = {De Micheli, Giovanni},
+  HowPublished             = {5th International Forum on Application-Specific Multi-Processor SoC},
+  Month                    = jul,
+  Year                     = {2005},
+
+  File                     = {dereliability05.pdf:dereliability05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Url                      = {http://www.mpsoc-forum.org/2005/slides/De_Micheli.pdf}
+}
+
+@Misc{DeMicheli2003,
+  Title                    = {{Designing Robust Systems with Uncertain Information}},
+
+  Author                   = {De Micheli, Giovanni},
+  HowPublished             = {{ASP-DAC 2003 Keynote Speech}},
+  Year                     = {2003},
+
+  File                     = {gidesigning.pdf:gidesigning.pdf:PDF;gidesigning_SLIDES.pdf:gidesigning_SLIDES.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{gidesigning,
+  Title                    = {{Designing Robust Systems with Uncertain Information}},
+
+  Author                   = {De Micheli, Giovanni},
+  HowPublished             = {{ASP-DAC 2003 Keynote Speech}},
+  Year                     = {2003},
+
+  File                     = {gidesigning.pdf:gidesigning.pdf:PDF;gidesigning_SLIDES.pdf:gidesigning_SLIDES.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{demay_03,
+  Title                    = {{I}mage feature extraction for application of biometric identification of iris - a morphological approach},
+  Author                   = {De Mira, J., Jr. and Mayer, J.},
+  Booktitle                = {Computer Graphics and Image Processing, 2003. SIBGRAPI 2003. XVI Brazilian Symposium on},
+  Year                     = {2003},
+  Month                    = {Oct},
+  Pages                    = {391-398},
+
+  Doi                      = {10.1109/SIBGRA.2003.1241035},
+  ISSN                     = {1530-1834},
+  Keywords                 = {biometrics (access control);feature extraction;image recognition;image segmentation;image sequences;mathematical morphology;biometric identification;eye image;image feature extraction;iris analysis;iris patterns;iris segmentation;morphological approach;morphological operators;Biometrics;Data mining;Educational technology;Feature extraction;Image segmentation;Iris;Laboratories;Laplace equations;Signal processing algorithms;Wavelet transforms},
+  Owner                    = {Sadri},
+  Timestamp                = {2014.07.11}
+}
+
+@Book{deschutter_14,
+  Title                    = {{B}etter {S}oftware. {F}aster!: {B}est {P}ractices in {V}irtual {P}rototyping},
+  Author                   = {De Schutter, Tom},
+  Publisher                = {Synopsys Press},
+  Year                     = {2014},
+
+  Address                  = {USA},
+
+  ISBN                     = {1617300136, 9781617300134},
+  Owner                    = {MJ},
+  Timestamp                = {2017-04-05}
+}
+
+@Electronic{dec_hp,
+  Title                    = {http://perso-etis.ensea.fr/~declercq/graphs.php},
+  Author                   = {D. Declercq},
+  Year                     = {2011},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2012.03.06}
+}
+
+@Electronic{Declercq2011,
+  Title                    = {http://perso-etis.ensea.fr/~declercq/graphs.php},
+  Author                   = {D. Declercq},
+  Year                     = {2011},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2012.03.06}
+}
+
+@Article{decfos_07,
+  Title                    = {{D}ecoding {A}lgorithms for {N}onbinary {LDPC} {C}odes {O}ver {GF}q},
+  Author                   = {Declercq, D. and Fossorier, M.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2007},
+  Number                   = {4},
+  Pages                    = {633--643},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCOMM.2007.894088},
+  File                     = {decfos_07.pdf:decfos_07.pdf:PDF},
+  Keywords                 = {non binary LDPC},
+  Owner                    = {Scholl},
+  Review                   = {Paper über nicht binären BP: Standard, FFT und EMS},
+  Timestamp                = {2012.03.02}
+}
+
+@Article{decfos_07a,
+  Title                    = {{D}ecoding {A}lgorithms for {N}onbinary {LDPC} {C}odes {O}ver {GF}},
+  Author                   = {Declercq, D. and Fossorier, M.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2007},
+  Number                   = {4},
+  Pages                    = {633--643},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCOMM.2007.894088},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4155118}
+}
+
+@InProceedings{decfos_05,
+  Title                    = {{E}xtended minsum algorithm for decoding {LDPC} codes over {GF}(q)},
+  Author                   = {Declercq, D. and Fossorier, M.},
+  Booktitle                = {Proc. International Symposium on Information Theory ISIT 2005},
+  Year                     = {2005},
+  Month                    = sep,
+  Pages                    = {464--468},
+
+  Doi                      = {10.1109/ISIT.2005.1523377},
+  File                     = {decfos_05.pdf:decfos_05.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@Article{deedia_10,
+  Title                    = {{M}oment matching approximation of {A}sian basket option prices },
+  Author                   = {Griselda Deelstra and Ibrahima Diallo and Michèle Vanmaele},
+  Journal                  = {Journal of Computational and Applied Mathematics },
+  Year                     = {2010},
+  Number                   = {4},
+  Pages                    = {1006 - 1016},
+  Volume                   = {234},
+
+  Abstract                 = {In this paper we propose some moment matching pricing methods for European-style discrete arithmetic Asian basket options in a Black &amp; Scholes framework. We generalize the approach of [M. Curran, Valuing Asian and portfolio by conditioning on the geometric mean price, Management Science 40 (1994) 1705–1711] and of [G. Deelstra, J. Liinev, M. Vanmaele, Pricing of arithmetic basket options by conditioning, Insurance: Mathematics &amp; Economics 34 (2004) 55–57] in several ways. We create a framework that allows for a whole class of conditioning random variables which are normally distributed. We moment match not only with a lognormal random variable but also with a log-extended-skew-normal random variable. We also improve the bounds of [G. Deelstra, I. Diallo, M. Vanmaele, Bounds for Asian basket options, Journal of Computational and Applied Mathematics 218 (2008) 215–228]. Numerical results are included and on the basis of our numerical tests, we explain which method we recommend depending on moneyness and time-to-maturity.},
+  Cds_grade                = {0},
+  Doi                      = {http://dx.doi.org/10.1016/j.cam.2009.03.004},
+  File                     = {deedia_10.pdf:deedia_10.pdf:PDF},
+  ISSN                     = {0377-0427},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.30},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0377042709002106}
+}
+
+@PhdThesis{Phddehon96,
+  Title                    = {{Reconfigurable Architectures for General-Purpose Computing}},
+  Author                   = {A. DeHon},
+  School                   = {Massachusetts Institue of Technology},
+  Year                     = {1996},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{delkim_10,
+  Title                    = {{E}fficient and exact sampling of simple graphs with given arbitrary degree sequence},
+  Author                   = {Del Genio, Charo I and Kim, Hyunju and Toroczkai, Zoltan and Bassler, Kevin E},
+  Journal                  = {PloS one},
+  Year                     = {2010},
+  Number                   = {4},
+  Pages                    = {e10012},
+  Volume                   = {5},
+
+  Owner                    = {Brugger},
+  Publisher                = {Public Library of Science},
+  Timestamp                = {2015.08.09}
+}
+
+@Article{delcan_01,
+  Title                    = {{H}ardware and {S}oftware {T}echniques for {C}ontrolling {DRAM} {P}ower {M}odes},
+  Author                   = {Delaluz, Victor and Kandemir, Mahmut and Vijaykrishnan, N. and Sivasubramaniam, Anand and Irwin, Mary Jane},
+  Journal                  = {IEEE Trans. Comput.},
+  Year                     = {2001},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {1154--1173},
+  Volume                   = {50},
+
+  Acmid                    = {507061},
+  Address                  = {Washington, DC, USA},
+  Doi                      = {10.1109/12.966492},
+  ISSN                     = {0018-9340},
+  Issue_date               = {November 2001},
+  Keywords                 = {Memory architecture, low power, low power compilation, software-directed energy management.},
+  Numpages                 = {20},
+  Owner                    = {MJ},
+  Publisher                = {IEEE Computer Society},
+  Timestamp                = {2016-12-13},
+  Url                      = {http://dx.doi.org/10.1109/12.966492}
+}
+
+@MastersThesis{MTdeliv12,
+  Title                    = {{C}ase {S}tudies in {A}cceleration of {H}eston’s {S}tochastic {V}olatility {F}inancial {E}ngineering {M}odel: {GPU}, {C}loud and {FPGA} {I}mplementations},
+  Author                   = {Christos Delivorias},
+  School                   = {The University of Edinburgh},
+  Year                     = {2012},
+  Month                    = aug,
+
+  File                     = {MTdeliv12.pdf:MTdeliv12.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2012.08.29},
+  Url                      = {http://www.hpcfinance.eu/sites/www.hpcfinance.eu/files/Christos_Delivorias_0.pdf}
+}
+
+@Article{del_08,
+  Title                    = {{S}ystem {RAS} implications of {DRAM} soft errors},
+  Author                   = {Dell, T. J. },
+  Journal                  = {IBM Journal of Research and Development},
+  Year                     = {2008},
+  Number                   = {3},
+  Pages                    = {307--314},
+  Volume                   = {52},
+
+  Doi                      = {10.1147/rd.523.0307},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{del_97,
+  Title                    = {{A} white paper on the benefits of chipkill-correct {ECC} for {PC} server main memory},
+  Author                   = {Dell, Timothy J.},
+  Journal                  = {IBM Microelectronics Division},
+  Year                     = {1997},
+  Volume                   = {11},
+
+  Owner                    = {kraft},
+  Timestamp                = {2017.09.12}
+}
+
+@Electronic{dem_11,
+  Title                    = {\#48{DAC} {R}eports: {F}reescale on {M}egatrends {D}riving {E}mbedded {M}ulticore {I}nnovation},
+  Author                   = {Mike Demler},
+  HowPublished             = {\url{http://www.eedailynews.com/2011/06/48dac-reports-freescale-on-megatrends_15.html}},
+  Language                 = {en},
+  Month                    = jun,
+  Note                     = {last access 2014-04-30},
+  Organization             = {EE Daily News},
+  Url                      = {\url{http://www.eedailynews.com/2011/06/48dac-reports-freescale-on-megatrends_15.html}},
+  Year                     = {2011},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {simulation speed vs. transistor count},
+  Cds_read                 = {2014-04-30},
+  Cds_review               = {Lisa Su from Freescale},
+  File                     = {dem_11.pdf:dem_11.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.04.30}
+}
+
+@Article{denrid_74,
+  Title                    = {{D}esign of ion-implanted {MOSFET}'s with very small physical dimensions},
+  Author                   = {Dennard, R.H. and Rideout, V.L. and Bassous, E. and LeBlanc, A.R.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {1974},
+  Number                   = {5},
+  Pages                    = {256--268},
+  Volume                   = {9},
+
+  Doi                      = {10.1109/JSSC.1974.1050511},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.08.26},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1050511}
+}
+
+@InProceedings{denrek_04,
+  Title                    = {{M}icroarchitecture development via metropolis successive platform refinement},
+  Author                   = {Densmore, D. and Rekhi, S. and Sangiovanni-Vincentelli, A.},
+  Booktitle                = {Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings},
+  Year                     = {2004},
+  Month                    = {Feb},
+  Pages                    = {346-351 Vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/DATE.2004.1268871},
+  ISSN                     = {1530-1591},
+  Keywords                 = {circuit simulation;integrated circuit design;memory architecture;Cypress Semiconductor;IC designs;architecture-level optimization;metropolis successive platform refinement;microarchitecture development;platform-based design;verification process;Application software;Computational modeling;Costs;Design methodology;Design optimization;Mechanical factors;Microarchitecture;Productivity;Refining;Space exploration},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.27}
+}
+
+@InProceedings{deosyl_05,
+  Title                    = {{G}ate-level mitigation techniques for neutron-induced soft error rate},
+  Author                   = {Deogun, H. S. and Sylvester, D. and Blaauw, D. },
+  Booktitle                = {Proc. Sixth Int. Symp. Quality of Electronic Design ISQED 2005},
+  Year                     = {2005},
+  Pages                    = {175--180},
+
+  Doi                      = {10.1109/ISQED.2005.61},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{derneu_12,
+  Title                    = {{A}n {E}uler-type method for the strong approximation of the {C}ox--{I}ngersoll--{R}oss process},
+  Author                   = {Dereich, Steffen and Neuenkirch, Andreas and Szpruch, Lukasz},
+  Journal                  = {Proceedings of the Royal Society A: Mathematical, Physical and Engineering Science},
+  Year                     = {2012},
+  Number                   = {2140},
+  Pages                    = {1105--1115},
+  Volume                   = {468},
+
+  Keywords                 = {finance},
+  Owner                    = {Brugger},
+  Publisher                = {The Royal Society},
+  Timestamp                = {2013.10.25}
+}
+
+@InProceedings{desdra_15,
+  Title                    = {{P}ath{F}inder: {A} {S}ignature-search {M}iniapp and {I}ts {R}untime {C}haracteristics},
+  Author                   = {Deshpande, Aditya M. and Draper, Jeffrey T. and Rigdon, J. Brian and Barrett, Richard F.},
+  Booktitle                = {Proceedings of the 5th Workshop on Irregular Applications: Architectures and Algorithms},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {9:1--9:4},
+  Publisher                = {ACM},
+  Series                   = {IA3 '15},
+
+  Acmid                    = {2833190},
+  Articleno                = {9},
+  Doi                      = {10.1145/2833179.2833190},
+  ISBN                     = {978-1-4503-4001-4},
+  Keywords                 = {HPC application, binary signature search, graph application, performance characterization},
+  Location                 = {Austin, Texas},
+  Numpages                 = {4},
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17},
+  Url                      = {http://doi.acm.org/10.1145/2833179.2833190}
+}
+
+@MastersThesis{MTdesme07,
+  Title                    = {{F}our {G}enerations of {A}sset {P}ricing {M}odels and {V}olatility {D}ynamics},
+  Author                   = {Sascha Desmettre},
+  School                   = {University of Kaiserslautern, Germany},
+  Year                     = {2007},
+  Month                    = jun,
+
+  Cds_grade                = {0},
+  File                     = {MTdesme07.pdf:MTdesme07.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.05.23}
+}
+
+@InCollection{deskor_15_unpublished,
+  Title                    = {10 {C}omputational {C}hallenges in {F}inance},
+  Author                   = {Sascha Desmettre and Ralf Korn},
+  Booktitle                = {FPGA Based Accelerators for Financial Applications},
+  Publisher                = {Springer},
+  Year                     = {2015},
+
+  Address                  = {Switzerland},
+  Chapter                  = {1},
+  Editor                   = {De Schryver, Christian},
+  Pages                    = {1-32},
+
+  Doi                      = {10.1007/978-3-319-15407-7},
+  Owner                    = {varela},
+  Timestamp                = {2015-08-21}
+}
+
+@Article{deskor_16,
+  Title                    = {{N}ested {MC}-{B}ased {R}isk {M}easurement of {C}omplex {P}ortfolios: {A}cceleration and {E}nergy {E}fficiency},
+  Author                   = {Sascha Desmettre and Ralf Korn and Javier Alejandro Varela and Norbert Wehn},
+  Journal                  = {Risks},
+  Year                     = {2016},
+  Number                   = {4},
+  Volume                   = {4},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.01.30},
+  Url                      = {http://www.mdpi.com/2227-9091/4/4/36}
+}
+
+@Book{dev_86,
+  Title                    = {{N}on-{U}niform {R}andom {V}ariate {G}eneration},
+  Author                   = {Devroye, Luc},
+  Publisher                = {Springer},
+  Year                     = {1986},
+
+  Address                  = {New York, USA},
+
+  Cds_keywords             = {random number generation},
+  Keywords                 = {finance},
+  Owner                    = {kostiuk},
+  Timestamp                = {2011.04.27}
+}
+
+@Article{dipro_02,
+  Title                    = {{Finite-Length Analysis of Low-Density Parity-Check Codes on the Binary Erasure Channel}},
+  Author                   = {C. Di and D. Proietti and I.E. Telatar and T.J. Richardson and R.L. Urbanke},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {2002},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {1570--1579},
+  Volume                   = {48},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{die_13,
+  Title                    = {{O}ptimization {A}lgorithms for {M}odel {P}redictive {C}ontrol},
+  Author                   = {Diehl, Moritz},
+  Editor                   = {Baillieul, John and Samad, Tariq},
+  Pages                    = {1--11},
+  Publisher                = {Springer London},
+  Year                     = {2013},
+
+  Address                  = {London},
+
+  Abstract                 = {This entry reviews optimization algorithms for both linear and nonlinear model predictive control (MPC). Linear MPC typically leads to specially structured convex quadratic programs (QP) that can be solved by structure exploiting active set, interior point, or gradient methods. Nonlinear MPC leads to specially structured nonlinear programs (NLP) that can be solved by sequential quadratic programming (SQP) or nonlinear interior point methods.},
+  Booktitle                = {Encyclopedia of Systems and Control},
+  Ccr_grade                = {n.a.},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1007/978-1-4471-5102-9_9-1},
+  ISBN                     = {978-1-4471-5102-9},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR},
+  Url                      = {https://doi.org/10.1007/978-1-4471-5102-9_9-1}
+}
+
+@Article{dieeng_08,
+  Title                    = {{M}ultistandard {FEC} {D}ecoders for {W}ireless {D}evices},
+  Author                   = {Dielissen, J. and Nur Engin and Sawitzki, S. and van Berkel, K.},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2008},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {284--288},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCSII.2008.918964},
+  File                     = {dieeng_08.pdf:dieeng_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InProceedings{diehek_07,
+  Title                    = {{Non-fractional parallelism in LDPC Decoder implementations}},
+  Author                   = {John Dielissen and Andries Hekstra},
+  Booktitle                = {Proc. 2007 Design, Automation and Test in Europe (DATE '07)},
+  Year                     = {2007},
+
+  Address                  = {Nice, France},
+  Month                    = apr,
+
+  File                     = {diehek_07.pdf:diehek_07.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{diehek_06,
+  Title                    = {{Low cost LDPC decoder for DVB-S2}},
+  Author                   = {J. Dielissen and Andries Hekstra and Vincent Berg},
+  Booktitle                = {Proc. 2006 Design, Automation and Test in Europe (DATE '06)},
+  Year                     = {2006},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+
+  File                     = {diehek_06.pdf:diehek_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{diehui_00,
+  Title                    = {{State Vector Reduction for Initialization of Sliding Windows MAP}},
+  Author                   = {J. Dielissen and J. Huiskens},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {387--390},
+
+  Comment                  = {MM: PII reference},
+  File                     = {diehui_00.pdf:diehui_00.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{diemee_01,
+  Title                    = {{P}ower-efficient layered turbo decoder processor},
+  Author                   = {Dielissen, J. and van Meerbergen, J. and Bekooij, M. and Harmsze, F. and Sawitzki, S. and Huiksen, J. and van der Werf, A.},
+  Booktitle                = {Proc. Conf Design, Automation and Test in Europe and Exhibition 2001},
+  Year                     = {2001},
+  Pages                    = {246--251},
+
+  Doi                      = {10.1109/DATE.2001.915033},
+  File                     = {diemee_01.pdf:diemee_01.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2010.06.15}
+}
+
+@InProceedings{dijmot_00,
+  Title                    = {{Generalised Trellis Termination}},
+  Author                   = {M. van Dijk and R. Motwani},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+
+  Optpages                 = {1--8},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{dimszi_09,
+  Title                    = {{Q}uanto option pricing in the parsimonious {H}eston model},
+  Author                   = {G. Dimitroff and A. Szimayer and A. Wagner},
+  Booktitle                = {Berichte des Fraunhofer ITWM},
+  Publisher                = {Fraunhofer ITWM},
+  Year                     = {2009},
+  Volume                   = {174},
+
+  Cds_grade                = {0},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.07},
+  Url                      = {http://www.itwm.fraunhofer.de/fileadmin/ITWM-Media/Zentral/Pdf/Berichte_ITWM/2011/bericht_174.pdf}
+}
+
+@Article{noimar_06,
+  Title                    = {{ASIP design for partially structured LDPC codes}},
+  Author                   = {Libero Dinoi and Raffaello Martini and Guido Masera and Federico Quaglio and Fabrizio Vacca},
+  Journal                  = {Electronics Letters},
+  Year                     = {2006},
+  Number                   = {18},
+  Pages                    = {1048--1049},
+  Volume                   = {42},
+
+  Keywords                 = {ASIP LDPC},
+  Mounth                   = {August},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{dioham_12,
+  Title                    = {{M}ulti-standard trellis-based {FEC} decoder},
+  Author                   = {Dion, J. and Hamon, M. and Penard, P. and Arzel, M. and Jezequel, M.},
+  Booktitle                = {Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on},
+  Year                     = {2012},
+  Month                    = {oct.},
+  Pages                    = {1 -7},
+
+  Keywords                 = {Complexity theory;Decoding;Equations;Iterative decoding;Random accessmemory;Standards;Long Term Evolution;forward error correction;iterative decoding;trelliscodes;wireless LAN;3GPP-LTE;IEEE802.11n codes;advanced forward error correctiontechnology;decoding algorithms;home automation;low-density parity-checkcodes;multistandard architectures;multistandard trellis-based FEC decoder;smartphone;trellis-based iterative algorithms;3GPP-LTE;Architecture;FECdecoding;IEEE802.11n;iterative decoding;trellis decoding;}
+}
+
+@InProceedings{diole_10,
+  Title                    = {{A}merican {O}ption {P}ricing with {R}andomized {Q}uasi-{M}onte {C}arlo {S}imulations},
+  Author                   = {Dion, M. and L'Ecuyer, P.},
+  Booktitle                = {Winter Simulation Conference (WSC), Proceedings of the 2010},
+  Year                     = {2010},
+  Month                    = dec,
+  Pages                    = {2705 -2720},
+
+  Abstract                 = {We study the pricing of American options using least-squares Monte Carlo combined with randomized quasi-Monte Carlo (RQMC), viewed as a variance reduction method. We find that RQMC reduces both the variance and the bias of the option price obtained in an out-of-sample evaluation of the retained policy, and improves the quality of the returned policy on average. Various sampling methods of the underlying stochastic processes are compared and the variance reduction is analyzed in terms of a functional ANOVA decomposition.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Monte Carlo, option pricing},
+  Doi                      = {10.1109/WSC.2010.5678966},
+  File                     = {diol'e_10.pdf:diol'e_10.pdf:PDF},
+  ISSN                     = {0891-7736},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.06.22}
+}
+
+@Article{divdol_01,
+  Title                    = {{Iterative Turbo Decoder Analysis Based on Density Evolution}},
+  Author                   = {D. Divsalar and S. Dolinar and F. Pollara},
+  Journal                  = {Selected Areas in Communications, IEEE Journal on},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {891--907},
+  Volume                   = {19},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{divdol_00,
+  Title                    = {{Low Complexity Turbo-like Codes}},
+  Author                   = {D. Divsalar and S. Dolinar and F. Pollara},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {73--80},
+
+  Optannote                = {This is actually a paper about convergency of iterative decoding. During his talk at the conference, Divsalar clarified the mismatch between title and contents: he had to provide the organizers very early with the title of his (invited) paper; then he decided to write a paper about a different topic.},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{divjon_05,
+  Title                    = {{P}rotograph based {LDPC} codes with minimum distance linearly growing with block size},
+  Author                   = {Divsalar, D. and Jones, C. and Dolinar, S. and Thorpe, J.},
+  Booktitle                = {Global Telecommunications Conference, 2005. GLOBECOM '05. IEEE},
+  Year                     = {2005},
+  Month                    = {Nov.},
+  Pages                    = {5pp.},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/GLOCOM.2005.1577834},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{divmce_98,
+  Title                    = {{On the Design of Concatenated Coding Systems With Interleavers}},
+  Author                   = {D. Divsalar and McEliece, R. J.},
+  Journal                  = {The Telecommunications and Mission Operations Progress Report 42--134},
+  Year                     = {1998},
+
+  Month                    = aug,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {1--22},
+  Volume                   = {134},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{divpol_95,
+  Title                    = {{On the Design of Turbo Codes}},
+  Author                   = {D. Divsalar and F. Pollara},
+  Journal                  = {The Telecommunications and Data Acquisition Progress Report 42--123},
+  Year                     = {1995},
+
+  Month                    = nov,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {99--121},
+  Volume                   = {123},
+
+  Optannote                = {e.g. decoder structure for three or more component codes},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{divpol_95a,
+  Title                    = {{Multiple Turbo Codes for Deep-Space Communications}},
+  Author                   = {D. Divsalar and F. Pollara},
+  Journal                  = {The Telecommunications and Data Acquisition Progress Report 42--121},
+  Year                     = {1995},
+
+  Month                    = may,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {66--77},
+  Volume                   = {121},
+
+  File                     = {divpol_95a.pdf:divpol_95a.pdf:PDF},
+  Optannote                = {e.g. three component codes},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{divpol_95b,
+  Title                    = {{Turbo Codes for Deep-Space Communications}},
+  Author                   = {D. Divsalar and F. Pollara},
+  Journal                  = {The Telecommunications and Data Acquisition Progress Report 42--120},
+  Year                     = {1995},
+
+  Month                    = feb,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {29--39},
+  Volume                   = {120},
+
+  File                     = {divpol_95b.pdf:divpol_95b.pdf:PDF},
+  Optannote                = {tailing},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{divpol_95c,
+  Title                    = {{Multiple Turbo Codes}},
+  Author                   = {D. Divsalar and F. Pollara},
+  Booktitle                = {Proc. IEEE Military Communications Conference},
+  Year                     = {1995},
+
+  Address                  = {San Diego, USA},
+  Pages                    = {279--285},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{divs.d_01,
+  Title                    = {{Iterative Turbo Decoder Analysis Based on Density Evolution}},
+  Author                   = {D. Divsalar and S.Dolinar and F. Pollara},
+  Journal                  = {IEEE Journal on Selected Areas in Communiations},
+  Year                     = {2001},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {891--907},
+  Volume                   = {19},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{dixwoo_11,
+  Title                    = {{T}he {I}mpact of {N}ew {T}echnology on {S}oft {E}rror {R}ates},
+  Author                   = {Dixit, A. and Wood, A.},
+  Booktitle                = {Proc. IEEE Int. Reliability Physics Symp. (IRPS)},
+  Year                     = {2011},
+
+  Cb_grade                 = {- gelesen 11/10/18
+- Reliability
+- soft error rates, measurement, processor, SER, SEU, MCU, cluster errors, bündelfehler, memory, technology
+- Oracle},
+  Doi                      = {10.1109/IRPS.2011.5784522},
+  File                     = {dixwoo_11.pdf:dixwoo_11.pdf:PDF},
+  Keywords                 = {Reliability, Processor, Techonology},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{dixzub_13,
+  Title                    = {{C}alibration of stochastic volatility models on a multi-core {CPU} cluster},
+  Author                   = {Dixon, Matthew and Zubair, Mohammad},
+  Booktitle                = {Proceedings of the 6th Workshop on High Performance Computational Finance},
+  Year                     = {2013},
+  Organization             = {ACM},
+  Pages                    = {6},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.12.30}
+}
+
+@InCollection{mat_12,
+  Title                    = {{M}onte {C}arlo-{B}ased {F}inancial {M}arket {V}alue-at-{R}isk {E}stimation on {GPU}s},
+  Author                   = {Matthew F. Dixon and Thomas Bradley and Jike Chong and Kurt Keutzer},
+  Booktitle                = {GPU Computing Gems},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2012},
+  Chapter                  = {25},
+  Edition                  = {Jade},
+  Editor                   = {Wen-Mei W. Hwu},
+  Pages                    = {337-353},
+  Volume                   = {2},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.23}
+}
+
+@Article{dizari_16,
+  Title                    = {{A} {H}igh-{T}hroughput {E}nergy-{E}fficient {I}mplementation of {S}uccessive {C}ancellation {D}ecoder for {P}olar {C}odes {U}sing {C}ombinational {L}ogic},
+  Author                   = {O. Dizdar and E. Arıkan},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2016},
+
+  Month                    = {March},
+  Number                   = {3},
+  Pages                    = {436-447},
+  Volume                   = {63},
+
+  Doi                      = {10.1109/TCSI.2016.2525020},
+  File                     = {dizari_16.pdf:dizari_16.pdf:PDF},
+  ISSN                     = {1549-8328},
+  Keywords                 = {application specific integrated circuits;combinational circuits;decoding;field programmable gate arrays;sequential circuits;ASIC;FPGA;combinational decoder delay;combinational logic;energy efficiency;high-throughput energy-efficient successive cancellation decoder architecture;hybrid-logic SC decoder;low clock frequency;medium block lengths;polar codes;power consumption analysis;sequential-logic decoders;synchronous architectures;Clocks;Complexity theory;Decoding;Encoding;Hardware;Power demand;Throughput;Energy efficiency;VLSI;error correcting codes;polar codes;successive cancellation decoder},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-29}
+}
+
+@InProceedings{djaelt_07,
+  Title                    = {{C}ross {L}ayer {E}rror {E}xploitation for {A}ggressive {V}oltage {S}caling},
+  Author                   = {Djahromi, Amin Khajeh and Eltawil, Ahmed M. and Kurdahi, Fadi J. and Kanj, Rouwaida},
+  Booktitle                = {Proc. 8th Int. Symp. Quality Electronic Design ISQED '07},
+  Year                     = {2007},
+  Pages                    = {192--197},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Kurdahi
+- Cross Layer, Co-design of circuit and system, Memory SPICE simulation
+ Turbo Decoder Chip used as test vehicle for the simulations},
+  Doi                      = {10.1109/ISQED.2007.53},
+  File                     = {djaelt_07.pdf:djaelt_07.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{djukuz_06,
+  Title                    = {{Relationships among classes of structured LDPC Codes and their application to data storage}},
+  Author                   = {I. Djurdjevic and A.V. Kuznetsov and E.M. Kurtas},
+  Booktitle                = {Proc. 4nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2006},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{djuxu_03,
+  Title                    = {{A} class of low-density parity-check codes constructed based on {R}eed-{S}olomon codes with two information symbols},
+  Author                   = {Djurdjevic, I. and Jun Xu and Abdel-Ghaffar, K. and Shu Lin},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2003},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {317--319},
+  Volume                   = {7},
+
+  Doi                      = {10.1109/LCOMM.2003.814716},
+  File                     = {djuxu_03.pdf:djuxu_03.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.08}
+}
+
+@Article{dobpel_05,
+  Title                    = {{P}arallel interleaver design and {VLSI} architecture for low-latency {MAP} turbo decoders},
+  Author                   = {Dobkin, R. and Peleg, M. and Ginosar, R.},
+  Journal                  = {IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS},
+  Year                     = {2005},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {427--438},
+  Volume                   = {13},
+
+  Doi                      = {10.1109/TVLSI.2004.842916},
+  File                     = {dobpel_05.pdf:dobpel_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@Misc{Dobkin2003,
+  Title                    = {{Parallel VLSI Architecture and Parallel Interleaver Design for Low-Latency MAP Turbo Decoders}},
+
+  Author                   = {R. Dobkin and M. Peleg and R. Ginosar},
+  Month                    = jul,
+  Note                     = {{{http://www-ee.technion.ac.il/\~{}ran/publications.html}}},
+  Year                     = {2003},
+
+  Booktitle                = {CCIT TR436, Electrical Engineering Dept., Technion--Israel Institute of Technology},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{dobparallel03,
+  Title                    = {{Parallel VLSI Architecture and Parallel Interleaver Design for Low-Latency MAP Turbo Decoders}},
+
+  Author                   = {R. Dobkin and M. Peleg and R. Ginosar},
+  Month                    = jul,
+  Note                     = {{{http://www-ee.technion.ac.il/\~{}ran/publications.html}}},
+  Year                     = {2003},
+
+  Booktitle                = {CCIT TR436, Electrical Engineering Dept., Technion--Israel Institute of Technology},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{dobpel_02,
+  Title                    = {{Parallel VLSI architecture for map turbo decoder}},
+  Author                   = {R. Dobkin and M. Peleg and R. Ginosar},
+  Booktitle                = {13th International Symposium on Personal, Indoor and Mobile Radio Communications 2002},
+  Year                     = {2002},
+  Pages                    = {384 -- 388},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{dodmas_03,
+  Title                    = {{B}asic mechanisms and modeling of single-event upset in digital microelectronics},
+  Author                   = {Dodd, P. E. and Massengill, L. W.},
+  Journal                  = {IEEE Transactions on Nuclear Science},
+  Year                     = {2003},
+
+  Month                    = jun,
+  Number                   = {3},
+  Pages                    = {583--602},
+  Volume                   = {50},
+
+  Doi                      = {10.1109/TNS.2003.813129},
+  File                     = {dodmas_03.pdf:dodmas_03.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Part                     = {3},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{doldiv_98,
+  Title                    = {{Code Performance as a Function of Block Size}},
+  Author                   = {{Dolinar}, S. and {Divsalar}, D. and {Pollara}, F.},
+  Journal                  = {Telecommunications and Mission Operations Progress Report},
+  Year                     = {1998},
+
+  Month                    = jan,
+  Pages                    = {1-23},
+  Volume                   = {133},
+
+  Adsnote                  = {Provided by the SAO/NASA Astrophysics Data System},
+  Adsurl                   = {http://adsabs.harvard.edu/abs/1998TMOPR.133....1D}
+}
+
+@InProceedings{dolerm_05,
+  Title                    = {{A}n {O}pen {TCP}/{IP} {C}ore for {R}econfigurable {L}ogic},
+  Author                   = {Dollas, A. and Ermis, I. and Koidis, I. and Zisis, I. and Kachris, C.},
+  Booktitle                = {Field-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on},
+  Year                     = {2005},
+  Pages                    = {297--298},
+
+  Abstract                 = {This project is aimed at developing the full TCP/IP protocol as an open-source IP core which can be freely used, as well as to develop know-how on protocol boosting for complex protocols such as TCP/IP. The problem was quite challenging, especially if we consider that just about all commercial implementations of TCP/IP do not fully implement all of the protocol specifications.},
+  Cds_grade                = {3},
+  Cds_keywords             = {FPGA, Ethernet, hardware-in-the-loop, TCP/IP},
+  Cds_read                 = {2013-07-15},
+  Cds_review               = {free, open-source TCP/IP core for FPGA implementation},
+  Doi                      = {10.1109/FCCM.2005.20},
+  File                     = {dolerm_05.pdf:dolerm_05.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2013.07.16}
+}
+
+@Article{donton_02,
+  Title                    = {{O}ptimal design and placement of pilot symbols for channel estimation},
+  Author                   = {Dong, Min and Lang Tong},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2002},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {3055-3069},
+  Volume                   = {50},
+
+  Doi                      = {10.1109/TSP.2002.805504},
+  ISSN                     = {1053-587X},
+  Keywords                 = {channel estimation;correlation methods;fading channels;mean square error methods;optimisation;probability;Cramer-Rao bound;FIR;MIMO channels;MSE;SISO channels;block-fading model;channel estimation;channel probability distribution;constant modulus symbols;correlated taps;data symbols;finite impulse response;frequency-selective random channels;i.i.d. channel taps;independent identical distributed channel taps;mean square error;multiple-input multiple-output channels;optimal pilot symbol design;optimal pilot symbol placement;orthogonal pilot sequences;quasi-periodic placement;semi-blind channel estimators;single-input single-output channels;Channel estimation;Decision feedback equalizers;Finite impulse response filter;Frequency estimation;MIMO;Mean square error methods;Multiaccess communication;OFDM;Partial transmit sequences;Probability distribution},
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-07}
+}
+
+@InProceedings{donarz_11,
+  Title                    = {{D}esign and {FPGA} implementation of stochastic turbo decoder},
+  Author                   = {Quang Trung Dong and Arzel, M. and Jego, C.},
+  Booktitle                = {New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International},
+  Year                     = {2011},
+  Month                    = {June},
+  Pages                    = {21-24},
+
+  Doi                      = {10.1109/NEWCAS.2011.5981209},
+  Keywords                 = {decoding;error correction codes;field programmable gate arrays;stochastic processes;FPGA;convolutional codes;error-correcting codes;latching problem;stochastic decoding;stochastic multiplications;stochastic turbo decoder;switching activity sensitivity;Computer architecture;Decoding;Hardware;Iterative decoding;Stochastic processes;Turbo codes},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@Article{donxu_12,
+  Title                    = {{NVS}im: {A} {C}ircuit-{L}evel {P}erformance, {E}nergy, and {A}rea {M}odel for {E}merging {N}onvolatile {M}emory},
+  Author                   = {X. Dong and C. Xu and Y. Xie and N. P. Jouppi},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2012},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {994-1007},
+  Volume                   = {31},
+
+  Doi                      = {10.1109/TCAD.2012.2185930},
+  ISSN                     = {0278-0070},
+  Keywords                 = {integrated circuit modelling;random-access storage;NVSim;circuit-level performance;energy model;area model;nonvolatile memory;spin-torque-transfer memory;phase-change random-access memory;resistive random-access memory;memory hierarchy levels;Nonvolatile memory;Arrays;Phase change random access memory;Wires;Distributed databases;Integrated circuit modeling;Analytical circuit model;MRAM;NAND Flash;nonvolatile memory;phase-change random-access memory (PCRAM);resistive random-access memory (ReRAM);spin-torque-transfer memory (STT-RAM)},
+  Timestamp                = {2018-08-29}
+}
+
+@Article{doneij_03,
+  Title                    = {{S}elf-{A}dapting {N}umerical {S}oftware for {N}ext {G}eneration {A}pplications},
+  Author                   = {Dongarra, Jack and Eijkhout, Victor},
+  Journal                  = {International Journal of High Performance Computing Applications},
+  Year                     = {2003},
+
+  Month                    = may,
+  Number                   = {2},
+  Pages                    = {125--131},
+  Volume                   = {17},
+
+  Abstract                 = {The challenge for the development of next generation software is the successful management of the complex grid environment while delivering to the scientist the full power of flexible compositions of the available algorithmic alternatives. Self-Adapting Numerical Software (SANS) systems are intended to meet this significant challenge.},
+  Cds_grade                = {0},
+  Cds_keywords             = {self-tuning},
+  File                     = {doneij_03.pdf:doneij_03.pdf:PDF},
+  Owner                    = {CDS},
+  Publisher                = {SAGE Publications},
+  Timestamp                = {2015-08-17}
+}
+
+@Article{donher_16,
+  Title                    = {{A} new metric for ranking high-performance computing systems},
+  Author                   = {Dongarra, Jack and Heroux, Michael A. and Luszczek, Piotr},
+  Journal                  = {National Science Review},
+  Year                     = {2016},
+  Number                   = {1},
+  Pages                    = {30},
+  Volume                   = {3},
+
+  Doi                      = {10.1093/nsr/nwv084},
+  Eprint                   = {/oup/backfile/content_public/journal/nsr/3/1/10.1093_nsr_nwv084/2/nwv084.pdf},
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17},
+  Url                      = { + http://dx.doi.org/10.1093/nsr/nwv084}
+}
+
+@InProceedings{Doninck2003,
+  Title                    = {{A} {DVB}-{RCS} {M}ulti-{C}hannel, {M}ulti-{F}requency {D}emodulator {B}ased on a {M}ulti-{T}asking {H}ardware-{S}oftware {A}rchitecture {U}sing a {S}ystem on {P}rogrammable {C}hip {T}echnology},
+  Author                   = {van Doninck, A and Dendoncker, M and Adriaensen, F and Delbeke, P and Rolle, A and Craey, T and Krekels, S},
+  Booktitle                = {DASIA 2003},
+  Year                     = {2003},
+  Pages                    = {60},
+  Volume                   = {532},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.03.26}
+}
+
+@Article{dor_74,
+  Title                    = {{A} decoding algorithm for binary block codes and${J}$-ary output channels ({C}orresp.)},
+  Author                   = {Dorsch, B.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1974},
+  Number                   = {3},
+  Pages                    = {391--394},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/TIT.1974.1055217},
+  File                     = {dor_74.pdf:dor_74.pdf:PDF},
+  Owner                    = {Scholl},
+  Timestamp                = {2013.02.26},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1055217}
+}
+
+@Unpublished{doshou_09,
+  Title                    = {{A} {F}ramework for {I}ntegrating {M}ultiple {R}econfigurable {C}omputing {T}ools},
+  Author                   = {Christopher Doss and Ramsey Hourani and Kenneth Williams and Alvernon Walker},
+
+  Month                    = dec,
+  Year                     = {2009},
+
+  Abstract                 = {Reconfigurable computing (RC) systems hold the promise of addressing computational needs of many application domains. Unfortunately, the application development community, including scientists and engineers, has not adopted them in a manner that merits this promise. Although members of the RC community have developed several tools and open source initiatives to ease the use of these systems in more designs, RC still has not gained wide acceptance. This paper proposes a framework, called the Hardware Development Platform (HDP), as a means of attaining this wide acceptance by allowing multiple tools to interact in the design process. The HDP is based on the content management system model, and utilizes the Eclipse IDE as a foundation. The HDP is used to integrate Ptolemy II and Fizzim for implementing finite state machines.},
+  Cds_grade                = {4},
+  Cds_keywords             = {FPGA, Reconfiguration, Reconfigurable Computing, Framework, Software Development},
+  Cds_read                 = {2009-12-11},
+  Cds_review               = {All in all a very well-written and interesting paper, showing a generally new approach in the RC domain. Even if your historical overview of general purpose computing development is rather exhaustive, it is very entertaining to read the story and to see where you link to the RC status quo and what you propose to do. After having read that section, one really agrees that we need a change in RC development in order to get these techniques widely accepted in a nearer future. You explain the CMS model in a very detailed way and show how this model can be adapted directly to the RC design flow - every level is clear for me from your description. So this part of the paper I would state is excellent.
+When it comes to the presentation of your work, I think you could elaborate a bit more detailed on effort it took to integrate these two tools into Eclipse, because that would be interesting with respect to gain support for your platform. In the conlusion, I'm missing a little bit of motivation to enhance your platform and your vision of how external contributors could contribute.
+But you've done really good work here, guys, with that paper. Thank you for the chance to review this and happy christmas to you all.},
+  File                     = {doshou_09.pdf:doshou_09.pdf:PDF},
+  Keywords                 = {Review},
+  Owner                    = {CdS},
+  Timestamp                = {2009.12.11}
+}
+
+@TechReport{doustr_13,
+  Title                    = {{E}ricsson {M}obility {R}eport},
+  Author                   = {Douglas Gilstrap, Senior Vice President and Head of Strategy (Publisher)},
+  Institution              = {Ericsson},
+  Year                     = {2013},
+  Month                    = {June},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.08.22}
+}
+
+@Article{douber_05,
+  Title                    = {{T}urbo codes with rate-m/(m+1) constituent convolutional codes},
+  Author                   = {C. Douillard AND C. Berrou},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2005},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {1630--1638},
+  Volume                   = {53},
+
+  Doi                      = {10.1109/TCOMM.2005.857165},
+  File                     = {douber_05.pdf:douber_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{drayed_07,
+  Title                    = {{ML} decoding via mixed-integer adaptive linear programming},
+  Author                   = {S. C. Draper and J. S. Yedidia and Y. Wang},
+  Booktitle                = {2007 IEEE International Symposium on Information Theory},
+  Year                     = {2007},
+  Month                    = {June},
+  Pages                    = {1656-1660},
+
+  Doi                      = {10.1109/ISIT.2007.4557459},
+  ISSN                     = {2157-8095},
+  Keywords                 = {adaptive decoding;integer programming;linear programming;maximum likelihood decoding;binary low density parity check codes;integer constraint;linear programming constraints;maximum likelihood decoder;mixed-integer adaptive linear programming decoding;optimal maximum likelihood decoding;pseudo-codeword;Iterative algorithms;Iterative decoding;Linear code;Linear programming;Maximum likelihood decoding;Parity check codes;Proposals;USA Councils}
+}
+
+@Conference{drenen_98,
+  Title                    = {{A}n architectural study of a digital signal processor for block codes},
+  Author                   = {Wolfram Drescher and Menno Mennenga and Gerhard Fettweis},
+  Booktitle                = {Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing},
+  Year                     = {1998},
+  Pages                    = {3129-3132},
+  Volume                   = {5},
+
+  Abstract                 = {This paper examines architectural issues for a domain specific digital signal processor (DS-DSP) which is capable of fast decoding of block codes. In real time systems it was not possible before to employ common processors for this task because of a lack of architectural and arithmetical support. We proposed solutions for the arithmetical problem in previous work. In this paper we focus on architectures for implementation of different block decoding algorithms on a new DS-DSP architecture. The paper also contains benchmarks for our architecture for some selected codes and compares our DS-DSP to common digital signal processors (DSP) and dedicated logic solutions.},
+  Cds_grade                = {3},
+  Cds_keywords             = {VLSI, Syndrome, BCH, Key Equation, Chien Search, Channel Code},
+  Cds_read                 = {2008-07},
+  Date-added               = {2008-07-03 16:24:08 +0200},
+  Date-modified            = {2008-07-03 16:55:32 +0200},
+  File                     = {drenen_98.pdf:drenen_98.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Article{dri_10,
+  Title                    = {{STT}-{RAM}: {T}he {C}oming {R}evolution in {M}emory},
+  Author                   = {Driskill-Smith, A},
+  Journal                  = {Future Fab Intl.},
+  Year                     = {2010},
+
+  Month                    = {November},
+  Pages                    = {26-32},
+  Volume                   = {35},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-08-16}
+}
+
+@InProceedings{drotha_18,
+  Title                    = {{A} {M}odel-{B}ased {S}afety {A}nalysis of {D}ependencies {A}cross {A}bstraction {L}ayers},
+  Author                   = {Dropmann, Christoph
+and Thaden, Eike
+and Trapp, Mario
+and Uecker, Denis
+and Amarnath, Rakshith
+and da Silva, Leandro Avila
+and Munk, Peter
+and Schweizer, Markus
+and Jung, Matthias
+and Adler, Rasmus},
+  Booktitle                = {Computer Safety, Reliability, and Security},
+  Year                     = {2018},
+
+  Address                  = {Cham},
+  Editor                   = {Gallina, Barbara
+and Skavhaug, Amund
+and Bitsch, Friedemann},
+  Pages                    = {73--87},
+  Publisher                = {Springer International Publishing},
+
+  Abstract                 = {Identifying and mitigating possible failure propagation from one safety-critical application to another through common infrastructural components is a challenging task. Examples of such dependencies across software-stack layers (e.g., between application and middleware layer) are common causes and failure propagation scenarios in which a failure of one software component propagates to another software component through shared services and/or common computational resources. To account for this, safety standards demand freedom from interference in order to control failure propagation between mixed-critical software components. Safety analysis is typically focused on one abstraction layer, while robustness tests try to find failure propagation paths across abstraction layers. To this end, this paper presents a model-based failure propagation analysis combining failure propagation within and across abstraction layers. A classification of dependencies in combination with fault trees is used to perform a model-based dependency analysis. In addition, a novel modeling technique for integrating failure propagation aspects resulting from shared services and resources is presented. The analysis was used to carry out an early safety assessment of a real-world automotive redundancy mechanism within an integrated architecture. The results show that the method improved reusability and modularity, and made it easier to estimate failure propagation issues, including possible violations of freedom from interference within an integrated system.},
+  Doi                      = {10.1007/978-3-319-99130-6_6},
+  ISBN                     = {978-3-319-99130-6},
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-02}
+}
+
+@InProceedings{dusol_03,
+  Title                    = {{VLSI} implementation of {DVB}/{RCS} turbo code},
+  Author                   = {Du, Y. and Soleymani, M. R.},
+  Booktitle                = {Proc. Canadian Conference on Electrical and Computer Engineering IEEE CCECE 2003},
+  Year                     = {2003},
+  Month                    = may,
+  Pages                    = {1581--1584},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/CCECE.2003.1226208},
+  File                     = {dusol_03.pdf:dusol_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Alles},
+  Timestamp                = {2009.10.29}
+}
+
+@Article{dua_95,
+  Title                    = {{T}he {GARCH} {O}ption {P}ricing {M}odel},
+  Author                   = {Jin-Chuan Duan},
+  Journal                  = {Mathematical Finance},
+  Year                     = {1995},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {13--32},
+  Volume                   = {5},
+
+  Abstract                 = {This article develops an option pricing model and its corresponding delta formula in the context of the generalized autoregressive conditional heteroskedastic (GARCH) asset return process. the development utilizes the locally risk-neutral valuation relationship (LRNVR). the LRNVR is shown to hold under certain combinations of preference and distribution assumptions. the GARCH option pricing model is capable of reflecting the changes in the conditional volatility of the underlying asset in a parsimonious manner. Numerical analyses suggest that the GARCH model may be able to explain some well-documented systematic biases associated with the Black-Scholes model.},
+  Cds_grade                = {0},
+  Doi                      = {10.1111/j.1467-9965.1995.tb00099.x},
+  File                     = {dua_95.pdf:dua_95.pdf:PDF},
+  ISSN                     = {1467-9965},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {John Wiley \& Sons},
+  Timestamp                = {2010.11.23}
+}
+
+@InBook{duayal_03,
+  Title                    = {{Interconnection Networks - An Engineering Approach}},
+  Author                   = {J. Duato and S. Yalamanchili and L. Ni},
+  Publisher                = {Morgan Kaufman Publishers},
+  Year                     = {2003},
+
+  Address                  = {San Francisco, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{duayal_97,
+  Title                    = {{Interconnection Networks: An Engineering Approach}},
+  Author                   = {J. Duato and S. Yalamanchili and L. Ni},
+  Publisher                = {IEEE Computer Society Press, 1997},
+  Year                     = {1997},
+
+  Address                  = {San Francisco, California, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{dub_05,
+  Title                    = {{Recognition, Mining and Synthesis Moves Computers to the Era of Tera}},
+  Author                   = {P. Dubey},
+  Journal                  = {Technology@Intel Magazine},
+  Year                     = {2005},
+
+  Month                    = feb,
+  Pages                    = {1--8},
+
+  File                     = {dub_05.pdf:dub_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.08.29}
+}
+
+@Book{dumghr_07,
+  Title                    = {{C}oding for {MIMO} {C}ommunication {S}ystems},
+  Author                   = {Tolga M. Duman and Ali Ghrayeb},
+  Publisher                = {WILEY},
+  Year                     = {2007},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.11.13}
+}
+
+@InProceedings{dumker_03,
+  Title                    = {{T}owards on-chip fault-tolerant communication},
+  Author                   = {Dumitras, T. and Kerner, S. and Marculescu, R.},
+  Booktitle                = {Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific},
+  Year                     = {2003},
+  Month                    = jan,
+  Pages                    = {225--232},
+
+  Doi                      = {10.1109/ASPDAC.2003.1195021},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@Article{dupnic_02,
+  Title                    = {{E}mbedded robustness {IP}s for transient-error-free {IC}s},
+  Author                   = {Dupont, E. and Nicolaidis, M. and Rohr, P.},
+  Journal                  = {IEEE Design Test of Computers},
+  Year                     = {2002},
+
+  Month                    = may,
+  Number                   = {3},
+  Pages                    = {54--68},
+  Volume                   = {19},
+
+  Doi                      = {10.1109/MDT.2002.1003798},
+  File                     = {dupnic_02.pdf:dupnic_02.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Electronic{hipeac_13,
+  Title                    = {{T}he {H}i{PEAC} {V}ision for {A}dvanced {C}omputing in {H}orizon 2020},
+  Author                   = {M. Duranton and D. Black-Schaffer and K. De Bosschere and J. Mabe},
+  Language                 = {en},
+  Note                     = {last access 2015-05-19},
+  Organization             = {European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)},
+  Url                      = {http://www.cs.ucy.ac.cy/courses/EPL605/Fall2014Files/HiPEAC-Roadmap-2013.pdf},
+  Year                     = {2013},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {data deluge, dark silicon, scaling, future trends},
+  Cds_read                 = {2013-08},
+  File                     = {hipeac_13.pdf:hipeac_13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-05-19}
+}
+
+@Misc{durde_15,
+  Title                    = {{H}i{PEAC} {V}ision 2015},
+
+  Author                   = {Duranton, Marc and De Bosschere, Koen and Cohen, Albert and Maebe, Jonas and Munk, Harm},
+  HowPublished             = {\url{https://www.hipeac.net/assets/public/publications/vision/hipeac-vision-2015_Dq0boL8.pdf}},
+  Month                    = jan,
+  Note                     = {last access 2015-07-14},
+  Year                     = {2015},
+
+  File                     = {durde_15.pdf:durde_15.pdf:PDF},
+  Owner                    = {Brugger},
+  Timestamp                = {2015-07-14},
+  Url                      = {https://www.hipeac.net/assets/public/publications/vision/hipeac-vision-2015_Dq0boL8.pdf}
+}
+
+@InProceedings{dutber_13,
+  Title                    = {{A} 0.9 p{J}/bit, 12.8 {GB}yte/s {W}ide{IO} memory interface in a 3{D}-{IC} {N}o{C}-based {MPS}o{C}},
+  Author                   = {Dutoit, Denis and Bernard, Christian and Cheramy, Severine and Clermidy, Fabien and Thonnart, Yvain and Vivet, Pascal and Freund, Christian and Guerin, Vincent and Guilhot, Stephane and Lecomte, Stephane and others},
+  Booktitle                = {VLSI Technology (VLSIT), 2013 Symposium on},
+  Year                     = {2013},
+  Organization             = {IEEE},
+  Pages                    = {C22--C23},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.11.29}
+}
+
+@TechReport{dutkub_13,
+  Title                    = {{T}heme 2: {P}latform {A}rchitectures and {O}perating {S}ystems},
+  Author                   = {Prabal Dutta and John D. Kubiatowicz},
+  Year                     = {2013},
+  Month                    = {October},
+  Note                     = {Read-ahead material for the TerraSwarm Annual Meeting, Berkeley, Nov. 5 \& 6, 2013},
+
+  Abstract                 = {Read-ahead material that provides an overview of
+ Theme 2: Platform Architectures and Operating
+ Systems.},
+  Cds_grade                = {0},
+  Day                      = {15},
+  Keywords                 = {CHPC},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.07},
+  Url                      = {http://terraswarm.org/pubs/143.html}
+}
+
+@PhdThesis{PhdEberli09,
+  Title                    = {{A}pplication-{S}pecific {P}rocessor for {MIMO}-{OFDM} {S}ofware-{D}efined {R}adio},
+  Author                   = {Stefan C. Eberli},
+  School                   = {ETH Zurich, Integrated Systems Laboratory},
+  Year                     = {2009},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.21}
+}
+
+@InProceedings{Ebert2012,
+  Title                    = {{T}he code-aided {FEPE} algorithm for joint frequency and phase estimation at {L}ow {SNR}},
+  Author                   = {Ebert, J. and Schlemmer, H. and Gappmair, W.},
+  Booktitle                = {6th Advanced Satellite Multimedia Systems Conference (ASMS) and 12th Signal Processing for Space Communications Workshop (SPSC), 2012},
+  Year                     = {2012},
+  Month                    = {Sept},
+  Pages                    = {350-354},
+
+  Doi                      = {10.1109/ASMS-SPSC.2012.6333099},
+  Keywords                 = {binary codes;decoding;digital communication;frequency estimation;phase estimation;telecommunication network reliability;turbo codes;FEPE module;burst mode system;carrier frequency;carrier parameter estimation;code-aided FEPE algorithm;code-aided joint recovery;digital communication;duo-binary turbo decoder;frequency estimation;low SNR;phase estimation;reliability;Binary phase shift keying;Decoding;Digital video broadcasting;Frequency estimation;Signal to noise ratio;Turbo codes;Code-aided estimation;duo-binary turbo code;frequency recovery by phase estimation},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.24}
+}
+
+@InProceedings{ebrmif_11,
+  Title                    = {{P}arallel {A}pplication {M}emory {S}cheduling},
+  Author                   = {Ebrahimi, Eiman and Miftakhutdinov, Rustam and Fallin, Chris and Lee, Chang Joo and Joao, Jos{\'e} A. and Mutlu, Onur and Patt, Yale N.},
+  Booktitle                = {Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture},
+  Year                     = {2011},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {362--373},
+  Publisher                = {ACM},
+  Series                   = {MICRO-44},
+
+  Acmid                    = {2155663},
+  Doi                      = {10.1145/2155620.2155663},
+  ISBN                     = {978-1-4503-1053-6},
+  Keywords                 = {CMP, memory controller, memory interference, multi-core, parallel applications, shared resources},
+  Location                 = {Porto Alegre, Brazil},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-02},
+  Url                      = {http://doi.acm.org/10.1145/2155620.2155663}
+}
+
+@Article{eccern_17,
+  Title                    = {{T}ackling the {B}us {T}urnaround {O}verhead in {R}eal-{T}ime {SDRAM} {C}ontrollers},
+  Author                   = {Ecco, Leonardo and Ernst, Rolf},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2017},
+
+  Month                    = {Nov},
+  Number                   = {11},
+  Pages                    = {1961-1974},
+  Volume                   = {66},
+
+  Doi                      = {10.1109/TC.2017.2714672},
+  ISSN                     = {0018-9340},
+  Keywords                 = {DRAM chips;cache storage;real-time systems;SDRAM controller;bank privatization;complex two-stage access protocol;data bus turnaround overhead;explicitly managed caching;internal level;many-core platforms;open-rowpolicy;predictability challenge;read and write operations;real-time SDRAM controllers;real-time guarantees;single data bus;synchronous dynamic random access memories;DRA chips;Decoding;Memory management;Power demand;Random access memory;Real-time systems;SDRAM;Transmission line matrix methods;Real-time and embedded systems;dynamic random access memory (DRAM);memory control and access},
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-03}
+}
+
+@InProceedings{eccern_17a,
+  Title                    = {{A}rchitecting high-speed command schedulers for open-row real-time {SDRAM} controllers},
+  Author                   = {L. Ecco and R. Ernst},
+  Booktitle                = {Design, Automation Test in Europe Conference Exhibition (DATE), 2017},
+  Year                     = {2017},
+  Month                    = {March},
+  Pages                    = {626-629},
+
+  Doi                      = {10.23919/DATE.2017.7927063},
+  Keywords                 = {DRAM chips;parallel architectures;real-time systems;hardware overhead;multistage architecture;open-row real-time SDRAM controllers;open-row real-time command scheduler;parallel architecture;Computer architecture;Hardware;Real-time systems;Registers;SDRAM;Switches;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-29}
+}
+
+@InProceedings{eccsai_15,
+  Title                    = {{R}eal-time {DRAM} throughput guarantees for latency sensitive mixed {Q}o{S} {MPS}o{C}s},
+  Author                   = {L. Ecco and S. Saidi and A. Kostrzewa and R. Ernst},
+  Booktitle                = {10th IEEE International Symposium on Industrial Embedded Systems (SIES)},
+  Year                     = {2015},
+  Month                    = {June},
+  Pages                    = {1-10},
+
+  Doi                      = {10.1109/SIES.2015.7185038},
+  ISSN                     = {2150-3109},
+  Keywords                 = {DRAM chips;quality of service;real-time systems;system-on-chip;BE requestors;GT requestors;formal timing analysis;latency reduction;latency-sensitive mixed QoS MPSoC;low-latency BE service;low-latency best-effort service;real-time DRAM throughput guarantees;real-time memory controllers;tight guarantees;traffic classes;DRAM chips;Delays;Privatization;Real-time systems;Throughput},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-29}
+}
+
+@InProceedings{ecctob_14,
+  Title                    = {{A} mixed critical memory controller using bank privatization and fixed
+ priority scheduling},
+  Author                   = {Leonardo Ecco and
+ Sebastian Tobuschat and
+ Selma Saidi and
+ Rolf Ernst},
+  Booktitle                = {{RTCSA}},
+  Year                     = {2014},
+  Pages                    = {1--10},
+  Publisher                = {{IEEE} Computer Society},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-18}
+}
+
+@Misc{eco_15,
+  Title                    = {{T}he end of {M}oore's law},
+
+  Author                   = {The Economist},
+  HowPublished             = {\url{http://www.economist.com/blogs/economist-explains/2015/04/economist-explains-17}},
+  Month                    = {April},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016.02.07}
+}
+
+@InProceedings{edrche_09,
+  Title                    = {{H}ardware-{O}ptimized {Z}iggurat {A}lgorithm for {H}igh-{S}peed {G}aussian {R}andom {N}umber {G}enerators},
+  Author                   = {Hassan Edrees and Brian Cheung and McCullen Sandora and David B. Nummey and Deian Stefan},
+  Booktitle                = {International Conference on Engineering of Reconfigurable Systems {\&} Algorithms, ERSA},
+  Year                     = {2009},
+  Month                    = jul,
+  Pages                    = {254-260},
+
+  Abstract                 = {Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the efficient generation of these random numbers using few resources and allowing for high clocking rates is an important design factor in the application performance. In this paper, we demonstrate scalable implementations of the Ziggurat algorithm, a Gaussian random number generator, which we have modified for optimal performance on the Xilinx Virtex-4 FX12 FPGA. The resource-efficient design uses a small number of slices (233) while delivering a high throughput of 240 million samples per second. A two-way parallelizable design is discussed and the estimated throughput scales almost linearly. The generation of multiple Gaussian random numbers per cycle allows for the implementation of multiple, concurrent simulations on FPGAs with minimal resource overhead.},
+  Cds_grade                = {0},
+  File                     = {edrche_09.pdf:edrche_09.pdf:PDF;author copy:http\://www.deian.net/pubs/conference/ersa2009.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.23}
+}
+
+@InProceedings{ejlal-_07,
+  Title                    = {{J}oint {C}onsideration of {F}ault-{T}olerance, {E}nergy-{E}fficiency and {P}erformance in {O}n-{C}hip {N}etworks},
+  Author                   = {Ejlali, Alireza and Al-Hashimi, Bashir M. and Rosinger, Paul and Miremadi, Seyed Ghassem},
+  Booktitle                = {Proc. 2007 Design, Automation and Test in Europe (DATE '07)},
+  Year                     = {2007},
+  Month                    = apr,
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- ??},
+  Doi                      = {10.1109/DATE.2007.364538},
+  File                     = {ejlal-_07.pdf:ejlal-_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm, may},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{elapra_06,
+  Title                    = {{T}ime redundancy based scan flip-flop reuse to reduce {SER} of combinational logic},
+  Author                   = {Elakkumanan, P. and Prasad, K. and Sridhar, R. },
+  Booktitle                = {Proc. 7th Int. Symp. Quality Electronic Design ISQED '06},
+  Year                     = {2006},
+
+  Doi                      = {10.1109/ISQED.2006.137},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{elabak_05,
+  Title                    = {{A} low power {VLSI} design paradigm for iterative decoders},
+  Author                   = {Elassal, M. and Baker, A. and Bayoumi, M. },
+  Booktitle                = {Proc. IEEE Workshop Signal Processing Systems Design and Implementation},
+  Year                     = {2005},
+  Pages                    = {272--277},
+
+  Doi                      = {10.1109/SIPS.2005.1579878},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{el-bay_02,
+  Title                    = {{A High Speed Architecture for MAP Decoder}},
+  Author                   = {M. El-Assal and M. Bayoumi},
+  Booktitle                = {Proc. 2002 Workshop on Signal Processing Systems (SiPS '02)},
+  Year                     = {2002},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = oct,
+  Pages                    = {69--74},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{elemit_01,
+  Title                    = {{Reduced-complexity decoding for low-density parity-check codes}},
+  Author                   = {E. Eleftheriou and T. Mittelholzer and A. Dholakia},
+  Journal                  = {Electronic Letters},
+  Year                     = {2001},
+
+  Month                    = jan,
+  Pages                    = {102--104},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{elgbay_03,
+  Title                    = {{Interconnect Noise Analysis and Optimization in Deep Submicron Technology}},
+  Author                   = {Elgamel, M. A. and Bayoumi, M. A.},
+  Journal                  = {Circuits and Systems Magazine, IEEE},
+  Year                     = {2003},
+  Number                   = {4},
+  Pages                    = {6--17},
+  Volume                   = {3},
+
+  File                     = {elgbay_03.pdf:elgbay_03.pdf:PDF},
+  Keywords                 = {Review},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@InProceedings{eli_55,
+  Title                    = {{C}oding for noisy channels},
+  Author                   = {Elias, Peter},
+  Booktitle                = {Proceedings of the Institute of Radio Engineers},
+  Year                     = {1955},
+  Number                   = {3},
+  Pages                    = {356--356},
+  Volume                   = {43},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.03.06}
+}
+
+@Article{eli_54,
+  Title                    = {{Error-free Coding}},
+  Author                   = {P. Elias},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {1954},
+
+  Month                    = sep,
+  Number                   = {4},
+  Pages                    = {29--39},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{el-_07,
+  Title                    = {{N}ew {A}pproaches to the {A}nalysis and {D}esign of {R}eed-{S}olomon {R}elated {C}odes},
+  Author                   = {Mostafa El-Khamy},
+  School                   = {California Institute of Technology},
+  Year                     = {2007},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2013.02.11}
+}
+
+@InProceedings{el-mce_04,
+  Title                    = {{I}terative {A}lgebraic {S}oft {D}ecision {D}ecoding of {R}eed-{S}olomon {C}odes},
+  Author                   = {El-Khamy, M. and McEliece, R.},
+  Booktitle                = {Proc. Int. Symp. Information Theory and its Applications},
+  Year                     = {2004},
+
+  Address                  = {Parma, Italy},
+  Month                    = {Mar.},
+  Pages                    = {1456-1461},
+
+  File                     = {el-mce_04.pdf:el-mce_04.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ABP},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.13}
+}
+
+@Article{el-mce_06,
+  Title                    = {{I}terative algebraic soft-decision list decoding of {R}eed-{S}olomon codes},
+  Author                   = {El-Khamy, M. and McEliece, R. J.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2006},
+  Number                   = {3},
+  Pages                    = {481--490},
+  Volume                   = {24},
+
+  Doi                      = {10.1109/JSAC.2005.862399},
+  File                     = {el-mce_06.pdf:el-mce_06.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ABP},
+  Owner                    = {Scholl},
+  Review                   = {kombiniert ABP, HDD und Koetter Vardy, gute Performance},
+  Timestamp                = {2011.06.21}
+}
+
+@Article{el-vik_09,
+  Title                    = {{P}erformance of sphere decoding of block codes},
+  Author                   = {El-Khamy, M. and Vikalo, H. and Hassibi, B. and McEliece, R. J.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2009},
+  Number                   = {10},
+  Pages                    = {2940--2950},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TCOMM.2009.10.080402},
+  File                     = {el-vik_09.pdf:el-vik_09.pdf:PDF},
+  Owner                    = {Scholl},
+  Review                   = {langes Paper zur Soft RS Decodierung},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{elldob_12,
+  Title                    = {{E}valuative and generative modes of thought during the creative process},
+  Author                   = {Ellamil, Melissa and Dobson, Charles and Beeman, Mark and Christoff, Kalina},
+  Journal                  = {Neuroimage},
+  Year                     = {2012},
+  Number                   = {2},
+  Pages                    = {1783--1794},
+  Volume                   = {59},
+
+  Owner                    = {Brugger},
+  Publisher                = {Elsevier},
+  Timestamp                = {2015.06.22}
+}
+
+@InProceedings{el-tai_16,
+  Title                    = {{A} survey on recent energy harvesting mechanisms},
+  Author                   = {A. R. El-Sayed and K. Tai and M. Biglarbegian and S. Mahmud},
+  Booktitle                = {2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)},
+  Year                     = {2016},
+  Month                    = {May},
+  Pages                    = {1-5},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7726698},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/CCECE.2016.7726698},
+  Keywords                 = {TCS},
+  Keywords_original        = {electrostatics;energy harvesting;piezoelectric transducers;cardiac implantations;civil structures;electromagnetic mechanisms;electrostatic mechanisms;health monitoring systems;human motion;large-scale vibration applications;medical devices;piezoelectric energy harvesters;portable devices;power generation;railway tracks;vehicle suspension;Electromagnetics;Electrostatics;Energy harvesting;Power generation;Transducers;Vibrations;Wireless sensor networks;Electromagnetic;Electrostatic;Energy harvesting;Piezoelectric;Transducer;Vibration},
+  Owner                    = {CCR}
+}
+
+@Article{elsgir_02,
+  Title                    = {{F}ine-grained {N}etwork {T}ime {S}ynchronization {U}sing {R}eference {B}roadcasts},
+  Author                   = {Elson, Jeremy and Girod, Lewis and Estrin, Deborah},
+  Journal                  = {SIGOPS Oper. Syst. Rev.},
+  Year                     = {2002},
+
+  Month                    = dec,
+  Number                   = {SI},
+  Pages                    = {147--163},
+  Volume                   = {36},
+
+  Acmid                    = {844143},
+  Address                  = {New York, NY, USA},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Elson:2002:FNT:844128.844143},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1145/844128.844143},
+  ISSN                     = {0163-5980},
+  Issue_date               = {Winter 2002},
+  Keywords                 = {BLE},
+  Numpages                 = {17},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Timestamp                = {2020-03-30},
+  Url                      = {http://doi.acm.org/10.1145/844128.844143}
+}
+
+@InProceedings{eltkur_06,
+  Title                    = {{S}ystem {R}edundancy; {A} {M}eans of {I}mproving {P}rocess {V}ariation {Y}ield {D}egradation in {M}emory {A}rrays},
+  Author                   = {Eltawil, A. M. and Kurdahi, F. J.},
+  Booktitle                = {Proc. International Symposium on VLSI Design, Automation and Test},
+  Year                     = {2006},
+  Month                    = apr,
+  Pages                    = {1--4},
+
+  Cb_grade                 = {- gelesen
+- Reliability
+- SPP 1500, Kurdahi
+-},
+  Doi                      = {10.1109/VDAT.2006.258144},
+  File                     = {eltkur_06.pdf:eltkur_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@TechReport{EMCSATCOM,
+  Title                    = {{SatLink Hub Family for TDM/TDMA \& SCPC Satellite Networks}},
+  Author                   = {{EMC SATCOM}},
+
+  Address                  = {http://www.emcsatcom.com/emcproducts/satlink-hubs},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.02.02}
+}
+
+@Misc{eng_17,
+  Title                    = {{V}irtual {P}latform {C}heckpointing ({S}ystem{C} {E}volution {D}ay 2017)},
+
+  Author                   = {Engblom, Jakob},
+  HowPublished             = {https://software.intel.com/en-us/blogs/2017/09/12/virtual-platform-checkpointing-systemc-evolution-day-2017},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-09}
+}
+
+@Electronic{engkos_11,
+  Title                    = {{C}alibration of the {H}eston {S}tochastic {L}ocal {V}olatility {M}odel: {A} {F}inite {V}olume {S}cheme},
+  Author                   = {Bernd Engelmann and Frank Koster and Daniel Oeltz},
+  Language                 = {en},
+  Month                    = apr,
+  Url                      = {http://www.quantsolutions.de/downloads/HestonLV.pdf},
+  Year                     = {2011},
+
+  Abstract                 = {The two most popular equity derivatives pricing models among practitioners are the local volatility model and the Heston model. While the former has the appealing property that it can be calibrated exactly to a given set of arbitrage free European vanilla option prices, the latter delivers a more realistic smile dynamics. In this article we combine both modeling approaches to the Heston stochastic local volatility model. The theoretical framework for this modeling approach was already developed in Ren et al. (2007). We focus on the numerical treatment of the model calibration which requires special care in the cases where the Feller condition is not met in the Heston model and zero volatility is attainable with positive probability. We propose a finite volume scheme to calibrate the model and demonstrate its accuracy in several numerical test cases.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Feller condition},
+  File                     = {engkos_11.pdf:engkos_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.11}
+}
+
+@InProceedings{entlop_01,
+  Title                    = {{A}utomatic insertion of fault-tolerant structures at the {RT} level},
+  Author                   = {Entrena, L. and Lopez, C. and Olias, E.},
+  Booktitle                = {Proc. Seventh International On-Line Testing Workshop},
+  Year                     = {2001},
+  Month                    = jul,
+  Pages                    = {48--50},
+
+  Doi                      = {10.1109/OLT.2001.937817},
+  File                     = {entlop_01.pdf:entlop_01.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{erfpas_94,
+  Title                    = {{Reduced Complexity Symbol Detectors with Parallel Structures for ISI Channels}},
+  Author                   = {J. Erfanian and S. Pasupathy and G. Gulak},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1994},
+
+  Month                    = feb # {--} # apr,
+  Number                   = {2/3/4},
+  Pages                    = {1661--1671},
+  Volume                   = {42},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{ernkim_03,
+  Title                    = {{Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation}},
+  Author                   = {Dan Ernst and Nam Sung Kim and Shidhartha Das and Sanjay Pant and Rajeev Rao and Toan Pham and Conrad Ziesler and David Blaauw and Todd Austin and Krisztian Flautner and Trevor Mudge},
+  Booktitle                = {Proc. 36th International Symposium on Microarchitecture},
+  Year                     = {2003},
+  Month                    = dec,
+  Pages                    = {7--18},
+
+  File                     = {ernkim_03.pdf:ernkim_03.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{erolee_05,
+  Title                    = {{S}tructured low-density parity-check code design for next generation digital video broadcast},
+  Author                   = {Eroz, M. and Lee, L.-N.},
+  Booktitle                = {Proc. IEEE Military Communications Conference MILCOM 2005},
+  Year                     = {2005},
+  Month                    = oct,
+  Pages                    = {2461--2466},
+
+  Doi                      = {10.1109/MILCOM.2005.1606037},
+  File                     = {erolee_05.pdf:erolee_05.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.08}
+}
+
+@Article{esmble_11,
+  Title                    = {{D}ark silicon and the end of multicore scaling},
+  Author                   = {Esmaeilzadeh, Hadi and Blem, Emily and St. Amant, Renee and Sankaralingam, Karthikeyan and Burger, Doug},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {2011},
+
+  Month                    = jun,
+  Number                   = {3},
+  Pages                    = {365--376},
+  Volume                   = {39},
+
+  Acmid                    = {2000108},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Cds_keywords             = {dark silicon, power, scaling},
+  Doi                      = {10.1145/2024723.2000108},
+  File                     = {esmble_11.pdf:esmble_11.pdf:PDF},
+  ISSN                     = {0163-5964},
+  Issue_date               = {June 2011},
+  Numpages                 = {12},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/2024723.2000108}
+}
+
+@InProceedings{esmble_11a,
+  Title                    = {{D}ark silicon and the end of multicore scaling},
+  Author                   = {Esmaeilzadeh, H. and Blem, E. and St.Amant, R. and Sankaralingam, K. and Burger, D.},
+  Booktitle                = {Computer Architecture (ISCA), 2011 38th Annual International Symposium on},
+  Year                     = {2011},
+  Pages                    = {365--376},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.08.18}
+}
+
+@Misc{Estevez2002,
+  Title                    = {{W}ireless display},
+
+  Author                   = {Estevez, L.W. and Moizio, F.J. and DuVal, M.A. and Bommersbach, W.M.},
+  Month                    = jun # {~12},
+  Note                     = {US Patent App. 10/167,790},
+  Year                     = {2002},
+
+  Owner                    = {scholl},
+  Publisher                = {Google Patents},
+  Timestamp                = {2015.06.11}
+}
+
+@Misc{estmoi_95,
+  Title                    = {{W}ireless display},
+
+  Author                   = {Estevez, L.W. and Moizio, F.J. and DuVal, M.A. and Bommersbach, W.M.},
+  Month                    = jun # {~12},
+  Note                     = {US Patent App. 10/167,790},
+  Year                     = {2002},
+
+  Publisher                = {Google Patents}
+}
+
+@Standard{dab_plus,
+  Title                    = {{D}igital {A}udio {B}roadcasting},
+  Author                   = {ETSI},
+  HowPublished             = {TS 102 563 V1.2.1},
+  Year                     = {2010},
+
+  Owner                    = {scholl},
+  Timestamp                = {2016.05.18}
+}
+
+@Standard{drm,
+  Title                    = {{D}igital {R}adio {M}ondiale; {S}ystem {S}pecification},
+  Author                   = {ETSI},
+  HowPublished             = {ES 201 980 V3.1.1},
+  Year                     = {2009},
+
+  Owner                    = {scholl},
+  Timestamp                = {2016.05.18}
+}
+
+@Misc{eurfactsheet17,
+  Title                    = {{F}actsheet - 10 years since the start of the crisis: back to recovery thanks to decisive {EU} action - in numbers},
+
+  Author                   = {{European Commission}},
+  HowPublished             = {Online: \url{http://europa.eu/rapid/press-release_IP-17-2401_en.htm}},
+  Month                    = {Aug.},
+  Note                     = {Last access: 10 Dec 2017},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.10}
+}
+
+@Misc{eurpress17,
+  Title                    = {{P}ress {R}elease: 10 years since the start of the crisis: back to recovery thanks to decisive {EU} action},
+
+  Author                   = {{European Commission}},
+  HowPublished             = {Online: \url{http://europa.eu/rapid/press-release_IP-17-2401_en.htm}},
+  Month                    = {Aug.},
+  Note                     = {Last access: 10 Dec 2017},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.10}
+}
+
+@Misc{ETSI,
+  Title                    = {{Digital Video Broadcasting (DVB) Second generation framing structure,channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; TM 2860r1 DVBS2-74r8}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Key                      = {dvbs2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{ETSIa,
+  Title                    = {{Digital Video Broadcasting (DVB) Second generation framing structure for broadband satellite applications; EN 302 307 V1.1.2}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Key                      = {dvbs2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{ETSIc,
+  Title                    = {{Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2), ETSI EN 302 755 V1.1.1}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-T2},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{ETSId,
+  Title                    = {{Digital Video Broadcasting (DVB); Interaction channel for satellite distribution systems; ETSI EN 301 790 V1.4.1}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-RCS},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{ETSIe,
+  Title                    = {{Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital transmission system for cable systems (DVB-C2); ETSI EN 302 769 V0.9.9}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-C2},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{ETSIf,
+  Title                    = {{Digital Video Broadcasting (DVB); Interaction channel for Digital Terrestrial Television (RCT) incorporating Multiple Access OFDM; ETSI EN 301 958 V1.1.1}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-RCT},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{eudigital,
+  Title                    = {{Digital Video Broadcasting (DVB) Second generation framing structure,channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; TM 2860r1 DVBS2-74r8}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Key                      = {dvbs2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{eudigitala,
+  Title                    = {{Digital Video Broadcasting (DVB) Second generation framing structure for broadband satellite applications; EN 302 307 V1.1.2}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Key                      = {dvbs2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{eudigitalb,
+  Title                    = {{Digital Video Broadcasting (DVB) Second generation framing structure,channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; EN 302 307 V1.1.2}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-S2},
+  Key                      = {dvbs2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{eudigitalc,
+  Title                    = {{Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2), ETSI EN 302 755 V1.1.1}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-T2},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{eudigitald,
+  Title                    = {{Digital Video Broadcasting (DVB); Interaction channel for satellite distribution systems; ETSI EN 301 790 V1.4.1}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-RCS},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{eudigitale,
+  Title                    = {{Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital transmission system for cable systems (DVB-C2); ETSI EN 302 769 V0.9.9}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-C2},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{eudigitalf,
+  Title                    = {{Digital Video Broadcasting (DVB); Interaction channel for Digital Terrestrial Television (RCT) incorporating Multiple Access OFDM; ETSI EN 301 958 V1.1.1}},
+
+  Author                   = {{European Telecommunications Standards Institude (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-RCT},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{ETSIb,
+  Title                    = {{Digital Video Broadcasting (DVB) Second generation framing structure,channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; EN 302 307 V1.1.2}},
+
+  Author                   = {{European Telecommunications Standards Institute (ETSI)}},
+  HowPublished             = {{{www.dvb.org}}},
+
+  Abstract                 = {DVB-S2},
+  Key                      = {dvbs2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{eva_95,
+  Title                    = {{A}lgebraic error detection: a new approach to concurrent error detection in arithmetic circuits},
+  Author                   = {Evans, R. A.},
+  Booktitle                = {Proc. ASP-DAC '95/CHDL '95/VLSI '95., IFIP Int. Conf. Hardware Description Languages; IFIP Int. Conf. Very Large Scale Integration. Asian and South Pacific Design Automation Conf.},
+  Year                     = {1995},
+  Pages                    = {717--722},
+
+  Doi                      = {10.1109/ASPDAC.1995.486393},
+  File                     = {eva_95.pdf:eva_95.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2011.08.04}
+}
+
+@Electronic{eve_17,
+  Title                    = {{C}inco-{P}lay: {M}emory {IS} that {C}ritical to {A}utonomous {D}riving},
+  Author                   = {Sven Evers},
+  Month                    = {November},
+  Url                      = {https://www.micron.com/about/blogs/2017/october/cinco-play-memory-is-that-critical-to-autonomous-driving},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-17}
+}
+
+@InProceedings{faccar_09,
+  Title                    = {{S}ystem-level power/performance evaluation of 3{D} stacked {DRAM}s for mobile applications},
+  Author                   = {Facchini, M. and Carlson, T. and Vignon, A. and Palkovic, M. and Catthoor, F. and Dehaene, W. and Benini, L. and Marchal, P. },
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conf. \& Exhibition},
+  Year                     = {2009},
+  Pages                    = {923--928},
+
+  Owner                    = {Weis},
+  Timestamp                = {2011.05.16}
+}
+
+@InProceedings{fackit_14,
+  Title                    = {{A} 16{G}b {R}e{RAM} with 200{MB}/s write and 1{GB}/s read in 27nm technology},
+  Author                   = {R. Fackenthal and M. Kitagawa and W. Otsuka and K. Prall and D. Mills and K. Tsutsui and J. Javanifard and K. Tedrow and T. Tsushima and Y. Shibahara and G. Hush},
+  Booktitle                = {2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)},
+  Year                     = {2014},
+  Month                    = {Feb},
+  Pages                    = {338-339},
+
+  Doi                      = {10.1109/ISSCC.2014.6757460},
+  ISSN                     = {0193-6530},
+  Keywords                 = {DRAM chips;memory architecture;pipeline processing;resistive RAM;flash memories;ReRAM design;low density array;high-density array;DDR interface;DRAM-like core architecture;pipelined data-path architecture;storage capacity 16 Gbit;bit rate 200 Mbit/s;bit rate 1 Gbit/s;size 27 nm;Computer architecture;Programming;Tiles;Microprocessors;Transistors;Sensors;Throughput},
+  Timestamp                = {2018-08-29}
+}
+
+@Book{faiker_10,
+  Title                    = {{A}lgorithmic {P}rinciples of {M}athematical {P}rogramming},
+  Author                   = {Faigle, Ulrich and Kern, Walter and Still, Georg},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {2010},
+  Volume                   = {24},
+
+  Owner                    = {helmling},
+  Timestamp                = {2014.01.17}
+}
+
+@InProceedings{falmah_10,
+  Title                    = {{D}iversity in {S}martphone {U}sage},
+  Author                   = {Falaki, Hossein and Mahajan, Ratul and Kandula, Srikanth and Lymberopoulos, Dimitrios and Govindan, Ramesh and Estrin, Deborah},
+  Booktitle                = {Proceedings of the 8th International Conference on Mobile Systems, Applications, and Services},
+  Year                     = {2010},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {179--194},
+  Publisher                = {ACM},
+  Series                   = {MobiSys '10},
+
+  Acmid                    = {1814453},
+  Doi                      = {10.1145/1814433.1814453},
+  ISBN                     = {978-1-60558-985-5},
+  Keywords                 = {smartphone usage, user behavior},
+  Location                 = {San Francisco, California, USA},
+  Numpages                 = {16},
+  Owner                    = {DMM},
+  Timestamp                = {2016-08-15},
+  Url                      = {http://doi.acm.org/10.1145/1814433.1814453}
+}
+
+@InProceedings{fan_00,
+  Title                    = {{Array Codes as Low-Density Parity-Check Codes}},
+  Author                   = {J.L. Fan},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {543--546},
+
+  File                     = {fan_00.pdf:fan_00.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{fankud_09,
+  Title                    = {{B}ridging the computation gap between programmable processors and hardwired accelerators},
+  Author                   = {Fan, K. and Kudlur, M. and Dasika, G. and Mahlke, S.},
+  Booktitle                = {Proc. IEEE 15th Int. Symp. High Performance Computer Architecture HPCA 2009},
+  Year                     = {2009},
+  Pages                    = {313--322},
+
+  Doi                      = {10.1109/HPCA.2009.4798266},
+  Owner                    = {Kienle},
+  Timestamp                = {2011.01.11}
+}
+
+@InProceedings{fancha_10,
+  Title                    = {{ESD} protection circuit schemes for {DDR}3 {DQ} drivers},
+  Author                   = {X. {Fan} and M. {Chaine}},
+  Booktitle                = {Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010},
+  Year                     = {2010},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Keywords                 = {DRAM chips;driver circuits;electrostatic discharge;failure analysis;MOSFET;ESD protection circuit schemes;DDR3 DQ drivers;high-speed interface;DQ pins;DDR3 DRAM;ESD characterization testing;pre-driver PMOSFET;pull-down NMOSFET gate oxide;special circuit design;ESD failure mechanism;power rail;Electrostatic discharge;Logic gates;Stress;Driver circuits;Electric potential;Pins;Random access memory}
+}
+
+@InProceedings{fanell_01,
+  Title                    = {{M}emory {C}ontroller {P}olicies for {DRAM} {P}ower {M}anagement},
+  Author                   = {Fan, Xiaobo and Ellis, Carla and Lebeck, Alvin},
+  Booktitle                = {Proceedings of the 2001 International Symposium on Low Power Electronics and Design},
+  Year                     = {2001},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {129--134},
+  Publisher                = {ACM},
+  Series                   = {ISLPED '01},
+
+  Acmid                    = {383118},
+  Doi                      = {10.1145/383082.383118},
+  ISBN                     = {1-58113-371-5},
+  Location                 = {Huntington Beach, California, USA},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-13},
+  Url                      = {http://doi.acm.org/10.1145/383082.383118}
+}
+
+@InProceedings{fanell_03,
+  Title                    = {{M}odeling of {DRAM} {P}ower {C}ontrol {P}olicies {U}sing {D}eterministic and {S}tochastic {P}etri {N}ets},
+  Author                   = {Fan, Xiaobo and Ellis, Carla S. and Lebeck, Alvin R.},
+  Booktitle                = {Proceedings of the 2Nd International Conference on Power-aware Computer Systems},
+  Year                     = {2003},
+
+  Address                  = {Berlin, Heidelberg},
+  Pages                    = {130--140},
+  Publisher                = {Springer-Verlag},
+  Series                   = {PACS'02},
+
+  Acmid                    = {1767003},
+  ISBN                     = {3-540-01028-9},
+  Location                 = {Cambridge, MA, USA},
+  Numpages                 = {11},
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-26},
+  Url                      = {http://dl.acm.org/citation.cfm?id=1766991.1767003}
+}
+
+@Article{fantsu_14,
+  Title                    = {{A}n {E}fficient {P}artial-{S}um {N}etwork {A}rchitecture for {S}emi-{P}arallel {P}olar {C}odes {D}ecoder {I}mplementation},
+  Author                   = {YouZhe Fan and Chi-Ying Tsui},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2014},
+
+  Month                    = {June},
+  Number                   = {12},
+  Pages                    = {3165-3179},
+  Volume                   = {62},
+
+  Doi                      = {10.1109/TSP.2014.2319773},
+  ISSN                     = {1053-587X},
+  Keywords                 = {application specific integrated circuits;decoding;field programmable gate arrays;ASIC;FPGA;SCD;area complexity;critical path delay;decoding complexity;decoding throughput;folded PSN architecture;folded decoding schedule;folded processing element architecture;partial-sum network architecture;semiparallel polar codes decoder implementation;successive cancellation decoder;Complexity theory;Computer architecture;Delays;Hardware;Maximum likelihood decoding;Signal processing;Partial sum;VLSI decoder architectures;polar codes;semi-parallel decoder;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{fanoos_09,
+  Title                    = {{A} {N}ovel {P}ricing {M}ethod for {E}uropean {O}ptions {B}ased on {F}ourier-{C}osine {S}eries {E}xpansions},
+  Author                   = {Fang, F. and Oosterlee, C.},
+  Journal                  = {SIAM Journal on Scientific Computing},
+  Year                     = {2009},
+  Number                   = {2},
+  Pages                    = {826-848},
+  Volume                   = {31},
+
+  Doi                      = {10.1137/080718061},
+  Eprint                   = { 
+ http://dx.doi.org/10.1137/080718061},
+  File                     = {fanoos_09.pdf:fanoos_09.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.18}
+}
+
+@InProceedings{fangao_05,
+  Title                    = {{A}n implementation of turbo decoder for high speed wireless packet transmission system},
+  Author                   = {Yunong Fang and Xiqi Gao},
+  Booktitle                = {Proc. IEEE International Workshop on VLSI Design and Video Technology},
+  Year                     = {2005},
+  Month                    = may,
+  Pages                    = {423--426},
+
+  Doi                      = {10.1109/IWVDVT.2005.1504640},
+  File                     = {fangao_05.pdf:fangao_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{fangou_13,
+  Title                    = {{I}ntrinsic switching variability in {H}f{O}2{RRAM}},
+  Author                   = {A. Fantini and L. Goux and R. Degraeve and D. J. Wouters and N. Raghavan and G. Kar and A. Belmonte and Y. -. Chen and B. Govoreanu and M. Jurczak},
+  Booktitle                = {2013 5th IEEE International Memory Workshop},
+  Year                     = {2013},
+  Month                    = {May},
+  Pages                    = {30-33},
+
+  Doi                      = {10.1109/IMW.2013.6582090},
+  ISSN                     = {2159-483X},
+  Keywords                 = {hafnium compounds;random-access storage;titanium compounds;trigger circuits;intrinsic switching variability;along systematic electrical characterization;RRAM elements;switching triggering voltage;wide operating current range;oxide stacks;DC condition;pulsed condition;device-to-device variability;cycle-to-cycle variability;TiN-HfO2-Hf-TiN;Resistance;Integrated circuits;Switches;Hafnium compounds;Fluctuations;Dispersion},
+  Timestamp                = {2018-08-29}
+}
+
+@InProceedings{farhem_14,
+  Title                    = {{A} scalable custom simulation machine for the {B}ayesian {C}onfidence {P}ropagation {N}eural {N}etwork model of the brain},
+  Author                   = {Farahini, N. and Hemani, A. and Lansner, A. and Clermidy, F. and Svensson, C.},
+  Booktitle                = {Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific},
+  Year                     = {2014},
+  Month                    = {Jan},
+  Pages                    = {578-585},
+
+  Doi                      = {10.1109/ASPDAC.2014.6742953},
+  Keywords                 = {DRAM chips;belief networks;biomedical electronics;brain;mainframes;medical computing;neural chips;neurophysiology;parallel machines;3D stacked DRAM memories;BCPNN model;Bayesian confidence propagation neural network model;custom designed logic chip;eBrain;general purpose supercomputers;human brain;hybrid memory cube;multichip custom digital supercomputer;scalable custom simulation machine;synaptic weights;technology node;Aggregates;Bandwidth;Brain modeling;Computational modeling;Delays;Random access memory;Three-dimensional displays},
+  Owner                    = {MJ},
+  Timestamp                = {2015.10.30}
+}
+
+@Article{farzhu_06,
+  Title                    = {{M}arkov chain {M}onte {C}arlo algorithms for {CDMA} and {MIMO} communication systems},
+  Author                   = {Farhang-Boroujeny, B. and Haidong Zhu and Zhenning Shi},
+  Journal                  = {Signal Processing, IEEE Transactions on},
+  Year                     = {2006},
+
+  Month                    = {may},
+  Number                   = {5},
+  Pages                    = { 1896 - 1909},
+  Volume                   = {54},
+
+  Doi                      = {10.1109/TSP.2006.872539},
+  File                     = {farzhu_06.pdf:farzhu_06.pdf:PDF},
+  ISSN                     = {1053-587X},
+  Keywords                 = {Bayesian methods;Communication systems;Computational modeling;Detectors;MIMO;Monte Carlo methods;Multiaccess communication;Multidimensional systems;Probability;Statistical analysis; Bayes methods; MIMO systems; Markov processes; code division multiple access; decoding; importance sampling; least mean squares methods; turbo codes; Bayesian detection methods; CDMA; MIMO communication systems; Markov chain Monte Carlo algorithms; Rao-Blackwellization technique; a posteriori probability; code-division multiple-access; importance sampling; minimum mean square error turbo detectors; multiple-input multiple-output communication; sphere decoding; statistical inference; Code-division multiple access (CDMA); Markov chain Monte Carlo; detection algorithms; multiple-input multiple-output (MIMO);},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.01.31}
+}
+
+@Article{farhen_06,
+  Title                    = {{DVB-H: Digital Broadcast Services to Handheld Devices}},
+  Author                   = {Faria, G. and Henriksson, J.A. and Stare, E. and Talmola, P.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2006},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {194--209},
+  Volume                   = {94},
+
+  Doi                      = {10.1109/JPROC.2005.861011},
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.27}
+}
+
+@Book{Fasthuber2013,
+  Title                    = {{E}nergy-{E}fficient {C}ommunication {P}rocessors: {D}esign and {I}mplementation for {E}merging {W}ireless {S}ystems},
+  Author                   = {Fasthuber, R. and Catthoor, F. and Raghavan, P. and Naessens, F.},
+  Publisher                = {Springer},
+  Year                     = {2013},
+
+  Address                  = {Netherlands},
+
+  Optnote                  = {ISBN 978-1461449911},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.02}
+}
+
+@InProceedings{fatphi_13,
+  Title                    = {{P}ricing {A}merican {O}ptions with {L}east {S}quares {M}onte {C}arlo on {GPU}s},
+  Author                   = {Massimiliano Fatica and Everett Phillips},
+  Booktitle                = {Proceedings of the 6th Workshop on High Performance Computational Finance (WHPCF '13)},
+  Year                     = {2013},
+  Publisher                = {ACM},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.04.01}
+}
+
+@Article{faugus_04,
+  Title                    = {{M}easuring {H}igh {P}erformance {C}omputing {P}roductivity},
+  Author                   = {Stuart Faulk and John Gustafson and Philip Johnson and Adam Porter and Walter Tichy and Lawrence Votta},
+  Journal                  = {Int. J. High Perform. Comput. Appl.},
+  Year                     = {2004},
+
+  Month                    = {Nov.},
+  Number                   = {4},
+  Pages                    = {459--473},
+  Volume                   = {18},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.29}
+}
+
+@Article{faybar_14,
+  Title                    = {{L}ow-{C}omplexity {S}oft-{O}utput {D}ecoding of {P}olar {C}odes},
+  Author                   = {U. U. Fayyaz and J. R. Barry},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2014},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {958-966},
+  Volume                   = {32},
+
+  Abstract                 = {The state-of-the-art soft-output decoder for polar codes is a message-passing algorithm based on belief propagation, which performs well at the cost of high processing and storage requirements. In this paper, we propose a low-complexity alternative for soft-output decoding of polar codes that offers better performance but with significantly reduced processing and storage requirements. In particular we show that the complexity of the proposed decoder is only 4% of the total complexity of the belief propagation decoder for a rate one-half polar code of dimension 4096 in the dicode channel, while achieving comparable error-rate performance. Furthermore, we show that the proposed decoder requires about 39% of the memory required by the belief propagation decoder for a block length of 32768.},
+  Doi                      = {10.1109/JSAC.2014.140515},
+  File                     = {faybar_14.pdf:faybar_14.pdf:PDF},
+  ISSN                     = {0733-8716},
+  Keywords                 = {decoding;error statistics;message passing;belief propagation decoder;dicode channel;error rate performance;low-complexity soft-output decoding;message passing algorithm;polar codes;Belief propagation;Complexity theory;Decoding;Iterative decoding;Memory management;Receivers;Polar codes;soft-output decoding;turbo equalization},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-29}
+}
+
+@PhdThesis{fel_03,
+  Title                    = {{D}ecoding {E}rror-{C}orrecting {C}odes via {L}inear {P}rogramming},
+  Author                   = {Feldman, Jon},
+  School                   = {Massachusetts Institute of Technology},
+  Year                     = {2003},
+
+  Owner                    = {scholl},
+  Timestamp                = {2012.02.10}
+}
+
+@Article{fel_05,
+  Title                    = {{U}sing linear programming to {D}ecode {B}inary linear codes},
+  Author                   = {Feldman, J.~ and Wainwright, M.~J.~ and Karger, D.~R.~},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2005},
+  Pages                    = {954-972},
+  Volume                   = {51},
+
+  Owner                    = {scholl},
+  Timestamp                = {2015.09.23}
+}
+
+@Electronic{fel_11,
+  Title                    = {{JP} {M}organ {B}uys {I}nto {FPGA} {S}upercomputing},
+  Author                   = {Michael Feldman},
+  HowPublished             = {\url{http://www.hpcwire.com/2011/07/13/jp\_morgan\_buys\_into\_fpga\_supercomputing/}},
+  Language                 = {en},
+  Month                    = jul,
+  Note                     = {last access 2015-02-09},
+  Organization             = {HPCwire},
+  Url                      = {http://www.hpcwire.com/2011/07/13/jp_morgan_buys_into_fpga_supercomputing/},
+  Year                     = {2011},
+
+  Cds_grade                = {3},
+  Cds_read                 = {2013-12-02},
+  Cds_review               = {news article about JP Morgan investing in FPGA supercomputer},
+  File                     = {fel_11.pdf:fel_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-02-13}
+}
+
+@Electronic{fel_11a,
+  Title                    = {{JP} {M}organ {B}uys {I}nto {FPGA} {S}upercomputing},
+  Author                   = {Michael Feldman},
+  Language                 = {en},
+  Month                    = jul,
+  Note                     = {last access 2015-10-19},
+  Organization             = {HPCwire},
+  Url                      = {http://www.hpcwire.com/2011/07/13/jp_morgan_buys_into_fpga_supercomputing/},
+  Year                     = {2011},
+
+  Cds_grade                = {3},
+  Cds_read                 = {2013-12-02},
+  Cds_review               = {news article about JP Morgan investing in FPGA supercomputer},
+  File                     = {fel_11.pdf:fel_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {Varela (Correction on CDS fel_11 version)},
+  Timestamp                = {2015-02-13}
+}
+
+@InProceedings{fensta_15,
+  Title                    = {{G}reen {S}imulation {D}esigns for {R}epeated {E}xperiments},
+  Author                   = {Mingbin Feng and Jeremy Staum},
+  Booktitle                = {Proceedings of the 2015 Winter Simulation Conference},
+  Year                     = {2015},
+
+  Address                  = {Piscataway, NJ, USA},
+  Pages                    = {403--413},
+  Publisher                = {IEEE Press},
+  Series                   = {WSC '15},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.10}
+}
+
+@InProceedings{feralm_16,
+  Title                    = {{S}urvey of industrial applications of embedded model predictive control},
+  Author                   = {H. J. Ferreau and S. Alm\'er and H. Peyrl and J. L. Jerez and A. Domahidi},
+  Booktitle                = {2016 European Control Conference (ECC)},
+  Year                     = {2016},
+  Month                    = {June},
+  Pages                    = {601-601},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {HETEROGENEOUS PLATFORMS; cite number in presentation [39]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/ECC.2016.7810351},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {embedded systems;industrial control;numerical analysis;optimisation;predictive control;industrial applications;embedded model predictive control;embedded controller hardware;computational resources;embedded {MPC};numerical optimization;commercial products;engineering tools;Predictive control;Electronic mail;Europe;Hardware;Reliability theory;Prediction algorithms},
+  Owner                    = {CCR}
+}
+
+@Article{fet_14,
+  Title                    = {{T}he {T}actile {I}nternet: {A}pplications and {C}hallenges},
+  Author                   = {Fettweis, G.P.},
+  Journal                  = {Vehicular Technology Magazine, IEEE},
+  Year                     = {2014},
+
+  Month                    = {March},
+  Number                   = {1},
+  Pages                    = {64-70},
+  Volume                   = {9},
+
+  Abstract                 = {Wireless communications today enables us to connect devices and people for an unprecedented exchange of multimedia and data content. The data rates of wireless communications continue to increase, mainly driven by innovation in electronics. Once the latency of communication systems becomes low enough to enable a round-trip delay from terminals through the network back to terminals of approximately 1 ms, an overlooked breakthrough?human tactile to visual feedback control?will change how humans communicate around the world. Using these controls, wireless communications can be the platform for enabling the control and direction of real and virtual objects in many situations of our life. Almost no area of the economy will be left untouched, as this new technology will change health care, mobility, education, manufacturing, smart grids, and much more. The Tactile Internet will become a driver for economic growth and innovation and will help bring a new level of sophistication to societies.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/MVT.2013.2295069},
+  File                     = {fet_14.pdf:fet_14.pdf:PDF},
+  ISSN                     = {1556-6072},
+  Keywords                 = {CHPC},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.07}
+}
+
+@Article{fet_95,
+  Title                    = {{Algebraic Survivor Memory Management Design for Viterbi Detectors}},
+  Author                   = {Fettweis, G.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {1995},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {2458--2463},
+  Volume                   = {43},
+
+  Doi                      = {10.1109/26.412720},
+  Owner                    = {vogt},
+  Timestamp                = {2007.02.28}
+}
+
+@TechReport{fetboc_14,
+  Title                    = {{T}he {T}actile {I}nternet - {ITU}-{T} {T}echnology {W}atch {R}eport},
+  Author                   = {Gerhard Fettweis and Holger Boche and Thomas Wiegand and Erich Zielinski and Hans Schotten and Peter Merz and Sandra Hirche and Andreas Festag and Walter Häffner and Michael Meyer and Eckehard Steinbach and Rolf Kraemer and Ralf Steinmetz and Frank Hofmann and Peter Eisert and Reinhard Scholl and Frank Ellinger and Erik Weiß and Ines Riedel},
+  Institution              = {ITU-T},
+  Year                     = {2014},
+  Month                    = aug,
+  Note                     = {last access 2015-01-19},
+
+  Cds_grade                = {0},
+  File                     = {fetboc_14.pdf:fetboc_14.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2015.01.19},
+  Url                      = {http://www.itu.int/dms_pub/itu-t/oth/23/01/T23010000230001PDFE.pdf}
+}
+
+@InProceedings{fetdaw_90,
+  Title                    = {{Minimized Method Viterbi Decoding: 600 Mbit/s per Chip}},
+  Author                   = {G. Fettweis and H. Dawid and H. Meyr},
+  Booktitle                = {Proc. 1990 Global Telecommunications Conference (GLOBECOM '90)},
+  Year                     = {1990},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = dec,
+  Pages                    = {1712--1716},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{fetmey_91,
+  Title                    = {{High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture}},
+  Author                   = {G. Fettweis and H. Meyr},
+  Journal                  = {IEEE Communications Magazine},
+  Year                     = {1991},
+
+  Month                    = may,
+  Pages                    = {46--55},
+  Volume                   = {29},
+
+  File                     = {fetmey_91.pdf:fetmey_91.pdf:PDF},
+  Keywords                 = {Convolutional, Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{fetmey_90,
+  Title                    = {{H}igh-{R}ate {V}iterbi {P}rocessor: {A} {S}ystolic {A}rray {S}olution},
+  Author                   = {Gerhard Fettweis and Heinrich Meyr},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {1990},
+  Number                   = {8},
+  Pages                    = {1520-1534},
+  Volume                   = {8},
+
+  Ee                       = {http://dx.doi.org/10.1109/49.62830},
+  File                     = {fetmey_90.pdf:fetmey_90.pdf:PDF}
+}
+
+@InProceedings{fetmey_90a,
+  Title                    = {{A} 100 {M}bit/s {V}iterbi decoder chip: novel architecture and its realization},
+  Author                   = {G. Fettweis and H. Meyr},
+  Booktitle                = {IEEE International Conference on Communications, Including Supercomm Technical Sessions},
+  Year                     = {1990},
+  Month                    = {Apr},
+  Pages                    = {463-467 vol.2},
+
+  Doi                      = {10.1109/ICC.1990.117124},
+  Owner                    = {kraft},
+  Timestamp                = {2017.03.16}
+}
+
+@InProceedings{fetnag_12,
+  Title                    = {{P}athways to {S}ervers of the {F}uture - {H}ighly {A}daptive {E}nergy {E}fficient {C}omputing ({HAEC})},
+  Author                   = {Gerhard Fettweis and Wolfgang Nagel and Wolfgang Lehner},
+  Booktitle                = {Proc. Design, Automation and Test in Europe, 2012 (DATE '12)},
+  Year                     = {2012},
+  Month                    = mar,
+
+  Cds_grade                = {5},
+  Cds_keywords             = {energy, server, HPC},
+  Cds_read                 = {2012-03-16},
+  Cds_review               = {new architecture approach for energy efficient servers, using optical and wireless communications
+a lot of sources for energy numbers cited},
+  File                     = {fetnag_12.pdf:fetnag_12.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.21}
+}
+
+@Conference{fetzim_08,
+  Title                    = {{ICT} {E}nergy {C}onsumption - {T}rends and {C}hallenges},
+  Author                   = {Gerhard Fettweis and Ernesto Zimmermann},
+  Booktitle                = {Proceedings of the 11th International Symposium on Wireless Personal Multimedia Communications},
+  Year                     = {2008},
+
+  Abstract                 = {Information and communications technology (ICT) systems
+are the core of today’s knowledge based society. Innovations
+in this area are adapted at tremendous speed and worldwide
+use of ICT has soared in recent years. However, this
+unprecedented growth comes at a price: ICT systems are
+meanwhile responsible for the same amount of CO2 emissions
+as global air travel. If the growth of ICT systems energy
+consumption continues at the present pace, it will endanger
+ambitious plans to reduce CO2 emissions and tackle climate
+change. Increasing the energy efficiency of ICT systems is
+thus clearly the major R&D challenge in the decades to come.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Energy, Trend},
+  Cds_read                 = {2010-08-08},
+  File                     = {fetzim_08.pdf:fetzim_08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.08.08}
+}
+
+@Article{feyfey_93,
+  Title                    = {{A}rchitectural tradeoffs for survivor sequence memory management in {V}iterbi decoders},
+  Author                   = {Feygin, G. and Feygin, G. and Gulak, P.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1993},
+  Number                   = {3},
+  Pages                    = {425--429},
+  Volume                   = {41},
+
+  Doi                      = {10.1109/26.221067},
+  Editor                   = {Gulak, P.},
+  ISSN                     = {0090-6778},
+  Keywords                 = {decoding, storage management, Viterbi decoder, architectural tradeoffs, implementational complexity, memory organization, multiprocessor realizations, one-pointer traceback method, survivor sequence memory management, traceback method, uniprocessor realisation},
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.02.22}
+}
+
+@Article{feygul_93,
+  Title                    = {{A Multiprocessor Architecture for Viterbi Decoders with Linear Speedup}},
+  Author                   = {G. Feygin and Gulak, P. G. and P. Chow},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {1993},
+  Number                   = {9},
+  Pages                    = {2907--2917},
+  Volume                   = {41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Tmonth                   = {#sep#}
+}
+
+@InProceedings{fiksal_14,
+  Title                    = {{STAC}-{A}2 on {I}ntel {A}rchitecture: {F}rom {S}calar {C}ode to {H}eterogeneous {A}pplication},
+  Author                   = {Fiksman, Evgeny and Salahuddin, Sania},
+  Booktitle                = {Proceedings of the 7th Workshop on High Performance Computational Finance},
+  Year                     = {2014},
+
+  Address                  = {Piscataway, NJ, USA},
+  Pages                    = {53--60},
+  Publisher                = {IEEE Press},
+  Series                   = {WHPCF '14},
+
+  Abstract                 = {STAC-A2™ is compute and memory intensive industry benchmark in the field of market risk analysis. The benchmark specifications were created by the Securities Technology Analysis Center (aka STAC®) and are based on inputs collected from the leading trading companies, universities, and high performance computing vendors. The specifications describe the models which represent realistic market risk analysis workloads.
+
+In this paper we discuss the development steps that lead to competitive performance of the STAC-A2 benchmark executed on systems consisting of Intel® Xeon® processor(s) and an Intel® Xeon Phi™ coprocessor. We show the importance of utilization of all parallel resources available on Intel architectures to achieve maximum performance. We demonstrate that the offload extension supported by Intel® Composer XE minimizes the efforts required to create accelerated applications by using only C/C++ language.
+
+With Intel's latest implementation of the STAC-A2 benchmark we were able to achieve a significant (800%) performance gain by using a heterogeneous approach running on two Intel Xeon E5-2699 v3 processors and a single Intel® Xeon Phi™ 7120A card, compared to earlier version running on only two Intel Xeon E5-2697 v2 processors. This implementation outperforms Nvidia's implementation based on an Intel Xeon processor based server with two NVIDIA* K20Xm cards.},
+  Acmid                    = {2688432},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/WHPCF.2014.6},
+  File                     = {fiksal_14.pdf:fiksal_14.pdf:PDF},
+  ISBN                     = {978-1-4799-7027-8},
+  Keywords                 = {finance},
+  Location                 = {New Orleans, Louisiana},
+  Numpages                 = {8},
+  Owner                    = {CDS},
+  Timestamp                = {2015-02-14},
+  Url                      = {http://dx.doi.org/10.1109/WHPCF.2014.6}
+}
+
+@InProceedings{filmey_12,
+  Title                    = {{A}n {FPGA}-{A}ccelerated {T}estbed for {H}ardware {C}omponent {D}evelopment in {MIMO} {W}ireless {C}ommunication {S}ystems},
+  Author                   = {Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, and Heinrich Meyr},
+  Booktitle                = {SAMOS XII: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation},
+  Year                     = {2012},
+  Month                    = {jul},
+
+  File                     = {filmey_12.pdf:filmey_12.pdf:PDF},
+  Keywords                 = {MIMO LDPC}
+}
+
+@TechReport{fsi_11,
+  Title                    = {{A View from the Top: Credit Risk Management Dashboard Reporting for Financial Institutions}},
+  Author                   = {{Financial Services Institute}},
+  Institution              = {PricewaterhouseCoopers LLP},
+  Year                     = {2011},
+  Month                    = {Jul},
+  Note                     = {\url{http://www.pwc.com/us/en/financial-services/publications/viewpoints/assets/viewpoint-view-from-the-top.pdf}},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@Article{finpoh_85,
+  Title                    = {{Improved Methods for Calculating Vectors of Short Length in a Lattice, Including a Complexity Analysis}},
+  Author                   = {U. Fincke and M. Pohst},
+  Journal                  = {Mathematics of Computation},
+  Year                     = {1985},
+  Pages                    = {463-471},
+  Volume                   = {44},
+
+  Owner                    = {kienle},
+  Timestamp                = {2008.02.12}
+}
+
+@Misc{finnis_17,
+  Title                    = {{N}issan's {R}ogue is its first {US} car with semi-autonomous driving},
+
+  Author                   = {Fingas, Jon},
+  HowPublished             = {https://www.engadget.com/2017/10/19/nissans-rogue-is-its-first-us-car-with-semi-autonomous-driving/},
+  Month                    = {October},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-01}
+}
+
+@Article{finwar_92,
+  Title                    = {{C}reative cognition: {T}heory, research, and applications},
+  Author                   = {Finke, Ronald A and Ward, Thomas B and Smith, Steven M},
+  Year                     = {1992},
+
+  Owner                    = {Brugger},
+  Publisher                = {MIT press Cambridge, MA},
+  Timestamp                = {2015.06.22}
+}
+
+@Article{Fitz1994,
+  Title                    = {{F}urther {R}esults in the {F}ast {E}stimation of a {S}ingle {F}requency},
+  Author                   = {Fitz, M.P.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1994},
+
+  Month                    = {Feb},
+  Number                   = {234},
+  Pages                    = {862-864},
+  Volume                   = {42},
+
+  Doi                      = {10.1109/TCOMM.1994.580190},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Autocorrelation;Equations;Frequency estimation;Frequency locked loops;Frequency shift keying;Gaussian noise;Maximum likelihood estimation;Recursive estimation;Signal processing;Signal to noise ratio},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.25}
+}
+
+@InProceedings{fit_91,
+  Title                    = {{P}lanar filtered techniques for burst mode carrier synchronization},
+  Author                   = {Fitz, M.P.},
+  Booktitle                = {Global Telecommunications Conference, 1991. GLOBECOM '91. 'Countdown to the New Millennium. Featuring a Mini-Theme on: Personal Communications Services},
+  Year                     = {1991},
+  Month                    = {Dec},
+  Pages                    = {365-369 vol.1},
+
+  Doi                      = {10.1109/GLOCOM.1991.188412},
+  Keywords                 = {filtering and prediction theory;information theory;parameter estimation;synchronisation;CRLB;Cramer-Rao lower bound;ML estimator;burst mode carrier synchronization;digital synchronizer;frequency estimation;maximum likelihood estimator;phase error;phase estimation;planar filtered carrier synchronizer;Equations;Frequency estimation;Frequency synchronization;Matched filters;Maximum likelihood estimation;Parameter estimation;Phase estimation;Pulse modulation;Pulse shaping methods;Shape},
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-07}
+}
+
+@Article{fitsto_17,
+  Title                    = {{C}ontinuous software engineering: {A} roadmap and agenda},
+  Author                   = {Brian Fitzgerald and Klaas-Jan Stol},
+  Journal                  = {Journal of Systems and Software},
+  Year                     = {2017},
+  Pages                    = {176 - 189},
+  Volume                   = {123},
+
+  Doi                      = {https://doi.org/10.1016/j.jss.2015.06.063},
+  ISSN                     = {0164-1212},
+  Keywords                 = {Continuous software engineering, Lean software development, DevOps},
+  Owner                    = {MJ},
+  Timestamp                = {2020-02-09},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0164121215001430}
+}
+
+@Book{fla_11a,
+  Title                    = {{J}ava{S}cript: {T}he {D}efinitive {G}uide},
+  Author                   = {Flanagan, D.},
+  Publisher                = {O'Reilly Media, Incorporated},
+  Year                     = {2011},
+  Series                   = {Definitive Guide Series},
+
+  ISBN                     = {9780596805524},
+  Lccn                     = {2011377767},
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-15},
+  Url                      = {https://books.google.de/books?id=4RChxt67lvwC}
+}
+
+@Article{fla_11,
+  Title                    = {{A} {U}nified {F}ramework for {L}inear-{P}rogramming {B}ased {C}ommunication {R}eceivers},
+  Author                   = {Flanagan, M. F.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2011},
+  Number                   = {12},
+  Pages                    = {3375--3387},
+  Volume                   = {59},
+
+  Doi                      = {10.1109/TCOMM.2011.100411.100417},
+  File                     = {fla_11.pdf:fla_11.pdf:PDF},
+  Keywords                 = {LPDecoding},
+  Owner                    = {Scholl},
+  Timestamp                = {2012.03.05}
+}
+
+@Misc{FlarionTechnologies,
+  Title                    = {{Vector-LDPC Core Solutions}},
+
+  Author                   = {{Flarion Technologies}},
+  HowPublished             = {{{www.flarion.com}}},
+
+  Key                      = {flarion},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{flvector-ldpc,
+  Title                    = {{Vector-LDPC Core Solutions}},
+
+  Author                   = {{Flarion Technologies}},
+  HowPublished             = {{{www.flarion.com}}},
+
+  Key                      = {flarion},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{flela_16,
+  Title                    = {{U}niting {G}radual and {A}brupt set {P}rocesses in {R}esistive {S}witching {O}xides},
+  Author                   = {Fleck, Karsten and La Torre, Camilla and Aslam, Nabeel and Hoffmann-Eifert, Susanne and B\"ottger, Ulrich and Menzel, Stephan},
+  Journal                  = {Phys. Rev. Applied},
+  Year                     = {2016},
+
+  Month                    = {Dec},
+  Pages                    = {064015},
+  Volume                   = {6},
+
+  Doi                      = {10.1103/PhysRevApplied.6.064015},
+  Issue                    = {6},
+  Numpages                 = {11},
+  Publisher                = {American Physical Society},
+  Timestamp                = {2018-08-29},
+  Url                      = {https://link.aps.org/doi/10.1103/PhysRevApplied.6.064015}
+}
+
+@Book{flegar_09,
+  Title                    = {{F}inancial {M}odelling in {P}ython},
+  Author                   = {Shayne Fletcher and Christopher Gardner},
+  Publisher                = {Wiley Publishing},
+  Year                     = {2009},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22}
+}
+
+@Article{floblu_05,
+  Title                    = {{I}mplementation and modeling of parametrizable high-speed {R}eed {S}olomon decoders on {FPGA}s},
+  Author                   = {A. Flocke and H. Blume and Noll, T. G.},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2005},
+  Pages                    = {271-276},
+  Volume                   = {3},
+
+  Abstract                 = {One of the most important error correction codes in digital signal processing is the Reed Solomon code. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrizable RS-decoder for FPGAs. By implementing resource-sharing and by using a fully pipelined multiplier/adder-unit in GF(2m) it was possible to achieve high throughput rates up to 1.3Gbit/s on a standard FPGA, while using only an attractive small amount of logical elements (LE). The implementation, written in a hardware description language (HDL), is based on an inversionless Berlekamp Algorithm (iBA), whose structure leads to a chain of identical processing elements (PE). The critical path of one PE runs only through one adder and one multiplier. A detailed description of a resource-sharing methodology for this Berlekamp Algorithm and the achievable gain are presented in this paper. The benchmarking for the design was done for different 8bit-codes against state-of-the-art FPGA-solutions and showed a gain of up to a factor of six regarding the AT-product, compared to other implementation},
+  Cds_grade                = {4},
+  Cds_read                 = {2008-07-03},
+  Date-added               = {2008-07-03 15:07:31 +0200},
+  Date-modified            = {2008-07-03 16:55:34 +0200},
+  File                     = {floblu_05.pdf:floblu_05.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10},
+  Url                      = {www.adv-radio-sci.net/3/271/2005/}
+}
+
+@PhdThesis{Floeck2010,
+  Title                    = {{A}ctivity {M}onitoring and {A}utomatic {A}larm {G}eneration in {AAL}-enabled {H}omes},
+  Author                   = {Floeck, M.},
+  Year                     = {2010},
+
+  Address                  = {Logos-Verlag, Berlin},
+
+  Owner                    = {Sebastian Wille},
+  Timestamp                = {2010.12.16}
+}
+
+@Article{flocou_16,
+  Title                    = {{Inside the Solvency 2 Black Box: Net Asset Values and Solvency Capital Requirements with a least-squares Monte-Carlo approach}},
+  Author                   = {Anthony Floryszczak and Olivier Le Courtois and Mohamed Majri},
+  Journal                  = {Insurance: Mathematics and Economics},
+  Year                     = {2016},
+  Number                   = {Supplement C},
+  Pages                    = {15--26},
+  Volume                   = {71},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.08}
+}
+
+@Book{hansch_02,
+  Title                    = {{S}tochastic {F}inance: {A}n {I}ntroduction in {D}iscrete {T}ime},
+  Author                   = {Hans Föllmer and Alexander Schied},
+  Publisher                = {Walter de Gruyter},
+  Year                     = {2002},
+
+  Address                  = {Berlin, New York},
+  Series                   = {Studies in Mathematics},
+  Volume                   = {27},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@Article{for_65,
+  Title                    = {{O}n decoding {BCH} codes},
+  Author                   = {G. Forney},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1965},
+
+  Month                    = {Oct},
+  Number                   = {4},
+  Pages                    = {549-557},
+  Volume                   = {11},
+
+  Doi                      = {10.1109/TIT.1965.1053825},
+  ISSN                     = {0018-9448},
+  Keywords                 = {BCH codes;Decoding;Algorithm design and analysis;Binary codes;Computer errors;Decoding;Equations;Error correction;Error correction codes;Galois fields;Helium;Parity check codes}
+}
+
+@Article{for_66a,
+  Title                    = {{G}eneralized minimum distance decoding},
+  Author                   = {Forney, G. , Jr.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1966},
+  Number                   = {2},
+  Pages                    = {125--131},
+  Volume                   = {12},
+
+  Doi                      = {10.1109/TIT.1966.1053873},
+  File                     = {for_66a.pdf:for_66a.pdf:PDF},
+  Keywords                 = {InfTheory},
+  Owner                    = {Scholl},
+  Review                   = {GMD Urpaper},
+  Timestamp                = {2011.07.20}
+}
+
+@InProceedings{for_00,
+  Title                    = {{Codes on Graphs: News and Views}},
+  Author                   = {Forney, Jr., G. D.},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {9--16},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{for_73,
+  Title                    = {{The Viterbi Algorithm}},
+  Author                   = {Forney, Jr., G. D.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {1973},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {268--278},
+  Volume                   = {61},
+
+  File                     = {for_73.pdf:for_73.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{for_72,
+  Title                    = {{Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference}},
+  Author                   = {Forney, Jr., G. D.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1972},
+
+  Month                    = may,
+  Pages                    = {363--378},
+  Volume                   = {18},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{for_66,
+  Title                    = {{C}oncatenated {C}odes},
+  Author                   = {Forney, Jr., G. D.},
+  Publisher                = {MIT Press},
+  Year                     = {1966},
+
+  Address                  = {Cambridge, Massachusetts},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.02.04}
+}
+
+@Article{fos_96,
+  Title                    = {{L}ayered space-time architecture for wireless communication in a fading environment when using multi-element antennas},
+  Author                   = {Foschini, Gerard J.},
+  Journal                  = {Bell Labs Technical Journal},
+  Year                     = {1996},
+  Number                   = {2},
+  Pages                    = {41--59},
+  Volume                   = {1},
+
+  Doi                      = {10.1002/bltj.2015},
+  ISSN                     = {1538-7305},
+  Owner                    = {Gimmler},
+  Publisher                = {Wiley Subscription Services, Inc., A Wiley Company},
+  Timestamp                = {2012.11.06},
+  Url                      = {http://dx.doi.org/10.1002/bltj.2015}
+}
+
+@Article{fosgol_99,
+  Title                    = {{S}implified processing for high spectral efficiency wireless communication employing multi-element arrays},
+  Author                   = {Foschini, G. J. and Golden, G. D. and Valenzuela, R. A. and Wolniansky, P. W.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {1999},
+  Number                   = {11},
+  Pages                    = {1841--1852},
+  Volume                   = {17},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.06}
+}
+
+@Article{fos_04,
+  Title                    = {{Quasicyclic low-density parity-check codes from circulant permutation matrices}},
+  Author                   = {M. Fossorier},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2004},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {1788--1793},
+  Volume                   = {50},
+
+  File                     = {fos_04.pdf:fos_04.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{fos_01,
+  Title                    = {{Iterative Reliability-based Decoding of Low-Density Parity Check Codes}},
+  Author                   = {M. Fossorier},
+  Journal                  = {IEEE Journal on selected Areas in Communications},
+  Year                     = {2001},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {908--917},
+  Volume                   = {19},
+
+  File                     = {fos_01.pdf:fos_01.pdf:PDF},
+  Keywords                 = {OSD, LDPC, BCH},
+  Owner                    = {Gimmler},
+  Review                   = {OSD für LDPC Codes},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Fossorier1998,
+  Title                    = {{R}eliability-based information set decoding of binary linear codes},
+  Author                   = {Fossorier, M. and Shu Lin},
+  Booktitle                = {Proc. 1998 IEEE International Symposium on Information Theory},
+  Year                     = {1998},
+
+  Doi                      = {10.1109/ISIT.1998.708833},
+  File                     = {foslin_98a.pdf:foslin_98a.pdf:PDF},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.06.30}
+}
+
+@Article{fosval_04,
+  Title                    = {{R}eliability-based decoding of {R}eed-{S}olomon codes using their binary image},
+  Author                   = {Fossorier, M. and Valembois, A.},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2004},
+  Number                   = {7},
+  Pages                    = {452--454},
+  Volume                   = {8},
+
+  Doi                      = {10.1109/LCOMM.2004.832754},
+  File                     = {fosval_04.pdf:fosval_04.pdf:PDF},
+  Keywords                 = {OSD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {analytische Performanceanalyse für OSD für Reed-Solomon Codes bei hohem SNR / sehr kleinem FER},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{fosmih_99,
+  Title                    = {{Reduced Complexity Iterative Decoding of Low-Density Parity Check Codes Based on Belief Propagation}},
+  Author                   = {Fossorier, M. C. P. and M. Mihaljevic and H. Imai},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1999},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {673--680},
+  Volume                   = {47},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{fosbur_98,
+  Title                    = {{On the Equivalence Between SOVA and Max-Log-MAP Decodings}},
+  Author                   = {Fossorier, M. P. C. and F. Burkert and S. Lin and J. Hagenauer},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {1998},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {137--139},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{foslin_98,
+  Title                    = {{S}oft-input soft-output decoding of linear block codes based on ordered statistics},
+  Author                   = {Fossorier, M. P. C. and Shu Lin},
+  Booktitle                = {Proc. Bridge to Global Integration. IEEE Global Telecommunications Conf. GLOBECOM 98},
+  Year                     = {1998},
+  Pages                    = {2828--2833},
+  Volume                   = {5},
+
+  Doi                      = {10.1109/GLOCOM.1998.776584},
+  File                     = {foslin_98.pdf:foslin_98.pdf:PDF},
+  Keywords                 = {OSD},
+  Owner                    = {Scholl},
+  Review                   = {SISO Version vom OSD},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{foslin_96,
+  Title                    = {{C}omputationally efficient soft-decision decoding of linear block codes based on ordered statistics},
+  Author                   = {Fossorier, M. P. C. and Shu Lin},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1996},
+  Number                   = {3},
+  Pages                    = {738--750},
+  Volume                   = {42},
+
+  Doi                      = {10.1109/18.490541},
+  File                     = {foslin_96.pdf:foslin_96.pdf:PDF},
+  Keywords                 = {OSD},
+  Owner                    = {Scholl},
+  Review                   = {Low Complexity Version vom OSD (spart u.a. viele Testpatterns)},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{foslin_95,
+  Title                    = {{S}oft-decision decoding of linear block codes based on ordered statistics},
+  Author                   = {Fossorier, M. P. C. and Shu Lin},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1995},
+  Number                   = {5},
+  Pages                    = {1379--1396},
+  Volume                   = {41},
+
+  Doi                      = {10.1109/18.412683},
+  File                     = {foslin_95.pdf:foslin_95.pdf:PDF},
+  Keywords                 = {InfTheory, Soft, OSD},
+  Owner                    = {Scholl},
+  Review                   = {first paper ordered statistics},
+  Timestamp                = {2011.04.27}
+}
+
+@Electronic{fou_17,
+  Title                    = {{T}he {P}ython {T}utorial},
+  Author                   = {Python Software Foundation},
+  Month                    = {Aug.},
+  Url                      = {https://docs.python.org/3/tutorial/},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22}
+}
+
+@Article{fouhan_07,
+  Title                    = {{MPFR}: {A} multiple-precision binary floating-point library with correct rounding},
+  Author                   = {Fousse, Laurent and Hanrot, Guillaume and Lef{\`e}vre, Vincent and P{\'e}lissier, Patrick and Zimmermann, Paul},
+  Journal                  = {ACM Transactions on Mathematical Software (TOMS)},
+  Year                     = {2007},
+  Number                   = {2},
+  Pages                    = {13},
+  Volume                   = {33},
+
+  Owner                    = {Brugger},
+  Publisher                = {ACM},
+  Timestamp                = {2015.07.04}
+}
+
+@InProceedings{fowbro_12,
+  Title                    = {{A} {P}erformance and {E}nergy {C}omparison of {FPGA}s, {GPU}s, and {M}ulticores for {S}liding-window {A}pplications},
+  Author                   = {Fowers, Jeremy and Brown, Greg and Cooke, Patrick and Stitt, Greg},
+  Booktitle                = {Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
+  Year                     = {2012},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {47--56},
+  Publisher                = {ACM},
+  Series                   = {FPGA '12},
+
+  Acmid                    = {2145704},
+  Doi                      = {10.1145/2145694.2145704},
+  ISBN                     = {978-1-4503-1155-7},
+  Keywords                 = {FPGA, GPU, multicore, parallelism, sliding window, speedup},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {10},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01},
+  Url                      = {http://doi.acm.org/10.1145/2145694.2145704}
+}
+
+@InProceedings{fowovt_14,
+  Title                    = {{A} {H}igh {M}emory {B}andwidth {FPGA} {A}ccelerator for {S}parse {M}atrix-{V}ector {M}ultiplication},
+  Author                   = {J. Fowers and K. Ovtcharov and K. Strauss and E. S. Chung and G. Stitt},
+  Booktitle                = {2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines},
+  Year                     = {2014},
+  Month                    = {May},
+  Pages                    = {36-43},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [32]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/FCCM.2014.23},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {field programmable gate arrays;graphics processing units;sparse matrices;vectors;high memory bandwidth {FPGA} accelerator;sparse matrix-vector multiplication;irregular memory access characteristics;{FPGA}-optimized SMVM architecture;sparse matrix encoding;hardware complexity;onchip memory usage;{GPU} SVMV performance;Vectors;Encoding;Field programmable gate arrays;Abstracts;Sparse matrices;Computer architecture;Decoding;sparse matrix vector multiplication;{FPGA};accelerator;SPMV;SMVM;reconfigurable computing;HPC},
+  Owner                    = {CCR}
+}
+
+@Article{fraand_98,
+  Title                    = {{Concatenated Decoding with a Reduced-Search BCJR Algorithm}},
+  Author                   = {V. Franz and J. B. Anderson},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {1998},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {186--195},
+  Volume                   = {16},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{frafat_06,
+  Title                    = {{D}efining 4{G} technology from the users perspective},
+  Author                   = {S. Frattasi and H. Fathi and F. H. P. Fitzek and R. Prasad and M. D. Katz},
+  Journal                  = {IEEE Network},
+  Year                     = {2006},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {35-41},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/MNET.2006.1580917},
+  ISSN                     = {0890-8044},
+  Keywords                 = {4G mobile communication;broadband networks;4G technology;mobile broadband technologies;user-centric methodology;wireless mobile communication systems;4G mobile communication;Communication industry;Communications technology;Consumer electronics;Electronics industry;Industrial electronics;Investments;Isolation technology;Wireless application protocol;Wireless communication},
+  Owner                    = {StW},
+  Timestamp                = {2017.02.21}
+}
+
+@Misc{FSFlastaccessApr.2012,
+  Title                    = {{GLPK} - {GNU} {L}inear {P}rogramming {K}it},
+
+  Author                   = {{Free Software Foundation Inc.}},
+  HowPublished             = {\url{http://www.gnu.org/software/glpk/}},
+  Year                     = {last access Apr. 2012},
+
+  Owner                    = {kienle},
+  Timestamp                = {2012.11.14}
+}
+
+@Misc{glpk,
+  Title                    = {{GLPK} - {GNU} {L}inear {P}rogramming {K}it},
+
+  Author                   = {{Free Software Foundation Inc.}},
+  HowPublished             = {\url{http://www.gnu.org/software/glpk/}},
+  Year                     = {last access Apr. 2012},
+
+  Owner                    = {kienle},
+  Timestamp                = {2012.11.14}
+}
+
+@Misc{frgsl11,
+  Title                    = {{GSL} - {GNU} {S}cientific {L}ibrary},
+
+  Author                   = {{Free Software Foundation Inc.}},
+  HowPublished             = {\url{http://www.gnu.org/software/gsl/}},
+  Month                    = apr,
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.28},
+  Url                      = {\url{http://www.gnu.org/software/gsl/}}
+}
+
+@Misc{FSF2011,
+  Title                    = {{GSL} - {GNU} {S}cientific {L}ibrary},
+
+  Author                   = {{Free Software Foundation Inc.}},
+  HowPublished             = {\url{http://www.gnu.org/software/gsl/}},
+  Month                    = apr,
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.28},
+  Url                      = {\url{http://www.gnu.org/software/gsl/}}
+}
+
+@Misc{FSF2011a,
+  Title                    = {{GSL} - {GNU} {S}cientific {L}ibrary},
+
+  Author                   = {{Free Software Foundation Inc.}},
+  HowPublished             = {\url{http://www.gnu.org/software/gsl/}},
+  Month                    = apr,
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.28},
+  Url                      = {\url{http://www.gnu.org/software/gsl/}}
+}
+
+@Misc{gnugsl,
+  Title                    = {{GSL} - {GNU} {S}cientific {L}ibrary},
+
+  Author                   = {{Free Software Foundation Inc.}},
+  HowPublished             = {\url{http://www.gnu.org/software/gsl}},
+  Month                    = apr,
+  Note                     = {last access 2014-07-02},
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.28},
+  Url                      = {\url{http://www.gnu.org/software/gsl/}}
+}
+
+@Electronic{fre_12,
+  Title                    = {{GNU} {O}ctave randn() {D}ocumentation},
+  Author                   = {{Free Software Foundation, Inc.}},
+  HowPublished             = {\url{http://www.gnu.org/software/octave/doc/interpreter/Special-Utility-Matrices.html}},
+  Language                 = {en},
+  Month                    = mar,
+  Note                     = {last access 2014-07-02},
+  Url                      = {http://www.gnu.org/software/octave/doc/interpreter/Special-Utility-Matrices.html},
+  Year                     = {2012},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation, Ziggurat},
+  Cds_read                 = {2012-03-22},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@Electronic{FSF2012,
+  Title                    = {{GNU} {O}ctave randn() {D}ocumentation},
+  Author                   = {{Free Software Foundation, Inc.}},
+  HowPublished             = {\url{http://www.gnu.org/software/octave/doc/interpreter/Special-Utility-Matrices.html}},
+  Language                 = {en},
+  Month                    = mar,
+  Year                     = {2012},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation, Ziggurat},
+  Cds_read                 = {2012-03-22},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@Article{fre_00,
+  Title                    = {{Turbo Decoding for Wireless Systems with Imperfect Channel Estimates}},
+  Author                   = {P. Frenger},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2000},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {1437--1440},
+  Volume                   = {48},
+
+  File                     = {fre_00.pdf:fre_00.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{fre_99,
+  Title                    = {{Turbo Decoding on Rayleigh Fading Channels with Noisy Channel Estimates}},
+  Author                   = {P. Frenger},
+  Booktitle                = {{Proc. 1999 Vehicular Technology Conference (VTC '99)}},
+  Year                     = {1999},
+
+  Address                  = {Houston, Texas, USA},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{fremac_99,
+  Title                    = {{Irregular Turbocodes}},
+  Author                   = {B.J. Frey and D.J.C. MacKay},
+  Booktitle                = {{Proc. of the 37th Allerton Conference on Communication, Control and Computing}},
+  Year                     = {1999},
+
+  Address                  = {Illinois, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{freksc_98,
+  Title                    = {{Early Detection and Trellis Splicing: Reduced-Complexity Iterative Decoding}},
+  Author                   = {Frey, B. J. and Kschischang, F. R.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {1998},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {153--159},
+  Volume                   = {16},
+
+  File                     = {freksc_98.pdf:freksc_98.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{fri_95,
+  Title                    = {{K}analcodierung},
+  Author                   = {Bernd Friedrichs},
+  Publisher                = {Springer Verlag Berlin Heidelberg},
+  Year                     = {1995},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {Channel Code, BCH, Syndrome, Chien Search, Key Equation, Berlekamp-Massey, Euclidean Algorithm, Galois Fields, RS},
+  Cds_read                 = {2008-10},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{frijoh_12,
+  Title                    = {{FFTW}: {F}astest {F}ourier transform in the west},
+  Author                   = {Frigo, Matteo and Johnson, Steven G},
+  Journal                  = {Astrophysics Source Code Library},
+  Year                     = {2012},
+  Note                     = {last access 2015-01-13},
+  Pages                    = {01015},
+  Volume                   = {1},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.24},
+  Url                      = {http://www.fftw.org/}
+}
+
+@InProceedings{fuli_08,
+  Title                    = {{ORBIT}: {E}ffective {I}ssue {Q}ueue {S}oft-{E}rror {V}ulnerability {M}itigation on {S}imultaneous {M}ultithreaded {A}rchitectures {U}sing {O}perand {R}eadiness-{B}ased {I}nstruction {D}ispatch},
+  Author                   = {Xin Fu and Tao Li and Fortes, J. },
+  Booktitle                = {Proc. 20th Int. Symp. Computer Architecture and High Performance Computing SBAC-PAD '08},
+  Year                     = {2008},
+  Pages                    = {71--78},
+
+  Doi                      = {10.1109/SBAC-PAD.2008.13},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{fuli_09,
+  Title                    = {{S}oft error vulnerability aware process variation mitigation},
+  Author                   = {Xin Fu and Tao Li and Fortes, J. A. B. },
+  Booktitle                = {Proc. IEEE 15th Int. Symp. High Performance Computer Architecture HPCA 2009},
+  Year                     = {2009},
+  Pages                    = {93--104},
+
+  Doi                      = {10.1109/HPCA.2009.4798241},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{fucsak_05,
+  Title                    = {{Some Classes of Quasi-Cyclic LDPC Codes: Properties and Efficient Encoding Method}},
+  Author                   = {H. Fucita and K. Sakaniwa},
+  Journal                  = {IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science},
+  Year                     = {2005},
+
+  Month                    = dec,
+  Number                   = {12},
+  Pages                    = {3627--3635},
+  Volume                   = {E88-A},
+
+  File                     = {fucsak_05.pdf:fucsak_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{funsha_07,
+  Title                    = {{D}ynamic {W}arp {F}ormation and {S}cheduling for {E}fficient {GPU} {C}ontrol {F}low},
+  Author                   = {Wilson W.L. Fung and Ivan Sham and George Yuan and Tor M. Aamodt},
+  Booktitle                = {40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)},
+  Year                     = {2007},
+  Month                    = {Dec.},
+  Pages                    = {407-420},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.27}
+}
+
+@Article{fus_89,
+  Title                    = {{A}n {E}quivalence {R}elation etween {T}ausworthe and {GFSR} {S}equences and {A}pplications},
+  Author                   = {Masanori Fushimi},
+  Journal                  = {Applied Mathematics Letters },
+  Year                     = {1989},
+  Number                   = {2},
+  Pages                    = {135--137},
+  Volume                   = {2},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {randomTausworthe, GFSR, comparison},
+  Cds_read                 = {2014-02-06},
+  Doi                      = {http://dx.doi.org/10.1016/0893-9659(89)90006-2},
+  File                     = {fus_89.pdf:fus_89.pdf:PDF},
+  ISSN                     = {0893-9659},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.06},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/0893965989900062}
+}
+
+@Article{g._14,
+  Title                    = {{A} {N}ovel {O}pen {S}ource {M}orphology {U}sing {GPU} {P}rocessing {W}ith {LTU}-{CUDA}},
+  Author                   = {G. Jagannathan,R. Subash, K.Senthil Raja},
+  Journal                  = {International Journal for Advance in Research and Technology},
+  Year                     = {2014},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Volume                   = {2},
+
+  Owner                    = {Sadri},
+  Timestamp                = {2014.07.28}
+}
+
+@InProceedings{gai_02,
+  Title                    = {{A} portable and fault-tolerant microprocessor based on the {SPARC} v8 architecture},
+  Author                   = {Gaisler, J.},
+  Booktitle                = {Proc. International Conference on Dependable Systems and Networks DSN 2002},
+  Year                     = {2002},
+  Month                    = jun,
+  Pages                    = {409--415},
+
+  Doi                      = {10.1109/DSN.2002.1028926},
+  File                     = {gai_02.pdf:gai_02.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Book{gal_63,
+  Title                    = {{Low-Density Parity-Check Codes}},
+  Author                   = {R. G. Gallager},
+  Publisher                = {M.I.T. Press},
+  Year                     = {1963},
+
+  Address                  = {Cambridge, Massachusetts},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{gal_62,
+  Title                    = {{Low-Density Parity-Check Codes}},
+  Author                   = {Gallager, R. G.},
+  Journal                  = {IRE Transactions on Information Theory},
+  Year                     = {1962},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {21--28},
+  Volume                   = {8},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{gal_10,
+  Title                    = {{O}n the {F}air {C}omparison of {FEC} {S}chemes},
+  Author                   = {Galli, S. },
+  Booktitle                = {Proc. IEEE Int Communications (ICC) Conf},
+  Year                     = {2010},
+  Pages                    = {1--6},
+
+  Doi                      = {10.1109/ICC.2010.5501811},
+  Owner                    = {Kienle},
+  Timestamp                = {2010.09.22}
+}
+
+@Conference{Gallinaro2010,
+  Title                    = {{I}mproving {F}requency {R}ecovery in a {DVB}-{RCS} {P}ilotless {S}ystem},
+  Author                   = {G. Gallinaro and F. Di Cecca},
+  Booktitle                = {16th KA and Broadband Communications, Navigations and Earth Observation Conference},
+  Year                     = {2010},
+
+  Address                  = {Milan, Italy},
+  Month                    = {October},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27}
+}
+
+@InProceedings{galgov_05,
+  Title                    = {{LU}-{GPU}: {E}fficient {A}lgorithms for {S}olving {D}ense {L}inear {S}ystems on {G}raphics {H}ardware},
+  Author                   = {Galoppo, Nico and Govindaraju, Naga K. and Henson, Michael and Manocha, Dinesh},
+  Booktitle                = {Proceedings of the 2005 ACM/IEEE Conference on Supercomputing},
+  Year                     = {2005},
+
+  Address                  = {Washington, DC, USA},
+  Pages                    = {3--},
+  Publisher                = {IEEE Computer Society},
+  Series                   = {SC '05},
+
+  Acmid                    = {1105768},
+  Doi                      = {10.1109/SC.2005.42},
+  ISBN                     = {1-59593-061-2},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.26},
+  Url                      = {http://dx.doi.org/10.1109/SC.2005.42}
+}
+
+@InCollection{gamphi_11,
+  Title                    = {{AETHER}: {S}elf-{A}daptive {N}etworked {E}ntities: {A}utonomous {C}omputing {E}lements for {F}uture {P}ervasive {A}pplications and {T}echnologies},
+  Author                   = {Gamrat, Christian and Philippe, Jean-Marc and Jesshope, Chris and Shafarenko, Alex and Bisdounis, Labros and Bondi, Umberto and Ferrante, Alberto and Cabestany, Joan and Hübner, Michael and Pärsinnen, Juha and Kadlec, Jiri and Danek, Martin and Tain, Benoit and Eisenbach, Susan and Auguin, Michel and Diguet, Jean-Philippe and Lenormand, Eric and Roux, Jean-Luc},
+  Booktitle                = {Reconfigurable Computing},
+  Publisher                = {Springer New York},
+  Year                     = {2011},
+  Editor                   = {Cardoso, João M. P. and Hübner, Michael},
+  Pages                    = {149-184},
+
+  Doi                      = {10.1007/978-1-4614-0061-5_7},
+  ISBN                     = {978-1-4614-0060-8},
+  Language                 = {English},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://dx.doi.org/10.1007/978-1-4614-0061-5_7}
+}
+
+@InProceedings{gankum_03,
+  Title                    = {{T}iming-sync {P}rotocol for {S}ensor {N}etworks},
+  Author                   = {Ganeriwal, Saurabh and Kumar, Ram and Srivastava, Mani B.},
+  Booktitle                = {Proceedings of the 1st International Conference on Embedded Networked Sensor Systems},
+  Year                     = {2003},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {138--149},
+  Publisher                = {ACM},
+  Series                   = {SenSys '03},
+
+  Acmid                    = {958508},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Ganeriwal:2003:TPS:958491.958508},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1145/958491.958508},
+  ISBN                     = {1-58113-707-9},
+  Keywords                 = {BLE},
+  Keywords_original        = {clock drift, medium access control, packet delay, sensor networks, time synchronization},
+  Location                 = {Los Angeles, California, USA},
+  Numpages                 = {12},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30},
+  Url                      = {http://doi.acm.org/10.1145/958491.958508}
+}
+
+@InProceedings{gansan_19,
+  Title                    = {{T}he {W}hat's {N}ext {I}ntermittent {C}omputing {A}rchitecture},
+  Author                   = {K. {Ganesan} and J. {San Miguel} and N. {Enright Jerger}},
+  Booktitle                = {2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)},
+  Year                     = {2019},
+  Month                    = {Feb},
+  Pages                    = {211-223},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8675223},
+  Ccr_keywords             = {CP, ensuring forward progress},
+  Ccr_relevance            = {medium},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/HPCA.2019.00039},
+  ISSN                     = {2378-203X},
+  Keywords                 = {TCS},
+  Keywords_original        = {approximation theory;checkpointing;energy harvesting;power system reliability;energy-harvesting devices;extremely tight energy constraints;power outage;subword pipelining;subword vectorization;checkpoint location;WN;approximation techniques;what's next intermittent computing architecture;skim point;Power system reliability;Pipeline processing;Program processors;Sugar;Blood;Computer architecture;Monitoring;energy harvesting,intermittent computing,approximate computing},
+  Owner                    = {CCR}
+}
+
+@InProceedings{ganmin_12,
+  Title                    = {{A}cceleration of {MPC} using graphic processing unit},
+  Author                   = {Y. Gang and L. Mingguang},
+  Booktitle                = {Proceedings of 2012 2nd International Conference on Computer Science and Network Technology},
+  Year                     = {2012},
+  Month                    = {Dec},
+  Pages                    = {1001-1004},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{GPU} PLATFORM; cite number in presentation [22]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/ICCSNT.2012.6526095},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {control engineering computing;graphics processing units;parallel architectures;predictive control;{MPC} acceleration;graphic processing unit;model predictive control algorithm;computational burden;{GPU};CUDA;compute united device architecture;{GPU};CUDA;Model predictive control;Parallel computing},
+  Owner                    = {CCR}
+}
+
+@InProceedings{ganami_01,
+  Title                    = {{BLAST} system capacity measurements at 2.44 {GH}z in suburban outdoor environment},
+  Author                   = {Gans, M .J. and Amitay, N. and Yeh, Y .S. and Xu, H. and Valenzuela, R .A. and Sizer, T. and Storz, R. and Taylor, D. and MacDonald, W. M. and Tran, C. and Adamiecki, A.},
+  Booktitle                = {Vehicular Technology Conference, 2001. VTC 2001 Spring. IEEE VTS 53rd},
+  Year                     = {2001},
+  Month                    = may,
+  Pages                    = {288--292vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/VETECS.2001.944850},
+  Owner                    = {kienle},
+  Timestamp                = {2008.03.17}
+}
+
+@InProceedings{gaozha_16,
+  Title                    = {{A} {S}urvey of {H}omogeneous and {H}eterogeneous {S}ystem {A}rchitectures in {H}igh {P}erformance {C}omputing},
+  Author                   = {Yuxiang Gao and Peng Zhang},
+  Booktitle                = {2016 IEEE International Conference on Smart Cloud (SmartCloud)},
+  Year                     = {2016},
+  Month                    = {Nov},
+  Pages                    = {170-175},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.16}
+}
+
+@InProceedings{garel-_17,
+  Title                    = {{A} 25 m{V}-startup cold start system with on-chip magnetics for thermal energy harvesting},
+  Author                   = {P. {Garcha} and D. {El-Damak} and N. {Desai} and J. {Troncoso} and E. {Mazotti} and J. {Mullenix} and S. {Tang} and D. {Trombley} and D. {Buss} and J. {Lang} and A. {Chandrakasan}},
+  Booktitle                = {ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference},
+  Year                     = {2017},
+  Month                    = {Sep.},
+  Pages                    = {127-130},
+
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8094542},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/ESSCIRC.2017.8094542},
+  Keywords                 = {TCS},
+  Keywords_original        = {DC-DC power convertors;electronics packaging;energy harvesting;low-power electronics;oscillators;starting;switched capacitor networks;Meissner Oscillator;switched capacitor DC-DC circuit;on-chip magnetics;on-chip transformer;boost converter circuits;fully-integrated low voltage startup solution;thermal energy harvesting systems;high-efficiency low voltage operation;integrated magnetics;integrated electrical startup;startup cold start system;depletion-mode NMOS start up;sourcemeter;voltage 25.0 mV;voltage 50.0 mV;System-on-chip;Magnetics;MOS devices;Low voltage;Oscillators;Capacitors;Circuit faults;energy harvesting;startup;on-chip transformer;integrated magnetics;optimization;Meissner oscillator;cold start},
+  Owner                    = {CCR}
+}
+
+@Article{garcan_11,
+  Title                    = {{H}igh-{T}hroughput {I}nterpolator {A}rchitecture for {L}ow-{C}omplexity {C}hase {D}ecoding of {RS} {C}odes},
+  Author                   = {Garcia-Herrero, F. and Canet, M. J. and Valls, J. and Meher, P. K.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2011},
+  Note                     = {Early Access},
+  Number                   = {99},
+
+  Doi                      = {10.1109/TVLSI.2010.2103961},
+  File                     = {garcan_11.pdf:garcan_11.pdf:PDF},
+  Keywords                 = {ASD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.27}
+}
+
+@Article{gardec_14,
+  Title                    = {{N}on-{B}inary {LDPC} {D}ecoder {B}ased on {S}ymbol {F}lipping with {M}ultiple {V}otes},
+  Author                   = {Garcia-Herrero, F. and Declercq, D. and Valls, J.},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2014},
+  Number                   = {5},
+  Pages                    = {749--752},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/LCOMM.2014.030914.132867},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6787156}
+}
+
+@Article{garli_ed,
+  Title                    = {{M}ultiple-{V}ote {S}ymbol-{F}lipping {D}ecoder for {N}onbinary {LDPC} {C}odes},
+  Author                   = {Garcia-Herrero, F. and Li, E. and Declercq, D. and Valls, J.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {to be published},
+  Note                     = {Early Access},
+
+  Doi                      = {10.1109/TVLSI.2013.2292900},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6731592}
+}
+
+@Article{garval_11,
+  Title                    = {{H}igh-{S}peed {RS}(255, 239) {D}ecoder {B}ased on {LCC} {D}ecoding},
+  Author                   = {García-Herrero, F. and Valls, J. and Meher, P.K.},
+  Journal                  = {Circuits, Systems, and Signal Processing},
+  Year                     = {2011},
+  Pages                    = {1643-1669},
+  Volume                   = {30},
+
+  Doi                      = {10.1007/s00034-011-9327-4},
+  File                     = {garval_11.pdf:garval_11.pdf:PDF},
+  ISSN                     = {0278-081X},
+  Issue                    = {6},
+  Keywords                 = {Reed–Solomon; Soft-decision; Low complexity chase decoder; FPGA implementation; ASIC implementation},
+  Language                 = {English},
+  Owner                    = {Scholl},
+  Publisher                = {SP Birkhäuser Verlag Boston},
+  Review                   = {echte Implementierung eines Soft RS Decoders},
+  Timestamp                = {2012.12.10},
+  Url                      = {http://dx.doi.org/10.1007/s00034-011-9327-4}
+}
+
+@Article{garpie_01,
+  Title                    = {{Computing the free distance of turbo codes and serially concatenated codes with interleavers: algorithms and applications}},
+  Author                   = {R. Garello and P. Pierleoni and S. Benedettoberr},
+  Journal                  = {IEEE Journal on Selected Areas in Communiations},
+  Year                     = {2001},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {800--812},
+  Volume                   = {19},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{garjoh_90,
+  Title                    = {{C}omputers and {I}ntractability; {A} {G}uide to the {T}heory of {NP}-{C}ompleteness},
+  Author                   = {Michael R. Garey and David S. Johnson},
+  Publisher                = {W. H. Freeman \& Co.},
+  Year                     = {1990},
+
+  Address                  = {New York, NY, USA},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.02.01}
+}
+
+@InProceedings{gardav_03,
+  Title                    = {{APP processing for high performance MIMO systems [receiver symbol detector]}},
+  Author                   = {Garrett, D. and Davis, L. and ten Brink, S. and Hochwald, B.},
+  Booktitle                = {Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003},
+  Year                     = {2003},
+  Month                    = sep,
+  Pages                    = {271--274},
+
+  Doi                      = {10.1109/CICC.2003.1249401},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{gardav_04,
+  Title                    = {{Silicon complexity for maximum likelihood MIMO detection using spherical decoding}},
+  Author                   = {Garrett, D. and Davis, L. and ten Brink, S. and Hochwald, B. and Knagge, G.},
+  Journal                  = {Solid-State Circuits, IEEE Journal of},
+  Year                     = {2004},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {1544--1552},
+  Volume                   = {39},
+
+  Doi                      = {10.1109/JSSC.2004.831454},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{garsta_01,
+  Title                    = {{A 2.5Mb/s, 23mW SOVA Traceback Chip for Turbo Decoding Applications}},
+  Author                   = {D. Garrett and M. Stan},
+  Booktitle                = {{Proc. 2000 International Symposium on Circuits and Systems (ISCAS '01)}},
+  Year                     = {2001},
+
+  Address                  = {Sydney, Australia},
+  Month                    = may,
+  Pages                    = {61--64},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{garsta_98,
+  Title                    = {{Low Power Architecture of the Soft-Output Viterbi Algorithm}},
+  Author                   = {D. Garrett and M. Stan},
+  Booktitle                = {Proc. 1998 International Symposium on Low Power Electronics and Design (ISLPED '98)},
+  Year                     = {1998},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = aug,
+  Pages                    = {262--267},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{garxu_01,
+  Title                    = {{Energy efficient Turbo Decoding for 3G Mobile}},
+  Author                   = {D. Garrett and B. Xu and C. Nicol},
+  Booktitle                = {Proc. 2001 International Symposium on Low Power Electronics and Design (ISLPED '01)},
+  Year                     = {2001},
+
+  Address                  = {Huntington Beach, California, USA},
+  Month                    = aug,
+  Pages                    = {328--333},
+
+  File                     = {garxu_01.pdf:garxu_01.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Electronic{gartner_dark_data,
+  Author                   = {Gartner},
+  HowPublished             = {\url{http://www.gartner.com/it-glossary/dark-data}},
+  Note                     = {last access 2014-07-02},
+  Url                      = {http://www.gartner.com/it-glossary/dark-data},
+
+  Cds_grade                = {3},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.20}
+}
+
+@Article{garnou_18,
+  Title                    = {{P}rotograph-{B}ased {I}nterleavers for {P}unctured {T}urbo {C}odes},
+  Author                   = {R. Garzón-Bohórquez and C. Abdel Nour and C. Douillard},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2018},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {1833-1844},
+  Volume                   = {66},
+
+  Doi                      = {10.1109/TCOMM.2017.2783971},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Hamming codes;interleaved codes;optimisation;parity check codes;turbo codes;TC extrinsic information exchange;constituent code Hamming distance spectrum;error-correction performance;improved error rate performance;joint optimization;periodic cross connection pattern;punctured turbo codes;uniform interleaving;Correlation;Decoding;Error analysis;Long Term Evolution;Turbo codes;Turbo codes;correlation girth;interleaver;protograph;puncturing pattern;span},
+  Owner                    = {StW},
+  Timestamp                = {2018.06.25}
+}
+
+@InProceedings{gasweh_93,
+  Title                    = {{ Synthesis of Complex VHDL Operators}},
+  Author                   = { M.~Gasteier and N.~Wehn and M.~Glesner },
+  Booktitle                = {Proc. EURO-DAC '93. European Design Automation Conference with EURO-VHDL '93},
+  Year                     = {1993},
+  Month                    = sep,
+  Pages                    = {566-571},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{gashow_12,
+  Title                    = {{H}eterogeneous {C}omputing with {O}pen{CL}},
+  Author                   = {Benedict R. Gaster and Lee Howes and David R. Kaeli and Perhaad Mistry and Dana Schaa},
+  Publisher                = {Morgan Kaufmannn},
+  Year                     = {2012},
+
+  Address                  = {Waltham},
+  Edition                  = {1},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.29}
+}
+
+@Book{gat_06,
+  Title                    = {{T}he volatility surface: a practitioner's guide},
+  Author                   = {Gatheral, Jim},
+  Publisher                = {John Wiley \& Sons},
+  Year                     = {2006},
+  Volume                   = {357},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.08.22}
+}
+
+@Article{gatjac_11,
+  Title                    = {{C}onvergence of {H}eston to {SVI}},
+  Author                   = {Gatheral, Jim and Jacquier, Antoine},
+  Journal                  = {Quantitative Finance},
+  Year                     = {2011},
+  Number                   = {8},
+  Pages                    = {1129--1132},
+  Volume                   = {11},
+
+  Cds_keywords             = {calibration, numerical analysis, FFT},
+  Cds_read                 = {2014-08-15},
+  Keywords                 = {finance},
+  Owner                    = {Brugger},
+  Timestamp                = {2014.08.21}
+}
+
+@InProceedings{geb_97,
+  Title                    = {{Low Energy Memory and Register Allocation using Network Flow}},
+  Author                   = {C. H. Gebotys},
+  Booktitle                = {Proc. 1997 Design Automation Conference (DAC '97)},
+  Year                     = {1997},
+  Month                    = jun,
+  Pages                    = {435--440},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{gelgot_13,
+  Title                    = {{EXIT}-{O}ptimized {I}ndex {A}ssignments for {T}urbo {D}ecoders with {U}nreliable {LLR} {T}ransfer},
+  Author                   = {Geldmacher, Jan and Gotze, Jurgen},
+  Journal                  = {Communications Letters, IEEE},
+  Year                     = {2013},
+  Number                   = {5},
+  Pages                    = {992-995},
+  Volume                   = {17},
+
+  Doi                      = {10.1109/LCOMM.2013.040213.130200},
+  File                     = {gelgot_13.pdf:gelgot_13.pdf:PDF},
+  ISSN                     = {1089-7798},
+  Keywords                 = {EXIT chart;Turbo codes;error resilience;fault tolerant decoder;index assignment;soft errors;unreliable LLRs},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@InProceedings{gelgot_12,
+  Title                    = {{O}n fault tolerant decoding of {T}urbo codes},
+  Author                   = {Geldmacher, J. and Gotze, J.},
+  Booktitle                = {Turbo Codes and Iterative Information Processing (ISTC), 2012 7th International Symposium on},
+  Year                     = {2012},
+  Pages                    = {245-249},
+
+  Doi                      = {10.1109/ISTC.2012.6325236},
+  File                     = {gelgot_12.pdf:gelgot_12.pdf:PDF},
+  ISSN                     = {2165-4700},
+  Keywords                 = {binary codes;buffer storage;channel coding;error compensation;fault tolerance;maximum likelihood decoding;quantisation (signal);turbo codes;binary representation;buffer memories;discrete memoryless channel;error compensation;fault tolerant decoding;index assignment;quantizer;turbo codes;turbo decoding algorithm;uniform bit errors;Bit error rate;Buffer storage;Decoding;Indexes;Iterative decoding;Optimization;Turbo codes},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@InProceedings{gelhue_11,
+  Title                    = {{T}urbo {E}qualization for {R}eceivers with {U}nreliable {B}uffer {M}emory},
+  Author                   = {Geldmacher, J. and Hueske, K. and G\"otze, J.},
+  Booktitle                = {Proc. IEEE Vehicular Technology Conf. (VTC Fall)},
+  Year                     = {2011},
+  Pages                    = {1--5},
+
+  Cb_grade                 = {- Reliability},
+  Doi                      = {10.1109/VETECF.2011.6092880},
+  File                     = {gelhue_11.pdf:gelhue_11.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2012.02.08}
+}
+
+@Article{gemgan_02,
+  Title                    = {{Implementation of scalable Power and Area Efficient High-Troughput Viterbi Decoders}},
+  Author                   = {T. Gemmeke and M. Gansen and Noll, T. G.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2002},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {941--948},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{gendie_18,
+  Title                    = {{I}mproved {M}aximum-{L}ikelihood {D}ecoding {U}sing {S}parse {P}arity-{C}heck {M}atrices},
+  Author                   = {Gensheimer, Florian and Dietz, Tobias and Ruzika, Stefan and Kraft, Kira and Wehn, Norbert},
+  Journal                  = {International Conference on Telecommunication},
+  Year                     = {2018},
+
+  Owner                    = {kraft},
+  Timestamp                = {2018.06.08}
+}
+
+@InProceedings{genruz_14,
+  Title                    = {{A} simplex algorithm for {LP} decoding hardware},
+  Author                   = {Gensheimer, F. and Ruzika, S. and Scholl, S. and Wehn, N.},
+  Booktitle                = {Personal, Indoor, and Mobile Radio Communication (PIMRC), 2014 IEEE 25th Annual International Symposium on},
+  Year                     = {2014},
+  Pages                    = {790--794},
+
+  Doi                      = {10.1109/PIMRC.2014.7136272},
+  Owner                    = {scholl},
+  Timestamp                = {2015.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7136272}
+}
+
+@InProceedings{genrov_10,
+  Title                    = {{A} multi-standard flexible turbo/{LDPC} decoder via {ASIC} design},
+  Author                   = {Gentile, G. and Rovini, M. and Fanucci, L.},
+  Booktitle                = {Proc. 6th Int Turbo Codes and Iterative Information Processing (ISTC) Symp},
+  Year                     = {2010},
+  Pages                    = {294--298},
+
+  Doi                      = {10.1109/ISTC.2010.5613886},
+  File                     = {genrov_10.pdf:genrov_10.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{genrov_10a,
+  Title                    = {{L}ow-power techniques for flexible channel decoders},
+  Author                   = {Gentile, G. and Rovini, M. and Fanucci, L.},
+  Booktitle                = {Proc. Int Applied Electronics (AE) Conf},
+  Year                     = {2010},
+  Pages                    = {1--4},
+
+  File                     = {genrov_10a.pdf:genrov_10a.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.08.15}
+}
+
+@InProceedings{genrov_07,
+  Title                    = {{Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes}},
+  Author                   = {Guiseppe Gentile and Massimo Rovini and Luca Fanucci},
+  Booktitle                = {Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on},
+  Year                     = {2007},
+
+  Address                  = {Lübeck, Germany},
+  Month                    = aug,
+  Pages                    = {369--375},
+
+  File                     = {genrov_07.pdf:genrov_07.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{geomar_06,
+  Title                    = {{P}robabilistic arithmetic and energy efficient embedded signal processing},
+  Author                   = {George, J. and Marr, B. and Akgul, B. E. S. and Palem, K. V.},
+  Booktitle                = {Proc. of the 2006 international conference on Compilers, architecture and synthesis for embedded systems (CASES '06)},
+  Year                     = {2006},
+  Pages                    = {158--168},
+
+  Doi                      = {http://doi.acm.org/10.1145/1176760.1176781},
+  File                     = {geomar_06.pdf:geomar_06.pdf:PDF},
+  ISBN                     = {1-59593-543-6},
+  Keywords                 = {Reliability},
+  Location                 = {Seoul, Korea}
+}
+
+@Misc{Gerlach2000,
+  Title                    = {{S}ystem-{O}n-{C}hip {D}esign with {S}ystem{C}},
+
+  Author                   = {Joachim Gerlach},
+  Year                     = {2000},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {SystemC, tutorial},
+  Cds_read                 = {2008-10-29},
+  Date-added               = {2008-10-29 17:51:15 +0100},
+  Date-modified            = {2008-10-29 17:54:12 +0100},
+  File                     = {gersystem-on-chip00.pdf:gersystem-on-chip00.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Misc{gersystem-on-chip00,
+  Title                    = {{S}ystem-{O}n-{C}hip {D}esign with {S}ystem{C}},
+
+  Author                   = {Joachim Gerlach},
+  Year                     = {2000},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {SystemC, tutorial},
+  Cds_read                 = {2008-10-29},
+  Date-added               = {2008-10-29 17:51:15 +0100},
+  Date-modified            = {2008-10-29 17:54:12 +0100},
+  File                     = {gersystem-on-chip00.pdf:gersystem-on-chip00.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Article{gessha_03,
+  Title                    = {{F}rom theory to practice: an overview of {MIMO} space-time coded wireless systems},
+  Author                   = {Gesbert, D. and Shafi, M. and shan Shiu, Da and Smith, P. J. and Naguib, A.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2003},
+  Number                   = {3},
+  Pages                    = {281--302},
+  Volume                   = {21},
+
+  Abstract                 = {This paper presents an overview of progress in the area of multiple input multiple output (MIMO) space-time coded wireless systems. After some background on the research leading to the discovery of the enormous potential of MIMO wireless links, we highlight the different classes of techniques and algorithms proposed which attempt to realize the various benefits of MIMO including spatial multiplexing and space-time coding schemes. These algorithms are often derived and analyzed under ideal independent fading conditions. We present the state of the art in channel modeling and measurements, leading to a better understanding of actual MIMO gains. Finally, the paper addresses current questions regarding the integration of MIMO links in practical wireless systems and standards.},
+  Doi                      = {10.1109/JSAC.2003.809458},
+  File                     = {gessha_03.pdf:gessha_03.pdf:PDF},
+  Grade                    = {5},
+  ISSN                     = {0733-8716},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Review                   = {CG:
+Gelesen am:
+09. 10. 2008},
+  Timestamp                = {2008.10.10}
+}
+
+@Misc{ge,
+  Author                   = {{Get2Chip, Inc.}},
+  HowPublished             = {{{www.get2chip.com}}},
+
+  Key                      = {g2c},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Get2Chip,
+  Author                   = {{Get2Chip, Inc.}},
+  HowPublished             = {{{www.get2chip.com}}},
+
+  Key                      = {g2c},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{ghasud_20,
+  Title                    = {{A}n {I}n-{DRAM} {A}rchitecture for {Q}uantized {CNN}s using {F}ast {W}inograd {C}onvolutions},
+  Author                   = {Ghaffar, Muhammad Mohsin and Sudarshan, Chirag and Weis, Christian and Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {International Symposium on Memory Systems (MEMSYS 2020)},
+  Year                     = {2020},
+  Month                    = {October},
+  Publisher                = {ACM/IEEE},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-09-19}
+}
+
+@InProceedings{ghagar_15,
+  Title                    = {{DR}e{AM}: {D}ynamic {R}e-arrangement of {A}ddress {M}apping to {I}mprove the {P}erformance of {DRAM}s},
+  Author                   = {Ghasempour, Mohsen and Jaleel, Aamer and Garside, Jim D. and Luj\'{a}n, Mikel},
+  Booktitle                = {Proceedings of the Second International Symposium on Memory Systems},
+  Year                     = {2016},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {362--373},
+  Publisher                = {ACM},
+  Series                   = {MEMSYS '16},
+
+  Acmid                    = {2989102},
+  Doi                      = {10.1145/2989081.2989102},
+  ISBN                     = {978-1-4503-4305-3},
+  Keywords                 = {Address Mapping, DRAM, Memory Systems},
+  Location                 = {Alexandria, VA, USA},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-19},
+  Url                      = {http://doi.acm.org/10.1145/2989081.2989102}
+}
+
+@Conference{ghabou_01,
+  Title                    = {{D}esign and performance analysis of a high speed {AWGN} communication channel emulator},
+  Author                   = {Ghazel, A. and Boutillon, E. and Danger, J.L. and Gulak, G. and Laamari, H.},
+  Booktitle                = {IEEE PACRIM Conference, Victoria, BC},
+  Year                     = {2001},
+  Organization             = {Citeseer},
+  Pages                    = {374--377},
+
+  Abstract                 = {A Gaussian noise generator model adapted to hardware implementation is developed for mobile communication channel emulation in FPGA circuit. High accuracy is reached for the random distribution by combining the Box-Muller and Central limit methods. The proposed present model is based on reduced computation operations and memories in order to get a fast and low-cost emulation plat-form. The performance of the designed model is investigated by MATLAB simulation. The complexity and the performance level are given for some configurations and show the interest of the proposed model.},
+  Cds_grade                = {0},
+  File                     = {ghabou_01.pdf:ghabou_01.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.23}
+}
+
+@InProceedings{gheeva_09,
+  Title                    = {{S}ystem-{L}evel {H}ardware-{B}ased {P}rotection of {M}emories {A}gainst {S}oft-{E}rrors},
+  Author                   = {Gherman, Valentin and Evain, Samuel and Cartron, Mickael and Seymour, Nathaniel and Bonhomme, Yannick},
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conference \& Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {1222--1225},
+
+  File                     = {gheeva_09.pdf:gheeva_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.01}
+}
+
+@InProceedings{gholas_15,
+  Title                    = {{T}oward large-scale access-transistor-free memristive crossbars},
+  Author                   = {A. Ghofrani and M. A. Lastras-Montaño and K. Cheng},
+  Booktitle                = {The 20th Asia and South Pacific Design Automation Conference},
+  Year                     = {2015},
+  Month                    = {Jan},
+  Pages                    = {563-568},
+
+  Doi                      = {10.1109/ASPDAC.2015.7059067},
+  ISSN                     = {2153-6961},
+  Keywords                 = {integrated memory circuits;memristor circuits;large-scale access-transistor-free memristive crossbar;ultradense memory system;per-cell access-transistor;parasitic effect;partially-selected device;memory access;ATF memristive crossbar scalability;Resistance;Memristors;Leakage currents;Sensors;Nanowires;Computer architecture;Switches},
+  Timestamp                = {2018-08-29}
+}
+
+@Article{ghoyag_18,
+  Title                    = {{What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study}},
+  Author                   = {Ghose, Saugata and Yaglik\c{c}i, Abdullah Giray and Gupta, Raghav and Lee, Donghyuk and Kudrolli, Kais and Liu, William X. and Hassan, Hasan and Chang, Kevin K. and Chatterjee, Niladrish and Agrawal, Aditya and et al.},
+  Journal                  = {Proc. ACM Meas. Anal. Comput. Syst.},
+  Year                     = {2018},
+
+  Month                    = dec,
+  Number                   = {3},
+  Volume                   = {2},
+
+  Address                  = {New York, NY, USA},
+  Articleno                = {Article 38},
+  Doi                      = {10.1145/3224419},
+  Issue_date               = {December 2018},
+  Keywords                 = {low-power design, dram, power consumption, experimental characterization, memory systems, data encoding, power modeling, energy},
+  Numpages                 = {41},
+  Publisher                = {Association for Computing Machinery},
+  Url                      = {https://doi.org/10.1145/3224419}
+}
+
+@InProceedings{gholee_07,
+  Title                    = {{S}mart {R}efresh: {A}n {E}nhanced {M}emory {C}ontroller {D}esign for {R}educing {E}nergy in {C}onventional and 3{D} {D}ie-{S}tacked {DRAM}s},
+  Author                   = {Ghosh, M. and Lee, H.-H.S.},
+  Booktitle                = {Microarchitecture, 2007. MICRO 2007. 40th Annual IEEE/ACM International Symposium on},
+  Year                     = {2007},
+  Month                    = {Dec},
+  Pages                    = {134-145},
+
+  Doi                      = {10.1109/MICRO.2007.13},
+  ISSN                     = {1072-4451},
+  Keywords                 = {DRAM chips;integrated circuit design;3D die-stacked DRAMs;Biobench benchmark programs;SPECint2000;SPLASH-2;data correctness maintenance;energy reduction;enhanced memory controller design;periodic refreshing;power reduction;time-out counter;Bandwidth;Counting circuits;Data engineering;Design engineering;Microarchitecture;Packaging;Power engineering and energy;Process design;Random access memory;Temperature},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@Article{ghoroy_10,
+  Title                    = {{P}arameter {V}ariation {T}olerance and {E}rror {R}esiliency: {N}ew {D}esign {P}aradigm for the {N}anoscale {E}ra},
+  Author                   = {Ghosh, S. and Roy, K.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2010},
+  Number                   = {10},
+  Pages                    = {1718--1751},
+  Volume                   = {98},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- referenced in novstu_10},
+  Doi                      = {10.1109/JPROC.2010.2057230},
+  File                     = {ghoroy_10.pdf:ghoroy_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.20}
+}
+
+@InProceedings{ghovig_15,
+  Title                    = {{E}xperimental evaluation of a pairwise broadcast synchronization in a low-power {C}yber-physical system},
+  Author                   = {Ghoshdastider, U. and Viga, R. and Kraft, M.},
+  Booktitle                = {Wireless Sensors and Sensor Networks (WiSNet), 2015 IEEE Topical Conference on},
+  Year                     = {2015},
+  Month                    = {Jan},
+  Pages                    = {50-52},
+
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7127399},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1109/WISNET.2015.7127399},
+  Keywords                 = {BLE},
+  Keywords_original        = {Bluetooth;brain-computer interfaces;open systems;protocols;synchronisation;telemedicine;wireless sensor networks;BCI;BLE;Bluetooth low energy medium;CPS based network;PBS;TPSN;autarkic hardware pair;brain-computer interface;energy costs;energy-efficient clock synchronization method;low-power cyber-physical system;medical certification procedure;memory requirement;multimodal vital sensors;neurophysiologist;pairwise broadcast synchronization;pairwise-broadcast synchronization;performance overhead;power consumption;pulse oximetry;timing-sync protocol for sensor networks;two-way message exchange protocol;Brain-computer interfaces;Collaboration;Protocols;Sensors;Synchronization;Wireless communication;Wireless sensor networks;Bluetooth Low Energy;Brain-computer interface;Cyber-physical systems;Time Synchronization},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30}
+}
+
+@InProceedings{ghovig_14,
+  Title                    = {{W}ireless time synchronization of a collaborative brain-computer-interface using bluetooth low energy},
+  Author                   = {Ghoshdastider, U. and Viga, R. and Kraft, M.},
+  Booktitle                = {SENSORS, 2014 IEEE},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {2250-2254},
+
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {6985489},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1109/ICSENS.2014.6985489},
+  Keywords                 = {BLE},
+  Keywords_original        = {Bluetooth;biomedical communication;brain-computer interfaces;data recording;electroencephalography;synchronisation;wireless LAN;BCI multiple EEG subsystems;Bluetooth;WLAN;biopotential data recording;brain-computer-interface;channel density;quartz crystal;quartz instability;software clock;video camera;wireless EEG-system;wireless time synchronization;Bluetooth;Collaboration;Delays;Electroencephalography;Protocols;Software;Synchronization;BCI;Bluetooth Low Energy;EEG;Time Synchronization},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30}
+}
+
+@PhdThesis{Phdgiard16,
+  Title                    = {{H}igh-{S}peed {D}ecoders for {P}olar {C}odes},
+  Author                   = {Pascal Giard},
+  School                   = {McGill University Montreal, Canada},
+  Year                     = {2016},
+
+  Owner                    = {MH},
+  Timestamp                = {2017-06-07}
+}
+
+@Article{giabal_17,
+  Title                    = {{A} {M}ulti-{G}bps {U}nrolled {H}ardware {L}ist {D}ecoder for a {S}ystematic {P}olar {C}ode},
+  Author                   = {{Giard}, P. and {Balatsoukas-Stimming}, A. and {M{\"u}ller}, T.~C. and {Burg}, A. and {Thibeault}, C. and {Gross}, W.~J.},
+  Journal                  = {ArXiv e-prints},
+  Year                     = {2017},
+
+  Month                    = feb,
+
+  Adsnote                  = {Provided by the SAO/NASA Astrophysics Data System},
+  Adsurl                   = {http://adsabs.harvard.edu/abs/2017arXiv170200938G},
+  Archiveprefix            = {arXiv},
+  Eprint                   = {1702.00938},
+  File                     = {giabal_17.pdf:giabal_17.pdf:PDF},
+  Keywords                 = {Computer Science - Hardware Architecture},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-30}
+}
+
+@Article{giasar_16,
+  Title                    = {{Hardware Decoders for Polar Codes: An Overview}},
+  Author                   = {{Giard}, P. and {Sarkis}, G. and {Balatsoukas-Stimming}, A. and {Fan}, Y. and {Tsui}, C.-y. and {Burg}, A. and {Thibeault}, C. and {Gross}, W.~J.},
+  Journal                  = {ArXiv e-prints},
+  Year                     = {2016},
+
+  Month                    = jun,
+
+  Adsnote                  = {Provided by the SAO/NASA Astrophysics Data System},
+  Adsurl                   = {http://adsabs.harvard.edu/abs/2016arXiv160600737G},
+  Archiveprefix            = {arXiv},
+  Eprint                   = {1606.00737},
+  File                     = {giasar_16.pdf:giasar_16.pdf:PDF},
+  Keywords                 = {Computer Science - Information Theory},
+  Owner                    = {CK},
+  Primaryclass             = {cs.IT},
+  Timestamp                = {2017-03-29}
+}
+
+@Article{giasar_15,
+  Title                    = {{U}nrolled {P}olar {D}ecoders, {P}art {I}: {H}ardware {A}rchitectures},
+  Author                   = {Giard, Pascal and Sarkis, Gabi and Thibeault, Claude and Gross, Warren J},
+  Journal                  = {arXiv preprint arXiv:1505.01459},
+  Year                     = {2015},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.10.20}
+}
+
+@Article{giasar_15a,
+  Title                    = {{M}ulti-mode {U}nrolled {A}rchitectures for {P}olar {D}ecoders},
+  Author                   = {{Giard}, P. and {Sarkis}, G. and {Thibeault}, C. and {Gross}, W.~J. },
+  Journal                  = {ArXiv e-prints},
+  Year                     = {2015},
+
+  Month                    = may,
+
+  Adsnote                  = {Provided by the SAO/NASA Astrophysics Data System},
+  Adsurl                   = {http://adsabs.harvard.edu/abs/2015arXiv150501459G},
+  Archiveprefix            = {arXiv},
+  Eprint                   = {1505.01459},
+  File                     = {giasar_15a.pdf:giasar_15a.pdf:PDF},
+  Keywords                 = {Computer Science - Hardware Architecture},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-30}
+}
+
+@Electronic{gil_08a,
+  Title                    = {{T}he {R}eal {R}eason for the {G}lobal {F}inancial {C}risis…the {S}tory {N}o {O}ne's {T}alking {A}bout},
+  Author                   = {Shah Gilani},
+  HowPublished             = {\url{http://moneymorning.com/2008/09/18/credit-default-swaps}},
+  Language                 = {en},
+  Month                    = sep,
+  Note                     = {last access 2014-07-02},
+  Organization             = {Money Morning},
+  Url                      = {http://moneymorning.com/2008/09/18/credit-default-swaps},
+  Year                     = {2008},
+
+  Cds_grade                = {4},
+  Cds_read                 = {2012-03-25},
+  Cds_review               = {overview reason for financial crisis: CDS, CDOs, suprime mortgage loans},
+  File                     = {gil_08a.pdf:gil_08a.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.15}
+}
+
+@Electronic{Gilani2008,
+  Title                    = {{T}he {R}eal {R}eason for the {G}lobal {F}inancial {C}risis…the {S}tory {N}o {O}ne's {T}alking {A}bout},
+  Author                   = {Shah Gilani},
+  Language                 = {en},
+  Month                    = sep,
+  Organization             = {Money Morning},
+  Url                      = {http://moneymorning.com/2008/09/18/credit-default-swaps/},
+  Year                     = {2008},
+
+  Cds_grade                = {4},
+  Cds_read                 = {2012-03-25},
+  Cds_review               = {overview reason for financial crisis: CDS, CDOs, suprime mortgage loans},
+  File                     = {gil_08a.pdf:gil_08a.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.15}
+}
+
+@PhdThesis{Phdgilbe03,
+  Title                    = {{O}ptimized, {H}ighly {P}arallel {A}rchitectures for {I}terative {D}ecoding {A}lgorithms},
+  Author                   = {Frank Gilbert},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2003},
+  Month                    = may,
+  Note                     = {ISBN 3-936890-06-4},
+
+  Cds_grade                = {0},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{gilkie_04,
+  Title                    = {{A}dvanced {A}rchitectures for {H}igh-{T}hroughput {T}urbo-{D}ecoders},
+  Author                   = {F. Gilbert and F. Kienle and G. Kreiselmaier and Thul, M. J. and T. Vogt and N. Wehn and F. Berens},
+  Journal                  = {STJournal of System Research -- Wireless Issue},
+  Year                     = {2004},
+
+  Month                    = feb,
+  Note                     = {nciht auffindbar},
+  Number                   = {1},
+  Pages                    = {81--95},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{gilkie_03,
+  Title                    = {{L}ow {C}omplexity {S}topping {C}riteria for {UMTS} {T}urbo-{D}ecoders},
+  Author                   = {F. Gilbert and F. Kienle and N. Wehn},
+  Booktitle                = {Proc. VTC 2003-Spring Vehicular Technology Conference The 57th IEEE Semiannual},
+  Year                     = {2003},
+
+  Address                  = {Jeju, Korea},
+  Month                    = apr,
+  Pages                    = {2376--2380},
+
+  File                     = {gilkie_03.pdf:gilkie_03.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Booklet{gilkre_04,
+  Title                    = {{E}inführung in die {H}ardwarebeschreibungssprache {VHDL}},
+  Author                   = {Frank Gilbert and Gerd Kreiselmaier and Uwe Wasenmüller},
+  Year                     = {2004},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {VHDL, RIIS, Rechnergestützte Implementierung integrierter Schaltungen},
+  Cds_read                 = {2008-09},
+  Date-added               = {2008-08-01 13:56:35 +0200},
+  Date-modified            = {2008-11-04 16:21:52 +0100},
+  File                     = {gilkre_04.pdf:gilkre_04.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{gilmic_02,
+  Title                    = {{Algorithmische Transformationen zur Reduktion des Leistungsverbrauchs in fortgeschrittenen Kanalcodierungsverfahren}},
+  Author                   = {F. Gilbert and H. Michel and N. Wehn},
+  Booktitle                = {{3. Kolloquium des Schwerpunktprogramms der Deutschen Forschungsgemeinschaft VIVA}},
+  Year                     = {2002},
+  Month                    = mar,
+  Pages                    = {84--92},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{gilthu_03,
+  Title                    = {{C}ommunication {C}entric {A}rchitectures for {T}urbo-{D}ecoding on {E}mbedded {M}ultiprocessors},
+  Author                   = {Frank Gilbert and Michael J. Thul and Norbert Wehn},
+  Booktitle                = {Proc. Design, Automation and Test in Europe Conference and Exhibition},
+  Year                     = {2003},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+  Pages                    = {356--361},
+
+  Cds_grade                = {3},
+  Cds_read                 = {2008-10},
+  File                     = {gilthu_03.pdf:gilthu_03.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{gilvog_05,
+  Title                    = {{Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders}},
+  Author                   = {F. Gilbert and T. Vogt and N. Wehn},
+  Journal                  = {Journal of Embedded Computing},
+  Year                     = {2005},
+  Pages                    = {391-402},
+  Volume                   = {1},
+
+  Optmonth                 = {#sep#},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{gilweh_03,
+  Title                    = {{Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders}},
+  Author                   = {F. Gilbert and N. Wehn},
+  Booktitle                = {In Proc. 13th International Workshop Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, PATMOS 2003},
+  Year                     = {2003},
+
+  Address                  = {Torino, Italy},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{gilweh_01,
+  Title                    = {{Voltage Scheduling Algorithms for UMTS Turbo-Decoding on Variable Supply Voltage Processors}},
+  Author                   = {F. Gilbert and N. Wehn},
+  Booktitle                = {{Kleinheubacher Berichte}},
+  Year                     = {2001},
+
+  Address                  = {Kleinheubach, Germany},
+  Month                    = oct,
+  Pages                    = {215--218},
+  Volume                   = {45},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{gilwor_01,
+  Title                    = {{L}ow {P}ower {I}mplementation of a {T}urbo-{D}ecoder on {P}rogrammable {A}rchitectures},
+  Author                   = {Frank Gilbert and Alexander Worm and Norbert Wehn},
+  Booktitle                = {Proc. Asia and South Pacific Design Automation Conference the ASP-DAC 2001},
+  Year                     = {2001},
+
+  Address                  = {Yokohama, Japan},
+  Month                    = jan,
+  Pages                    = {400--403},
+
+  Abstract                 = {Low Power is an extremely important issue for future mobile
+radio systems. Channel decoders are essential building blocks of base-band
+signal processing units in mobile terminal architectures. Thus low power
+implementations of advanced channel decoding techniques are mandatory.
+In this paper we present a low power implementation of the most sophisticated
+channel decoding algorithm (Turbo-decoding) on programmable architectures.
+Low power optimization is performed on two abstraction levels:
+on system level by the use of an intelligent cancellation technique, on
+implementation level by the use of dynamic voltage scaling. With these
+techniques we can reduce the worst case energy consumption to 55% using
+data of state-of-the-art processors. Our approach is also applicable for
+hardware implementations. To the best of our knowledge, this is the first
+in-depth study of low power implementations of Turbo-decoders based on
+voltage scheduling for third generation wireless systems.},
+  Cds_grade                = {4},
+  Cds_keywords             = {low-power, turbo decoding, early stopping criterion, dynamic voltage scaling},
+  Cds_read                 = {2008-12-18},
+  Cds_review               = {two power reduction approaches:
+- intelligent cancellation technique
+ - CRC check of data frames <- old
+ - new approach: increase in mean of LLRs is different for decodable and undecodable blocks
+- dynamic voltage scaling
+ - if maximum CPU speed is needed only in a fraction of time
+ - algorithm on basis of remaining decoding time},
+  File                     = {gilwor_01.pdf:gilwor_01.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{gil_12,
+  Title                    = {{A}pproximating the erfinv {F}unction},
+  Author                   = {Mike Giles},
+  Booktitle                = {GPU Computing Gems},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2012},
+  Chapter                  = {10},
+  Edition                  = {{Jade}},
+  Editor                   = {Wen-Mei W. Hwu},
+  Pages                    = {109-116},
+  Volume                   = {2},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.26}
+}
+
+@Article{gil_15,
+  Title                    = {{M}ultilevel {M}onte {C}arlo methods},
+  Author                   = {Giles, Michael B},
+  Journal                  = {Acta Numerica},
+  Year                     = {2015},
+  Pages                    = {259--328},
+  Volume                   = {24},
+
+  Owner                    = {Brugger},
+  Publisher                = {Cambridge Univ Press},
+  Timestamp                = {2015.11.29}
+}
+
+@Unpublished{gil_15_unpublished,
+  Title                    = {{M}ultilevel {M}onte {C}arlo methods},
+  Author                   = {Michael B. Giles},
+  Note                     = {Accepted for Publication in Acta Numerica},
+  Year                     = {2015},
+
+  Booktitle                = {Accepted for publication in Acta Numerica},
+  Owner                    = {Brugger},
+  Publisher                = {Cambridge Univ Press},
+  Timestamp                = {2015.06.01}
+}
+
+@Article{gil_13,
+  Title                    = {{M}ultilevel {M}onte {C}arlo methods},
+  Author                   = {Giles, Michael B},
+  Journal                  = {arXiv preprint arXiv:1304.5472},
+  Year                     = {2013},
+
+  Archiveprefix            = {arXiv},
+  Eprint                   = {1304.5472},
+  File                     = {gil_13.pdf:gil_13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {Brugger},
+  Timestamp                = {2014.03.05}
+}
+
+@Article{gil_08,
+  Title                    = {{M}ultilevel {M}onte {C}arlo path simulation},
+  Author                   = {Michael B. Giles},
+  Journal                  = {Operations Research-Baltimore},
+  Year                     = {2008},
+  Number                   = {3},
+  Pages                    = {607--617},
+  Volume                   = {56},
+
+  Abstract                 = {We show that multigrid ideas can be used to reduce the computa-tional complexity of estimating an expected value arising from a stochas-tic differential equation using Monte Carlo path simulations. In thesimplest case of a Lipschitz payoff and an Euler discretisation, the com-putational cost to achieve an accuracy of O(ϵ) is reduced from O(ϵ−3) toO(ϵ−2(log ϵ)2). The analysis is supported by numerical results showingsignificant computational savings.},
+  Cds_grade                = {0},
+  Doi                      = {10.1.1.121.713},
+  File                     = {gil_08.pdf:gil_08.pdf:PDF},
+  ISSN                     = {0030-364X},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Citeseer},
+  Timestamp                = {2010.11.23}
+}
+
+@InCollection{gilsch_12,
+  Title                    = {{C}alibrating {O}ption {P}ricing {M}odels with {H}euristics},
+  Author                   = {Gilli, Manfred and Schumann, Enrico},
+  Booktitle                = {Natural Computing in Computational Finance},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2012},
+  Editor                   = {Brabazon, Anthony and O’Neill, Michael and Maringer, Dietmar},
+  Pages                    = {9-37},
+  Series                   = {Studies in Computational Intelligence},
+  Volume                   = {380},
+
+  Abstract                 = {Calibrating option pricing models to market prices often leads to optimisation problems to which standard methods (such as those based on gradients) cannot be applied.We investigate two models: Heston’s stochastic volatility model, and Bates’s model which also includes jumps. We discuss how to price options under these models, and how to calibrate the parameters of the models with heuristic techniques.},
+  Cds_keywords             = {calibration},
+  Cds_read                 = {0},
+  Doi                      = {10.1007/978-3-642-23336-4_2},
+  File                     = {gilsch_12.pdf:gilsch_12.pdf:PDF},
+  ISBN                     = {978-3-642-23335-7},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Url                      = {http://dx.doi.org/10.1007/978-3-642-23336-4_2}
+}
+
+@InProceedings{gimkie_12a,
+  Title                    = {{ASIC} {D}esign of a {G}bit/s {LDPC} {D}ecoder for {I}terative {MIMO} {S}ystems},
+  Author                   = {Gimmler, Christina and Kienle, Frank and Weis, Christian and Wehn, Norbert and Alles, Matthias},
+  Booktitle                = {Proc. Int Computing, Networking and Communications (ICNC) Conf},
+  Year                     = {2012},
+  Pages                    = {192--197},
+
+  Doi                      = {10.1109/ICCNC.2012.6167409},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.03.30}
+}
+
+@InProceedings{gimleh_10,
+  Title                    = {{L}ow-{C}omplexity {I}teration {C}ontrol for {MIMO}-{BICM} {S}ystems},
+  Author                   = {C. Gimmler and T. Lehnigk-Emden and N. Wehn},
+  Booktitle                = {Proc. IEEE 21 th International Symposium on Personal, Indoor and Mobile Radio Communications PIMRC 2010},
+  Year                     = {2010},
+
+  Address                  = {Istanbul, Turkey},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Iteration Control, AGmay},
+  File                     = {gimleh_10.pdf:gimleh_10.pdf:PDF},
+  Owner                    = {Brehm, lehnigk},
+  Timestamp                = {2011.10.18}
+}
+
+@PhdThesis{Gimmler-Dumont2014,
+  Title                    = {{I}mplementation {A}spects of {E}nergy-efficient, {R}eliable {MIMO}-{BICM} {R}eceivers},
+  Author                   = {Christina Gimmler-Dumont},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+
+  Owner                    = {Imran Ali},
+  Timestamp                = {2015.02.02}
+}
+
+@PhdThesis{Gimmler-Dumont2013,
+  Title                    = {{D}issertation in preparation},
+  Author                   = {Gimmler-Dumont, Christina},
+  School                   = {Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2013},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.12.16}
+}
+
+@PhdThesis{Phdgimml13,
+  Title                    = {{I}mplementation aspects of enery-efficient, reliable {MIMO}-{BICM} receivers},
+  Author                   = {Gimmler-Dumont, Christina},
+  School                   = {Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2013},
+
+  Keywords                 = {AGWehn, MIMO, Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.12.16}
+}
+
+@InProceedings{gimbre_12,
+  Title                    = {{R}eliability {S}tudy on {S}ystem {M}emories of an {I}terative {MIMO}-{BICM} {S}ystem},
+  Author                   = {C. Gimmler-Dumont and C. Brehm and N. Wehn},
+  Booktitle                = {Proc. IFIP/IEEE International Conference on Very Large Scale Integration 2012},
+  Year                     = {2012},
+  Month                    = {October},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.06.26}
+}
+
+@Article{gimkie_12,
+  Title                    = {{A} {S}ystem {V}iew on {I}terative {MIMO} {D}etection: {D}ynamic {S}phere {D}etection versus {F}ixed {E}ffort {L}ist {D}etection},
+  Author                   = {C. Gimmler-Dumont and F. Kienle and B. Wu and G. Masera},
+  Journal                  = {VLSI Design Journal, Article ID 826350},
+  Year                     = {2012},
+  Volume                   = {2012},
+
+  Doi                      = {doi:10.1155/2012/826350},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.02.22}
+}
+
+@Article{gimmay_13,
+  Title                    = {{C}ross-{L}ayer {E}rror {R}esilience and {I}ts {A}pplication to {W}ireless {C}ommunication {S}ystems},
+  Author                   = {Christina Gimmler-Dumont and Matthias May and Norbert Wehn},
+  Journal                  = {Journal of Low Power Electronics (JOLPE)},
+  Year                     = {2013},
+
+  Month                    = {April},
+  Number                   = {1},
+  Volume                   = {9},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.29}
+}
+
+@InProceedings{gimsch_13,
+  Title                    = {{ASIC} implementation of a modified {QR} decomposition for tree search based {MIMO} detection},
+  Author                   = {Christina Gimmler-Dumont and Philipp Schlaefer and Norbert Wehn},
+  Booktitle                = {Proceedings of 4th IEEE Latin American Symposium on Circuits and Systems},
+  Year                     = {2013},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.12.13}
+}
+
+@InProceedings{gimsch_12,
+  Title                    = {{FPGA}-based {R}apid {P}rototyping {P}latform for {MIMO}-{BICM} {D}esign {S}pace {E}xploration},
+  Author                   = {C. Gimmler-Dumont and P. Schläfer and N. Wehn},
+  Booktitle                = {Proc. IEEE International Conference on ReConFigurable Computing and FPGAs 2012},
+  Year                     = {2012},
+  Month                    = {December},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.19}
+}
+
+@Article{Gimmler-Dumont2013d,
+  Title                    = {{An energy efficient weakly programmable MIMO detector architecture}},
+  Author                   = {Gimmler-Dumont, C. and Wehn, N.},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2013},
+
+  Month                    = sep,
+  Volume                   = {11},
+
+  Address                  = {Miltenberg, Germany},
+  Booktitle                = {Proc. Kleinheubacher Tagung},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.05.07}
+}
+
+@Article{gimweh_13,
+  Title                    = {{A} {C}ross-{L}ayer {R}eliability {D}esign {M}ethodology for {E}fficient, {D}ependable {W}ireless {R}eceivers},
+  Author                   = {Christina Gimmler-Dumont and Norbert Wehn},
+  Journal                  = {ACM Transactions on Embedded Computing Systems},
+  Year                     = {2013},
+
+  File                     = {gimweh_13.pdf:gimweh_13.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.29}
+}
+
+@Article{gimweh_13a,
+  Title                    = {{An energy-efficient weakly programmable MIMO detector architecture}},
+  Author                   = {Gimmler-Dumont, C. and Wehn, N.},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2013},
+
+  Month                    = jul,
+  Pages                    = {131–136},
+  Volume                   = {11},
+
+  Address                  = {Miltenberg, Germany},
+  Booktitle                = {Proc. Kleinheubacher Tagung},
+  Doi                      = {10.5194/ars-11-131-2013},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.05.07},
+  Url                      = {http://www.adv-radio-sci.net/11/131/2013/ars-11-131-2013.pdf}
+}
+
+@InProceedings{gimweh_12,
+  Title                    = {{An energy efficient weakly programmable MIMO detector architecture}},
+  Author                   = {Gimmler-Dumont, C. and Wehn, N.},
+  Booktitle                = {Proc. Kleinheubacher Tagung},
+  Year                     = {2012},
+
+  Address                  = {Miltenberg, Germany},
+  Month                    = sep
+}
+
+@Article{gioman_07,
+  Title                    = {{A}ssessing data mining results via swap randomization},
+  Author                   = {Aristides Gionis and Heikki Mannila and Taneli Mielik{\"a}inen and Panayiotis Tsaparas},
+  Journal                  = {ACM Transactions on Knowledge Discovery from Data},
+  Year                     = {2007},
+  Number                   = {3},
+  Pages                    = {article no. 14},
+  Volume                   = {1},
+
+  Owner                    = {Netzwerkerin},
+  Timestamp                = {2010.09.23}
+}
+
+@InProceedings{gioman_06,
+  Title                    = {{A}ssessing data mining results via swap randomization},
+  Author                   = {Aristides Gionis and Heikki Mannila and Taneli Mielik{\"a}inen and Panayiotis Tsaparas},
+  Booktitle                = {International conference on knowledge discovery and data mining},
+  Year                     = {2006},
+  Pages                    = {167--176},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.08.09}
+}
+
+@Article{gio_05,
+  Title                    = {{M}arket risk models for intraday data},
+  Author                   = {Pierre Giot},
+  Journal                  = {The European Journal of Finance},
+  Year                     = {2005},
+  Number                   = {4},
+  Pages                    = {309-324},
+  Volume                   = {11},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@Book{girval_13,
+  Title                    = {{P}etri nets for systems engineering: a guide to modeling, verification, and applications},
+  Author                   = {Girault, Claude and Valk, R{\"u}diger},
+  Publisher                = {Springer Science \& Business Media},
+  Year                     = {2013},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-27}
+}
+
+@InProceedings{girmor_13,
+  Title                    = {{O}n the convergence of mainstream and mission-critical markets},
+  Author                   = {S. Girbal and M. Moretó and A. Grasset and J. Abella and E. Quiñones and F. J. Cazorla and S. Yehia},
+  Booktitle                = {2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)},
+  Year                     = {2013},
+  Month                    = {May},
+  Pages                    = {1-10},
+
+  Doi                      = {10.1145/2463209.2488962},
+  ISSN                     = {0738-100X},
+  Keywords                 = {consumer behaviour;consumer electronics;avionic;computing industry;consumer electronics market;high performance computing market;mission critical functionality;mission critical market;mobile market;Convergence;Mission critical systems;Mobile communication;Multicore processing;Program processors;Quality of service;Timing;High Performance;Mission Critical;Quality of Service},
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-17}
+}
+
+@Article{gisdoa_13,
+  Title                    = {{A}ccelerated gradient methods and dual decomposition in distributed model predictive control},
+  Author                   = {Giselsson, Pontus and Doan, Minh Dang and Keviczky, Tam{\'a}s and De Schutter, Bart and Rantzer, Anders},
+  Journal                  = {Automatica},
+  Year                     = {2013},
+  Number                   = {3},
+  Pages                    = {829--833},
+  Volume                   = {49},
+
+  Ccr_grade                = {n.a.},
+  Ccr_topic                = {NetControl Paper},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR},
+  Publisher                = {Elsevier}
+}
+
+@InProceedings{giubou_02,
+  Title                    = {{A 80 Mb/s low-power scalable turbo codec core}},
+  Author                   = {A. Giulietti and B. Bougard and V. Derudder and S. Dupont and J.-W. Weijers and L. van der Perre},
+  Booktitle                = {Custom Integrated Circuits Conference (CICC) 2002},
+  Year                     = {2002},
+
+  Address                  = {Orlando, Florida, USA},
+  Month                    = may,
+  Pages                    = {389--392},
+
+  File                     = {giubou_02.pdf:giubou_02.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Giulietti2004,
+  Title                    = {{Method and Apparatus for Interleaving, Deinterleaving and Combined Interleaving-Deinterleaving}},
+
+  Author                   = {A. Giulietti and V. Derudder and B. Bougard and G. Cosgul and M. Thul and J. Giese and C. Schurgers},
+  HowPublished             = {US Patent No. 6,678,843 B2},
+  Month                    = jan,
+  Year                     = {2004},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{giumethod04,
+  Title                    = {{Method and Apparatus for Interleaving, Deinterleaving and Combined Interleaving-Deinterleaving}},
+
+  Author                   = {A. Giulietti and V. Derudder and B. Bougard and G. Cosgul and M. Thul and J. Giese and C. Schurgers},
+  HowPublished             = {US Patent No. 6,678,843 B2},
+  Month                    = jan,
+  Year                     = {2004},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Giulietti2002a,
+  Title                    = {{Method and Apparatus for Interleaving, Deinterleaving and Combined Interleaving-Deinterleaving}},
+
+  Author                   = {A. Giulietti and V. Derudder and B. Bougard and G. Cosgul and M. Thul and J. Giese and C. Schurgers},
+  HowPublished             = {European Patent Application No. 02076939.4},
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{giumethod02,
+  Title                    = {{Method and Apparatus for Interleaving, Deinterleaving and Combined Interleaving-Deinterleaving}},
+
+  Author                   = {A. Giulietti and V. Derudder and B. Bougard and G. Cosgul and M. Thul and J. Giese and C. Schurgers},
+  HowPublished             = {European Patent Application No. 02076939.4},
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{giuper_02,
+  Title                    = {{Parallel turbo decoding interleavers: avoiding collisions in accesses to storage elements}},
+  Author                   = {A. Giulietti and L. van der Perre and M. Strum},
+  Journal                  = {Electronics Letters},
+  Year                     = {2002},
+
+  Month                    = feb,
+  Number                   = {5},
+  Pages                    = {232--234},
+  Volume                   = {38},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{giv_58,
+  Title                    = {{C}omputation of {P}lain {U}nitary {R}otations {T}ransforming a {G}eneral {M}atrix to {T}riangular {F}orm},
+  Author                   = {Givens, W.},
+  Journal                  = {Journal of the Society for Industrial and Applied Mathematics},
+  Year                     = {1958},
+  Number                   = {1},
+  Pages                    = {26-50},
+  Volume                   = {6},
+
+  Doi                      = {10.1137/0106004},
+  Eprint                   = {http://epubs.siam.org/doi/pdf/10.1137/0106004},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.12},
+  Url                      = {http://epubs.siam.org/doi/abs/10.1137/0106004}
+}
+
+@InProceedings{glanit_15,
+  Title                    = {{T}emporal decoupling with error-bounded predictive quantum control},
+  Author                   = {G. Glaser and G. Nitschey and E. Hennig},
+  Booktitle                = {2015 Forum on Specification and Design Languages (FDL)},
+  Year                     = {2015},
+  Month                    = {Sept},
+  Pages                    = {1-6},
+
+  ISSN                     = {1636-9874},
+  Keywords                 = {digital control;discrete systems;embedded systems;intelligent sensors;mixed analogue-digital integrated circuits;predictive control;virtual prototyping;temporal decoupling;error-bounded predictive quantum control;integrated mixed-signal smart-sensor systems;virtual prototyping;analog frontend circuitry;digital controller hardware;embedded real-time software;SystemC-TLM 2.0;digital components;firmware code execution;clock cycle accuracy;time quantum boundaries;optimal time quanta;blackbox sources;a-priori event timing information;coupled analog simulators;hardware in the loop;event processing latency;SystemC model;linear prediction scheme;smart-sensor system model;quasiperiodic events;Synchronization;Stochastic processes;Predictive models;Simulation;Microcontrollers;Signal processing algorithms},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-08}
+}
+
+@InProceedings{glani_92,
+  Title                    = {{The Turn Model for Adaptive Routing}},
+  Author                   = {C.J. Glass and L.M. Ni},
+  Booktitle                = {Proc. 19th International Symposium on Computer Architecture},
+  Year                     = {1992},
+  Month                    = may,
+  Pages                    = {278--287},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{gla_03,
+  Title                    = {{M}onte {C}arlo {M}ethods in {F}inancial {E}ngineering},
+  Author                   = {Paul Glasserman},
+  Publisher                = {Springer Verlag New York},
+  Year                     = {2003},
+
+  Doi                      = {10.1007/978-0-387-21617-1},
+  Owner                    = {varela},
+  Timestamp                = {2015.03.25}
+}
+
+@Article{pausha_00,
+  Title                    = {{V}ariance {R}eduction {T}echniques for {E}stimating {V}alue-at-{R}isk},
+  Author                   = {Paul Glasserman and Philip Heidelberger and Perwez Shahabuddin},
+  Journal                  = {Management Science},
+  Year                     = {2000},
+
+  Month                    = {Oct},
+  Number                   = {10},
+  Pages                    = {1349-1364},
+  Volume                   = {46},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@InProceedings{glebon_87,
+  Title                    = {{Algorithms and Tools for ASICs Design}},
+  Author                   = {M. Glesner and W. Bonath and J. Schuck and N. Wehn},
+  Booktitle                = {Journees d'Electronique},
+  Year                     = {1987},
+
+  Address                  = {Lausanne},
+  Pages                    = {139--151},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{glehae_88,
+  Title                    = {{A Silicon Compiler based Design of an Acoustical Echo Compensator}},
+  Author                   = {M.~Glesner and B.~Haetty and N.~Wehn and A.~Laudenbach and J.~Schuck and H.~Ebert and D.~Weinsziehr},
+  Booktitle                = {VLSI Signal Processing},
+  Year                     = {1988},
+  Pages                    = {21--29},
+  Publisher                = {IEEE Press, Montery},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{glelan_87,
+  Title                    = {{Multi-Project-Chip Realisation at the TH Darmstadt}},
+  Author                   = {M.~Glesner and W.~Langheinrich and N.~Wehn and J.~Schuck},
+  Booktitle                = {SEFI Conference},
+  Year                     = {1987},
+
+  Address                  = {Helsinki},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{glivuc_97,
+  Title                    = {{S}pread {S}pectrum {CDMA} {S}ystems for {W}ireless {C}ommunications},
+  Author                   = {Savo G. Glisic and Vucetic, B.},
+  Publisher                = {Artech House},
+  Year                     = {1997},
+
+  Address                  = {MA, USA},
+  Series                   = {Artech House telecommunications library},
+
+  ISBN                     = {9780890068588},
+  Lccn                     = {97000860},
+  Url                      = {http://books.google.co.uk/books?id=oepSAAAAMAAJ}
+}
+
+@Misc{glotra_17,
+  Title                    = {{D}eutsche {P}ost {DHL} {S}elects {NVIDIA} for {A}utonomous {T}rucks},
+
+  Author                   = {Global Trade, Staff},
+  HowPublished             = {http://www.globaltrademag.com/global-logistics/deutsche-post-dhl-selects-nvidia-autonomous-trucks},
+  Month                    = {October},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-01}
+}
+
+@Electronic{glo_12,
+  Title                    = {14{XM} {L}aunch},
+  Author                   = {Globalfoundries},
+  HowPublished             = {\url{http://www.globalfoundries.com/technology/pdf/GF-14XM-Press-FINAL.pdf}},
+  Note                     = {last access 2014-01-08},
+  Url                      = {http://www.globalfoundries.com/technology/pdf/GF-14XM-Press-FINAL.pdf},
+  Year                     = {2012},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {power, technology, trends},
+  Cds_read                 = {2014-01-08},
+  Cds_review               = {presentation, convergence computing + communication + ...},
+  File                     = {glo_12.pdf:glo_12.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.08}
+}
+
+@InProceedings{gloian_06,
+  Title                    = {{The Sandbridge SB3011 SDR Platform}},
+  Author                   = {Glossner, J. and Iancu, D. and Moudgill, M. and Nacer, G. and Jinturkar, S. and Schulte, M.},
+  Booktitle                = {Joint IST Workshop on Mobile Future and the Symposium on Trends in Communications (SympoTIC '06)},
+  Year                     = {2006},
+  Month                    = jun,
+  Pages                    = {ii--v},
+
+  File                     = {gloian_06.pdf:gloian_06.pdf:PDF},
+  Owner                    = {vogt},
+  Timestamp                = {2006.11.30}
+}
+
+@Misc{enocean,
+  Title                    = {http://www.enocean.com/},
+
+  Author                   = {EnOcean GmbH},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://www.enocean.com/}
+}
+
+@Misc{GmbH,
+  Title                    = {http://www.enocean.com/},
+
+  Author                   = {EnOcean GmbH},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://www.enocean.com/}
+}
+
+@PhdThesis{Phdgnaed05,
+  Title                    = {{H}igh-{S}peed decoding of convolutional {T}urbo {C}odes},
+  Author                   = {Gnaedig, David},
+  School                   = {Université de Bretagne Sud},
+  Year                     = {2005},
+
+  File                     = {Phdgnaed05.pdf:Phdgnaed05.pdf:PDF},
+  Owner                    = {Lehnigk},
+  Timestamp                = {2011.09.17}
+}
+
+@InProceedings{gnabou_03,
+  Title                    = {{On multiple slice turbo codes}},
+  Author                   = {D. Gnaedig and E. Boutillon and M. J\'{e}z\'{e}quel and V. C. Gaudet and P. G.Gulak},
+  Booktitle                = {Proc. 3rd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+
+  File                     = {gnabou_03.pdf:gnabou_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{gnabou_06,
+  Title                    = {{Towards an optimal parallel decoding of turbo codes}},
+  Author                   = {D. Gnaedig and E. Boutillon and J. Tousch and M. J\'{e}z\'{e}quel},
+  Booktitle                = {Proc. 4nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2006},
+  Month                    = apr,
+
+  File                     = {gnabou_06.pdf:gnabou_06.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {may},
+  Timestamp                = {2007.02.08}
+}
+
+@InBook{gob_09,
+  Title                    = {{A}dvanced {M}onte {C}arlo methods for barrier and related exotic options},
+  Author                   = {Emmanuel Gobet},
+  Editor                   = {P. Ciarlet and A. Bensoussan and Q. Zhang},
+  Pages                    = {497-528},
+  Publisher                = {Elsevier},
+  Year                     = {2009},
+
+  Address                  = {Amsterdam},
+  Edition                  = {Mathematical Modeling and Numerical Methods in Finance},
+  Series                   = {Handbook of Numerical Analysis},
+  Volume                   = {15},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@InProceedings{gobluc_19,
+  Title                    = {{I}ntelligence {B}eyond the {E}dge: {I}nference on {I}ntermittent {E}mbedded {S}ystems},
+  Author                   = {Gobieski, Graham and Lucia, Brandon and Beckmann, Nathan},
+  Booktitle                = {Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems},
+  Year                     = {2019},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {199--213},
+  Publisher                = {ACM},
+  Series                   = {ASPLOS '19},
+
+  Acmid                    = {3304011},
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Gobieski:2019:IBE:3297858.3304011},
+  Ccr_keywords             = {MSP430 LNA, use DNN to face TC-related challenges},
+  Ccr_relevance            = {low},
+  Ccr_topic                = {n.y.a},
+  Doi                      = {10.1145/3297858.3304011},
+  ISBN                     = {978-1-4503-6240-5},
+  Keywords                 = {TCS},
+  Keywords_original        = {deep neural network (DNN) inference, energy efficiency, intermittent computing},
+  Location                 = {Providence, RI, USA},
+  Numpages                 = {15},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/3297858.3304011}
+}
+
+@Article{god_97,
+  Title                    = {{A}pplication of antenna arrays to mobile communications. {II}. {B}eam-forming and direction-of-arrival considerations},
+  Author                   = {Godara, L.C.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {1997},
+
+  Month                    = {aug},
+  Number                   = {8},
+  Pages                    = {1195 -1245},
+  Volume                   = {85},
+
+  Doi                      = {10.1109/5.622504},
+  ISSN                     = {0018-9219},
+  Keywords                 = { DOA estimation; adaptive algorithms; antenna arrays; array signal processing; array system performance; beamforming techniques; cochannel interference; direction-of-arrival estimation; errors; mobile communications; review; adaptive signal processing; antenna arrays; array signal processing; conjugate gradient methods; direction-of-arrival estimation; errors; land mobile radio; least squares approximations; maximum entropy methods; maximum likelihood estimation; reviews;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.05}
+}
+
+@InProceedings{godhad_07,
+  Title                    = {{S}ynchronization of {L}arge {C}arrier {F}requency {O}ffsets at {L}ow {S}ignal-to-{N}oise {R}atios},
+  Author                   = {Godtmann, Susanne and Hadaschik, Niels and Steinert, Wolfgang and Ascheid, Gerd and Meyr, Heinrich},
+  Booktitle                = {16th IST Mobile and Wireless Communications Summit, 2007.},
+  Year                     = {2007},
+  Organization             = {IEEE},
+  Pages                    = {1--4},
+
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-07}
+}
+
+@InProceedings{Godtmann2006,
+  Title                    = {{C}oarse and {T}urbo {S}ynchronization: {A} {C}ase-{S}tudy for {DVB}-{RCS}},
+  Author                   = {S. Godtmann and N. Hadaschik and W. Steinert and A. Pollok and Gerd Ascheid and H. Meyr},
+  Booktitle                = {NEWCOM-ACoRN Workshop},
+  Year                     = {2006},
+
+  Address                  = {Vienna, Austria},
+  Month                    = {sep},
+
+  Journal                  = {NEWCOM-ACoRN Workshop}
+}
+
+@InProceedings{godpol_06,
+  Title                    = {{Joint Iterative Synchronization and Decoding Assisted by Pilot Symbols}},
+  Author                   = {S. Godtmann and A. Pollok and N. Hadaschik and W. Steinert and G Ascheid and H. Meyr},
+  Booktitle                = {{IST Mobile \& Wireless Communications Summit}},
+  Year                     = {2006},
+
+  Address                  = {Myconos, Greece},
+  Month                    = jul,
+
+  File                     = {godpol_06.pdf:godpol_06.pdf:PDF},
+  Owner                    = {lehnigk},
+  Timestamp                = {2007.05.02}
+}
+
+@Article{goebos_17,
+  Title                    = {3rd {I}nternational {W}orkshop on {R}apid {C}ontinuous {S}oftware {E}ngineering ({RC}o{S}e 2017)},
+  Author                   = {M. Goedicke and J. Bosch and H. H. Olsson and E. Almeida},
+  Year                     = {2017},
+
+  Month                    = {May},
+  Pages                    = {1-1},
+
+  Booktitle                = {2017 IEEE/ACM 3rd International Workshop on Rapid Continuous Software Engineering (RCoSE)},
+  Doi                      = {10.1109/RCoSE.2017.12},
+  Keywords                 = {Requirements engineering;Research and development;Software;Software engineering;System integration},
+  Owner                    = {MJ},
+  Timestamp                = {2020-02-09}
+}
+
+@Article{goesch_91,
+  Title                    = {{A} square root and division free givens rotation for solving least squares problems on systolic arrays},
+  Author                   = {Goetze, J. and Schwiegelshohn, U.@INPROCEEDINGS{5456449,
+author={Wenyao Xue and Wiegand, T. and Paul, S.},
+booktitle={Smart Antennas (WSA), 2010 International ITG Workshop on}, title={Implementation of an SDFG based parallel depth-first complex sphere decoding algorithm},
+year={2010},
+month={feb.},
+volume={},
+number={},
+pages={213 -217},
+keywords={Bit error rate;Communication standards;Equations;Iterative algorithms;Iterative decoding;MIMO;Maximum likelihood decoding;Maximum likelihood detection;Mobile communication;Wireless communication;MIMO communication;iterative decoding;tree searching;SDFG;complex transmit symbols;iterative tree search algorithms;multiple input multiple output transmission;orthogonality;parallel depth-first complex sphere decoding algorithm;square root and division free givens rotation algorithm;wireless communications systems;QR-decomposition;SDFG;Sphere decoder;complex;},
+doi={10.1109/WSA.2010.5456449},
+ISSN={},}},
+  Journal                  = {SIAM J. Sci. Stat. Comput.},
+  Year                     = {1991},
+
+  Month                    = may,
+  Number                   = {4},
+  Pages                    = {800--807},
+  Volume                   = {12},
+
+  Acmid                    = {110633},
+  Address                  = {Philadelphia, PA, USA},
+  Doi                      = {10.1137/0912042},
+  ISSN                     = {0196-5204},
+  Issue_date               = {July 1991},
+  Numpages                 = {8},
+  Owner                    = {Gimmler},
+  Publisher                = {Society for Industrial and Applied Mathematics},
+  Timestamp                = {2013.01.17},
+  Url                      = {http://dx.doi.org/10.1137/0912042}
+}
+
+@InProceedings{gofgla_94,
+  Title                    = {{Turbo-Codes and High Spectral Efficiency Modulation}},
+  Author                   = {S. Le Goff and A. Glavieux and C. Berrou},
+  Booktitle                = {Proc. 1994 International Conference on Communications (ICC '94)},
+  Year                     = {1994},
+  Month                    = may,
+  Pages                    = {645-649},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{goehbir_11,
+  Title                    = {{R}econfigurable {MPS}o{C} versus {GPU}: {P}erformance, power and energy evaluation},
+  Author                   = {Diana Göhringer and Birk, M. and Dasse-Tiyo, Y. and Ruiter, N. and Michael Hübner and Jürgen Becker},
+  Booktitle                = {Industrial Informatics (INDIN), 2011 9th IEEE International Conference on},
+  Year                     = {2011},
+  Month                    = jul,
+  Pages                    = {848--853},
+
+  Abstract                 = {Different characteristics of algorithms, perform better or worse on various target hardware. The consequent of this is, that the selection of one suitable hardware, such as Graphic Processing Units (GPU), Field Programmable Gate Arrays (FPGAs) or traditional processor cores is a challenging task for developers. The challenge is to choose the most suitable platform satisfying the requirements of the given application, such as real-time and power- / energy consumption constraints. Due to short time to market pressure, a fast development cycle is also a very important characteristic in industrial applications. This work evaluates the performance, power- /energy consumption and the development effort for three processor-based systems: an FPGA-based multiprocessor platform called RAMPSoC, a GPU and a CPU. Two real-world applications have been selected for this evaluation: 3D Ultrasound Computer Tomography and Object Recognition. The paper presents the realization of the applications on the different target hardware and discusses the results of the power and performance evaluation.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/INDIN.2011.6035003},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.13}
+}
+
+@InProceedings{goehhueb_10,
+  Title                    = {{A} semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only)},
+  Author                   = {Diana Göhringer and Michael Hübner and Michael Benz and Jürgen Becker},
+  Booktitle                = {Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays},
+  Year                     = {2010},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {286--286},
+  Publisher                = {ACM},
+  Series                   = {FPGA '10},
+
+  Abstract                 = {The efficient automatized application partitioning and mapping process for multiprocessor systems is a challenging task in academics as well as in industry until today. The introduction of reconfigurable hardware in this domain helps to meet the application requirements more efficiently due to the method of hardware adaptation at design and runtime. The combination of multiprocessor systems-on-chip (MPSoC) and reconfigurable hardware results in the RAMPSoC approach (Runtime Adaptive MPSoC). A RAMPSoC consists of an adaptive network of processors and hardware accelerators. This novel degree of freedom in MPSoC technology and the resulting design space has to be processed by a suitable toolchain, which helps to hide the complexity of the hardware architecture and its realization alternatives from the developer. This work investigates in an approach for a semi-automatic toolchain for the development of the hardware architecture and the application partitioning and mapping. A multistep approach is used to analyze and partition the software application. First each function of the software application is profiled and the communication overhead between the functions is analyzed. The results, obtained from the profiling and the communication analysis, are used as parameters for the cost function of a hierarchical clustering algorithm. The functions are clustered into multiple application modules for a given number of processors. In a second step, for each processor the corresponding application module is analyzed concerning computation intensive blocks or loops. Out of this results a Hardware/Software Co-design partitioning with a suggestion for possible hardware accelerators for each of the processors. This allows to achieve a performance near to the maximum of the local processors and therefore in general for the MPSoC. The third and last step in the designflow handles the generation of the bitstream for the complete system together with the software executables for each of the processors. This semi-automatic toolchain has been evaluated using an image processing algorithm.},
+  Acmid                    = {1723170},
+  Cds_grade                = {0},
+  Doi                      = {http://doi.acm.org/10.1145/1723112.1723170},
+  ISBN                     = {978-1-60558-911-4},
+  Keywords                 = {finance},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {1},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.13},
+  Url                      = {http://doi.acm.org/10.1145/1723112.1723170}
+}
+
+@Article{Goke1973,
+  Title                    = {{B}anyan {N}etworks for {P}artitioning {M}ultiprocessor {S}ystems},
+  Author                   = {L. Rodney Goke and G. Jack Lipovski},
+  Journal                  = {1st Annual Symposium on Computer Architecture},
+  Year                     = {1973},
+  Pages                    = {21--28},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2013.12.12}
+}
+
+@Book{gokgra_06,
+  Title                    = {{R}econfigurable {C}omputing: {A}ccelerating {C}omputation with {F}ield-{P}rogrammable {G}ate {A}rrays},
+  Author                   = {Gokhale, M.B. and Graham, P.S.},
+  Publisher                = {Springer US},
+  Year                     = {2006},
+
+  ISBN                     = {9780387261065},
+  Lccn                     = {2006275154},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {https://books.google.de/books?id=EekiPw1SpmkC}
+}
+
+@Article{golrot_03,
+  Title                    = {{A}ssessing experimentally derived interactions in a small world},
+  Author                   = {Debra S. Goldberg and Frederick P. Roth},
+  Journal                  = {Proceedings of the National Academy of Science},
+  Year                     = {2003},
+  Number                   = {8},
+  Pages                    = {4372--4376},
+  Volume                   = {100},
+
+  Owner                    = {nina},
+  Timestamp                = {2013.03.02}
+}
+
+@Article{golvar_97,
+  Title                    = {{C}apacity of fading channels with channel side information},
+  Author                   = {Goldsmith, Andrea J and Varaiya, Pravin P},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1997},
+  Number                   = {6},
+  Pages                    = {1986--1992},
+  Volume                   = {43},
+
+  Publisher                = {IEEE}
+}
+
+@InProceedings{golreb_03,
+  Title                    = {{S}oft-{E}rror {D}etection {U}sing {C}ontrol {F}low {A}ssertions},
+  Author                   = {O. Goloubeva and M. Rebaudengo and M. Sonza Reorda and M. Violante},
+  Booktitle                = {Proc. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '03)},
+  Year                     = {2003},
+
+  Address                  = {Washington, DC, USA},
+  Pages                    = {581},
+  Publisher                = {IEEE Computer Society},
+
+  ISBN                     = {0-7695-2042-1}
+}
+
+@Book{golloa_96,
+  Title                    = {{M}atrix {C}omputations},
+  Author                   = {Gene H. Golub and Charles F. Van Loan},
+  Publisher                = {The Johns Hopkins University Press},
+  Year                     = {1996},
+  Edition                  = {3rd edition},
+  Month                    = {October},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.28}
+}
+
+@Book{golvan_96,
+  Title                    = {{Matrix Computations (Johns Hopkins Studies in Mathematical Sciences)(3rd Edition)}},
+  Author                   = {Golub, Gene H. and Van Loan, Charles F.},
+  Publisher                = {The Johns Hopkins University Press},
+  Year                     = {1996},
+  Edition                  = {3rd},
+  Month                    = oct,
+
+  Abstract                 = {{<P>Revised and updated, the third edition of Golub and Van Loan's classic text in computer science provides essential information about the mathematical background and algorithmic skills required for the production of numerical software. This new edition includes thoroughly revised chapters on matrix multiplication problems and parallel matrix computations, expanded treatment of CS decomposition, an updated overview of floating point arithmetic, a more accurate rendition of the modified Gram-Schmidt process, and new material devoted to GMRES, QMR, and other methods designed to handle the sparse unsymmetric linear system problem.</P>}},
+  Citeulike-article-id     = {252315},
+  Citeulike-linkout-0      = {http://www.amazon.ca/exec/obidos/redirect?tag=citeulike09-20\&amp;path=ASIN/0801854148},
+  Citeulike-linkout-1      = {http://www.amazon.de/exec/obidos/redirect?tag=citeulike01-21\&amp;path=ASIN/0801854148},
+  Citeulike-linkout-10     = {http://www.worldcat.org/oclc/34515797},
+  Citeulike-linkout-2      = {http://www.amazon.fr/exec/obidos/redirect?tag=citeulike06-21\&amp;path=ASIN/0801854148},
+  Citeulike-linkout-3      = {http://www.amazon.jp/exec/obidos/ASIN/0801854148},
+  Citeulike-linkout-4      = {http://www.amazon.co.uk/exec/obidos/ASIN/0801854148/citeulike00-21},
+  Citeulike-linkout-5      = {http://www.amazon.com/exec/obidos/redirect?tag=citeulike07-20\&path=ASIN/0801854148},
+  Citeulike-linkout-6      = {http://www.worldcat.org/isbn/0801854148},
+  Citeulike-linkout-7      = {http://books.google.com/books?vid=ISBN0801854148},
+  Citeulike-linkout-8      = {http://www.amazon.com/gp/search?keywords=0801854148\&index=books\&linkCode=qs},
+  Citeulike-linkout-9      = {http://www.librarything.com/isbn/0801854148},
+  Day                      = {15},
+  HowPublished             = {Paperback},
+  ISBN                     = {0801854148},
+  Keywords                 = {compsci, cs, linearalgebra, math, mathematics, matrix},
+  Owner                    = {Gimmler},
+  Posted-at                = {2008-08-01 17:09:15},
+  Priority                 = {2},
+  Timestamp                = {2012.11.12},
+  Url                      = {http://www.worldcat.org/isbn/0801854148}
+}
+
+@Book{Gomes2010,
+  Title                    = {{S}ensors everywhere.{W}ireless {N}etwork {T}echnologies and {S}olutions},
+  Author                   = {Gómes, Carles, and Paradells, Josep, and Caballero, José E.},
+  Publisher                = {Vodafone_ISBN_978-84-934740-5-8},
+  Year                     = {2010},
+
+  Address                  = {ISBN 978-84-934740-5-8},
+  Month                    = {September},
+
+  Keywords                 = {WSN, Vodafone, Overview},
+  Owner                    = {Sebastian Wille},
+  Pages                    = {430},
+  Timestamp                = {2011.07.18},
+  Url                      = {http://fundacion.vodafone.es/fundacion/es/conocenos/difusion/publicaciones/sensors-everywherewireless-network-technologies/}
+}
+
+@InProceedings{gomfal_08,
+  Title                    = {{S}calable and parallel codec architectures for the {DVB}-{S}2 {FEC} system},
+  Author                   = {Gomes, M. and Falcao, G. and Silva, V. and Ferreira, V. and Sengo, A. and Silva, L. and Marques, N. and Falcao, M.},
+  Booktitle                = {Proc. IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008},
+  Year                     = {2008},
+  Month                    = nov,
+  Pages                    = {1506--1509},
+
+  Doi                      = {10.1109/APCCAS.2008.4746318},
+  File                     = {gomfal_08.pdf:gomfal_08.pdf:PDF},
+  Keywords                 = {DVB-S2},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InProceedings{gomsig_16,
+  Title                    = {{D}ynamic {E}nergy {B}urst {S}caling for {T}ransiently {P}owered {S}ystems},
+  Author                   = {Andres Gomez and Lukas Sigrist and Michele Magno and Luca Benini and Lothar Thiele},
+  Booktitle                = {Proceedings of the 2016 Design, Automation \& Test in Europe Conference \& Exhibition (DATE 2016)},
+  Year                     = {2016},
+
+  Address                  = {Dresden},
+  Month                    = {Mar},
+  Pages                    = {349--354},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {GSMBT2016a},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Keywords                 = {TCS},
+  Owner                    = {CCR}
+}
+
+@InProceedings{gomsig_17,
+  Title                    = {{W}earable, energy-opportunistic vision sensing for walking speed estimation},
+  Author                   = {A. Gomez and L. Sigrist and T. Schalch and L. Benini and L. Thiele},
+  Booktitle                = {2017 IEEE Sensors Applications Symposium (SAS)},
+  Year                     = {2017},
+  Month                    = {March},
+  Pages                    = {1-6},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7894074},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/SAS.2017.7894074},
+  Keywords                 = {TCS},
+  Keywords_original        = {Energy harvesting;Estimation;Legged locomotion;Nonvolatile memory;Optical imaging;Optical sensors;Robot sensing systems},
+  Owner                    = {CCR}
+}
+
+@Article{gomsig_17a,
+  Title                    = {{E}fficient, {L}ong-{T}erm {L}ogging of {R}ich {D}ata {S}ensors using {T}ransient {S}ensor {N}odes},
+  Author                   = {Andres Gomez and Lukas Sigrist and Thomas Schalch and Luca Benini and Lothar Thiele},
+  Journal                  = {ACM Transactions on Embedded Computing Systems},
+  Year                     = {2017},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {noID20170},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Keywords                 = {TCS},
+  Owner                    = {CCR}
+}
+
+@InProceedings{gomwei_12,
+  Title                    = {{DRAM} {S}election and {C}onfiguration for {R}eal-{T}ime {M}obile {S}ystems},
+  Author                   = {M. D. Gomony and C. Weis and B. Akesson and N. Wehn and K. Goossens},
+  Booktitle                = {IEEE Conference Design, Automation and Test in Europe (DATE)},
+  Year                     = {2012},
+
+  Address                  = {Dresden, Germany},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@InProceedings{gomwei_12a,
+  Title                    = {{DRAM selection and configuration for real-time mobile systems}},
+  Author                   = {Gomony, Manil Dev and Weis, Christian and Akesson, Benny and Wehn, Norbert and Goossens, Kees},
+  Booktitle                = {{DATE}},
+  Year                     = {2012},
+  Pages                    = {51--56},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.10}
+}
+
+@Article{gonchu_15,
+  Title                    = {{E}xploiting {R}efresh {E}ffect of {DRAM} {R}ead {O}perations: {A} {P}ractical {A}pproach to {L}ow-power {R}efresh},
+  Author                   = {Gong, Young-Ho and Chung, S.W.},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2015},
+  Number                   = {99},
+  Pages                    = {1-1},
+  Volume                   = {PP},
+
+  Doi                      = {10.1109/TC.2015.2448079},
+  ISSN                     = {0018-9340},
+  Keywords                 = {Buffer storage;DRAM chips;Hardware;Memory management;Temperature dependence;Temperature distribution;DRAM Refresh;Low-power Scheme;Main Memory;Refresh Interval},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@Article{gonchu_16,
+  Title                    = {{E}xploiting {R}efresh {E}ffect of {DRAM} {R}ead {O}perations: {A} {P}ractical {A}pproach to {L}ow-{P}ower {R}efresh},
+  Author                   = {Gong, Young-Ho and Chung, Sung Woo},
+  Journal                  = {IEEE Trans. Comput.},
+  Year                     = {2016},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {1507--1517},
+  Volume                   = {65},
+
+  Acmid                    = {2925338},
+  Address                  = {Washington, DC, USA},
+  Doi                      = {10.1109/TC.2015.2448079},
+  ISSN                     = {0018-9340},
+  Issue_date               = {May 2016},
+  Numpages                 = {11},
+  Owner                    = {MJ},
+  Publisher                = {IEEE Computer Society},
+  Timestamp                = {2016-11-17},
+  Url                      = {http://dx.doi.org/10.1109/TC.2015.2448079}
+}
+
+@InProceedings{gonqiu_17,
+  Title                    = {{R}etention state-enabled and progress-driven energy management for self-powered nonvolatile processors},
+  Author                   = {Z. Gong and K. Qiu and D. Zhou and W. Chen and Y. Xu and X. Shi and Y. Liu},
+  Booktitle                = {2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)},
+  Year                     = {2017},
+  Month                    = {Aug},
+  Pages                    = {1-8},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8046326},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/RTCSA.2017.8046326},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;power aware computing;probability;random-access storage;energy harvesting;great probability;nonvolatile processors;power resumption;retention state-aware energy management strategy;self-powered nonvolatile processors;Biomedical monitoring;Computational modeling;Energy management;Mathematical model;Nonvolatile memory;Power supplies;Program processors},
+  Owner                    = {CCR}
+}
+
+@InProceedings{gon_00,
+  Title                    = {{Xtensa: A Configurable and Extensible Processor}},
+  Author                   = {R. Gonzalez},
+  Booktitle                = {IEEE Micro},
+  Year                     = {2000},
+  Month                    = mar # {--} # apr,
+  Pages                    = {60--70},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{gonvaz_07,
+  Title                    = {{L}ayered {LDGM} codes: a capacity-approaching structure for arbitrary rates},
+  Author                   = {Gonzalez-Lopez, M. and Vazquez-Araujo, F. J. and Castedo, L. and Garcia-Frias, J.},
+  Booktitle                = {Wireless Communication Systems, 2007. ISWCS 2007. 4th International Symposium on},
+  Year                     = {2007},
+  Month                    = oct,
+  Pages                    = {16--20},
+
+  Doi                      = {10.1109/ISWCS.2007.4392293},
+  Owner                    = {kienle},
+  Timestamp                = {2008.03.04}
+}
+
+@InProceedings{goo_07,
+  Title                    = {{M}ulti-{ASIP} {S}o{C}s - or how to design ultra-low power architectures for wireless and multi-media systems},
+  Author                   = {Goossens, Gert},
+  Booktitle                = {Proc. Int System-on-Chip Symp},
+  Year                     = {2007},
+
+  Doi                      = {10.1109/ISSOC.2007.4427452},
+  File                     = {goo_07.pdf:goo_07.pdf:PDF},
+  Keywords                 = {ASIP Multi-Processor},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{gooake_13,
+  Title                    = {{C}onservative open-page policy for mixed time-criticality memory controllers},
+  Author                   = {S. Goossens and B. Akesson and K. Goossens},
+  Booktitle                = {2013 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2013},
+  Month                    = {March},
+  Pages                    = {525-530},
+
+  Doi                      = {10.7873/DATE.2013.118},
+  ISSN                     = {1530-1591},
+  Keywords                 = {Bandwidth;Bismuth;Real-time systems;SDRAM;Schedules;Time factors;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-29}
+}
+
+@Book{gooake_16,
+  Title                    = {{M}emory {C}ontrollers for {M}ixed-{T}ime-{C}riticality {S}ystems},
+  Author                   = {Goossens, Sven and Akesson, Benny and Goossens, Kees and Chandrasekar, Karthik},
+  Publisher                = {Springer},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-05}
+}
+
+@Book{goocha_16,
+  Title                    = {{M}emory {C}ontrollers for {M}ixed-{T}ime-{C}riticality {S}ystems: {A}rchitectures, {M}ethodologies and {T}rade-offs},
+  Author                   = {Goossens, S. and Chandrasekar, K. and Akesson, B. and Goossens, K.},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2016},
+  Series                   = {Embedded Systems},
+
+  ISBN                     = {9783319320946},
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-18},
+  Url                      = {https://books.google.de/books?id=l9\_7CwAAQBAJ}
+}
+
+@Article{goocha_16a,
+  Title                    = {{P}ower/{P}erformance {T}rade-{O}ffs in {R}eal-{T}ime {SDRAM} {C}ommand {S}cheduling},
+  Author                   = {S. Goossens and K. Chandrasekar and B. Akesson and K. Goossens},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2016},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {1882-1895},
+  Volume                   = {65},
+
+  Doi                      = {10.1109/TC.2015.2458859},
+  ISSN                     = {0018-9340},
+  Keywords                 = {DRAM chips;processor scheduling;real-time systems;DDR4 memories;ILP formulation;bounded worst-case bandwidth;generalized close-page memory command scheduling algorithm;hard bounds;memory devices;memory generations;pairwise bank-group interleaving scheme;power consumption;power usage;real-time SDRAM command scheduling;real-time SDRAM controllers;real-time safety-critical systems;response time;schedule length;scheduler-configuration design space;schedulers performance;Bandwidth;Bismuth;Performance evaluation;Real-time systems;SDRAM;Scheduling algorithms;Timing;Dynamic random access memory (DRAM);Memory control and access,;Real-time and embedded systems;dynamic random access memory (DRAM),;memory control and access;real-time and embedded systems},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-29}
+}
+
+@Article{Goplen2006,
+  Title                    = {{P}lacement of thermal vias in 3-{D} {IC}s using various thermal objectives},
+  Author                   = {Goplen, B. and Sapatnekar, S.S.},
+  Journal                  = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
+  Year                     = {2006},
+
+  Month                    = {April},
+  Number                   = {4},
+  Pages                    = {692-709},
+  Volume                   = {25},
+
+  Doi                      = {10.1109/TCAD.2006.870069},
+  ISSN                     = {0278-0070},
+  Keywords                 = {VLSI;finite element analysis;integrated circuit design;thermal conductivity;3D IC;3D VLSI;FEA;design aids;effective-thermal conductivities;finite-element analysis;maximum thermal gradients;thermal objectives;thermal optimization;thermal vias placement;three-dimensional integrated circuit;Finite element methods;Integrated circuit technology;Iterative methods;Routing;Space technology;Temperature;Thermal conductivity;Thermal resistance;Three-dimensional integrated circuits;Two dimensional displays;Algorithms;design;design aids;experimentation;finite-element analysis (FEA);integrated circuits (ICs);performance;placement;routing;temperature;thermal gradient;thermal optimization;thermal via;three-dimensional integrated circuit (3-D IC);three-dimensional very large scale integration (3-D VLSI)},
+  Owner                    = {weis},
+  Timestamp                = {2015.04.14}
+}
+
+@Article{gorjun_10,
+  Title                    = {{N}ested {S}imulation in {P}ortfolio {R}isk {M}easurement},
+  Author                   = {Michael B. Gordy and Sandeep Juneja},
+  Journal                  = {Management Science},
+  Year                     = {2010},
+  Number                   = {10},
+  Pages                    = {1833-1848},
+  Volume                   = {56},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.01.30}
+}
+
+@InProceedings{Gortan2010,
+  Title                    = {{A}chieving near-{MLD} performance with soft information-set decoders implemented in {FPGA}s},
+  Author                   = {Gortan, A. and Jasinski, R.P. and Godoy, W. and Pedroni, V.},
+  Booktitle                = {Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on},
+  Year                     = {2010},
+  Pages                    = {312--315},
+
+  Doi                      = {10.1109/APCCAS.2010.5775037},
+  File                     = {gorjas_10.pdf:gorjas_10.pdf:PDF},
+  Keywords                 = {OSD},
+  Owner                    = {Scholl},
+  Timestamp                = {2013.06.24},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5775037}
+}
+
+@Misc{gotperformance15,
+  Title                    = {{P}erformance {M}emory {B}andwidth {R}oadmap},
+
+  Author                   = {Goto, Hiroshige},
+  HowPublished             = {https://pc.watch.impress.co.jp/video/pcw/docs/1054/618/p5.pdf},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-07}
+}
+
+@InProceedings{goukan_06,
+  Title                    = {{M}odified {B}elief {P}ropagation {D}ecoding {A}lgorithm for {L}ow-{D}ensity {P}arity {C}heck {C}ode {B}ased on {O}scillation},
+  Author                   = {Gounai, S. and Ohtsuki, T. and Kaneko, T.},
+  Booktitle                = {Vehicular Technology Conference, 2006. VTC 2006-Spring. IEEE 63rd},
+  Year                     = {2006},
+  Pages                    = {1467--1471},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/VETECS.2006.1683079},
+  File                     = {gouoht_06a.pdf:gouoht_06a.pdf:PDF},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.05.13},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1683079}
+}
+
+@InProceedings{govcha_95,
+  Title                    = {{Comparing Algorithms for Dynamic Speed-Setting of a Low-Power CPU}},
+  Author                   = {K. Govil and E. Chan and H. Wasserman},
+  Booktitle                = {Proc. 1995 International Conference on Mobile Computing and Networking},
+  Year                     = {1995},
+  Month                    = nov,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{govgra_06,
+  Title                    = {{GPUT}era{S}ort: {H}igh {P}erformance {G}raphics {C}o-processor {S}orting for {L}arge {D}atabase {M}anagement},
+  Author                   = {Govindaraju, Naga and Gray, Jim and Kumar, Ritesh and Manocha, Dinesh},
+  Booktitle                = {Proceedings of the 2006 ACM SIGMOD International Conference on Management of Data},
+  Year                     = {2006},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {325--336},
+  Publisher                = {ACM},
+  Series                   = {SIGMOD '06},
+
+  Acmid                    = {1142511},
+  Doi                      = {10.1145/1142473.1142511},
+  ISBN                     = {1-59593-434-0},
+  Location                 = {Chicago, IL, USA},
+  Numpages                 = {12},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.26},
+  Url                      = {http://doi.acm.org/10.1145/1142473.1142511}
+}
+
+@Other{GrA¼tter,
+  Title                    = {http://www.informationsuebertragung.ch/index{A}lgorithmen.html},
+  Abstract                 = {Einleitung Applets
+Die folgenden Applets entstanden im Zuge einer Semesterarbeit an der Fachhochschule Nordwestschweiz. Sie sollen verschiedene Algorithmen der Kommunikationstechnik und der Krypthographie visualisieren, um dem Leser die Algorithmen etwas näher zu bringen.
+Bei jedem Applet wird kurz wiederholt wozu der Algorithmus dient und wie das Applet zu bedienen ist. Es wird dabei nicht zu detailiert auf die Algorithmen und deren Verwendungszweck eingegangen, die Visualisierung soll das jeweils das Verständnis fördern und erhebt nicht den Anspruch, alle Grundlagen zu vermitteln.
+Februar 2007 Patrick Grütter
+Die Applets Berlekamp-Massey und IDEA entstanden ein Jahr später ebenfalls in Rahmen einer Semesterarbeit{\ldots}
+November 2007 Bachmann Till, Rüde Benjamin},
+  Author                   = {Patrick Grütter and Till Bachmann and Benjamin Rüde},
+  Cds_grade                = {4},
+  Cds_keywords             = {Berlekamp-Massey, BCH, Key Equation, Euclidean Algorithm},
+  Cds_read                 = {2007-11},
+  Date-added               = {2008-07-11 14:51:32 +0200},
+  Date-modified            = {2008-07-11 14:54:29 +0200},
+  LastChecked              = {2008-07-11},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10},
+  Url                      = {http://www.informationsuebertragung.ch/indexAlgorithmen.html},
+  Urldate                  = {2007-11}
+}
+
+@InProceedings{gracro_08,
+  Title                    = {{C}onvergence performance and {EXIT} analysis of 4-state partially-systematic {T}urbo codes},
+  Author                   = {K. Gracie and S. Crozier},
+  Booktitle                = {2008 5th International Symposium on Turbo Codes and Related Topics},
+  Year                     = {2008},
+  Month                    = {Sept},
+  Pages                    = {414-419},
+
+  Doi                      = {10.1109/TURBOCODING.2008.4658735},
+  ISSN                     = {2165-4700},
+  Keywords                 = {channel capacity;error statistics;turbo codes;4-state PSTC;EXIT analysis;binary channel capacity;convergence performance;data symbol;error-rate performance;extrinsic information transfer chart;partially-systematic turbo codes;Channel capacity;Channel coding;Concatenated codes;Convergence;Decoding;Degradation;Error analysis;Parity check codes;Performance analysis;Turbo codes},
+  Owner                    = {StW},
+  Timestamp                = {2018.06.25}
+}
+
+@Article{Gracie2007,
+  Title                    = {{T}urbo and turbo-like codes: {P}rinciples and applications in telecommunications},
+  Author                   = {K. Gracie and M. Hamon},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2007},
+  Number                   = {6},
+  Pages                    = {1228--1254},
+  Volume                   = {95},
+
+  Owner                    = {ali},
+  Publisher                = {IEEE},
+  Timestamp                = {2015.03.21}
+}
+
+@Article{graham_07,
+  Title                    = {{T}urbo and {T}urbo-{L}ike {C}odes: {P}rinciples and {A}pplications in {T}elecommunications},
+  Author                   = {Gracie, K. and Hamon, M.-H.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2007},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {1228--1254},
+  Volume                   = {95},
+
+  Doi                      = {10.1109/JPROC.2007.895197},
+  File                     = {graham_07.pdf:graham_07.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.10.29}
+}
+
+@Misc{gra_15,
+  Title                    = {{S}ome notes on {DRAM} {R}owhammer},
+
+  Author                   = {Robert Graham},
+  HowPublished             = {\url{http://blog.erratasec.com/2015/03/some-notes-on-dram-rowhammer.html}},
+  Month                    = {March},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-23}
+}
+
+@InProceedings{gra_01,
+  Title                    = {{C}onvergence of non-binary iterative decoding},
+  Author                   = {Grant, A.},
+  Booktitle                = {Global Telecommunications Conference, 2001. GLOBECOM '01. IEEE},
+  Year                     = {2001},
+  Month                    = nov,
+  Pages                    = {1058--1062vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/GLOCOM.2001.965633},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Misc{green_17,
+  Title                    = {{U}nderstanding {A}utomotive {DDR} {DRAM}},
+
+  Author                   = {Greenberg, Marc},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-03},
+  Url                      = {https://www.synopsys.com/designware-ip/technical-bulletin/automotive-ddr-dram.html}
+}
+
+@InProceedings{gresta_02,
+  Title                    = {{The Evolution of Hardware Platforms for Mobile 'Software Defined Radio' Terminals}},
+  Author                   = {D. Greifendorf and J. Stammen and P. Jung},
+  Booktitle                = {Proc. 2002 International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC '02)},
+  Year                     = {2002},
+
+  Address                  = {Lisbon, Portugal},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{griwys_11,
+  Title                    = {{O}n the {V}aluation of {F}ader and {D}iscrete {B}arrier {O}ptions in {H}eston's {S}tochastic {V}olatility {M}odel},
+  Author                   = {Susanne A. Griebsch and Uwe Wystup},
+  Journal                  = {Quantitative Finance},
+  Year                     = {2011},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {693--709},
+  Volume                   = {11},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {Heston, closed-form, algorithm},
+  File                     = {griwys_11.pdf:griwys_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Taylor \& Francis},
+  Timestamp                = {2012.08.28}
+}
+
+@InProceedings{gri_98,
+  Title                    = {{M}odeling a {M}emory {S}ubsystem with {P}etri {N}ets: a {C}ase {S}tudy},
+  Author                   = {Matthias Gries},
+  Booktitle                = {Workshop Hardware Design and Petri Nets HWPN98},
+  Year                     = {1998},
+  Pages                    = {186--201},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-05}
+}
+
+@MastersThesis{griluk_13,
+  Title                    = {{A}spect {O}riented {D}esign for {D}ataflow {E}ngines},
+  Author                   = {Paul Grigoras and Wayne Luk and Stephen Weston},
+  School                   = {Imperial College London},
+  Year                     = {2013},
+  Month                    = jun,
+  Note                     = {last access 2014-01-24},
+
+  Cds_grade                = {0},
+  File                     = {griluk_13.pdf:griluk_13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24},
+  Url                      = {\url{http://www.doc.ic.ac.uk/teaching/distinguished-projects/2013/p.grigoras.pdf}}
+}
+
+@InProceedings{griniu_13,
+  Title                    = {{A}spect driven compilation for {D}ataflow designs},
+  Author                   = {Grigoras, Paul and Niu, Xinyu and Coutinho, Jos{\'e} Gabriel F and Luk, Wayne and Bower, Jacob and Pell, Oliver},
+  Booktitle                = {Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on},
+  Year                     = {2013},
+  Organization             = {IEEE},
+  Pages                    = {18--25},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@InProceedings{gritot_14,
+  Title                    = {{E}lastic {M}anagement of {R}econfigurable {A}ccelerators},
+  Author                   = {Grigoras, P. and Tottenham, M. and Xinyu Niu and Coutinho, J.G.F. and Luk, W.},
+  Booktitle                = {Parallel and Distributed Processing with Applications (ISPA), 2014 IEEE International Symposium on},
+  Year                     = {2014},
+  Month                    = {Aug},
+  Pages                    = {174-181},
+
+  Doi                      = {10.1109/ISPA.2014.31},
+  Keywords                 = {cloud computing;field programmable gate arrays;reconfigurable architectures;resource allocation;scheduling;FPGA;accelerator resources sharing;cloud computing;dynamic Monte Carlo bond options pricing design;elastic management;field programmable gate array;quality-of-service requirements;reconfigurable accelerators;resources allocation;runtime system;scheduling algorithms;Dynamic scheduling;Elasticity;Field programmable gate arrays;Hydrogen;Resource management;Runtime;Scheduling algorithms},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@Misc{gri250015,
+  Title                    = {2500 {EUR} {P}falz{M}etall {A}ward},
+
+  Author                   = {Valenting Grigorovici},
+  HowPublished             = {PfalzMetall-Tag, Neustadt a. d. Weinstraße, Germany},
+  Month                    = jun,
+  Note                     = {For the master thesis titled "Accessing Big Data on FPGAs: Finding Missing Links in Complex Networks", Supervised by: N. Wehn, C. Brugger},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.31}
+}
+
+@MastersThesis{MTgrigo14,
+  Title                    = {{A}ccessing {B}ig {D}ata on {FPGA}s – {F}inding {M}issing {L}inks in {C}omplex {N}etworking},
+  Author                   = {Valentin Grigorovici},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+  Month                    = aug,
+
+  Cds_grade                = {0},
+  File                     = {MTgrigo14.pdf:MTgrigo14.pdf:PDF},
+  Keywords                 = {AGWehn, CHPC},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.07}
+}
+
+@Article{grogul_98,
+  Title                    = {{Simplified MAP Algorithm Suitable for Implementation of Turbo Decoders}},
+  Author                   = {Gross, W. J. and Gulak, P. G.},
+  Journal                  = {Electronic Letters},
+  Year                     = {1998},
+
+  Month                    = aug,
+  Number                   = {16},
+  Pages                    = {1577--1578},
+  Volume                   = {34},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{groksc_07,
+  Title                    = {{A}rchitecture and {I}mplementation of an {I}nterpolation {P}rocessor for {S}oft-{D}ecision {R}eed\&ndash;{S}olomon {D}ecoding},
+  Author                   = {Gross, W. J. and Kschischang, F. R. and Gulak, P. G.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2007},
+  Number                   = {3},
+  Pages                    = {309--318},
+  Volume                   = {15},
+
+  Doi                      = {10.1109/TVLSI.2007.893609},
+  File                     = {groksc_07.pdf:groksc_07.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ASD},
+  Owner                    = {Scholl},
+  Review                   = {FPGA Implementierung},
+  Timestamp                = {2011.07.27}
+}
+
+@InProceedings{groksc_04,
+  Title                    = {{A}n {FPGA} interpolation processor for soft-decision {R}eed-{S}olomon decoding},
+  Author                   = {Gross, W. J. and Kschischang, F. R. and Gulak, P. G.},
+  Booktitle                = {Proc. 12th Annual IEEE Symp. Field-Programmable Custom Computing Machines FCCM 2004},
+  Year                     = {2004},
+  Pages                    = {310--311},
+
+  Doi                      = {10.1109/FCCM.2004.16},
+  File                     = {groksc_04.pdf:groksc_04.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ASD},
+  Owner                    = {Scholl},
+  Review                   = {erste FPGA Implementierung eines KV (Interpolation Teil)},
+  Timestamp                = {2011.07.27}
+}
+
+@Article{groksc_06,
+  Title                    = {{A}pplications of algebraic soft-decision decoding of {R}eed-{S}olomon codes},
+  Author                   = {W. J. Gross and F. R. Kschischang and R. Koetter and P. G. Gulak},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2006},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {1224-1234},
+  Volume                   = {54},
+
+  Doi                      = {10.1109/TCOMM.2006.877972},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Rayleigh channels;Reed-Solomon codes;algebraic codes;channel coding;computational complexity;decoding;magnetic recording;quadrature amplitude modulation;queueing theory;Koetter-Vardy algorithm;Rayleigh fading channels;Reed-Solomon codes;algebraic soft-decision decoding;computational complexity;error-detection criterion;magnetic recording channels;quadrature amplitude modulation;queueing analysis;redecoding architecture;wireless communications;Algorithm design and analysis;Amplitude modulation;Computational complexity;Decoding;Fading;Gain;Magnetic recording;Queueing analysis;Reed-Solomon codes;Wireless communication;List decoding;Reed&#8211;Solomon (RS) codes;soft-decision decoding (SDD)}
+}
+
+@InProceedings{groksc_02,
+  Title                    = {{A} {VLSI} architecture for interpolation in soft-decision list decoding of {R}eed-{S}olomon codes},
+  Author                   = {Gross, W. J. and Kschischang, F. R. and Koetter, R. and Gulak, R. G.},
+  Booktitle                = {Proc. IEEE Workshop Signal Processing Systems (SIPS '02)},
+  Year                     = {2002},
+  Pages                    = {39--44},
+
+  Doi                      = {10.1109/SIPS.2002.1049682},
+  File                     = {groksc_02.pdf:groksc_02.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ASD},
+  Owner                    = {Scholl},
+  Review                   = {erstes Hardware Architekturpaper für KV Algorithmus},
+  Timestamp                = {2011.07.27}
+}
+
+@Article{grohar_12,
+  Title                    = {{O}ptimizing {D}ata-{C}enter {TCO} with {S}cale-{O}ut {P}rocessors},
+  Author                   = {Grot, B. and Hardy, D. and Lotfi-Kamran, P. and Falsafi, B. and Nicopoulos, C. and Sazeides, Y.},
+  Journal                  = {Micro, IEEE},
+  Year                     = {2012},
+
+  Month                    = sep,
+  Number                   = {5},
+  Pages                    = {52--63},
+  Volume                   = {32},
+
+  Abstract                 = {Performance and total cost of ownership (TCO) are key optimization metrics in large-scale data centers. According to these metrics, data centers designed with conventional server processors are inefficient. Recently introduced processors based on low-power cores can improve both throughput and energy efficiency compared to conventional server chips. However, a specialized Scale-Out Processor (SOP) architecture maximizes on-chip computing density to deliver the highest performance per TCO and performance per watt at the data-center level.},
+  Cds_grade                = {0},
+  Cds_read                 = {2014-02-07},
+  Doi                      = {10.1109/MM.2012.71},
+  File                     = {grohar_12.pdf:grohar_12.pdf:PDF},
+  ISSN                     = {0272-1732},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Book{groelia_02,
+  Title                    = {{S}ystem {D}esign with {S}ystem{C}},
+  Author                   = {Thorsten Grötker and Stan Liao and Grant Martin and Stuart Swan},
+  Year                     = {2002},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {SystemC, system design},
+  Owner                    = {CdS},
+  Timestamp                = {2009.03.12}
+}
+
+@Other{gruehttp://www.informationsuebertragung.ch/indexalgorithmen.html,
+  Title                    = {http://www.informationsuebertragung.ch/index{A}lgorithmen.html},
+  Abstract                 = {Einleitung Applets
+Die folgenden Applets entstanden im Zuge einer Semesterarbeit an der Fachhochschule Nordwestschweiz. Sie sollen verschiedene Algorithmen der Kommunikationstechnik und der Krypthographie visualisieren, um dem Leser die Algorithmen etwas näher zu bringen.
+Bei jedem Applet wird kurz wiederholt wozu der Algorithmus dient und wie das Applet zu bedienen ist. Es wird dabei nicht zu detailiert auf die Algorithmen und deren Verwendungszweck eingegangen, die Visualisierung soll das jeweils das Verständnis fördern und erhebt nicht den Anspruch, alle Grundlagen zu vermitteln.
+Februar 2007 Patrick Grütter
+Die Applets Berlekamp-Massey und IDEA entstanden ein Jahr später ebenfalls in Rahmen einer Semesterarbeit{\ldots}
+November 2007 Bachmann Till, Rüde Benjamin},
+  Author                   = {Patrick Grütter and Till Bachmann and Benjamin Rüde},
+  Cds_grade                = {4},
+  Cds_keywords             = {Berlekamp-Massey, BCH, Key Equation, Euclidean Algorithm},
+  Cds_read                 = {2007-11},
+  Date-added               = {2008-07-11 14:51:32 +0200},
+  Date-modified            = {2008-07-11 14:54:29 +0200},
+  LastChecked              = {2008-07-11},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10},
+  Url                      = {http://www.informationsuebertragung.ch/indexAlgorithmen.html},
+  Urldate                  = {2007-11}
+}
+
+@InCollection{gruehar_11,
+  Title                    = {{ANDRES} – {A}nalysis and {D}esign of {R}un-{T}ime {R}econfigurable, {H}eterogeneous {S}ystems},
+  Author                   = {Grüttner, Kim and Hartmann, PhilippA. and Herrholz, Andreas and Oppenheimer, Frank},
+  Booktitle                = {Reconfigurable Computing},
+  Publisher                = {Springer New York},
+  Year                     = {2011},
+  Editor                   = {Cardoso, João M. P. and Hübner, Michael},
+  Pages                    = {185-210},
+
+  Doi                      = {10.1007/978-1-4614-0061-5_8},
+  ISBN                     = {978-1-4614-0060-8},
+  Language                 = {English},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://dx.doi.org/10.1007/978-1-4614-0061-5_8}
+}
+
+@MastersThesis{MTgu12,
+  Title                    = {{E}in neues {E}mpfehlungssystem mit {FDSM}-basierter einseitiger {P}rojektion und {L}ink {C}ommunity {C}lustering},
+  Author                   = {Ying Gu},
+  School                   = {Universität Heidelberg, Betreuer: G. Reinelt, K. A. Zweig},
+  Year                     = {2012},
+  Month                    = Feb,
+  Type                     = {Diplomarbeit},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.23}
+}
+
+@Misc{gueeigen10,
+  Title                    = {{E}igen v3},
+
+  Author                   = {Ga\"{e}l Guennebaud and Beno\^{i}t Jacob and others},
+  HowPublished             = {http://eigen.tuxfamily.org},
+  Note                     = {last access 2015-01-13},
+  Year                     = {2010},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.24}
+}
+
+@InProceedings{guireg_16,
+  Title                    = {{O}n {H}ow to {I}mprove {FPGA}-{B}ased {S}ystems {D}esign {P}roductivity via {SDA}ccel},
+  Author                   = {Giulia Guidi and Enrico Reggiani and Lorenzo {Di Tucci} and Gianluca Durelli and Michaela Blott and Marco D. Santambrogio},
+  Booktitle                = {Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
+  Year                     = {2016},
+  Month                    = {May},
+  Pages                    = {247-252},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@PhdThesis{Phdguill04,
+  Title                    = {{Architecture g\'en\'rique de décodeur de codes LDPC}},
+  Author                   = {F. Guilloud},
+  School                   = {L'\'Ecole nationale sup\'erieure des t\'el\'ecommunications},
+  Year                     = {2004},
+  Month                    = jul,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{guibou_03,
+  Title                    = {{$\lambda$-Min Decoding Algorithm of Regular and Irregular LDPC Codes}},
+  Author                   = {F. Guilloud and E. Boutillon and J.L. Danger},
+  Booktitle                = {Proc. 3nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {451--454},
+
+  File                     = {guibou_03.pdf:guibou_03.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTguite14,
+  Title                    = {{ASIC} {I}mplementation of a {H}igh {S}peed {F}lexible {LDPC} {D}ecoder {A}rchitecture},
+  Author                   = {Antonio Guiterres},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+  Type                     = {Master Thesis},
+
+  Owner                    = {Schläfer},
+  Timestamp                = {2014.07.23}
+}
+
+@Article{gulkai_88,
+  Title                    = {{Locally connected VLSI architectures for the Viterbi Algorithm}},
+  Author                   = {Gulak, P. G. and T. Kailath},
+  Journal                  = {IEEE Journal on Selected Areas in Communiations},
+  Year                     = {1988},
+
+  Month                    = apr,
+  Number                   = {3},
+  Pages                    = {527--537},
+  Volume                   = {6},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{gulsan_16,
+  Title                    = {{FPGA}-{B}ased {M}odel {P}redictive {C}ontroller for {D}irect {M}atrix {C}onverter},
+  Author                   = {O. Gulbudak and E. Santi},
+  Journal                  = {IEEE Transactions on Industrial Electronics},
+  Year                     = {2016},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {4560-4570},
+  Volume                   = {63},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [27]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/TIE.2016.2546223},
+  ISSN                     = {0278-0046},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {digital control;digital signal processing chips;dynamic response;field programmable gate arrays;matrix convertors;predictive control;parallel computation capability;dSPACE;DSP;digital signal processor;digital control platform;DMC;field-programmable gate array;dynamic response;cost function;discrete-time model;power converter;FCS-{MPC};finite control set model predictive control;direct matrix converter;{FPGA}-based model predictive controller;Switches;Predictive models;Load modeling;Mathematical model;Matrix converters;Predictive control;Field programmable gate arrays;Model Predictive Control;Field-programmable gate array;Digital Control, Direct Matrix Converter;Digital control;direct matrix converter (DMC);field-programmable gate array ({FPGA});model predictive control ({MPC})},
+  Owner                    = {CCR}
+}
+
+@Book{gumamm_14,
+  Title                    = {{F}arming {S}imulator {M}odding {F}or {D}ummies},
+  Author                   = {van Gumster, J. and Ammann, C.},
+  Publisher                = {Wiley},
+  Year                     = {2014},
+  Series                   = {--For dummies},
+
+  ISBN                     = {9781118940273},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.25}
+}
+
+@MastersThesis{MTguente07,
+  Title                    = {{I}mplementierung eines flexiblen {R}eed-{S}olomon-{E}ncoders},
+  Author                   = {Waldemar Günter},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2007},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {Channel Code, RS, Galois Fields},
+  Cds_read                 = {2008-03},
+  Date-added               = {2007-11-28 11:52:29 +0100},
+  Date-modified            = {2008-08-08 10:48:37 +0200},
+  File                     = {MTguente07.pdf:MTguente07.pdf:PDF},
+  Owner                    = {CdS},
+  Publisher                = {Waldemar Günter},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{guoqin_14,
+  Title                    = {{E}nhanced belief propagation decoding of polar codes through concatenation},
+  Author                   = {Jing Guo and Minghai Qin and A. Guillen i Fabregas and P. H. Siegel},
+  Booktitle                = {Information Theory (ISIT), 2014 IEEE International Symposium on},
+  Year                     = {2014},
+  Month                    = {June},
+  Pages                    = {2987-2991},
+
+  Doi                      = {10.1109/ISIT.2014.6875382},
+  Keywords                 = {concatenated codes;decoding;parity check codes;BP decoding;belief propagation decoding;bit-channels;concatenated polar code;enhanced concatenation;finite length polar codes;intermediate channels;low density parity check code;Bit error rate;Decoding;Iron;Parity check codes},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Article{guoshi_16,
+  Title                    = {{M}ulti-{CRC} {P}olar {C}odes and {T}heir {A}pplications},
+  Author                   = {J. Guo and Z. Shi and Z. Liu and Z. Zhang and Q. Liu},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2016},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {212-215},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/LCOMM.2015.2508022},
+  ISSN                     = {1089-7798},
+  Keywords                 = {automatic repeat request;cyclic redundancy check codes;CRC;HARQ system;SCL decoding;hybrid automatic repeat request system;multi CRC polar codes;novel coding scheme;single cyclic redundancy check;successive cancelation list decoding;Complexity theory;Delays;Encoding;Estimation;Maximum likelihood decoding;Parity check codes;CRC;HARQ;Polar codes;SCL decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Article{guoshi_16a,
+  Title                    = {{M}ulti-{CRC} {P}olar {C}odes and {T}heir {A}pplications},
+  Author                   = {J. Guo and Z. Shi and Z. Liu and Z. Zhang and Q. Liu},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2016},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {212-215},
+  Volume                   = {20},
+
+  Abstract                 = {Polar codes under successive cancelation list (SCL) decoding are capable of achieving almost the same or better performance than turbo codes or low density parity-check codes with the help of single cyclic redundancy check (CRC). This decoding scheme, however, suffers from very high complexity with long delay and large memory space. Motivated by this research problem, we propose a novel coding scheme called multi-CRC polar code for significant reduction of memory size and decoding delay but with negligible performance loss. Our analysis and simulation have shown that about half reduction of memory size and decoding delay can be achieved in SCL decoding. We also apply this scheme to hybrid automatic repeat request (HARQ) system to aid retransmission and show that the throughput of multi-CRC polar code is higher than that of the single-CRC one.},
+  Doi                      = {10.1109/LCOMM.2015.2508022},
+  ISSN                     = {1089-7798},
+  Keywords                 = {automatic repeat request;cyclic redundancy check codes;CRC;HARQ system;SCL decoding;hybrid automatic repeat request system;multi CRC polar codes;novel coding scheme;single cyclic redundancy check;successive cancelation list decoding;Complexity theory;Delays;Encoding;Estimation;Maximum likelihood decoding;Parity check codes;CRC;HARQ;Polar codes;SCL decoding},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-29}
+}
+
+@InProceedings{guonaj_04,
+  Title                    = {{A} {Q}uantitative {A}nalysis of the {S}peedup {F}actors of {FPGA}s over {P}rocessors},
+  Author                   = {Guo, Zhi and Najjar, Walid and Vahid, Frank and Vissers, Kees},
+  Booktitle                = {Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays},
+  Year                     = {2004},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {162--170},
+  Publisher                = {ACM},
+  Series                   = {FPGA '04},
+
+  Acmid                    = {968304},
+  Doi                      = {10.1145/968280.968304},
+  ISBN                     = {1-58113-829-6},
+  Keywords                 = {FPGA, VHDL, analysis, performance, reconfigurable computing},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {9},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01},
+  Url                      = {http://doi.acm.org/10.1145/968280.968304}
+}
+
+@Article{guonil_06,
+  Title                    = {{A}lgorithm and implementation of the {K}-best sphere decoding for {MIMO} detection},
+  Author                   = {Zhan Guo and Nilsson, P.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2006},
+  Number                   = {3},
+  Pages                    = {491--503},
+  Volume                   = {24},
+
+  Doi                      = {10.1109/JSAC.2005.862402},
+  File                     = {guonil_06.pdf:guonil_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.12.02}
+}
+
+@InProceedings{gupoat_07,
+  Title                    = {{U}nderstanding {V}oltage {V}ariations in {C}hip {M}ultiprocessors using a {D}istributed {P}ower-{D}elivery {N}etwork},
+  Author                   = {Gupta, M.S. and Oatley, J.L. and Joseph, R. and Gu-Yeon Wei and Brooks, D.M.},
+  Booktitle                = {Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07},
+  Year                     = {2007},
+  Month                    = {april},
+  Pages                    = {1 -6},
+
+  Doi                      = {10.1109/DATE.2007.364663},
+  Keywords                 = {chip multiprocessors;power management;power-delivery network;supply fluctuations;voltage scaling; voltage variations;microprocessor chips;}
+}
+
+@InProceedings{gupkar_10,
+  Title                    = {{VEDA}: {V}ariation-aware energy-efficient {D}iscrete {W}avelet {T}ransform architecture},
+  Author                   = {Gupta, V. and Karakonstantis, G. and Mohapatra, D. and Roy, K.},
+  Booktitle                = {Proc. IEEE Int Computer Design (ICCD) Conf},
+  Year                     = {2010},
+  Pages                    = {260--265},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/ICCD.2010.5647753},
+  File                     = {gupkar_10.pdf:gupkar_10.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.26}
+}
+
+@InProceedings{gursud_98,
+  Title                    = {{I}mproved decoding of {R}eed-{S}olomon and algebraic-geometric codes},
+  Author                   = {Guruswami, V. and Sudan, M.},
+  Booktitle                = {Proc. 39th Annual Symp. Foundations of Computer Science},
+  Year                     = {1998},
+  Pages                    = {28--37},
+
+  Doi                      = {10.1109/SFCS.1998.743426},
+  File                     = {gursud_98.pdf:gursud_98.pdf:PDF},
+  Keywords                 = {ASD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {Guruswami Sudan Algorithmus, Vorarbeit zum Koetter Vardy Algorithmus, Soft Decodierung RS-Codes},
+  Timestamp                = {2011.07.20}
+}
+
+@Patent{cho_01,
+  Title                    = {{Self-Refresh Apparatus for a Semiconductor Memory Device}},
+  Year                     = {2001},
+
+  Address                  = {{US Patent 6,229,747}},
+  Author                   = {{H.Y. Cho et al.}},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-15}
+}
+
+@TechReport{hae_00,
+  Title                    = {{M}obilfunk verdr\"angt {F}estnetz: \"{U}bersicht zu den {E}rgebnissen einer {D}elphi-{S}tudie zur {Z}ukunft des {M}obilfunks},
+  Author                   = {H\"ader, M.},
+  Institution              = {ZUMA},
+  Year                     = {2000},
+
+  Address                  = {Mannheim},
+  Number                   = {5},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.02.21}
+}
+
+@Article{hakim_04,
+  Title                    = {{R}ate-compatible puncturing of low-density parity-check codes},
+  Author                   = {Jeongseok Ha and Jaehong Kim and S. W. McLaughlin},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2004},
+
+  Month                    = {Nov},
+  Number                   = {11},
+  Pages                    = {2824-2836},
+  Volume                   = {50},
+
+  Doi                      = {10.1109/TIT.2004.836667},
+  ISSN                     = {0018-9448},
+  Keywords                 = {AWGN channels;decoding;error correction codes;parity check codes;AWGN channels;LDPC codes;additive white Gaussian noise;decoder;low-density parity-check codes;mother encoder;punctured code;puncturing patterns;rate-compatible puncturing;threshold performance;AWGN;Additive white noise;Automatic repeat request;Bipartite graph;Decoding;Equations;Parity check codes;Performance loss;Sparse matrices;Time-varying channels;Capacity-approaching code;LDPC;code;low-density parity-check;puncturing}
+}
+
+@InProceedings{haasei_17,
+  Title                    = {{A} {H}eterogeneous {SDR} {MPS}o{C} in 28 {N}m {CMOS} for {L}ow-{L}atency {W}ireless {A}pplications},
+  Author                   = {Haas, Sebastian and Seifert, Tobias and N\"{o}then, Benedikt and Scholze, Stefan and H\"{o}ppner, Sebastian and Dixius, Andreas and Adeva, Esther P{\'e}rez and Augustin, Thomas and Pauls, Friedrich and Moriam, Sadia and Hasler, Mattis and Fischer, Erik and Chen, Yong and Mat\'{u}\v{s}, Emil and Ellguth, Georg and Hartmann, Stephan and Schiefer, Stefan and Cederstr\"{o}m, Love and Walter, Dennis and Henker, Stephan and H\"{a}nzsche, Stefan and Uhlig, Johannes and Eisenreich, Holger and Weithoffer, Stefan and Wehn, Norbert and Sch\"{u}ffny, Ren{\'e} and Mayr, Christian and Fettweis, Gerhard},
+  Booktitle                = {Proceedings of the 54th Annual Design Automation Conference 2017},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {47:1--47:6},
+  Publisher                = {ACM},
+  Series                   = {DAC '17},
+
+  Acmid                    = {3062188},
+  Articleno                = {47},
+  Doi                      = {10.1145/3061639.3062188},
+  ISBN                     = {978-1-4503-4927-7},
+  Location                 = {Austin, TX, USA},
+  Numpages                 = {6},
+  Owner                    = {StW},
+  Timestamp                = {2017.10.05},
+  Url                      = {http://doi.acm.org/10.1145/3061639.3062188}
+}
+
+@Article{haapel_10,
+  Title                    = {{E}fficient, almost exact simulation of the {H}eston stochastic volatility model},
+  Author                   = {Alexander Van Haastrecht and Antoon Pelsser},
+  Journal                  = {International Journal of Theoretical and Applied Finance},
+  Year                     = {2010},
+  Number                   = {1},
+  Pages                    = {1--43},
+  Volume                   = {13},
+
+  Abstract                 = {We deal with discretization schemes for the simulation of the Heston stochastic volatility model. These simulation methods yield a popular and flexible pricing alternative for pricing and managing a book of exotic derivatives which cannot be valued using closed-form expressions. For the Heston dynamics an exact simulation method was developed by Broadie and Kaya (2006), however we argue why its practical use is limited. Instead we focus on efficient approximations of the exact scheme, aimed to resolve the disadvantages of this method; one of the main bottlenecks in the exact scheme is the simulation of the Non-central Chi-squared distributed variance process, for which we suggest an efficient caching technique. At first sight the creation of a cache containing the inverses of this distribution might seem straightforward, however as the parameter space of the inverse Non-central Chi-squared distribution is three-dimensional, the design of such a direct cache is rather complicated, as pointed out by Broadie and Andersen. Nonetheless, for the case of the Heston model we are able to tackle this dimensionality problem and show that the three-dimensional inverse of the non-central chi-squared distribution can effectively be reduced to a one dimensional cache. The performed analysis hence leads to the development of three new efficient simulation methods (the NCI, NCI-QE and BK-DI scheme). Finally, we conclude with a comprehensive numerical study of these new schemes and the exact scheme of Broadie and Kaya, the almost exact scheme of Smith, the Kahl-Jäckel scheme, the FT scheme of Lord et al. and the QE-M scheme of Andersen. From these results, we find that the QE-M scheme is the most efficient, followed closely by the NCI-M, NCI-QE-M and BK-DI-M schemes, whilst we observe that all other considered schemes perform a factor 6 to 70 times less efficient than the latter four methods.},
+  Cds_grade                = {0},
+  Doi                      = {10.1142/S0219024910005668},
+  File                     = {haapel_10.pdf:haapel_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.23}
+}
+
+@Article{habpar_10,
+  Title                    = {{D}esign {S}pace {E}xploration of {H}ard-{D}ecision {V}iterbi {D}ecoding: {A}lgorithm and {VLSI} {I}mplementation},
+  Author                   = {Habib, I. and Paker, O. and Sawitzki, S.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2010},
+
+  Month                    = {may },
+  Number                   = {5},
+  Pages                    = {794 -807},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/TVLSI.2009.2017024},
+  ISSN                     = {1063-8210},
+  Keywords                 = {VLSI;Viterbi decoding;convolutional codes;VLSI Implementation;bit detection method;convolutional codes;hard-decision Viterbi decoding;VLSI design;Viterbi algorithm;survey;}
+}
+
+@TechReport{hac_76,
+  Title                    = {{PETRI} {NET} {LANGUAGE}},
+  Author                   = {Hack, M.},
+  Year                     = {1976},
+
+  Address                  = {Cambridge, MA, USA},
+
+  Owner                    = {MJ},
+  Publisher                = {Massachusetts Institute of Technology},
+  Source                   = {http://www.ncstrl.org:8900/ncstrl/servlet/search?formname=detail\&id=oai%3Ancstrlh%3Amitai%3AMIT-LCS%2F%2FMIT%2FLCS%2FTR-159},
+  Timestamp                = {2017-02-27}
+}
+
+@InProceedings{Hagenauer04theexit,
+  Title                    = {{T}he {EXIT} {C}hart - {I}ntroduction to {E}xtrinsic {I}nformation {T}ransfer},
+  Author                   = {Joachim Hagenauer},
+  Booktitle                = {in Iterative Processing, In Proc. 12th Europ. Signal Proc. Conf (EUSIPCO},
+  Year                     = {2004},
+  Pages                    = {1541--1548},
+
+  File                     = {Hagenauer04theexit.pdf:Hagenauer04theexit.pdf:PDF},
+  Keywords                 = {InfTheory},
+  Owner                    = {Scholl},
+  Review                   = {Hagenauers Introduction to EXIT Charts},
+  Timestamp                = {2011.02.23}
+}
+
+@InProceedings{hag_97,
+  Title                    = {{The Turbo Principle: Tutorial Introduction and State of the Art}},
+  Author                   = {J. Hagenauer},
+  Booktitle                = {Proc. International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {1997},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hag_95,
+  Title                    = {{Source-Controlled Channel Coding}},
+  Author                   = {J. Hagenauer},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1995},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {2449--2457},
+  Volume                   = {43},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hag_88,
+  Title                    = {{Rate-Compatible Punctured Convolutional Codes (RCPC codes) and their Applications}},
+  Author                   = {Hagenauer, J.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {1988},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {389--400},
+  Volume                   = {36},
+
+  Doi                      = {10.1109/26.2763},
+  Owner                    = {vogt},
+  Timestamp                = {2007.01.29}
+}
+
+@InProceedings{haghoe_89,
+  Title                    = {{A Viterbi Algorithm with Soft-Decision Outputs and its Applications}},
+  Author                   = {J. Hagenauer and P. Hoeher},
+  Booktitle                = {Proc. 1989 Global Telecommunications Conference (GLOBECOM '89)},
+  Year                     = {1989},
+
+  Address                  = {Dallas, Texas, USA},
+  Month                    = nov,
+  Pages                    = {1680--1686},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hagkuh_07,
+  Title                    = {{T}he {L}ist-{S}equential ({LISS}) {A}lgorithm and {I}ts {A}pplication},
+  Author                   = {Hagenauer, J. and Kuhn, C.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2007},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {918--928},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCOMM.2007.896097},
+  File                     = {hagkuh_07.pdf:hagkuh_07.pdf:PDF},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.08.03}
+}
+
+@InProceedings{hagmoe_02,
+  Title                    = {{A}nalog decoders and receivers for high speed applications},
+  Author                   = {Hagenauer, J. and Moerz, M. and Schaefer, A.},
+  Booktitle                = {Proc. Networking Broadband Communications Access, Transmission 2002 International Zurich Seminar on},
+  Year                     = {2002},
+  Month                    = feb,
+  Pages                    = {3-1--3-8},
+
+  Doi                      = {10.1109/IZSBC.2002.991743},
+  File                     = {hagmoe_02.pdf:hagmoe_02.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.29}
+}
+
+@InProceedings{hagm_00,
+  Title                    = {{Analog Turbo-Networks in VLSI: The Next Step in Turbo Decoding and Equalization}},
+  Author                   = {J. Hagenauer and M. Mörz and E. Offer},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {209--218},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hagm_00a,
+  Title                    = {{A Circuit-Based Interpretation of Analog MAP Decoding with Binary Trellises}},
+  Author                   = {J. Hagenauer and M. Mörz and E. Offer},
+  Booktitle                = {Proc. 3rd ITG Conference Source and Channel Coding},
+  Year                     = {2000},
+
+  Address                  = {Munich, Germany},
+  Month                    = jan,
+  Pages                    = {175--180},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hagoff_96,
+  Title                    = {{Iterative Decoding of Binary Block and Convolutional Codes}},
+  Author                   = {J. Hagenauer and E. Offer and L. Papke},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1996},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {429--445},
+  Volume                   = {42},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hagpap_94,
+  Title                    = {{Decoding ``Turbo''-Codes with the Soft Output Viterbi Algorithm (SOVA)}},
+  Author                   = {J. Hagenauer and L. Papke},
+  Booktitle                = {Proc. 1994 IEEE International Symposium on Information Theory (ISIT)},
+  Year                     = {1994},
+
+  Address                  = {Trondheim, Norway},
+  Pages                    = {164},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hagrob_94,
+  Title                    = {{Iterative (``TURBO'') Decoding of Systematic Convolutional Codes with the MAP and SOVA Algorithms}},
+  Author                   = {J. Hagenauer and P. Robertson and L. Papke},
+  Booktitle                = {ITG-Fachbericht 130, Codierung für Quelle, Kanal und Übertragung},
+  Year                     = {1994},
+
+  Address                  = {Munich, Germany},
+  Month                    = oct,
+  Pages                    = {21--29},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hagses_90,
+  Title                    = {{The Performance of Rate-Compatible Punctured Convolutional Codes for Digital Mobile Radio}},
+  Author                   = {Hagenauer, J. and Seshadri, N. and Sundberg, C.-E.W.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {1990},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {966--980},
+  Volume                   = {38},
+
+  Doi                      = {10.1109/26.57495},
+  Owner                    = {vogt},
+  Timestamp                = {2007.01.29}
+}
+
+@InProceedings{hagwin_98,
+  Title                    = {{The Analog Decoder}},
+  Author                   = {J. Hagenauer and M. Winklhofer},
+  Booktitle                = {Proc. 1998 International Symposium on Information Theory (ISIT '98)},
+  Year                     = {1998},
+
+  Address                  = {Cambridge, Massachusetts, USA},
+  Month                    = aug,
+  Pages                    = {145},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{hagreverse00,
+  Title                    = {{R}everse {G}enerator {MT}19937},
+
+  Author                   = {Hagita, Katsumi and Takano, Hiroshi and Nishimura, Takuji and Matsumoto, Makoto},
+  HowPublished             = {Fortran source code},
+  Month                    = {June},
+  Note                     = {last access 2014-09-16},
+  Year                     = {2000},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.09.16},
+  Url                      = {http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/VERSIONS/FORTRAN/REVmt19937b.f}
+}
+
+@Article{halsch_09,
+  Title                    = {{L}est {W}e {R}emember: {C}old-boot {A}ttacks on {E}ncryption {K}eys},
+  Author                   = {Halderman, J. Alex and Schoen, Seth D. and Heninger, Nadia and Clarkson, William and Paul, William and Calandrino, Joseph A. and Feldman, Ariel J. and Appelbaum, Jacob and Felten, Edward W.},
+  Journal                  = {Commun. ACM},
+  Year                     = {2009},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {91--98},
+  Volume                   = {52},
+
+  Acmid                    = {1506429},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/1506409.1506429},
+  ISSN                     = {0001-0782},
+  Issue_date               = {May 2009},
+  Numpages                 = {8},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2017-09-11},
+  Url                      = {http://doi.acm.org/10.1145/1506409.1506429}
+}
+
+@Article{halpon_05,
+  Title                    = {{S}oft-in soft-out decoding of {R}eed-{S}olomon codes based on {V}ardy and {B}e'ery's decomposition},
+  Author                   = {T. R. Halford and V. Ponnampalam and A. J. Grant and K. M. Chugg},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2005},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {4363-4368},
+  Volume                   = {51},
+
+  Doi                      = {10.1109/TIT.2005.859287},
+  ISSN                     = {0018-9448},
+  Keywords                 = {Reed-Solomon codes;binary codes;decoding;matrix decomposition;Be'erys decomposition;Reed-Solomon code;SISO;Vardy decomposition;binary image;graphical model;soft-in hard-out algorithm;soft-in soft-out decoding;AWGN;Additive white noise;Australia;Code standards;Gain;Information theory;Iterative algorithms;Iterative decoding;Lakes;Statistics;Graphical models;Reed–Solomon (RS) codes;soft-in soft-out (SISO) decoding}
+}
+
+@Article{halwil_98,
+  Title                    = {{Design and Analysis of Turbo Codes on Rayleigh Fading Channels}},
+  Author                   = {Hall, E. K. and Wilsonm, S. G.},
+  Journal                  = {IEEE Journal on Selected Areas in Communiations},
+  Year                     = {1998},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {160--174},
+  Volume                   = {16},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Halter1998,
+  Title                    = {{Reconfigurable Signal Processor for Channel Coding \& Decoding in Low SNR Wireless Communications}},
+  Author                   = {S. Halter and M. Öberg and P. M. Chau and P. H. Siegel},
+  Booktitle                = {Proc. 1998 Workshop on Signal Processing Systems (SiPS '98)},
+  Year                     = {1998},
+
+  Address                  = {Cambridge, Massachusetts, USA},
+  Month                    = oct,
+  Pages                    = {260-274},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{halo_98,
+  Title                    = {{Reconfigurable Signal Processor for Channel Coding \& Decoding in Low SNR Wireless Communications}},
+  Author                   = {S. Halter and M. Öberg and P. M. Chau and P. H. Siegel},
+  Booktitle                = {Proc. 1998 Workshop on Signal Processing Systems (SiPS '98)},
+  Year                     = {1998},
+
+  Address                  = {Cambridge, Massachusetts, USA},
+  Month                    = oct,
+  Pages                    = {260-274},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{hamkla_06,
+  Title                    = {{L}inear and network optimization: },
+  Author                   = {Hamacher, H.W. and Klamroth, K.},
+  Publisher                = {Vieweg+Teubner Verlag},
+  Year                     = {2006},
+
+  ISBN                     = {9783834801852}
+}
+
+@Article{hamsug_98,
+  Title                    = {{On the retention time distribution of dynamic random access memory (DRAM)}},
+  Author                   = {Hamamoto, T. and Sugiura, S. and Sawada, S.},
+  Journal                  = {Electron Devices, IEEE Transactions on},
+  Year                     = {1998},
+
+  Month                    = {Jun},
+  Number                   = {6},
+  Pages                    = {1300-1309},
+  Volume                   = {45},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.10}
+}
+
+@Article{hamsug_98a,
+  Title                    = {{On the retention time distribution of dynamic random access memory (DRAM)}},
+  Author                   = {Hamamoto, T. and Sugiura, S. and Sawada, S.},
+  Journal                  = {Electron Devices, IEEE Transactions on},
+  Year                     = {1998},
+
+  Month                    = {Jun},
+  Number                   = {6},
+  Pages                    = {1300-1309},
+  Volume                   = {45}
+}
+
+@InProceedings{hambed_95,
+  Title                    = {{A} tool for automatic generation of self-checking data paths},
+  Author                   = {Hamdi, B. and Bederr, H. and Nicolaidis, M.},
+  Booktitle                = {Proc. 13th IEEE VLSI Test Symposium},
+  Year                     = {1995},
+  Month                    = apr # {--} # may,
+  Pages                    = {460--466},
+
+  Doi                      = {10.1109/VTEST.1995.512675},
+  File                     = {hambed_95.pdf:hambed_95.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.20}
+}
+
+@Article{ham_50,
+  Title                    = {{E}rror {D}etecting and {E}rror {C}orrecting {C}odes},
+  Author                   = {Richard Wesley Hamming},
+  Journal                  = {Bell System Technical Journal},
+  Year                     = {1950},
+  Number                   = {2},
+  Pages                    = {147-160},
+  Volume                   = {26},
+
+  Biburl                   = {http://www.bibsonomy.org/bibtex/26c41477e6a694681dadcea442dfe8c55/lysander07},
+  Keywords                 = {codingtheory www01 wwwbook wwwkap4},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.18}
+}
+
+@InProceedings{hanors_13,
+  Title                    = {{A}pproximate computing: {A}n emerging paradigm for energy-efficient design},
+  Author                   = {Jie Han and Orshansky, M.},
+  Booktitle                = {Test Symposium (ETS), 2013 18th IEEE European},
+  Year                     = {2013},
+  Month                    = {May},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/ETS.2013.6569370},
+  Keywords                 = {adders;logic design;probability;stochastic processes;algorithm-level techniques;approximate arithmetic block design;approximate arithmetic circuits;approximate computing techniques;approximate full adders;digital systems;energy-efficient design;pertinent error;probabilistic computing;quality measures;stochastic computing;Adders;Algorithm design and analysis;Approximation algorithms;Probabilistic logic;Signal processing algorithms;Timing;adder;approximate computing;low-energy design;multiplier;probabilistic computing;stochastic computation},
+  Owner                    = {MJ},
+  Timestamp                = {2015.10.26}
+}
+
+@InProceedings{hanerd_05,
+  Title                    = {{A} {P}ower {E}fficient {R}econfigurable {M}ax-{L}og-{MAP} {T}urbo {D}ecoder for {W}ireless {C}ommunication {S}ystems},
+  Author                   = {Han, J. H. and Erdogan, A. T. and Arslan, T. },
+  Booktitle                = {Proc. IEEE International SOC Conference},
+  Year                     = {2005},
+  Month                    = sep,
+  Pages                    = {247--250},
+
+  Doi                      = {10.1109/SOCC.2005.1554504},
+  File                     = {hanerd_05.pdf:hanerd_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{hanerd_05a,
+  Title                    = {{H}igh speed max-log-{MAP} turbo {SISO} decoder implementation using branch metric normalization},
+  Author                   = {Han, J. H. and Erdogan, A. T. and Arslan, T. },
+  Booktitle                = {Proc. IEEE Computer Society Annual Symposium on VLSI},
+  Year                     = {2005},
+  Month                    = may,
+  Pages                    = {173--178},
+
+  Doi                      = {10.1109/ISVLSI.2005.37},
+  File                     = {hanerd_05a.pdf:hanerd_05a.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@Article{Han2009,
+  Title                    = {{L}ow-floor decoders for {LDPC} codes},
+  Author                   = {Y. Han and Ryan, W.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2009},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {1663--1673},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TCOMM.2009.06.070325},
+  Owner                    = {punekar},
+  Timestamp                = {2009.09.04}
+}
+
+@Article{hanhar_93,
+  Title                    = {{E}fficient priority-first search maximum-likelihood soft-decision decoding of linear block codes},
+  Author                   = {Y. S. Han and C. R. P. Hartmann and Chih-Chieh Chen},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1993},
+
+  Month                    = {Sep},
+  Number                   = {5},
+  Pages                    = {1514-1523},
+  Volume                   = {39},
+
+  Doi                      = {10.1109/18.259636},
+  ISSN                     = {0018-9448},
+  Keywords                 = {BCH codes;block codes;decoding;maximum likelihood estimation;search problems;binary extended BCH code;binary extended quadratic residue code;evaluation function;generalized Dijkstra's algorithm;linear block codes;maximum-likelihood soft-decision decoding;priority-first search strategy;transmitted code;Block codes;Communication channels;Helium;Impedance matching;Information science;Matched filters;Maximum likelihood decoding;Noise level;Out of order;Search problems}
+}
+
+@InProceedings{hantak_08,
+  Title                    = {{R}eliability of n-{B}it {N}anotechnology {A}dder},
+  Author                   = {Hanninen, I. and Takala, J.},
+  Booktitle                = {Proc. IEEE Computer Society Annual Symposium on VLSI ISVLSI '08},
+  Year                     = {2008},
+  Month                    = apr,
+  Pages                    = {34--39},
+
+  Doi                      = {10.1109/ISVLSI.2008.6},
+  File                     = {hantak_08.pdf:hantak_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{hanaga_14,
+  Title                    = {{S}imulating {DRAM} controllers for future system architecture exploration},
+  Author                   = {Hansson, A. and Agarwal, N. and Kolli, A. and Wenisch, T. and Udipi, A.N.},
+  Booktitle                = {Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on},
+  Year                     = {2014},
+  Month                    = {March},
+  Pages                    = {201-210},
+
+  Doi                      = {10.1109/ISPASS.2014.6844484},
+  Keywords                 = {DRAM chips;logic design;parallel architectures;CPU;DRAM controllers;GPU;LPDDR3;WideIO;contemporary controller architecture;event-based model;full-system exploration;future system architectures;high-level memory controller model;mobile devices;multiprocessor memory system;open-source gem5 simulation framework;parallel architectures;servers;Bandwidth;Computer architecture;Data models;Generators;Random access memory;Switches;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.17}
+}
+
+@InProceedings{hapmey_13,
+  Title                    = {{O}n-{T}he-{F}ly {C}omputing: {A} novel paradigm for individualized {IT} services},
+  Author                   = {Happe, Markus and Meyer auf der Heide, Friedhelm and Kling, Peter and Platzner, Marco and Plessl, Christian},
+  Booktitle                = {Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), 2013 IEEE 16th International Symposium on},
+  Year                     = {2013},
+  Month                    = {June},
+  Pages                    = {1-10},
+
+  Abstract                 = {In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and — in the light of rising energy cost — energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ISORC.2013.6913232},
+  File                     = {hapmey_13.pdf:hapmey_13.pdf:PDF},
+  Keywords                 = {CHPC},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.07}
+}
+
+@Article{hartom_09,
+  Title                    = {{P}roposal and {Q}uantitative {A}nalysis of the {CHS}tone {B}enchmark {P}rogram {S}uite for {P}ractical {C}-based {H}igh-level {S}ynthesis},
+  Author                   = {Yuko Hara and Hiroyuki Tomiyama and Shinya Honda and Hiroaki Takada},
+  Journal                  = {Journal of Information Processing},
+  Year                     = {2009},
+  Number                   = { },
+  Pages                    = {242-254},
+  Volume                   = {17},
+
+  Doi                      = {10.2197/ipsjjip.17.242},
+  Owner                    = {EFZ},
+  Timestamp                = {2016-09-05}
+}
+
+@Article{harmat_08,
+  Title                    = {{E}fficient {J}ump {A}head for {F}2-{L}inear {R}andom
+{N}umber {G}enerators},
+  Author                   = {Haramoto, Hiroshi and Matsumoto, Makoto and Nishimura, Takuji and Panneton, Fran{\c{c}}ois and L'Ecuyer, Pierre},
+  Journal                  = {INFORMS Journal on Computing},
+  Year                     = {2008},
+  Number                   = {3},
+  Pages                    = {385--390},
+  Volume                   = {20},
+
+  Doi                      = {10.1287/ijoc.1070.0251},
+  Owner                    = {weithoffer},
+  Timestamp                = {2013.12.18}
+}
+
+@InCollection{harnar_07,
+  Title                    = {{A}ccelerating {L}arge {G}raph {A}lgorithms on the {GPU} {U}sing {CUDA}},
+  Author                   = {Harish, Pawan and Narayanan, P.J.},
+  Booktitle                = {High Performance Computing (HiPC)},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2007},
+  Editor                   = {Aluru, Srinivas and Parashar, Manish and Badrinath, Ramamurthy and Prasanna, ViktorK.},
+  Pages                    = {197-208},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {4873},
+
+  Doi                      = {10.1007/978-3-540-77220-0_21},
+  ISBN                     = {978-3-540-77219-4},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.28},
+  Url                      = {http://dx.doi.org/10.1007/978-3-540-77220-0_21}
+}
+
+@InProceedings{harnou_14,
+  Title                    = {{S}ymbol-based {BP} detection for {MIMO} systems associated with non-binary {LDPC} codes},
+  Author                   = {A. Haroun and C. A. Nour and M. Arzel and C. Jego},
+  Booktitle                = {Wireless Communications and Networking Conference (WCNC), 2014 IEEE},
+  Year                     = {2014},
+  Month                    = {April},
+  Pages                    = {212-217},
+
+  Doi                      = {10.1109/WCNC.2014.6951949},
+  File                     = {harnou_14.pdf:harnou_14.pdf:PDF},
+  Keywords                 = {MIMO communication;belief maintenance;iterative decoding;maximum likelihood detection;parity check codes;radio receivers;EXIT charts;MIMO-BP detector;NB-LDPC decoder;belief propagation algorithm;digital communication systems;error correction performance;extrinsic information transfer charts;high-order constellation demapper;iterative receiver;maximum likelihood detector;multiple-input multiple-output detector;nonbinary low-density parity-check decoder;receiver latency;Decoding;Detectors;Iterative decoding;MIMO;Schedules;Silicon},
+  Owner                    = {MH},
+  Timestamp                = {2016-03-09}
+}
+
+@Book{har_15,
+  Title                    = {{T}rading and {E}lectronic {M}arkets: {W}hat {I}nvestment {P}rofessionals {N}eed to {K}now},
+  Author                   = {Larry Harris},
+  Publisher                = {CFA Institute Research Foundation},
+  Year                     = {2015},
+
+  Address                  = {Charlottesville, USA},
+  Month                    = {Oct},
+  Number                   = {4},
+  Series                   = {Research Foundation Publications},
+  Volume                   = {2015},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.06}
+}
+
+@Book{har_03,
+  Title                    = {{T}rading and {E}xchanges: {M}arket {M}icrostructure for {P}ractitioners},
+  Author                   = {Larry Harris},
+  Publisher                = {Oxford University Press},
+  Year                     = {2003},
+
+  Address                  = {New York, USA},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.06}
+}
+
+@InCollection{harbuc_05,
+  Title                    = {{GPU} {F}low-{C}ontrol {I}dioms},
+  Author                   = {Mark Harris and Ian Buck},
+  Booktitle                = {GPU gems 2: programming techniques for high-performance graphics and general-purpose computation},
+  Publisher                = {Addison-Wesley},
+  Year                     = {2005},
+  Chapter                  = {34},
+  Editor                   = {Matt Pharr and Randima Fernando},
+  Month                    = {Apr.},
+  Pages                    = {547--556},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.27}
+}
+
+@TechReport{har_89,
+  Title                    = {{F}ault {T}olerant {VLSI} {D}esign {U}sing {E}rror {C}orrecting {C}odes, {F}inal {T}echnical {R}eport},
+  Author                   = {Hartmann, C. R. P. Lala, P. K. Ali, A. M.},
+  Institution              = {Syracuse University},
+  Year                     = {1989},
+  Month                    = feb,
+
+  File                     = {har_89.pdf:har_89.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2011.08.04}
+}
+
+@InProceedings{harbak_10,
+  Title                    = {{M}ain {M}emory with {P}roximity {C}ommunication: {A} {W}ide {I}/{O} {DRAM} {A}rchitecture},
+  Author                   = {Q. Harvard and R. J. Baker and R. Drost},
+  Booktitle                = {2010 IEEE Workshop on Microelectronics and Electron Devices},
+  Year                     = {2010},
+  Month                    = {April},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/WMED.2010.5453754},
+  ISSN                     = {1947-3834},
+  Keywords                 = {DRAM chips;I/O DRAM architecture;computer system;dynamic random access memory;efficiency 59.9 percent;main memory system;power consumption;proximity communication;storage capacity 4 Gbit;Bandwidth;Capacitors;Circuits;Computer architecture;Delay;Energy consumption;Manufacturing processes;Power engineering computing;Random access memory;Sun},
+  Owner                    = {MJ},
+  Timestamp                = {2016-08-10}
+}
+
+@InProceedings{hasamb_99,
+  Title                    = {{S}ingle event transients in deep submicron {CMOS}},
+  Author                   = {Hass, K. J. and Ambles, J. W.},
+  Booktitle                = {Proc. 42nd Midwest Symposium on Circuits and Systems},
+  Year                     = {1999},
+  Month                    = aug,
+  Pages                    = {122--125},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/MWSCAS.1999.867224},
+  File                     = {hasamb_99.pdf:hasamb_99.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{haskau_15,
+  Title                    = {{R}everse-engineering embedded memory controllers through latency-based analysis},
+  Author                   = {Mohamed Hassan and A. M. Kaushik and H. Patel},
+  Booktitle                = {21st IEEE Real-Time and Embedded Technology and Applications Symposium},
+  Year                     = {2015},
+  Month                    = {April},
+  Pages                    = {297-306},
+
+  Doi                      = {10.1109/RTAS.2015.7108453},
+  ISSN                     = {1545-3421},
+  Keywords                 = {DRAM chips;reverse engineering;storage management;DRAM MC;DRAM memory controllers;address mapping scheme;command arbitration scheme;embedded memory controllers;latency-based analysis;microarchitecture simulation framework;microbenchmark;page policies;reverse-engineering;worst-case bound;Data transfer;Delays;Hardware;Radiation detectors;Random access memory;Software},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-23}
+}
+
+@Article{haspat_18,
+  Title                    = {{MCX}plore: {A}utomating the {V}alidation {P}rocess of {DRAM} {M}emory {C}ontroller {D}esigns},
+  Author                   = {M. {Hassan} and H. {Patel}},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2018},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {1050-1063},
+  Volume                   = {37},
+
+  Doi                      = {10.1109/TCAD.2017.2705123},
+  ISSN                     = {0278-0070},
+  Keywords                 = {DRAM chips;formal specification;program testing;MCXplore;validation process;DRAM memory controller designs;automated framework;memory controllers;formal models;memory requests;NuSMV model-checker;test templates;memory tests;regression test suites;Random access memory;Space exploration;Model checking;Computational modeling;Delays;Benchmark testing;Dynamic random access memory (DRAM);memory controller (MC);model checking;testing;validation;verification},
+  Owner                    = {MJ},
+  Timestamp                = {2019-05-27}
+}
+
+@InProceedings{haspat_16,
+  Title                    = {{MCX}plore: {A}n automated framework for validating memory controller designs},
+  Author                   = {M. Hassan and H. Patel},
+  Booktitle                = {2016 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2016},
+  Month                    = {March},
+  Pages                    = {1357-1362},
+
+  Keywords                 = {DRAM chips;formal specification;integrated circuit design;regression analysis;temporal logic;DRAM MC;DRAM command interaction;MCXplore;NuSMV model-checker;automated framework;dynamic random access memory controllers;formal models;hard-to-detect timing violations;memory controller designs;open-source framework;regression tests;temporal logic specifications;Benchmark testing;Delays;Model checking;Random access memory;Space exploration;Switches},
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-15}
+}
+
+@Misc{hascan11,
+  Title                    = {{C}an {A}gile {D}evelopment {W}ork in {H}ardware {P}rojects?},
+
+  Author                   = {Shane Hastie},
+  HowPublished             = {InfoQ, \url{http://www.infoq.com/news/2011/10/agile-hardware-values}},
+  Month                    = oct,
+  Note                     = {last access 2015-06-26},
+  Year                     = {2011},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.26}
+}
+
+@Book{haudeh_08,
+  Title                    = {{R}econfigurable {C}omputing: {T}he {T}heory and {P}ractice of {FPGA}-based {C}omputation},
+  Author                   = {Hauck, S. and DeHon, A.},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2008},
+  Series                   = {Systems on Silicon Series},
+
+  ISBN                     = {9780123705228},
+  Lccn                     = {2007029773},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://books.google.de/books?id=vYgweLqkRzMC}
+}
+
+@InProceedings{hau_01,
+  Title                    = {{Integrated Circuits for Next Generation Wireless Systems}},
+  Author                   = {J. Hausner},
+  Booktitle                = {Proceedings of the 27th European Solid-State Circuits Conference (ESSCIRC 2001)},
+  Year                     = {2001},
+
+  Address                  = {Villach, Austria},
+  Month                    = sep,
+  Pages                    = {26--29},
+
+  File                     = {hau_01.pdf:hau_01.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{hawfor_18,
+  Title                    = {{F}ord wants to be the self-driving {OS} for the future of transportation},
+
+  Author                   = {Hawkins, Andrew J.},
+  HowPublished             = {https://www.theverge.com/2018/1/9/16868814/ford-self-driving-autonomous-vehicle-ces-2018},
+  Month                    = {January},
+  Year                     = {2018},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-01}
+}
+
+@InProceedings{haypol_07,
+  Title                    = {{A}n {A}nalysis {F}ramework for {T}ransient-{E}rror {T}olerance},
+  Author                   = {Hayes, J. P. and Polian, I. and Becker, B. },
+  Booktitle                = {Proc. 25th IEEE VLSI Test Symposium},
+  Year                     = {2007},
+  Month                    = may,
+  Pages                    = {249--255},
+
+  Doi                      = {10.1109/VTS.2007.13},
+  File                     = {haypol_07.pdf:haypol_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.20}
+}
+
+@InProceedings{hazkar_03,
+  Title                    = {{N}eutron soft error rate measurements in a 90-nm {CMOS} process and scaling trends in {SRAM} from 0.25-m to 90-nm generation},
+  Author                   = {Hazucha, P. and Karnik, T. and Maiz, J. and Walstra, S. and Bloechel, B. and Tschanz, J. and Dermer, G. and Hareland, S. and Armstrong, P. and Borkar, S.},
+  Booktitle                = {Proc. IEDM '03 Technical Digest Electron Devices Meeting IEEE International},
+  Year                     = {2003},
+  Month                    = dec,
+  Pages                    = {21.5.1--21.5.4},
+
+  Doi                      = {10.1109/IEDM.2003.1269336},
+  File                     = {hazkar_03.pdf:hazkar_03.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{hecos_03,
+  Title                    = {{Joint Interleaver Design for Low Complexity Multiple Turbo Codes}},
+  Author                   = {C. He and D.J. Costello and A. Huebner and K.S. Zigangirov},
+  Booktitle                = {Proc. of the 41th Allerton Conference on Communication, Control and Computing},
+  Year                     = {2003},
+
+  Address                  = {Illinois, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hewan_10,
+  Title                    = {{M}emory-reduced {MAP} decoding for double-binary convolutional {T}urbo code},
+  Author                   = {Jinjin He and Zhongfeng Wang and Huaping Liu},
+  Booktitle                = {Proc. IEEE Int Circuits and Systems (ISCAS) Symp},
+  Year                     = {2010},
+  Pages                    = {469--472},
+
+  Doi                      = {10.1109/ISCAS.2010.5537637},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{heluo_05,
+  Title                    = {{A} novel storage scheme for parallel turbo decoder},
+  Author                   = {Xiang He and HanWen Luo and HaiBin Zhang},
+  Booktitle                = {Proc. VTC-2005-Fall Vehicular Technology Conference 2005 IEEE 62nd},
+  Year                     = {2005},
+  Month                    = sep,
+  Pages                    = {1950--1954},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/VETECF.2005.1558448},
+  File                     = {heluo_05.pdf:heluo_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{heroy_05,
+  Title                    = {{H}igh-speed and low-power design of parallel turbo decoder},
+  Author                   = {Zhiyong He and Roy, S. and Fortier, P.},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2005},
+  Year                     = {2005},
+  Month                    = may,
+  Pages                    = {6018--6021},
+
+  Doi                      = {10.1109/ISCAS.2005.1466011},
+  File                     = {heroy_05.pdf:heroy_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Review                   = {MM: PII used},
+  Timestamp                = {2009.03.17}
+}
+
+@Article{heagon_16,
+  Title                    = {{A}n {O}verview of {S}ignal {P}rocessing {T}echniques for {M}illimeter {W}ave {MIMO} {S}ystems},
+  Author                   = {R. W. Heath and N. González-Prelcic and S. Rangan and W. Roh and A. M. Sayeed},
+  Journal                  = {IEEE Journal of Selected Topics in Signal Processing},
+  Year                     = {2016},
+
+  Month                    = {April},
+  Number                   = {3},
+  Pages                    = {436-453},
+  Volume                   = {10},
+
+  Doi                      = {10.1109/JSTSP.2016.2523924},
+  ISSN                     = {1932-4553},
+  Owner                    = {MH},
+  Timestamp                = {2017-05-30}
+}
+
+@Article{heapau_05,
+  Title                    = {{S}witching between diversity and multiplexing in {MIMO} systems},
+  Author                   = {Heath, R. W. and Paulraj, A. J.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2005},
+  Number                   = {6},
+  Pages                    = {962--968},
+  Volume                   = {53},
+
+  Abstract                 = {Multiple-input multiple-output (MIMO) wireless communication systems can offer high data rates through spatial multiplexing or substantial diversity using transmit diversity. In this letter, switching between spatial multiplexing and transmit diversity is proposed as a simple way to improve the diversity performance of spatial multiplexing. In the proposed approach, for a fixed rate, either multiplexing or diversity is chosen based on the instantaneous channel state and the decision is conveyed to the transmitter via a low-rate feedback channel. The minimum Euclidean distance at the receiver is computed for spatial multiplexing and transmit diversity and is used to derive the selection criterion. Additionally, the Demmel condition number of the matrix channel is shown to provide a sufficient condition for multiplexing to outperform diversity. Monte Carlo simulations demonstrate improvement over either multiplexing or diversity individually in terms of bit error rate.},
+  Doi                      = {10.1109/TCOMM.2005.849774},
+  File                     = {heapau_05.pdf:heapau_05.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {0090-6778},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@InProceedings{heapau_01,
+  Title                    = {{C}haracterization of {MIMO} channels for spatial multiplexing systems},
+  Author                   = {Heath, R. W. , Jr. and Paulraj, A.},
+  Booktitle                = {Proc. IEEE International Conference on Communications ICC 2001},
+  Year                     = {2001},
+  Pages                    = {591--595 vol.2},
+  Volume                   = {2},
+
+  Abstract                 = {Future wireless systems will employ multiple antennas at both transmitter and receiver to take advantage of large capacity gains. Two competing spatial modulation techniques for such systems are multiplexing, for high spectrum efficiency; and diversity, for high reliability. In this paper we show that the Demmel (1988) condition number of a MIMO (multiple-input multiple-output) channel characterizes its suitability for multiplexed transmission, over diversity transmission, based on a minimum Euclidean distance comparison. We examine the probability of obtaining channels suitable for multiplexing as a function of constellation, rate, and number of antennas, for i.i.d. flat-fading Rayleigh matrix channels},
+  Doi                      = {10.1109/ICC.2001.937008},
+  File                     = {heapau_01.pdf:heapau_01.pdf:PDF},
+  Grade                    = {4},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Review                   = {CG:
+Gelesen am:
+17. 10. 2008
+MIMO channels are characterized according to their suitability for spatial multiplexing or MIMO diversity. Probabilities are derived for multiplexing preferred channels dependent on bits per channel use and number of antennas.},
+  Timestamp                = {2008.10.10}
+}
+
+@Book{heewic_99,
+  Title                    = {{T}urbo {C}oding},
+  Author                   = {C. Heegard and Stephen B. Wicker},
+  Publisher                = {Kluwer Academic Publisher},
+  Year                     = {1999},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hegsha_01,
+  Title                    = {{S}oft digital signal processing},
+  Author                   = {Hegde, R. and Shanbhag, N.R.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2001},
+
+  Month                    = dec,
+  Number                   = {6},
+  Pages                    = {813--823},
+  Volume                   = {9},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Shanbhag
+- VOS, ANT?},
+  Doi                      = {10.1109/92.974895},
+  File                     = {hegsha_01.pdf:hegsha_01.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{hegsha_04,
+  Title                    = {{A voltage overscaled low-power digital filter IC}},
+  Author                   = {R. Hegde and Shanbhag, N. R.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2004},
+
+  Month                    = feb,
+  Pages                    = {388-391},
+  Volume                   = {39},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Kurdahi
+- Turbo, Simulation Input Memories},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{hehhub_10a,
+  Title                    = {{M}ultiple-bases belief-propagation decoding of high-density cyclic codes},
+  Author                   = {Hehn, T. and Huber, J. and Milenkovic, O. and Laendner, S.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2010},
+  Number                   = {1},
+  Pages                    = {1--8},
+  Volume                   = {58},
+
+  Doi                      = {10.1109/TCOMM.2010.01.070468},
+  File                     = {hehhub_10a.pdf:hehhub_10a.pdf:PDF},
+  Keywords                 = {MBBP},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.07}
+}
+
+@Misc{hehhub_08,
+  Title                    = {{M}ultiple-{B}ases {B}elief-{P}ropagation with {L}eaking for {D}ecoding of {M}oderate-{L}ength {B}lock {C}odes},
+
+  Author                   = {Hehn, Thorsten and Huber, Johannes B. and He, Pei and Laendner, Stefan},
+  Note                     = {Source and Channel Coding (SCC), 2008 7th International ITG Conference on},
+  Year                     = {2008},
+
+  File                     = {hehhub_08.pdf:hehhub_08.pdf:PDF},
+  Keywords                 = {MBBP, BCH},
+  Owner                    = {Scholl},
+  Pages                    = {1--6},
+  Review                   = {MBBP mit Leaking Algorithmus},
+  Timestamp                = {2011.07.07}
+}
+
+@Misc{Hehn2008,
+  Title                    = {{M}ultiple-{B}ases {B}elief-{P}ropagation with {L}eaking for {D}ecoding of {M}oderate-{L}ength {B}lock {C}odes},
+
+  Author                   = {Hehn, Thorsten and Huber, Johannes B. and He, Pei and Laendner, Stefan},
+  Note                     = {Source and Channel Coding (SCC), 2008 7th International ITG Conference on},
+  Year                     = {2008},
+
+  File                     = {hehhub_08.pdf:hehhub_08.pdf:PDF},
+  Keywords                 = {MBBP, BCH},
+  Owner                    = {Scholl},
+  Pages                    = {1--6},
+  Review                   = {MBBP mit Leaking Algorithmus},
+  Timestamp                = {2011.07.07}
+}
+
+@InProceedings{hehhub_10,
+  Title                    = {{I}mproved iterative decoding of {LDPC} codes from the {IEEE} {W}i{MAX} standard},
+  Author                   = {Hehn, T. and Huber, J. B. and Laendner, S.},
+  Booktitle                = {Proc. Int Source and Channel Coding (SCC) ITG Conf},
+  Year                     = {2010},
+  Pages                    = {1--6},
+
+  File                     = {hehhub_10.pdf:hehhub_10.pdf:PDF},
+  Keywords                 = {MBBP, LDPC},
+  Owner                    = {Scholl},
+  Review                   = {MBBP angewedet auf Wimax LDPC Codes},
+  Timestamp                = {2011.07.07}
+}
+
+@InProceedings{hehhub_07,
+  Title                    = {{M}ultiple-{B}ases {B}elief-{P}ropagation for {D}ecoding of {S}hort {B}lock {C}odes},
+  Author                   = {Hehn, Thorsten and Huber, Johannes B. and Laendner, Stefan and Milenkovic, Olgica},
+  Booktitle                = {Proc. IEEE Int. Symp. Information Theory ISIT 2007},
+  Year                     = {2007},
+  Pages                    = {311--315},
+
+  Doi                      = {10.1109/ISIT.2007.4557244},
+  File                     = {hehhub_07.pdf:hehhub_07.pdf:PDF},
+  Keywords                 = {MBBP, BCH},
+  Owner                    = {Scholl},
+  Review                   = {Urpaper für den Mutiple Bases Belief Propagation},
+  Timestamp                = {2011.07.07}
+}
+
+@InProceedings{hei_05,
+  Title                    = {{SEU} tolerant device, circuit and processor design},
+  Author                   = {Heidergott, W. },
+  Booktitle                = {Proc. 42nd Design Automation Conf},
+  Year                     = {2005},
+  Pages                    = {5--10},
+
+  Doi                      = {10.1109/DAC.2005.193763},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{heinie_06,
+  Title                    = {{S}oft-{E}rror {R}ate {T}esting of {D}eep-{S}ubmicron {I}ntegrated {C}ircuits},
+  Author                   = {Heijmen, T. and Nieuwland, A. },
+  Booktitle                = {Proc. Eleventh IEEE European Test Symp. ETS '06},
+  Year                     = {2006},
+  Pages                    = {247--252},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Technology},
+  Doi                      = {10.1109/ETS.2006.42},
+  File                     = {heinie_06.pdf:heinie_06.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InCollection{heiweh_99,
+  Title                    = {{Embedded DRAM Applications and Challenges}},
+  Author                   = {S. Hein and N. Wehn},
+  Booktitle                = {{Embedded Memories in System Design --- From Technology to System Architecture}},
+  Publisher                = {Tutorial, Design Automation Conference 1999},
+  Year                     = {1999},
+
+  Address                  = {New Orleans},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{heiweh_98,
+  Title                    = {{Embedded DRAM Applications and Challenges}},
+  Author                   = {S. Hein and N. Wehn},
+  Booktitle                = {{Embedded Memories in System Design --- From Technology to System Architecture}},
+  Publisher                = {Tutorial, International Conference on Computer-Aided Design 1998},
+  Year                     = {1998},
+
+  Address                  = {San Jose, CA},
+  Month                    = nov,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hei_01,
+  Title                    = {{M}ultilevel {M}onte {C}arlo methods},
+  Author                   = {Stefan Heinrich},
+  Journal                  = {Large-Scale Scientific Computing},
+  Year                     = {2001},
+  Pages                    = {58--67},
+
+  Cds_grade                = {0},
+  File                     = {hei_01.pdf:hei_01.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Springer},
+  Timestamp                = {2012.09.07}
+}
+
+@Article{hei_98,
+  Title                    = {{M}onte {C}arlo {C}omplexity of {G}lobal {S}olution of {I}ntegral {E}quations},
+  Author                   = {S. Heinrich},
+  Journal                  = {Journal of Complexity},
+  Year                     = {1998},
+  Number                   = {2},
+  Pages                    = {151 - 175},
+  Volume                   = {14},
+
+  Doi                      = {http://dx.doi.org/10.1006/jcom.1998.0471},
+  File                     = {hei_98.pdf:hei_98.pdf:PDF},
+  ISSN                     = {0885-064X},
+  Keywords                 = {finance}
+}
+
+@Article{hek_89,
+  Title                    = {{A}n {A}lternative to {M}etric {R}escaling in {V}iterbi {D}ecoders},
+  Author                   = {Hekstra, A. P.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1989},
+  Number                   = {11},
+  Pages                    = {1220--1222},
+  Volume                   = {37},
+
+  Abstract                 = {In the Viterbi algorithm, the negative log-likelihood estimates, accumulated distances, or path metrics are unboundedly increasing functions of time. For implementation, all variables must be confined to a finite range. The following properties of the Viterbi algorithm can be exploited for this purpose: (1) path selection depends only on differences of metrics; an (2) the difference between metrics is bounded. In the rescaling scheme, at each iteration the minimum metric is subtracted from all metrics. The use of two's complement arithmetic is proposed as an alternative to the rescaling method. This scheme avoids any kind of rescaling subtractions. Obvious advantages in implementation are hardware savings and a speedup inside the metric update loop, which is critical to the decoder's computational throughput},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/26.46516},
+  File                     = {hek_89.pdf:hek_89.pdf:PDF},
+  Grade                    = {4},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Convolutional},
+  Owner                    = {Gimmler},
+  Review                   = {CG:
+Gelesen: 19.11.2008
+modulo arithmetic for viterbi algorithm},
+  Timestamp                = {2008.11.18}
+}
+
+@InProceedings{helwun_99,
+  Title                    = {{E}rror detecting refreshment for embedded {DRAM}s},
+  Author                   = {Hellebrand, S. and Wunderlich, H. J. and Ivaniuk, A. and Klimets, Y. and Yarmolik, V. N.},
+  Booktitle                = {Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)},
+  Year                     = {1999},
+  Pages                    = {384-390},
+
+  Doi                      = {10.1109/VTEST.1999.766693},
+  ISSN                     = {1093-0167},
+  Keywords                 = {DRAM chips;data compression;error detection;integrated circuit testing;memory architecture;embedded DRAMs;error detecting refreshment;error detection latency;high error coverage;low hardware costs;memory contents;online consistency checking;periodic refresh operation;precomputed reference characteristic;test characteristic;Built-in self-test;Code standards;Computer architecture;Computer errors;Concurrent computing;Delay;Memory architecture;Random access memory;Test pattern generators;Testing},
+  Owner                    = {MJ},
+  Timestamp                = {2017-01-23}
+}
+
+@Article{heljac_71,
+  Title                    = {{Viterbi decoding for satellite and space communication}},
+  Author                   = {Heller, J. A. and Jacobs, I. M.},
+  Journal                  = {IEEE Transactions on Communication Technology},
+  Year                     = {1971},
+
+  Month                    = oct,
+  Pages                    = {835--848},
+  Volume                   = {19},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Conference{helros_14,
+  Title                    = {{E}fficient {M}aximum-{L}ikelihood {D}ecoding of {L}inear {B}lock {C}odes on {B}inary {M}emoryless {C}hannels},
+  Author                   = {Helmling, M. and Rosnes, E. and Ruzika S. and Scholl, S.},
+  Booktitle                = {In Proc. IEEE International Symposium on Information Theory},
+  Year                     = {2014},
+
+  Keywords                 = {LPDecoding, LDPC, InfTheory},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.08}
+}
+
+@Misc{helsch_18,
+  Title                    = {{D}atabase of {C}hannel {C}odes and {ML} {S}imulation {R}esults},
+
+  Author                   = {Helmling, Michael and Scholl, Stefan and Gensheimer, Florian and Dietz, Tobias and Kraft, Kira and Ruzika, Stefan and Wehn, Norbert},
+  HowPublished             = {\url{www.uni-kl.de/channel-codes}},
+  Year                     = {2018},
+
+  Owner                    = {kraft},
+  Timestamp                = {2018.06.08}
+}
+
+@Conference{helsch_11,
+  Title                    = {{M}athematical {O}ptimization {B}ased {C}hannel {C}oding: {C}urrent {A}chievements and {F}uture {C}hallenges},
+  Author                   = {Michael Helmling and Stefan Scholl and Akin Tanatmis},
+  Booktitle                = {Young Researcher's Symposium (YRS) 2011, Proceedings on},
+  Year                     = {2011},
+  Organization             = {Center for Mathematical and Computational Modelling (CM)\textsuperscript{2}},
+  Pages                    = {16-21},
+  Publisher                = {(CM)\textsuperscript{2} Nachwuchsring},
+
+  Abstract                 = {Channel coding and mathematical optimization---two omnipresent branches of science which heavily influence our everyday life,
+which is certainly unimaginable without the epochal achievements of each of the two disciplines since they affect nearly every communication system as well as every transportation, manufacturing, and organization process. The following report is dedicated to some of the achievements of a research project decisively influenced by a cooperative interplay of these two disciplines.},
+  File                     = {helsch_11.pdf:helsch_11.pdf:PDF},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.05.17}
+}
+
+@InProceedings{heller_12,
+  Title                    = {{S}tochastic chase decoder for reed-solomon codes},
+  Author                   = {Heloir, R. and Leroux, C. and Hemati, S. and Arzel, M. and Gross, W.J.},
+  Booktitle                = {New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International},
+  Year                     = {2012},
+  Month                    = {june},
+  Pages                    = {5 -8},
+
+  Doi                      = {10.1109/NEWCAS.2012.6328942},
+  File                     = {heller_12.pdf:heller_12.pdf:PDF},
+  Keywords                 = {Reed-Solomon code;Virtex-5 FPGA;bit rate 800 Mbit/s;flexible architecture;soft-decision Reed-Solomon decoder;stochastic chase algorithm;stochastic chase decoder;Reed-Solomon codes;decoding;stochastic processes;},
+  Owner                    = {Scholl},
+  Review                   = {ein echter Soft RS Decoder},
+  Timestamp                = {2012.12.10}
+}
+
+@Misc{hemwill14,
+  Title                    = {{W}ill 2015 {B}e the {Y}ear of the {FPGA}?},
+
+  Author                   = {Nicole Hemsoth},
+  HowPublished             = {HPCwire, \url{http://www.hpcwire.com/2014/09/04/will-2015-year-fpga/}},
+  Month                    = sep,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2014},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Article{hen_16,
+  Title                    = {{A}pproximate {C}omputing: {S}olving {C}omputing's {I}nefficiency {P}roblem?},
+  Author                   = {Henkel, J.},
+  Journal                  = {IEEE Design and Test},
+  Year                     = {2016},
+
+  Month                    = {February},
+  Number                   = {1},
+  Volume                   = {33},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-05}
+}
+
+@InProceedings{henbau_11_version_for_ARCS_paper,
+  Title                    = {{D}esign and architectures for dependable embedded systems},
+  Author                   = {Henkel, J. and Bauer, L. and Becker, J. and Bringmann, O. and Brinkschulte, U. and Chakraborty, S. and Engel, M. and Ernst, R. and Hartig, H. and Hedrich, L. and Herkersdorf, A and Kapitza, R. and Lohmann, D. and Marwedel, P. and Platzner, M. and Rosenstiel, W. and Schlichtmann, U. and Spinczyk O. and Tahoori, M. and Teich, J. and Wehn, N. and Wunderlich, H.-J.},
+  Booktitle                = {Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2011 Proceedings of the 9th International Conference on},
+  Year                     = {2011},
+  Organization             = {IEEE},
+  Pages                    = {69--78}
+}
+
+@InProceedings{henbau_11,
+  Title                    = {{D}esign and architectures for dependable embedded systems},
+  Author                   = {Henkel, J. and Bauer, L. and Becker, J. and Bringmann, O. and Brinkschulte, U. and Chakraborty, S. and Engel, M. and Ernst, R. and Hartig, H. and Hedrich, L. and others},
+  Booktitle                = {Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2011 Proceedings of the 9th International Conference on},
+  Year                     = {2011},
+  Organization             = {IEEE},
+  Pages                    = {69--78}
+}
+
+@InProceedings{henbau_13,
+  Title                    = {{R}eliable {O}n-chip {S}ystems in the {N}ano-era: {L}essons {L}earnt and {F}uture {T}rends},
+  Author                   = {Henkel, Jörg and Bauer, Lars and Dutt, Nikil and Gupta, Puneet and Nassif, Sani and Shafique, Muhammad and Tahoori, Mehdi and Wehn, Norbert},
+  Booktitle                = {Proceedings of the 50th Annual Design Automation Conference (DAC)},
+  Year                     = {2013},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {99:1--99:10},
+  Publisher                = {ACM},
+  Series                   = {DAC '13},
+
+  Acmid                    = {2488857},
+  Articleno                = {99},
+  Doi                      = {10.1145/2463209.2488857},
+  ISBN                     = {978-1-4503-2071-9},
+  Keywords                 = {AGWehn},
+  Location                 = {Austin, Texas},
+  Numpages                 = {10},
+  Owner                    = {CDS},
+  Timestamp                = {2016-02-17},
+  Url                      = {http://doi.acm.org/10.1145/2463209.2488857}
+}
+
+@InProceedings{henkhd_15,
+  Title                    = {{N}ew trends in dark silicon},
+  Author                   = {Henkel, J. and Khdr, H. and Pagani, S. and Shafique, M.},
+  Booktitle                = {Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE},
+  Year                     = {2015},
+  Pages                    = {1--6},
+
+  Doi                      = {10.1145/2744769.2747938},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.08.26},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7167304}
+}
+
+@Book{henpat_12,
+  Title                    = {{C}omputer {A}rchitecture: {A} {Q}uantitative {A}pproach},
+  Author                   = {Hennessy, John L. and Patterson, David A.},
+  Publisher                = {Morgan Kaufmann Publishers Inc.},
+  Year                     = {2012},
+
+  Address                  = {San Francisco, CA, USA},
+  Edition                  = {5th},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.03.06}
+}
+
+@InBook{henpat_96,
+  Title                    = {{Computer Architecture A Quantitive Approach}},
+  Author                   = {J. L. Hennessy and D. A. Patterson},
+  Publisher                = {Morgan Kauffmann Publishers, Inc.},
+  Year                     = {1996},
+
+  Address                  = {San Francisco, California, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{heo_03,
+  Title                    = {{Analysis of scaling soft information on low density parity check code}},
+  Author                   = {J. Heo},
+  Journal                  = {Electronics Letters},
+  Year                     = {2003},
+
+  Month                    = jan,
+  Number                   = {2},
+  Pages                    = {219--221},
+  Volume                   = {39},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{heochu_05,
+  Title                    = {{Optimization of Scaling Soft Information in Iterative Decoding via Density Evolution Methods}},
+  Author                   = {J. Heo and Chugg, K. M.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2005},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {957--961},
+  Volume                   = {53},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{herkis_07,
+  Title                    = {{XEEMU}: {A}n {I}mproved {XScale} {P}ower {S}imulator},
+  Author                   = {Z. Herczeg and Á. Kiss and D. Schmidt and N. Wehn and T. Gyimóthy},
+  Booktitle                = {Proc. 2007 International Workshop on Power and Timing Modeling, Optimization and Simulation {PATMOS 2007}},
+  Year                     = {2007},
+
+  Address                  = {Göteborg, Sweden},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hersch_09,
+  Title                    = {{E}nergy {S}imulation of {E}mbedded {XScale} systems with {XEEMU}},
+  Author                   = {Zoltán Herczeg and Daniel Schmidt and Ákos Kiss and Norbert Wehn and Tibor Gyimóthy},
+  Journal                  = {Journal of Embedded Computing},
+  Year                     = {2009},
+  Number                   = {3},
+  Pages                    = {209--219},
+  Volume                   = {3},
+
+  Address                  = {Amsterdam, The Netherlands},
+  ISSN                     = {1740-4460},
+  Owner                    = {schmidt},
+  Publisher                = {{IOS} Press},
+  Timestamp                = {2009.07.16}
+}
+
+@Article{herali_14,
+  Title                    = {{R}esilience {A}rticulation {P}oint ({RAP}): {C}ross-layer dependability modeling for nanometer system-on-chip resilience},
+  Author                   = {Herkersdorf, Andreas and Aliee, Hananeh and Engel, Michael and Gla{\ss}, Michael and Gimmler-Dumont, Christina and Henkel, J{\"o}rg and Kleeberger, Veit B and Kochte, Michael A and K{\"u}hn, Johannes M and Mueller-Gritschneder, Daniel and Wehn, Norbert and others},
+  Journal                  = {Microelectronics Reliability},
+  Year                     = {2014},
+  Number                   = {6},
+  Pages                    = {1066--1074},
+  Volume                   = {54},
+
+  Owner                    = {schlaefer},
+  Publisher                = {Elsevier},
+  Timestamp                = {2015.09.16}
+}
+
+@InProceedings{herkle_13,
+  Title                    = {{C}ross-{L}ayer {D}ependability {M}odeling and {A}bstraction in {S}ystems on {C}hip},
+  Author                   = {Andreas Herkersdorf and Veit Kleeberger and Sani Nassif and Ulf Schlichtmann and Christian Weis and Norbert Wehn},
+  Booktitle                = {Proc. 9th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)},
+  Year                     = {2013},
+  Month                    = {March},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.05.21}
+}
+
+@InProceedings{herweh_91,
+  Title                    = {{ Verifikation mikroelektronischer Systeme zur Prozessteuerung durch schnelle Prototyprealisierung}},
+  Author                   = {H.~Herpel and N.~Wehn and M.~Glesner},
+  Booktitle                = { Fortschritte in der Simulationstechnik},
+  Year                     = {1991},
+  Pages                    = {567--572},
+  Publisher                = {Vieweg-Verlag},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{herweh_93,
+  Title                    = {{A Reconfigurable Computer for Embedded Control Applications}},
+  Author                   = {Herpel, H.~J. and Wehn, N. and Gasteier, M. and Glesner, M.},
+  Booktitle                = {Proc. IEEE Workshop on FPGAs for Custom Computing Machines},
+  Year                     = {1993},
+  Month                    = apr,
+  Pages                    = {111-120},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{herweh_94,
+  Title                    = {{Computer Aided Prototyping of Application Specific Embedded Controllers}},
+  Author                   = {H.-J.~Herpel and N.~Wehn and M.~Glesner},
+  Booktitle                = {Codesign: Computer-Aided Software/Hardware Engineering},
+  Publisher                = {IEEE PRESS},
+  Year                     = {1994},
+  Chapter                  = {21},
+  Editor                   = {Jerzy Rozenblit and Klaus Buchenrieder},
+  Pages                    = {425--442},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTherrm14,
+  Title                    = {{I}teration {C}ontrol {T}echniques in {MIMO}-{BICM} {S}ystem for {C}omplexity {R}eduction and {D}etection of {H}ardware {E}rrors},
+  Author                   = {Matthias Herrmann},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+  Type                     = {Diploma Thesis},
+
+  Owner                    = {Schläfer},
+  Timestamp                = {2014.07.23}
+}
+
+@Article{Herzet2006,
+  Title                    = {{C}ode-aided synchronization for digital burst communications},
+  Author                   = {Herzet, Cédric},
+  Year                     = {2006},
+
+  Abstract                 = {This thesis deals with the synchronization of digital communication systems. Synchronization (from the Greek syn (together) and chronos (time)) denotes the task of making two systems running at the same time. In communication systems, the synchronization of the transmitter and the receiver requires to accurately estimate a number of parameters such as the carrier frequency and phase offsets, the timing epoch... In the early days of digital communications, synchronizers used to operate in either data-aided (DA) or non-data-aided (NDA) modes. However, with the recent advent of powerful coding techniques, these conventional synchronization modes have been shown to be unable to properly synchronize state-of-the-art receivers. In this context, we investigate in this thesis a new family of synchronizers referred to as code-aided (CA) synchronizers. The idea behind CA synchronization is to take benefit from the structure of the code used to protect the data to improve the estimation quality achieved by the synchronizers. In a first part of the thesis, we address the issue of turbo synchronization, i.e., the iterative synchronization of continuous parameters. In particular, we derive several mathematical frameworks enabling a systematic derivation of turbo synchronizers and a deeper understanding of their behavior. In a second part, we focus on the so-called CA hypothesis testing problem. More particularly, we derive optimal solutions to deal with this problem and propose efficient implementations of the proposed algorithms. Finally, in a last part of this thesis, we derive theoretical lower bounds on the performance of turbo synchronizers.},
+  Institution              = {BICFB - NDLTD Union Engine [http://edoc.bib.ucl.ac.be:80/DBUnion/ndltd/oaiunion.pl] (Belgium)},
+  Keywords                 = {Factor graph, EM algorithm, Synchronization, SP algorithm, Digital communications, Signal processing, Timing recovery, Turbo code, Phase recovery},
+  Location                 = {http://www.scientificcommons.org/8566190},
+  Owner                    = {scholl},
+  Publisher                = {Universite Catholique de Louvain},
+  Timestamp                = {2015.06.11},
+  Url                      = {http://edoc.bib.ucl.ac.be:81/ETD-db/collection/available/BelnUcetd-04182006-151245/}
+}
+
+@PhdThesis{Phdherze06,
+  Title                    = {{C}ode-aided {S}ynchronization for {D}igital {B}urst {C}ommunications},
+  Author                   = {Herzet, C.},
+  School                   = {available at http://www.tele.ucl.ac.be/digicom/herzet/index.php},
+  Year                     = {2006}
+}
+
+@Article{hernoe_07,
+  Title                    = {{Code-Aided Turbo Synchronization}},
+  Author                   = {Herzet, C. and Noels, N. and Lottici, V. and Wymeersch, H. and Luise, M. and Moeneclaey, M. and Vandendorpe, L.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2007},
+  Number                   = {6},
+  Pages                    = {1255--1271},
+  Volume                   = {95},
+
+  Abstract                 = {{<para> The introduction of turbo and low-density parity-check (LDPC) codes with iterative decoding that almost attain Shannon capacity challenges the synchronization subsystems of a data modem. Fast and accurate signal synchronization has to be performed at a much lower value of signal-to-noise ratio (SNR) than in previous less efficiently coded systems. The solution to this issue is developing specific synchronization techniques that take advantage of the presence of the channel code and of the iterative nature of decoding: the so-called <emphasis emphasistype="italic"> turbo-synchronization</emphasis> algorithms. The aim of this paper within this special issue devoted to the turbo principle is twofold: on the one hand, it shows how the many turbo-synchronization algorithms that have already appeared in the literature can be cast into a simple and rigorous theoretical framework. On the other hand, it shows the application of such techniques in a few simple cases, and evaluates improvement that can be obtained from them, especially in the low-SNR regime. </para>}},
+  Booktitle                = {Proceedings of the IEEE},
+  Citeulike-article-id     = {1727775},
+  Citeulike-linkout-0      = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=4282126},
+  Keywords                 = {synchronization, turbo},
+  Posted-at                = {2007-10-04 16:38:39},
+  Priority                 = {3}
+}
+
+@InProceedings{heswen_07,
+  Title                    = {{R}educed-complexity mimo detector with close-to ml error rate performance},
+  Author                   = {Hess, C. and Wenk, M. and Burg, A. and Luethi, P. and Studer, C. and Felber, N. and Fichtner, W.},
+  Booktitle                = {Proceedings of the 17th ACM Great Lakes symposium on VLSI},
+  Year                     = {2007},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {200--203},
+  Publisher                = {ACM},
+  Series                   = {GLSVLSI '07},
+
+  Acmid                    = {1228836},
+  Doi                      = {10.1145/1228784.1228836},
+  File                     = {heswen_07.pdf:heswen_07.pdf:PDF},
+  ISBN                     = {978-1-59593-605-9},
+  Keywords                 = {FSD, MIMO, VLSI, sphere decoding},
+  Location                 = {Stresa-Lago Maggiore, Italy},
+  Numpages                 = {4},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.09},
+  Url                      = {http://doi.acm.org/10.1145/1228784.1228836}
+}
+
+@InProceedings{hesjia_18,
+  Title                    = {{H}olistic {E}nergy {M}anagement with μ{P}rocessor {C}o-{O}ptimization in {F}ully {I}ntegrated {B}attery-{L}ess {I}o{T}s},
+  Author                   = {J. {Hester} and T. {Jia} and J. {Gu}},
+  Booktitle                = {2018 31st IEEE International System-on-Chip Conference (SOCC)},
+  Year                     = {2018},
+  Month                    = {Sep.},
+  Pages                    = {7-12},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8618523},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/SOCC.2018.8618523},
+  ISSN                     = {2164-1706},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;integrated circuit testing;Internet of Things;microprocessor chips;optimisation;solar cells;system-on-chip;voltage regulators;fully integrated battery-less IoT;energy efficiency;systematic optimization;power converter;battery-less energy harvesting operation;system-on-a-chip;microprocessor;on-chip power management modules;μProcessor Co-Optimization;holistic energy management;65nm fully integrated test chip;battery-less solar energy harvesting system;minimum energy point;operation strategy;optimal scheduling;microprocessors;on-chip voltage regulators;solar cells;power efficiency;size 65.0 nm;Regulators;Microprocessors;Photovoltaic cells;System-on-chip;Optimization;Energy harvesting;Voltage control;Low-power design;Power/energy/thermal aware architecture design;Multi-domain power/energy management},
+  Owner                    = {CCR}
+}
+
+@InProceedings{hessit_15,
+  Title                    = {{T}ragedy of the {C}oulombs: {F}ederating {E}nergy {S}torage for {T}iny, {I}ntermittently-{P}owered {S}ensors},
+  Author                   = {Hester, Josiah and Sitanayah, Lanny and Sorber, Jacob},
+  Booktitle                = {Proceedings of the 13th ACM Conference on Embedded Networked Sensor Systems},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {5--16},
+  Publisher                = {ACM},
+  Series                   = {SenSys '15},
+
+  Acmid                    = {2809707},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Hester:2015:TCF:2809695.2809707},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/2809695.2809707},
+  ISBN                     = {978-1-4503-3631-4},
+  Keywords                 = {TCS},
+  Keywords_original        = {capacitor, embedded system, energy harvesting, federated energy, task coupling},
+  Location                 = {Seoul, South Korea},
+  Numpages                 = {12},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/2809695.2809707}
+}
+
+@Article{hes_93,
+  Title                    = {{A} {C}losed-{F}orm {S}olution for {O}ptions with {S}tochastic {V}olatility with {A}pplications to {B}ond and {C}urrency {O}ptions},
+  Author                   = {Steven L. Heston},
+  Journal                  = {Review of Financial Studies},
+  Year                     = {1993},
+  Number                   = {2},
+  Pages                    = {327},
+  Volume                   = {6},
+
+  Abstract                 = {I use a new technique to derive a closed-form solution for the price of a European call option on an asset with stochastic volatility. The model allows arbitrary correlation between volatility and spot asset returns. I introduce stochastic interest rates and show how to apply the model to bond options and foreign currency options. Simulations show that correlation between volatility and the spot asset's price is important for explaining return skewness and strike-price biases in the Black-Scholes (1973) model. The solution technique is based on characteristic functions and can be applied to other problems},
+  Cds_grade                = {0},
+  Doi                      = {10.1093/rfs/6.2.327},
+  File                     = {hes_93.pdf:hes_93.pdf:PDF},
+  ISSN                     = {0893-9454},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Soc Financial Studies},
+  Timestamp                = {2010.11.23}
+}
+
+@InProceedings{hevwil_14,
+  Title                    = {{M}onitoring {H}ousehold {A}ctivities and {U}ser {L}ocation with a {C}heap, {U}nobtrusive {T}hermal {S}ensor {A}rray},
+  Author                   = {Hevesi, Peter and Wille, Sebastian and Pirkl, Gerald and Wehn, Norbert and Lukowicz, Paul},
+  Booktitle                = {Proceedings of the 2014 ACM International Joint Conference on Pervasive and Ubiquitous Computing},
+  Year                     = {2014},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {141--145},
+  Publisher                = {ACM},
+  Series                   = {UbiComp '14},
+
+  Acmid                    = {2636084},
+  Doi                      = {10.1145/2632048.2636084},
+  ISBN                     = {978-1-4503-2968-2},
+  Keywords                 = {AGWehn},
+  Location                 = {Seattle, Washington},
+  Numpages                 = {5},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.07},
+  Url                      = {http://doi.acm.org/10.1145/2632048.2636084}
+}
+
+@InBook{heytre_03,
+  Title                    = {{G}rid {C}omputing: {M}aking the {G}lobal {I}nfrastructure a {R}eality},
+  Author                   = {Hey, Tony and Trefethen, Anne},
+  Chapter                  = {The Data Deluge: An e-Science Perspective},
+  Pages                    = {809--824},
+  Publisher                = {John Wiley \& Sons, Ltd},
+  Year                     = {2003},
+
+  Abstract                 = {This chapter contains sections titled:
+* Introduction * The Imminent Scientific Data Deluge * Scientific Metadata, Information and Knowledge * Data Grids and Digital Libraries * Open Archives and Scholarly Publishing * Digital Preservation and Data Curation * Concluding Remarks * Acknowledgements * References},
+  Booktitle                = {Grid Computing},
+  Cds_grade                = {0},
+  Cds_keywords             = {data deluge},
+  Doi                      = {10.1002/0470867167.ch36},
+  ISBN                     = {9780470867167},
+  Url                      = {http://dx.doi.org/10.1002/0470867167.ch36}
+}
+
+@Article{hic_17,
+  Title                    = {{C}lank: {A}rchitectural {S}upport for {I}ntermittent {C}omputation},
+  Author                   = {Hicks, Matthew},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {2017},
+
+  Month                    = jun,
+  Number                   = {2},
+  Pages                    = {228--240},
+  Volume                   = {45},
+
+  Acmid                    = {3080238},
+  Address                  = {New York, NY, USA},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Hicks:2017:CAS:3140659.3080238},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3140659.3080238},
+  ISSN                     = {0163-5964},
+  Issue_date               = {May 2017},
+  Keywords                 = {TCS},
+  Keywords_original        = {Batteryless Devices, Energy Harvesting, Idempotence, Intermittent Computation},
+  Numpages                 = {13},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/3140659.3080238}
+}
+
+@Book{hig_02,
+  Title                    = {{A}ccuracy and {S}tability of {N}umerical {A}lgorithms},
+  Author                   = {Nicholas J. Higham},
+  Publisher                = {Society for Industrial and Applied Mathematics},
+  Year                     = {2002},
+  Edition                  = {2nd},
+  Note                     = {ISBN: 978-0898715217},
+
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.15}
+}
+
+@Article{hilmaz_13,
+  Title                    = {{D}istribution of random streams for simulation practitioners},
+  Author                   = {Hill, David R. C. and Mazel, Claude and Passerat-Palmbach, Jonathan and Traore, Mamadou K.},
+  Journal                  = {Concurrency and Computation: Practice and Experience},
+  Year                     = {2013},
+  Number                   = {10},
+  Pages                    = {1427--1442},
+  Volume                   = {25},
+
+  Abstract                 = {There is an increasing interest in the distribution of parallel random number streams in the high-performance computing community particularly, with the manycore shift. Even if we have at our disposal statistically sound random number generators according to the latest and thorough testing libraries, their parallelization can still be a delicate problem. Indeed, a set of recent publications shows it still has to be mastered by the scientific community. With the arrival of multi-core and manycore processor architectures on the scientist desktop, modelers who are non-specialists in parallelizing stochastic simulations need help and advice in distributing rigorously their experimental plans and replications according to the state of the art in pseudo-random numbers parallelization techniques. In this paper, we discuss the different partitioning techniques currently in use to provide independent streams with their corresponding software. In addition to the classical approaches in use to parallelize stochastic simulations on regular processors, this paper also presents recent advances in pseudo-random number generation for general-purpose graphical processing units. The state of the art given in this paper is written for simulation practitioners. Copyright © 2012 John Wiley & Sons, Ltd.},
+  Cds_grade                = {4},
+  Cds_keywords             = {RNG, PRNG, parallel stream, leap-frog, testing, TestU01, sequence splitting, random spacing, jump-ahead},
+  Cds_read                 = {2013-12-17},
+  Cds_review               = {good overview about how to generate parallel RN streams
+highlights the importance of good jump-ahead algorithms
+evaluation of MTGP with TestU01},
+  Doi                      = {10.1002/cpe.2942},
+  File                     = {hilmaz_13.pdf:hilmaz_13.pdf:PDF},
+  ISSN                     = {1532-0634},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.16},
+  Url                      = {http://dx.doi.org/10.1002/cpe.2942}
+}
+
+@Book{hil_14,
+  Title                    = {{P}ython for {F}inance: {A}nalyze {B}ig {F}inancial {D}ata},
+  Author                   = {Yves Hilpisch},
+  Publisher                = {O'Reilly Media, Inc.},
+  Year                     = {2014},
+  Edition                  = {1st},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22}
+}
+
+@Misc{hipsqlite15,
+  Title                    = {{SQL}ite},
+
+  Author                   = {Hipp, D. Richard and Kennedy, Dan and Mistachkin, Joe},
+  HowPublished             = {http://www.sqlite.org},
+  Year                     = {Last Access: 18.02.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.18}
+}
+
+@Article{hozha_12,
+  Title                    = {{O}ptimal {E}nergy {A}llocation for {W}ireless {C}ommunications {W}ith {E}nergy {H}arvesting {C}onstraints},
+  Author                   = {C. K. Ho and R. Zhang},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2012},
+
+  Month                    = {Sept},
+  Number                   = {9},
+  Pages                    = {4808-4818},
+  Volume                   = {60},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {6202352},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/TSP.2012.2199984},
+  ISSN                     = {1053-587X},
+  Keywords                 = {TCS},
+  Keywords_original        = {convex programming;dynamic programming;energy harvesting;energy storage;radiocommunication;battery;convex optimization;dynamic programming;energy harvesting constraint;energy storage;optimal energy allocation;point-to-point wireless communication;side information;staircase function;time selective fading;water level;water-filling energy allocation solution;Batteries;Energy harvesting;Resource management;Silicon;Throughput;Transmitters;Convex optimization;dynamic programming;energy harvesting;optimal policy;wireless communications},
+  Owner                    = {CCR}
+}
+
+@InProceedings{homai_01,
+  Title                    = {{The Future of Wires}},
+  Author                   = {R. Ho and K. Mai and M. Horowitz},
+  Booktitle                = {Proceedings of the IEEE. Volume:89, 2001},
+  Year                     = {2001},
+  Pages                    = {490--504},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hoc_04,
+  Title                    = {{A reduced complexity decoder architecture via layered decoding of LDPC codes}},
+  Author                   = {D.E. Hocevar},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems (SiPS '04)},
+  Year                     = {2004},
+
+  Address                  = {Austin,USA},
+  Month                    = oct,
+  Pages                    = {107--112},
+
+  File                     = {hoc_04.pdf:hoc_04.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hoc_03,
+  Title                    = {{LDPC Code Construction with Flexible Hardware Implementation}},
+  Author                   = {D.E. Hocevar},
+  Booktitle                = {Proc. 2003 International Conference on Communications (ICC '03)},
+  Year                     = {2003},
+  Month                    = may,
+  Pages                    = {2708--2712},
+
+  File                     = {hoc_03.pdf:hoc_03.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hocqui_89,
+  Title                    = {{S}ystolic {G}aussian elimination over {GF}(p) with partial pivoting},
+  Author                   = {Hochet, B. and Quinton, P. and Robert, Y.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {1989},
+
+  Month                    = {sep},
+  Number                   = {9},
+  Pages                    = {1321 -1324},
+  Volume                   = {38},
+
+  Doi                      = {10.1109/12.29471},
+  File                     = {hocqui_89.pdf:hocqui_89.pdf:PDF},
+  ISSN                     = {0018-9340},
+  Keywords                 = {Gauss; Gaussian Elimination; systolic array},
+  Owner                    = {Scholl},
+  Timestamp                = {2013.02.04}
+}
+
+@InProceedings{hocqui_87,
+  Title                    = {{S}ystolic solution of linear systems over {GF}(p) with partial pivoting},
+  Author                   = {Hochet, Bertrand and Quinton, Patrice and Robert, Yves},
+  Booktitle                = {Computer Arithmetic (ARITH), 1987 IEEE 8th Symposium on},
+  Year                     = {1987},
+  Month                    = {may},
+  Pages                    = {161 -168},
+
+  Doi                      = {10.1109/ARITH.1987.6158700},
+  File                     = {hocqui_87.pdf:hocqui_87.pdf:PDF},
+  Keywords                 = {Gauss; Gaussian Elimination; systolic array}
+}
+
+@Article{hocbri_03,
+  Title                    = {{A}chieving {N}ear-{C}apacity on a {M}ultiple-{A}ntenna {C}hannel},
+  Author                   = {Hochwald, B.M. and ten Brink, S.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2003},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {389--399},
+  Volume                   = {51},
+
+  Doi                      = {10.1109/TCOMM.2003.809789},
+  File                     = {hocbri_03.pdf:hocbri_03.pdf:PDF},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{hoc_59,
+  Title                    = {{C}odes correcteurs d’erreurs},
+  Author                   = {Hocquenghem, A.},
+  Journal                  = {Chiffres},
+  Year                     = {1959},
+  Number                   = {2},
+  Pages                    = {147--56},
+  Volume                   = {2},
+
+  Cds_grade                = {0},
+  File                     = {hoc_59.pdf:hoc_59.pdf:PDF},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.14}
+}
+
+@Article{Hocquenghem1959,
+  Title                    = {{C}odes correcteurs d’erreurs},
+  Author                   = {Hocquenghem, A.},
+  Journal                  = {Chiffres},
+  Year                     = {1959},
+  Number                   = {2},
+  Pages                    = {147--56},
+  Volume                   = {2},
+
+  Cds_grade                = {0},
+  File                     = {hoc_59.pdf:hoc_59.pdf:PDF},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.14}
+}
+
+@InProceedings{hoe_99,
+  Title                    = {{Data Transmission with Reliability Indication}},
+  Author                   = {P. Hoeher},
+  Booktitle                = {Proc. 2nd German--American Symposium ``Frontiers of Engineering''},
+  Year                     = {1999},
+
+  Address                  = {Irvine, California, USA},
+  Month                    = apr,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hoe_97,
+  Title                    = {{New Iterative (``Turbo'') Decoding Algorithms}},
+  Author                   = {P. Hoeher},
+  Booktitle                = {Proc. International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {1997},
+
+  Address                  = {Brest, France},
+  Pages                    = {63--70},
+
+  Optmonth                 = {#sep#},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hoe_95,
+  Title                    = {{Optimal Subblock-by-Subblock Detection}},
+  Author                   = {P. Hoeher},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1995},
+
+  Month                    = feb # {--} # apr,
+  Number                   = {2/3/4},
+  Pages                    = {714--717},
+  Volume                   = {43},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hoelan_00,
+  Title                    = {{Log-Likelihood Values and Monte Carlo Simulation -- Some Fundamental Results}},
+  Author                   = {P. Hoeher and I. Land and U. Sorger},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {43--46},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{hoebar_09,
+  Title                    = {{T}he {D}atacenter {A}s a {C}omputer: {A}n {I}ntroduction to the {D}esign of {W}arehouse-{S}cale {M}achines},
+  Author                   = {Hoelzle, Urs and Barroso, Luiz Andre},
+  Publisher                = {Morgan and Claypool Publishers},
+  Year                     = {2009},
+  Edition                  = {1st},
+
+  ISBN                     = {159829556X, 9781598295566},
+  Owner                    = {MJ},
+  Timestamp                = {2016-05-09}
+}
+
+@InProceedings{hofsch_01,
+  Title                    = {{A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA}},
+  Author                   = {Hoffmann, A. and Schliebusch, O. and Nohl, A. and Braun, G. and Wahlen, O. and Meyr, H.},
+  Booktitle                = {Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on},
+  Year                     = {2001},
+  Month                    = nov,
+  Pages                    = {625--630},
+
+  Doi                      = {10.1109/ICCAD.2001.968726},
+  File                     = {hofsch_01.pdf:hofsch_01.pdf:PDF},
+  Keywords                 = {ASIP},
+  Owner                    = {vogt},
+  Timestamp                = {2007.05.29}
+}
+
+@PhdThesis{Phdho90,
+  Title                    = {{Kohärenter Empfang trelliscodierter PSK Signale auf frequenzselektiven Mobilfunkkanälen}},
+  Author                   = {P. Hoher},
+  School                   = {University of Kaiserslautern},
+  Year                     = {1990},
+
+  Address                  = {VDI-Verlag, Düsseldorf, Germany},
+  Note                     = {In German},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{holzer2008design,
+  Title                    = {{D}esign space exploration for the development of embedded systems},
+  Author                   = {Holzer, Martin},
+  Publisher                = {Vienna University of Technology},
+  Year                     = {2008},
+
+  Timestamp                = {2018-03-27}
+}
+
+@InProceedings{honkir_98,
+  Title                    = {{Power Optimization of Variable Voltage Core-Based Systems}},
+  Author                   = {I. Hong and D. Kirovski and G. Qu and M. Potkonjak and M. B. Srivastava},
+  Booktitle                = {Proc. 1998 Design Automation Conference (DAC '98)},
+  Year                     = {1998},
+
+  Address                  = {San Francisco, California, USA},
+  Month                    = jun,
+  Pages                    = {176--181},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{honpot_98,
+  Title                    = {{On-Line Scheduling of Hard Real-Time Tasks on Variable Voltage Processors}},
+  Author                   = {I. Hong and M. Potkonjak and M. B. Srivastava},
+  Booktitle                = {Proc. 1998 International Conference on Computer-Aided Design (ICCAD '98)},
+  Year                     = {1998},
+
+  Address                  = {San Jose, California, USA},
+  Pages                    = {653--656},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{honhu_14,
+  Title                    = {{M}onte {C}arlo {M}ethods for {V}alue-at-{R}isk and {C}onditional {V}alue-at-{R}isk: {A} {R}eview},
+  Author                   = {L. Jeff Hong and Zhaolin Hu and Guangwu Liu},
+  Journal                  = {ACM Trans. Model. Comput. Simul.},
+  Year                     = {2014},
+
+  Month                    = {nov},
+  Number                   = {4},
+  Pages                    = {22:1--22:37},
+  Volume                   = {24},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.01.30}
+}
+
+@Article{honsta_00,
+  Title                    = {{Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications}},
+  Author                   = {S. Hong and Stark, W. E.},
+  Journal                  = {Journal of VLSI Signal Processing Systems},
+  Year                     = {2000},
+  Note                     = {Kluwer Academic Publishers, Boston},
+  Pages                    = {43--57},
+  Volume                   = {24},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{honyi_98,
+  Title                    = {{VLSI Design and Implementation of Low-Complexity Adaptive Turbo-Code Encoder and Decoder for Wireless Mobile Communication Applications}},
+  Author                   = {S. Hong and J. Yi and W. E. Stark},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems (SiPS '98)},
+  Year                     = {1998},
+
+  Address                  = {Cambridge, Massachusetts, USA},
+  Month                    = oct,
+  Pages                    = {233--242},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hoo_13,
+  Title                    = {{V}ariation tolerance and error resilience in a low power wireless receiver},
+  Author                   = {Hoogerbrugge, J.},
+  Booktitle                = {Computer Design (ICCD), 2013 IEEE 31st International Conference on},
+  Year                     = {2013},
+  Pages                    = {343--348},
+
+  Doi                      = {10.1109/ICCD.2013.6657063},
+  Owner                    = {Schläfer},
+  Timestamp                = {2014.07.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6657063}
+}
+
+@Article{horzha_13,
+  Title                    = {{A} network-based method to assess the statistical significance of mild co-regulation effects},
+  Author                   = {Em{\H o}ke-{\'A}gnes Horv{\'a}t and Jitao David Zhang and Stefan Uhlmann and {\"O}zg{\"u}r Sahin and Katharina A. Zweig},
+  Journal                  = {PLOS ONE},
+  Year                     = {2013},
+  Number                   = {9},
+  Pages                    = {e73413},
+  Volume                   = {8},
+
+  Owner                    = {nina},
+  Timestamp                = {2013.09.24}
+}
+
+@Article{horzwe_13,
+  Title                    = {{A} fixed degree sequence model for the one-mode projection of multiplex bipartite graphs},
+  Author                   = {Horv{\'a}t, Em{\H{o}}ke-{\'A}gnes and Zweig, Katharina Anna},
+  Journal                  = {Social Network Analysis and Mining},
+  Year                     = {2013},
+  Number                   = {4},
+  Pages                    = {1209--1224},
+  Volume                   = {3},
+
+  Owner                    = {Brugger},
+  Publisher                = {Springer},
+  Timestamp                = {2015.08.15}
+}
+
+@InProceedings{horzwe_12,
+  Title                    = {{O}ne-mode projection of multiplex bipartite graphs},
+  Author                   = {Horv{\'a}t, Emoke-Agnes and Zweig, Katharina A},
+  Booktitle                = {Proceedings of the 2012 International Conference on Advances in Social Networks Analysis and Mining (ASONAM 2012)},
+  Year                     = {2012},
+  Organization             = {IEEE Computer Society},
+  Pages                    = {599--606},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.08.09}
+}
+
+@InProceedings{hoshab_03,
+  Title                    = {{Hardware-Software Codesign of a 14.4Mbit - 64 State - Viterbi Decoder for an Application-Specific Digital Signal Processor}},
+  Author                   = {M. Hosemann and R. Habendorf and G. P. Fettweis},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems 2003 (SIPS'03)},
+  Year                     = {2003},
+
+  Address                  = {Seoul, Korea},
+  Month                    = aug,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{houli_13,
+  Title                    = {{A}n {FPGA}-based test platform for analyzing data retention time distribution of {DRAM}s},
+  Author                   = {Chih-Sheng Hou and Jin-Fu Li and Chih-Yen Lo and Ding-Ming Kwai and Yung-Fa Chou and Cheng-Wen Wu},
+  Booktitle                = {VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on},
+  Year                     = {2013},
+  Month                    = {April},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/VLDI-DAT.2013.6533853},
+  Keywords                 = {DRAM chips;field programmable gate arrays;logic testing;DRAM data retention time distribution analysis;FPGA-based test platform;Micron DRAM;dynamic random access memory;field programmable gate arrays;Built-in self-test;Circuit faults;Current measurement;Leakage currents;Random access memory;Temperature distribution;Temperature measurement},
+  Owner                    = {MJ},
+  Timestamp                = {2016.02.10}
+}
+
+@Article{housie_03,
+  Title                    = {{C}apacity-approaching bandwidth-efficient coded modulation schemes based on low-density parity-check codes},
+  Author                   = {Hou, J. and Siegel, P.H. and Milstein, L.B. and Pfister, H.D.},
+  Journal                  = {Information Theory, IEEE Transactions on},
+  Year                     = {2003},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {2141--2155},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/TIT.2003.815777},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.02}
+}
+
+@Article{hou_58,
+  Title                    = {{U}nitary {T}riangularization of a {N}onsymmetric {M}atrix},
+  Author                   = {Householder, Alston S.},
+  Journal                  = {J. ACM},
+  Year                     = {1958},
+
+  Month                    = oct,
+  Number                   = {4},
+  Pages                    = {339--342},
+  Volume                   = {5},
+
+  Acmid                    = {320947},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/320941.320947},
+  ISSN                     = {0004-5411},
+  Issue_date               = {Oct. 1958},
+  Numpages                 = {4},
+  Owner                    = {Gimmler},
+  Publisher                = {ACM},
+  Timestamp                = {2012.11.12},
+  Url                      = {http://doi.acm.org/10.1145/320941.320947}
+}
+
+@InProceedings{howdig_10,
+  Title                    = {{A} 48-core {IA}-32 message-passing processor with {DVFS} in 45nm {CMOS}},
+  Author                   = {Howard, Jason and Dighe, Saurabh and Hoskote, Yatin and Vangal, Sriram and Finan, David and Ruhl, Gregory and Jenkins, David and Wilson, Howard and Borkar, Nitin and Schrom, Gerhard and others},
+  Booktitle                = {Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International},
+  Year                     = {2010},
+  Organization             = {IEEE},
+  Pages                    = {108--109},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.11.29}
+}
+
+@Standard{howmun_14,
+  Title                    = {{T}he {O}pen{CL} {S}pecification},
+  Institution              = {Khronos OpenCL Working Group},
+  Organization             = {Khronos OpenCL Working Group},
+  Author                   = {Lee Howes and Aaftab Munshi},
+  HowPublished             = {\url{https://www.khronos.org/registry/cl/specs/opencl-2.0.pdf}},
+  Month                    = {Jul},
+  Note                     = {last access 2015-10-13},
+  Number                   = {2.0},
+  Revision                 = {29},
+  Url                      = {https://www.khronos.org/registry/cl/specs/opencl-2.0.pdf},
+  Year                     = {2015},
+
+  Comment                  = {last access 2015-10-13},
+  Owner                    = {varela},
+  Timestamp                = {2015.07.29}
+}
+
+@Standard{howmun_15,
+  Title                    = {{T}he {O}pen{CL} {S}pecification},
+  Organization             = {Khronos OpenCL Working Group},
+  Author                   = {Lee Howes and Aaftab Munshi},
+  HowPublished             = {online},
+  Month                    = {Jan},
+  Number                   = {2.1},
+  Revision                 = {8},
+  Url                      = {https://www.khronos.org/registry/cl/specs/opencl-2.1.pdf},
+  Year                     = {2015},
+
+  Comment                  = {Last access: 29 July 2015},
+  Owner                    = {varela},
+  Timestamp                = {2015.07.29}
+}
+
+@InCollection{howtho_08,
+  Title                    = {{Efficient Random Number Generation and Application Using CUDA}},
+  Author                   = {Lee Howes and David Thomas},
+  Booktitle                = {GPU Gems 3},
+  Publisher                = {Addison-Wesley},
+  Year                     = {2008},
+  Chapter                  = {37},
+  Editor                   = {Hubert Nguyen},
+  Series                   = {Lab Companion},
+  Volume                   = {3},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@Article{hsi_70,
+  Title                    = {{A} class of optimal minimum odd-weight-column {SEC}-{DED} codes},
+  Author                   = {Hsiao, Mu-Yue},
+  Journal                  = {IBM Journal of Research and Development},
+  Year                     = {1970},
+  Number                   = {4},
+  Pages                    = {395--401},
+  Volume                   = {14},
+
+  Owner                    = {kraft},
+  Publisher                = {IBM},
+  Timestamp                = {2017.09.12}
+}
+
+@InProceedings{hsiped_02,
+  Title                    = {{Architectural Energy Optimization by Bus Splitting}},
+  Author                   = {C. Hsieh and M. Pedram},
+  Booktitle                = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 21, 2002},
+  Year                     = {2002},
+  Pages                    = {408--414},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hsulin_11,
+  Title                    = {{A} 2.56 {G}b/s soft {RS} (255,239) decoder chip for optical communication systems},
+  Author                   = {Chih-Hsiang Hsu and Yi-Min Lin and Hsie-Chia Chang and Chen-Yi Lee},
+  Booktitle                = {Proc. ESSCIRC (ESSCIRC)},
+  Year                     = {2011},
+  Pages                    = {79--82},
+
+  Doi                      = {10.1109/ESSCIRC.2011.6044919},
+  File                     = {hsulin_11.pdf:hsulin_11.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {2,5 GBit Decoderchip für den RS(255,239) mit 0,4 db gain
+Chase ähnlicher Algorithmus, sehr nahe an der HDD Hardware dran},
+  Timestamp                = {2011.12.16}
+}
+
+@InProceedings{hsuwan_99,
+  Title                    = {{On Finite-Precision Implementation of a Decoder for Turbo Codes}},
+  Author                   = {J.-M. Hsu and C.-L. Wang},
+  Booktitle                = {Proc. 1999 International Symposium on Circuits and Systems (ISCAS '99)},
+  Year                     = {1999},
+
+  Address                  = {Orlando, Florida, USA},
+  Month                    = may # {--} # jun,
+  Pages                    = {IV-423--IV-426},
+
+  Optvolume                = {4},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{hsuwan_98,
+  Title                    = {{A Parallel Decoding Scheme for Turbo-Codes}},
+  Author                   = {J.-M. Hsu and C.-L. Wang},
+  Booktitle                = {{Proc. 1998 International Symposium on Circuits and Systems (ISCAS '98)}},
+  Year                     = {1998},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = jun,
+  Pages                    = {445--448},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{netflixdata,
+  Author                   = {http://www.netflixprize.com/},
+  Year                     = {last access: 2014-12-01},
+
+  Owner                    = {Ninasnet},
+  Timestamp                = {2014.12.01}
+}
+
+@InProceedings{huele_01,
+  Title                    = {{Efficient Implementations of the Sum-Product Algorithm for Decoding LDPC Codes}},
+  Author                   = {X.Y. Hu and E. Eleftheriou and D.M. Arnold and A. Dholakia},
+  Booktitle                = {Proc. 2001 Global Telecommunications Conference (GLOBECOM '01)},
+  Year                     = {2001},
+
+  Address                  = {San Antonio, TX ,USA},
+  Pages                    = {1036--1041},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{hufos_04,
+  Title                    = {{On the Computation of the Minimum Distance of Low-Density Parity-Check Codes}},
+  Author                   = {Hu, X.Y. and Fossorier, M.P.C.},
+  Journal                  = {Communications, 2004 IEEE International Conference on},
+  Year                     = {2004},
+  Pages                    = {767--771},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{huele_04,
+  Title                    = {{B}inary representation of cycle {T}anner-graph {GF}(2b) codes},
+  Author                   = {Hu, X.-Yu. and Eleftheriou, E.},
+  Booktitle                = {Proc. IEEE Int Communications Conf},
+  Year                     = {2004},
+  Pages                    = {528--532},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ICC.2004.1312545},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.26}
+}
+
+@InProceedings{huele_03,
+  Title                    = {{C}ycle {T}anner-graph codes over {GF}(2b)},
+  Author                   = {Hu, X.-Y. and Eleftheriou, E. },
+  Booktitle                = {Proc. IEEE International Symposium on Information Theory},
+  Year                     = {2003},
+  Month                    = jun # {--} # jul,
+  Pages                    = {87},
+
+  Doi                      = {10.1109/ISIT.2003.1228101},
+  File                     = {huele_03.pdf:huele_03.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@Article{huele_05,
+  Title                    = {{R}egular and irregular progressive edge-growth tanner graphs},
+  Author                   = {Hu, X.-Y. and Eleftheriou, E. and Arnold, D. M. },
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2005},
+  Number                   = {1},
+  Pages                    = {386--398},
+  Volume                   = {51},
+
+  Doi                      = {10.1109/TIT.2004.839541},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.26}
+}
+
+@InProceedings{huai_97,
+  Title                    = {{I}mproving detection and estimation in pilot-aided frequency selective {CDMA} channels},
+  Author                   = {Huang, H. and Chih-Lin I and ten Brink, S.},
+  Booktitle                = {Universal Personal Communications Record, 1997. Conference Record., 1997 IEEE 6th International Conference on},
+  Year                     = {1997},
+  Month                    = oct,
+  Pages                    = {198--201vol.1},
+
+  Doi                      = {10.1109/ICUPC.1997.625541},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{huashi_05,
+  Title                    = {{I}mproving {E}nergy {E}fficiency by {M}aking {DRAM} {L}ess {R}andomly {A}ccessed},
+  Author                   = {Huang, Hai and Shin, Kang G. and Lefurgy, Charles and Keller, Tom and Krishna T. Malladi and Ian Shaeffer and Liji Gopalakrishnan and David Lo and Benjamin C. Lee and Mark Horowitz},
+  Booktitle                = {Proceedings of the 2005 International Symposium on Low Power Electronics and Design},
+  Year                     = {2005},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {393--398},
+  Publisher                = {ACM},
+  Series                   = {ISLPED '05},
+
+  Acmid                    = {1077696},
+  Doi                      = {10.1145/1077603.1077696},
+  ISBN                     = {1-59593-137-6},
+  Keywords                 = {DDR, low power, memory system},
+  Location                 = {San Diego, CA, USA},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-22},
+  Url                      = {http://doi.acm.org/10.1145/1077603.1077696}
+}
+
+@InProceedings{huazhu_12,
+  Title                    = {{A}n {FPGA} top-hat transform module with two different structure elements},
+  Author                   = {Jianjun Huang and Xiangang Zhu and Yuan Zi},
+  Booktitle                = {Signal Processing (ICSP), 2012 IEEE 11th International Conference on},
+  Year                     = {2012},
+  Month                    = {Oct},
+  Pages                    = {465-468},
+  Volume                   = {1},
+
+  Abstract                 = {In this paper, a top-hat transformation module is implemented for infrared small target detection. The top-hat algorithm uses two different structure elements in erosion and dilation. Erosion implements a 5×5 ring structure element process unit while dilation implements a 3×3 structure element one. The time delay of open operation is formulated and used for background subtraction. The experiment shows that the designed module meets the real-time application requirement and has good performance in suppressing interference.},
+  Cds_grade                = {3},
+  Cds_keywords             = {morphological filter, FPGA, top-hat},
+  Cds_read                 = {2014-07-15},
+  Cds_review               = {2-SE implementation
+no CPU and GPU comparison
+no energy numbers},
+  Doi                      = {10.1109/ICoSP.2012.6491525},
+  File                     = {huazhu_12.pdf:huazhu_12.pdf:PDF},
+  ISSN                     = {2164-5221},
+  Owner                    = {CdS},
+  Timestamp                = {2014.07.15}
+}
+
+@InProceedings{huali_04,
+  Title                    = {{VLSI Design of Dual-Mode Viterbi/Turbo Ddecoder for 3GPP}},
+  Author                   = {K. Huang and F.-M. Li and P.-L. Shen and A.-Y. Wu},
+  Booktitle                = {Proc. 2004 IEEE International Symposium on Circuits and Systems (ISCAS '04)},
+  Year                     = {2004},
+
+  Address                  = {Vancouver, Canada},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{huaoth_08,
+  Title                    = {{T}he promise of high-performance reconfigurable computing},
+  Author                   = {Huang, Miaoqing and others},
+  Journal                  = {Computer},
+  Year                     = {2008},
+  Number                   = {2},
+  Pages                    = {69--76},
+  Volume                   = {41},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@TechReport{hua_13,
+  Title                    = {5{G}: {A} technology vision},
+  Author                   = {Huawei},
+  Institution              = {Huawei Technologies Co.},
+  Year                     = {2013},
+
+  Address                  = {Shenzen, China},
+  Month                    = {Nov},
+  Number                   = {M3-023985},
+  Type                     = {White Paper},
+
+  Owner                    = {StW},
+  Timestamp                = {2016.07.13}
+}
+
+@InProceedings{huebre_00,
+  Title                    = {{Memory Efficient Implementation of the BCJR Algorithm}},
+  Author                   = {S. Huettinger and M. Breiling and J. Huber},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {479--482},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{huehub_03,
+  Title                    = {{P}erformance estimation for concatenated coding schemes},
+  Author                   = {Huettinger, S. and Huber, J.},
+  Booktitle                = {Information Theory Workshop, 2003. Proceedings. 2003 IEEE},
+  Year                     = {2003},
+  Month                    = mar # {--} # apr,
+  Pages                    = {123--126},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{huehub_02,
+  Title                    = {{C}onstruction of low-rate power-efficient coding schemes and their application to {CDMA}},
+  Author                   = {Huettinger, S. and Huber, J.},
+  Booktitle                = {Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE},
+  Year                     = {2002},
+  Month                    = nov,
+  Pages                    = {1021--1025vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/GLOCOM.2002.1188349},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{huf_52,
+  Title                    = {{A} {M}ethod for the {C}onstruction of {M}inimum-{R}edundancy {C}odes},
+  Author                   = {D.A. Huffman},
+  Journal                  = {Proceedings of the IRE},
+  Year                     = {1952},
+
+  Month                    = sep,
+  Pages                    = {1098--1102},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.07.28}
+}
+
+@PhdThesis{huf_14,
+  Title                    = {{T}owards the {E}fficient {C}reation of {A}ccurate and {H}igh-{P}erformance {V}irtual {P}rototypes},
+  Author                   = {Simon Hufnagel},
+  School                   = {Technische Universit{\"a}t Kaiserslautern},
+  Year                     = {2014},
+  Type                     = {doctoralthesis},
+
+  Owner                    = {MJ},
+  Pages                    = {135},
+  Timestamp                = {2018-09-13},
+  Url                      = {http://nbn-resolving.de/urn:nbn:de:hbz:386-kluedo-38928}
+}
+
+@Book{hul_12,
+  Title                    = {{O}ptions, {F}utures, {A}nd {O}ther {D}erivatives},
+  Author                   = {John C. Hull},
+  Publisher                = {Pearson},
+  Year                     = {2012},
+  Edition                  = {8th},
+
+  Cds_grade                = {0},
+  File                     = {hul_12.pdf:hul_12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.04.02}
+}
+
+@InProceedings{hunkao_10,
+  Title                    = {{A} {R}eal-{T}ime {H}igh-{T}hroughput {LDPC} {D}ecoder for {IEEE} 802.3an {S}tandard},
+  Author                   = {Jui-Hui Hung and Li-Wei Kao and Sau-Gee Chen},
+  Year                     = {2010},
+  Note                     = {Vehicular Technology Conference (VTC 2010-Spring), 2010 IEEE 71st},
+  Pages                    = {1--5},
+
+  Abstract                 = {The existing <span class='snippet'>LDPC</span> <span class='snippet'>decoders</span> are mostly based on the belief-propagation (BP) algorithms, due to good BER performances. However, they demand large chip areas. This paper proposes <span class='snippet'>a</span> <span class='snippet'>high</span>-<span class='snippet'>throughput</span> <span class='snippet'>LDPC</span> <span class='snippet'>decoder</span> based on the bit-flipping algorithms, <span class='snippet'>for</span> the (2048, 1723) RS-<span class='snippet'>LDPC</span> code adopted in the <span class='snippet'>IEEE</span> <span class='snippet'>802</span>.<span class='snippet'>3an</span> <span class='snippet'>standard</span>. <span class='snippet'>High</span> decoding performances and low iteration numbers are achieved by introducing <span class='snippet'>a</span> strategy of flipping low-correlation bits and an additional syndrome vote scheme. As <span class='snippet'>a</span> result, the decoding performance is very close to the most popular BP-based min-sum algorithm (MSA) but with much lower computational complexity. Besides, the <span class='snippet'>decoder</span> achieves <span class='snippet'>high</span> hardware utilization with <span class='snippet'>real</span>-<span class='snippet'>time</span> processing capability. Synthesized with UMC 90nm process, the <span class='snippet'>decoder</span> chip area, <span class='snippet'>throughput</span> and average power dissipation are 1.42M gates, 16Gbps and 368mW, respectively, at 500MHz clock rate. Compared with existing BP-based designs, it has much smaller chip area and lower power dissipation, with comparable performances.},
+  Doi                      = {10.1109/VETECS.2010.5493796},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.07.15}
+}
+
+@InProceedings{hungos_05,
+  Title                    = {{M}itigating soft errors in highly associative cache with {CAM}-based tag},
+  Author                   = {Hung, L. D. and Goshima, M. and Sakai, S. },
+  Booktitle                = {Proc. IEEE Int. Conf. Computer Design: VLSI in Computers and Processors ICCD 2005},
+  Year                     = {2005},
+  Pages                    = {342--347},
+
+  Doi                      = {10.1109/ICCD.2005.76},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Misc{Hung2010,
+  Title                    = {{A} 5.7{G}bps row-based layered scheduling {LDPC} decoder for {IEEE} 802.15.3c applications},
+
+  Author                   = {Shiang-Yu Hung and Shao-Wei Yen and Chih-Lung Chen and Hsie-Chia Chang and Shyh-Jye Jou and Chen-Yi Lee},
+  Note                     = {Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian},
+  Year                     = {2010},
+
+  Doi                      = {10.1109/ASSCC.2010.5716617},
+  File                     = {Hung2010.pdf:Hung2010.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {schlaefer},
+  Pages                    = {1--4},
+  Timestamp                = {2012.01.26}
+}
+
+@Misc{Hung2010b,
+  Title                    = {{A} 5.7{G}bps row-based layered scheduling {LDPC} decoder for {IEEE} 802.15.3c applications},
+
+  Author                   = {Shiang-Yu Hung and Shao-Wei Yen and Chih-Lung Chen and Hsie-Chia Chang and Shyh-Jye Jou and Chen-Yi Lee},
+  Note                     = {Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian},
+  Year                     = {2010},
+
+  Doi                      = {10.1109/ASSCC.2010.5716617},
+  File                     = {Hung2010.pdf:Hung2010.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {schlaefer},
+  Pages                    = {1--4},
+  Timestamp                = {2012.01.26}
+}
+
+@InProceedings{hunlin_06,
+  Title                    = {{I}nterconnect and {T}hermal-aware {F}loorplanning for 3{D} {M}icroprocessors},
+  Author                   = {Hung, W.-L. and Link, G. M. and Xie, Yuan and Vijaykrishnan, N. and Irwin, M. J.},
+  Booktitle                = {Proceedings of the 7th International Symposium on Quality Electronic Design ({ISQED})},
+  Year                     = {2006},
+  Pages                    = {98--104}
+}
+
+@InProceedings{huncro_06,
+  Title                    = {{A} completely safe early-stopping criterion for max-log {T}urbo code decoding},
+  Author                   = {Andrew Hunt and Stewart Crozier and Ken Gracie and Paul Guinand},
+  Booktitle                = {4th International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2006},
+
+  Address                  = {Munich, Germany},
+  Month                    = apr,
+
+  File                     = {huncro_06.pdf:huncro_06.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{hurlin_08,
+  Title                    = {{A} comprehensive approach to {DRAM} power management},
+  Author                   = {I. Hur and C. Lin},
+  Booktitle                = {2008 IEEE 14th International Symposium on High Performance Computer Architecture},
+  Year                     = {2008},
+  Month                    = {Feb},
+  Pages                    = {305-316},
+
+  Doi                      = {10.1109/HPCA.2008.4658648},
+  ISSN                     = {1530-0897},
+  Keywords                 = {DRAM chips;DRAM energy efficiency;DRAM power management;adaptive history-based memory scheduler;memory controller;Adaptive scheduling;Delay estimation;Energy consumption;Energy efficiency;Energy management;Memory management;Power system management;Random access memory;SDRAM;Technology management},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-22}
+}
+
+@InProceedings{hurlin_04,
+  Title                    = {{A}daptive {H}istory-{B}ased {M}emory {S}chedulers},
+  Author                   = {Hur, Ibrahim and Lin, Calvin},
+  Booktitle                = {Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture},
+  Year                     = {2004},
+
+  Address                  = {Washington, DC, USA},
+  Pages                    = {343--354},
+  Publisher                = {IEEE Computer Society},
+  Series                   = {MICRO 37},
+
+  Acmid                    = {1038953},
+  Doi                      = {10.1109/MICRO.2004.4},
+  ISBN                     = {0-7695-2126-6},
+  Location                 = {Portland, Oregon},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11},
+  Url                      = {http://dx.doi.org/10.1109/MICRO.2004.4}
+}
+
+@Article{hurrhi_19,
+  Title                    = {{A}daptive {L}inear {A}ddress {M}ap for {B}ank {I}nterleaving in {DRAM}s},
+  Author                   = {J. Y. {Hur} and S. W. {Rhim} and B. H. {Lee} and W. {Jang}},
+  Journal                  = {IEEE Access},
+  Year                     = {2019},
+  Pages                    = {129604-129616},
+  Volume                   = {7},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-06-05}
+}
+
+@InProceedings{huskha_11,
+  Title                    = {{A} {C}lass of {L}ow {P}ower {E}rror {C}ompensation {I}terative {D}ecoders},
+  Author                   = {Hussien, A.M.A. and Khairy, M.S. and Khajeh, A. and Eltawil, A.M. and Kurdahi, F.J.},
+  Booktitle                = {Global Telecommunications Conference (GLOBECOM 2011), 2011 IEEE},
+  Year                     = {2011},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/GLOCOM.2011.6134075},
+  File                     = {huskha_11.pdf:huskha_11.pdf:PDF},
+  ISSN                     = {1930-529X},
+  Keywords                 = {error compensation;iterative decoding;low-power electronics;parity check codes;turbo codes;LDPC decoders;embedded buffering memories;low power error compensation iterative decoders;turbo decoders;Decoding;Hardware;Measurement;Parity check codes;Peer to peer computing;Signal to noise ratio},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@InProceedings{huskha_10,
+  Title                    = {{A} {C}ombined {C}hannel and {H}ardware {N}oise {R}esilient {V}iterbi {D}ecoder},
+  Author                   = {Hussien, A. M. A. and Khairy, M. S. and Khajeh, A. and Amiri, K. and Eltawil, A. M. and Kurdahi, F. J.},
+  Booktitle                = {Proc. Conf Signals, Systems and Computers (ASILOMAR) Record of the Forty Fourth Asilomar Conf},
+  Year                     = {2010},
+  Pages                    = {395--399},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Kurdahi
+- Viterbi, Modified Channel model due to HW errors, see khaami_10},
+  Doi                      = {10.1109/ACSSC.2010.5757543},
+  File                     = {huskha_10.pdf:huskha_10.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@TechReport{iDirect,
+  Title                    = {{U}niversal {S}atellite {H}ub},
+  Author                   = {{i}Direct},
+  Year                     = {2011},
+
+  Address                  = {http://www.idirect.net},
+  Month                    = {July},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.02.02}
+}
+
+@Misc{cplex,
+  Title                    = {{IBM ILOG CPLEX Optimizer}},
+
+  Author                   = {{IBM}},
+  HowPublished             = {\url{http://www-01.ibm.com/software/integration/optimization/cplex-optimizer/}},
+  Month                    = {apr},
+  Year                     = {last access Apr. 2012},
+
+  Owner                    = {Kienle},
+  Timestamp                = {2012.11.14}
+}
+
+@Misc{IBMlastaccessApr.2012,
+  Title                    = {{IBM ILOG CPLEX Optimizer}},
+
+  Author                   = {{IBM}},
+  HowPublished             = {\url{http://www-01.ibm.com/software/integration/optimization/cplex-optimizer/}},
+  Month                    = {apr},
+  Year                     = {last access Apr. 2012},
+
+  Owner                    = {Kienle},
+  Timestamp                = {2012.11.14}
+}
+
+@Misc{802_15_4_group,
+  Title                    = {802.15.4 working group: http://www.ieee802.org/15/pub/{TG}4.html},
+
+  Author                   = {IEEE},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://www.ieee802.org/15/pub/TG4.html}
+}
+
+@Misc{IEEE,
+  Title                    = {802.15.4 working group: http://www.ieee802.org/15/pub/{TG}4.html},
+
+  Author                   = {IEEE},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://www.ieee802.org/15/pub/TG4.html}
+}
+
+@Misc{IEEEa,
+  Title                    = {{Wireless Fidelity (Wireless LAN)}},
+
+  Author                   = {{IEEE 802.11}},
+  HowPublished             = {{{http://grouper.ieee.org/groups/802/11/}}},
+
+  Key                      = {WIFI},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{iewireless,
+  Title                    = {{Wireless Fidelity (Wireless LAN)}},
+
+  Author                   = {{IEEE 802.11}},
+  HowPublished             = {{{http://grouper.ieee.org/groups/802/11/}}},
+
+  Key                      = {WIFI},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{IEEE2010,
+  Title                    = {{Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications - Amendment: Enhancements for Very High Throughput in the 60 GHz Band}},
+
+  Author                   = {{IEEE 802.11ad}},
+  HowPublished             = {{IEEE 802.11ad-draft}},
+  Month                    = may,
+  Year                     = {2010},
+
+  Key                      = {WIRELESSLAN},
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.01.26}
+}
+
+@Misc{IEEE802.11ad2010,
+  Title                    = {{Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications - Amendment: Enhancements for Very High Throughput in the 60 GHz Band}},
+
+  Author                   = {{IEEE 802.11ad}},
+  HowPublished             = {{IEEE 802.11ad-draft}},
+  Month                    = may,
+  Year                     = {2010},
+
+  Key                      = {WIRELESSLAN},
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.01.26}
+}
+
+@Misc{IEEE2007,
+  Title                    = {{Wireless LAN Medium Access Control and Physical Layer specifications: Enhancements for Higher Throughput}},
+
+  Author                   = {{IEEE 802.11n}},
+  HowPublished             = {{IEEE P802.11n/D3.0}},
+  Month                    = sep,
+  Year                     = {2007},
+
+  Key                      = {WIRELESSLAN},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{iewireless07,
+  Title                    = {{Wireless LAN Medium Access Control and Physical Layer specifications: Enhancements for Higher Throughput}},
+
+  Author                   = {{IEEE 802.11n}},
+  HowPublished             = {{IEEE P802.11n/D3.0}},
+  Month                    = sep,
+  Year                     = {2007},
+
+  Key                      = {WIRELESSLAN},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{IEEE2009,
+  Title                    = {{Part 15.3: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPANs)}},
+
+  Author                   = {{IEEE 802.15.3c}},
+  HowPublished             = {{IEEE 802.15.3c-2009}},
+  Month                    = oct,
+  Year                     = {2009},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{iepart09,
+  Title                    = {{Part 15.3: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPANs)}},
+
+  Author                   = {{IEEE 802.15.3c}},
+  HowPublished             = {{IEEE 802.15.3c-2009}},
+  Month                    = oct,
+  Year                     = {2009},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{ieair05,
+  Title                    = {{Air Interface for Fixed and Mobile Broadband Wireless Access Systems}},
+
+  Author                   = {{IEEE 802.16e}},
+  HowPublished             = {{IEEE P802.16e/D12 Draft}},
+  Month                    = oct,
+  Year                     = {2005},
+
+  Key                      = {WIRELESSMAN},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{IEEE2005,
+  Title                    = {{Air Interface for Fixed and Mobile Broadband Wireless Access Systems}},
+
+  Author                   = {{IEEE 802.16e}},
+  HowPublished             = {{IEEE P802.16e/D12 Draft}},
+  Month                    = oct,
+  Year                     = {2005},
+
+  Key                      = {WIRELESSMAN},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{IEEEb,
+  Title                    = {{LAN/MAN CSMA/CD Access Method}},
+
+  Author                   = {{IEEE 802.3}},
+  HowPublished             = {{{http://standards.ieee.org/getieee802/802.3.html}}},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.08}
+}
+
+@Misc{ielan/man,
+  Title                    = {{LAN/MAN CSMA/CD Access Method}},
+
+  Author                   = {{IEEE 802.3}},
+  HowPublished             = {{{http://standards.ieee.org/getieee802/802.3.html}}},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.08}
+}
+
+@Misc{iepart06,
+  Title                    = {{Part 3: CSMA/CD Access Method and Physical Layer Specifications - Amendment: Physical Layer and Management Parameters for 10 Gb/s Operation, Type 10GBASE-T }},
+
+  Author                   = {{IEEE 802.3an-2006}},
+  HowPublished             = {{IEEE 802.3an-2006}},
+  Year                     = {2006},
+
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.04.24}
+}
+
+@Misc{iepart10,
+  Title                    = {{Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications - Amendment 4: Media Access Control Parameters, Physical Layers and Management Parameters for 40 Gb/s and 100 Gb/s Operation }},
+
+  Author                   = {{IEEE 802.3ba}},
+  HowPublished             = {{IEEE 802.3ba-2010}},
+  Month                    = jun,
+  Year                     = {2010},
+
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.04.24}
+}
+
+@Standard{ieee754-2008,
+  Title                    = {{IEEE} 754-2008 {S}tandard for {F}loating-{P}oint {A}rithmetic},
+  Organization             = {IEEE Computer Society},
+  Author                   = {{IEEE-SA Standards Board}},
+  Language                 = {en},
+  Month                    = aug,
+  Revision                 = {2008},
+  Year                     = {2008},
+
+  File                     = {ieee754-2008.pdf:ieee754-2008.pdf:PDF},
+  Keywords                 = {Standard},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.21}
+}
+
+@Article{III2010,
+  Title                    = {{L}ow-{C}omplexity {R}eal-{T}ime {S}ingle-{T}one {P}hase and {F}requency {E}stimation},
+  Author                   = {D. R. Brown III and Y. Liao and N. Fox},
+  Journal                  = {IEEE Military Communication},
+  Year                     = {2010},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.03.03}
+}
+
+@PhdThesis{Phdiln13,
+  Title                    = {{S}tandard {C}ompliant {U}ltra {H}igh {T}hroughput {T}urbo {C}ode {D}ecoders},
+  Author                   = {Thomas Ilnseher},
+  School                   = {Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2013},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {StW},
+  Timestamp                = {2017.03.06}
+}
+
+@PhdThesis{Phdilnpre12,
+  Title                    = {{D}issertation in preparation},
+  Author                   = {Thomas Ilnseher},
+  School                   = {Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2012},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {May},
+  Timestamp                = {2012.04.10}
+}
+
+@InProceedings{ilnkie_12a,
+  Title                    = {{A 2.12Gbit/s Turbo Code Decoder for LTE Advanced Base Station Applications}},
+  Author                   = {Thomas Ilnseher and Frank Kienle and Christian Weis and Norbert Wehn},
+  Booktitle                = {2012 7th International Symposium on Turbo Codes and Iterative Information Processing (ISTC) (ISTC 2012)},
+  Year                     = {2012},
+
+  Address                  = {Gothenburg, Sweden},
+  Month                    = aug,
+
+  Abstract                 = {The LTE standard, will soon be upgraded to LTE advanced, which will add new techniques like multi user MIMO using iterative demodulation, cooperative multi point reception (CoMP) and beam forming to increase the system throughput in the uplink of one cell. An eNodeB supporting multiple cells will require a throughput of multiple GBit/s. Thus a turbo code decoder with a very high throughput target while maintaining an excellent communications performance is required. The major challenge is the support of very high code rates and the stringent latency requirements. We present the first LTE advanced compliant LTE turbo code decoder with a throughput of 2.15GBit/s at frequency of 450MHz and area of 7.7mm² in a 65nm process node with worst case P\&R constraints. The decoder can perform 6 full iterations at a large window size of 192 at full throughput, which results in a highly competitive communications performance.},
+  Days                     = {27},
+  File                     = {ilnkie_12.pdf:ilnkie_12.pdf:PDF},
+  Keywords                 = {Turbo Code; LTE Advanced; LTE; Base Station; High throughput}
+}
+
+@InProceedings{ilnmay_11,
+  Title                    = {{A} {M}onolithic {LTE} {I}nterleaver {G}enerator for {H}ighly {P}arallel {SMAP} {D}ecoders},
+  Author                   = {Thomas Ilnseher and Matthias May and Norbert Wehn},
+  Booktitle                = {Proc. Tenth Annual Wireless Telecommunications Symposium (WTS 2011)},
+  Year                     = {2011},
+  Month                    = apr,
+
+  File                     = {ilnmay_11.pdf:ilnmay_11.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {matthias},
+  Timestamp                = {2011.05.02}
+}
+
+@InProceedings{ilnmay_10,
+  Title                    = {{A} {M}ulti-{M}ode {3GPP}-{LTE}/{HSDPA} {T}urbo {D}ecoder},
+  Author                   = {Thomas Ilnseher and Matthias May and Norbert Wehn},
+  Booktitle                = {Proc. IEEE International Conference on Communication Systems (ICCS 2010)},
+  Year                     = {2010},
+  Month                    = nov,
+  Pages                    = {336 --340},
+
+  File                     = {ilnmay_10.pdf:ilnmay_10.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {matthias},
+  Timestamp                = {2010.09.21}
+}
+
+@Misc{IMEC2006,
+  Title                    = {{Scientific Report 2006: Software Defined Radio Flexible Air Interface}},
+
+  Author                   = {{IMEC}},
+  HowPublished             = {{{www.microelektronica.be/ wwwinter/mediacenter/en/SR2006/681340.html}}},
+  Year                     = {2006},
+
+  Owner                    = {vogt},
+  Timestamp                = {2007.05.31}
+}
+
+@Misc{imscientific06,
+  Title                    = {{Scientific Report 2006: Software Defined Radio Flexible Air Interface}},
+
+  Author                   = {{IMEC}},
+  HowPublished             = {{{www.microelektronica.be/ wwwinter/mediacenter/en/SR2006/681340.html}}},
+  Year                     = {2006},
+
+  Owner                    = {vogt},
+  Timestamp                = {2007.05.31}
+}
+
+@Misc{imote2,
+  Title                    = {i{M}ote2: http://docs.tinyos.net/index.php/{I}mote2},
+
+  Author                   = {Crossbow Technology Inc.},
+  Year                     = {2007},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://docs.tinyos.net/index.php/Imote2}
+}
+
+@Misc{Inc.2007,
+  Title                    = {i{M}ote2: http://docs.tinyos.net/index.php/{I}mote2},
+
+  Author                   = {Crossbow Technology Inc.},
+  Year                     = {2007},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://docs.tinyos.net/index.php/Imote2}
+}
+
+@Electronic{inf_16,
+  Title                    = {{A}urix {F}amily},
+  Author                   = {Infineon},
+  HowPublished             = {\url{http://www.infineon.com/cms/de/product/microcontroller/32-bit-tricore-tm-microcontroller/aurix-tm-family/channel.html?channel=db3a30433727a44301372b2eefbb48d9}},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-24}
+}
+
+@InProceedings{ingtho_13,
+  Title                    = {{A} {H}eterogeneous {C}omputing {F}ramework for {C}omputational {F}inance},
+  Author                   = {Inggs, G. and Thomas, D. and Luk, W.},
+  Booktitle                = {Parallel Processing (ICPP), 2013 42nd International Conference on},
+  Year                     = {2013},
+
+  Address                  = {Lyon, France},
+  Month                    = oct,
+  Pages                    = {688-697},
+
+  Abstract                 = {This paper presents the Forward Financial Framework (F3), an application framework for describing and implementing forward looking financial computations on high performance, heterogeneous platforms. F3 allows the computational finance problem specification to be captured precisely yet succinctly, then automatically creates efficient implementations for heterogeneous platforms, utilising both multi-core CPUs and FPGAs. The automatic mapping of a high-level problem description to a low-level heterogeneous implementation is possible due to the domain-specific knowledge which is built in F3, along with a software architecture that allows for additional domain knowledge and rules to be added to the framework. Currently the system is able to utilise domain-knowledge of the run-time characteristics of pricing tasks to partition pricing problems and allocate them to appropriate compute resources, and to exploit relationships between financial instruments to balance computation against communication. The versatility of the framework is demonstrated using a benchmark of option pricing problems, where F3 achieves comparable speed and energy efficiency to external manual implementations. Further, the domain-knowledge guided partitioning scheme suggests a partitioning of subtasks that is 13% faster than the average, while exploiting domain dependencies to reduce redundant computations results in an average gain in efficiency of 27%.},
+  Cds_grade                = {0},
+  Cds_review               = {cites schshc_11
+uses our benchmark},
+  Doi                      = {10.1109/ICPP.2013.82},
+  File                     = {ingtho_13.pdf:ingtho_13.pdf:PDF},
+  ISSN                     = {0190-3918},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-04-22}
+}
+
+@Misc{Inmarsat,
+  Title                    = {{Vector-LDPC Core Solutions}},
+
+  Author                   = {{Inmarsat}},
+  HowPublished             = {{{www.inmarsat.com}}},
+
+  Key                      = {inmarsat},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{invector-ldpc,
+  Title                    = {{Vector-LDPC Core Solutions}},
+
+  Author                   = {{Inmarsat}},
+  HowPublished             = {{{www.inmarsat.com}}},
+
+  Key                      = {inmarsat},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{inoli_08,
+  Title                    = {{VAST}: {V}irtualization-{A}ssisted {C}oncurrent {A}utonomous {S}elf-{T}est},
+  Author                   = {Inoue, H. and Yanjing Li and Mitra, S.},
+  Booktitle                = {Proc. IEEE International Test Conference ITC 2008},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {1--10},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/TEST.2008.4700583},
+  File                     = {inoli_08.pdf:inoli_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.14}
+}
+
+@Misc{cc1000,
+  Title                    = {{CC}1000 datasheet: http://focus.ti.com/lit/ds/symlink/cc1000.pdf},
+
+  Author                   = {Texas Instruments},
+  Month                    = {February},
+  Year                     = {2007},
+
+  File                     = {cc1000.pdf:cc1000.pdf:PDF},
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://focus.ti.com/lit/ds/symlink/cc1000.pdf}
+}
+
+@Misc{cc2420,
+  Title                    = {{CC}2420 datasheet: http://focus.ti.com/lit/ds/symlink/cc2420.pdf},
+
+  Author                   = {Texas Instruments},
+  Month                    = {March},
+  Year                     = {2007},
+
+  File                     = {cc2420.pdf:cc2420.pdf:PDF},
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://focus.ti.com/lit/ds/symlink/cc2420.pdf}
+}
+
+@Misc{Instruments2007,
+  Title                    = {{CC}1000 datasheet: http://focus.ti.com/lit/ds/symlink/cc1000.pdf},
+
+  Author                   = {Texas Instruments},
+  Month                    = {February},
+  Year                     = {2007},
+
+  File                     = {cc1000.pdf:cc1000.pdf:PDF},
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://focus.ti.com/lit/ds/symlink/cc1000.pdf}
+}
+
+@Misc{Instruments2007a,
+  Title                    = {{CC}2420 datasheet: http://focus.ti.com/lit/ds/symlink/cc2420.pdf},
+
+  Author                   = {Texas Instruments},
+  Month                    = {March},
+  Year                     = {2007},
+
+  File                     = {cc2420.pdf:cc2420.pdf:PDF},
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://focus.ti.com/lit/ds/symlink/cc2420.pdf}
+}
+
+@Misc{IntegratedBroadb,
+  Title                    = {{Synthesis report on the performance and complexity obtained with the HW and SW platforms (D7.2)}},
+
+  Author                   = {MATRICE - MC-CDMA Transmission Techniques for Integrated Broadband Cellular Systems},
+  HowPublished             = {{{http://ist-matrice.org}}},
+
+  Key                      = {MATRICE},
+  Optannote                = {D7.2},
+  Optmonth                 = {#oct#},
+  Optyear                  = {2004},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{IntegratedBroadba,
+  Title                    = {{Synthesis Report on worldwide research on 4G systems (D7.1)}},
+
+  Author                   = {MATRICE -- MC-CDMA Transmission Techniques for Integrated Broadband Cellular Systems},
+  HowPublished             = {{{http://ist-matrice.org}}},
+
+  Key                      = {MATRICE},
+  Optannote                = {D7.1},
+  Optmonth                 = {#sep#},
+  Optyear                  = {2003},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{intsynthesis,
+  Title                    = {{Synthesis report on the performance and complexity obtained with the HW and SW platforms (D7.2)}},
+
+  Author                   = {MATRICE - MC-CDMA Transmission Techniques for Integrated Broadband Cellular Systems},
+  HowPublished             = {{{http://ist-matrice.org}}},
+
+  Key                      = {MATRICE},
+  Optannote                = {D7.2},
+  Optmonth                 = {#oct#},
+  Optyear                  = {2004},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{intsynthesisa,
+  Title                    = {{Synthesis Report on worldwide research on 4G systems (D7.1)}},
+
+  Author                   = {MATRICE -- MC-CDMA Transmission Techniques for Integrated Broadband Cellular Systems},
+  HowPublished             = {{{http://ist-matrice.org}}},
+
+  Key                      = {MATRICE},
+  Optannote                = {D7.1},
+  Optmonth                 = {#sep#},
+  Optyear                  = {2003},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Electronic{intel_xpoint,
+  Title                    = {3{D} {XP}oint: {A} {B}reakthrough in {N}on-{V}olatile {M}emory {T}echnology},
+  Author                   = {Intel},
+  Url                      = {https://www.intel.com/content/www/us/en/architecture-and-technology/intel-micron-3d-xpoint-webcast.html},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-08-29}
+}
+
+@Electronic{intintegrated,
+  Title                    = {{I}ntegrated {P}erformance {P}rimitives},
+  Author                   = {Intel},
+  HowPublished             = {\url{https://software.intel.com/en-us/intel-ipp}},
+  Note                     = {last access 2015-01-13},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.24}
+}
+
+@Misc{intmath,
+  Title                    = {{M}ath {K}ernel {L}ibrary},
+
+  Author                   = {Intel},
+  HowPublished             = {\url{https://software.intel.com/en-us/intel-mkl}},
+  Note                     = {last access 2015-01-13},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.24}
+}
+
+@Electronic{int_14,
+  Title                    = {{T}hunderbolt},
+  Author                   = {Intel},
+  Url                      = {http://www.thunderbolttechnology.net},
+  Year                     = {2014},
+
+  Owner                    = {Schlaefer},
+  Timestamp                = {2014.05.22}
+}
+
+@Electronic{int_14a,
+  Title                    = {{OpenCL Design and Programming Guide for the Intel Xeon Phi Coprocessor}},
+  Author                   = {{Intel}},
+  Month                    = {Jan},
+  Note                     = {last access: 31 Aug 2017},
+  Url                      = {https://software.intel.com/en-us/articles/opencl-design-and-programming-guide-for-the-intel-xeon-phi-coprocessor?language=ru},
+  Year                     = {2014},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.08.21}
+}
+
+@Electronic{int_13,
+  Title                    = {{M}onte {C}arlo {M}ethod for {S}tock {O}ptions {P}ricing {S}ample ({O}pen{CL})},
+  Author                   = {{Intel}},
+  HowPublished             = {\url{https://software.intel.com/en-us/intel-opencl-code-builder-support/code-samples}},
+  Language                 = {en},
+  Note                     = {last access 2015-10-13},
+  Url                      = {\url{https://software.intel.com/en-us/intel-opencl-code-builder-support/code-samples}},
+  Year                     = {2013},
+
+  Keywords                 = {finance},
+  Owner                    = {varela},
+  Timestamp                = {2015.08.18}
+}
+
+@Misc{initrs,
+  Title                    = {{ITRS home page}},
+
+  Author                   = {{International Technology Roadmap for Semiconductors 2011}},
+  HowPublished             = {{{http://public.itrs.net}}},
+
+  File                     = {initrs_ITRS_2007_ExecSum.pdf:initrs_ITRS_2007_ExecSum.pdf:PDF;initrs_ITRS_2006_Design_Update.pdf:initrs_ITRS_2006_Design_Update.pdf:PDF;initrs_ITRS_2007_ERD.pdf:initrs_ITRS_2007_ERD.pdf:PDF;initrs_ITRS_2007_PIDS.pdf:initrs_ITRS_2007_PIDS.pdf:PDF;initrs_ITRS_2005_Design.pdf:initrs_ITRS_2005_Design.pdf:PDF;initrs_ITRS_2007_Design.pdf:initrs_ITRS_2007_Design.pdf:PDF;initrs_ITRS_2007_Wireless.pdf:initrs_ITRS_2007_Wireless.pdf:PDF;initrs_ITRS_2007_Yield.pdf:initrs_ITRS_2007_Yield.pdf:PDF;initrs_ITRS_2007_SystemDrivers.pdf:initrs_ITRS_2007_SystemDrivers.pdf:PDF},
+  Key                      = {itrs},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{ITRS,
+  Title                    = {{ITRS home page}},
+
+  Author                   = {{International Technology Roadmap for Semiconductors 2011}},
+  HowPublished             = {{{http://public.itrs.net}}},
+
+  File                     = {initrs_ITRS_2007_ExecSum.pdf:initrs_ITRS_2007_ExecSum.pdf:PDF;initrs_ITRS_2006_Design_Update.pdf:initrs_ITRS_2006_Design_Update.pdf:PDF;initrs_ITRS_2007_ERD.pdf:initrs_ITRS_2007_ERD.pdf:PDF;initrs_ITRS_2007_PIDS.pdf:initrs_ITRS_2007_PIDS.pdf:PDF;initrs_ITRS_2005_Design.pdf:initrs_ITRS_2005_Design.pdf:PDF;initrs_ITRS_2007_Design.pdf:initrs_ITRS_2007_Design.pdf:PDF;initrs_ITRS_2007_Wireless.pdf:initrs_ITRS_2007_Wireless.pdf:PDF;initrs_ITRS_2007_Yield.pdf:initrs_ITRS_2007_Yield.pdf:PDF;initrs_ITRS_2007_SystemDrivers.pdf:initrs_ITRS_2007_SystemDrivers.pdf:PDF},
+  Key                      = {itrs},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{initu-r,
+  Title                    = {{ITU-R home page}},
+
+  Author                   = {{International Telecommunication Union -- Radiocommunication Sector}},
+  HowPublished             = {{{www.itu.int/ITU-R/}}},
+
+  Key                      = {ITU-R},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{ITURS,
+  Title                    = {{ITU-R home page}},
+
+  Author                   = {{International Telecommunication Union -- Radiocommunication Sector}},
+  HowPublished             = {{{www.itu.int/ITU-R/}}},
+
+  Key                      = {ITU-R},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Electronic{irds_17,
+  Title                    = {{I}nternational {R}oadmap for {D}evices and {S}ystems},
+  Author                   = {IRDS2017},
+  Year                     = {2017},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-05-02}
+}
+
+@Article{irmbaj_05,
+  Title                    = {{A rapid system prototyping platform for error control coding in optical CDMA networks}},
+  Author                   = {Martin Irman and Jan Bajcsy},
+  Journal                  = {IEEE International Workshop on Rapid System Prototyping},
+  Year                     = {2005},
+
+  Month                    = jun,
+  Pages                    = {232-234},
+
+  File                     = {irmbaj_05.pdf:irmbaj_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{isejoh_09,
+  Title                    = {{ESKIMO} - energy savings using semantic knowledge of inconsequential memory occupancy for {DRAM} subsystem},
+  Author                   = {Isen, C. and John, L.},
+  Booktitle                = {Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on},
+  Year                     = {2009},
+  Month                    = {Dec},
+  Pages                    = {337-346},
+
+  ISSN                     = {1072-4451},
+  Keywords                 = {DRAM chips;operating systems (computers);optimisation;power aware computing;power consumption;storage management;DRAM subsystem;DRAMsim;ESKIMO;dynamic random access memory;energy saving;hardware validated DRAM simulator;inconsequential memory occupancy;memory manager;operating systems;optimization;power consumption reduction;semantic knowledge;Computer architecture;DRAM chips;Energy consumption;Energy management;Memory management;Microarchitecture;Operating systems;Power system management;Prefetching;Random access memory;Memory power and energy;allocated and freed memory states;cross-boundary or cross-layer architecture optimizations;program semantic aware architecture},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@InProceedings{ishyas_98,
+  Title                    = {{Voltage Scheduling Problem for Dynamically Variable Voltage Processors}},
+  Author                   = {T. Ishihara and H. Yasuura},
+  Booktitle                = {Proc. 1998 International Symposium on Low Power Electronics and Design (ISLPED '98)},
+  Year                     = {1998},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = aug,
+  Pages                    = {197--202},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{ishshi_06,
+  Title                    = {{High-throughput deocder for low-density parity-check code}},
+  Author                   = {Tatsuyuki Ishikawa and Kazunori Shimizu and Takeshi Ikenaga and Satoshi Goto},
+  Booktitle                = {Proc. 2006 conference on Asia South Pacific design automation (ASPDAC)},
+  Year                     = {2006},
+
+  Address                  = {Yokohama, Japan},
+  Month                    = feb,
+  Pages                    = {112-113},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{iso26262,
+  Title                    = {{Road vehicles -- Functional safety}},
+
+  Author                   = {ISO},
+  Year                     = {{2011}},
+
+  Added-at                 = {2013-09-11T11:25:58.000+0200},
+  Key                      = {{ISO 26262}},
+  Keywords                 = {26262 iso},
+  Number                   = {{ISO 26262}},
+  Owner                    = {MJ},
+  Publisher                = {{ISO, Geneva, Switzerland}},
+  Timestamp                = {2013-09-11T11:25:58.000+0200},
+  Type                     = {{Norm}}
+}
+
+@Electronic{ITRS15,
+  Title                    = {{International Technology Roadmap for Semiconductors, 2015 Edition, Section 5: More Moore.}},
+  Author                   = {{ITRS 2.0}},
+  Url                      = {http://www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/},
+
+  Owner                    = {MH},
+  Timestamp                = {2017-05-25},
+  Urldate                  = {25.05.2017}
+}
+
+@Misc{itu_4g,
+  Title                    = {{B}ackground on {IMT}-{A}dvanced},
+
+  Author                   = {ITU},
+  HowPublished             = {Document IMT-ADV/1-E},
+  Month                    = {March},
+  Year                     = {2008},
+
+  Owner                    = {ilnseher},
+  Timestamp                = {2011.07.21},
+  Url                      = {http://www.itu.int/md/R07-IMT.ADV-C-0001/en}
+}
+
+@Misc{ITU2008,
+  Title                    = {{B}ackground on {IMT}-{A}dvanced},
+
+  Author                   = {ITU},
+  HowPublished             = {Document IMT-ADV/1-E},
+  Month                    = {March},
+  Year                     = {2008},
+
+  Owner                    = {ilnseher},
+  Timestamp                = {2011.07.21},
+  Url                      = {http://www.itu.int/md/R07-IMT.ADV-C-0001/en}
+}
+
+@InProceedings{itulop_06,
+  Title                    = {{New Schemes in Clustered VLIW Processors Applied to Turbo Decoding}},
+  Author                   = {Ituero, P. and Lopez-Vallejo, M.},
+  Booktitle                = {Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on},
+  Year                     = {2006},
+  Month                    = sep,
+  Pages                    = {291--296},
+
+  Doi                      = {10.1109/ASAP.2006.48},
+  File                     = {itulop_06.pdf:itulop_06.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.05}
+}
+
+@InProceedings{itulop_05,
+  Title                    = {{A Configurable Application Specific Processor for Turbo Decoding}},
+  Author                   = {Ituero, P. and Lopez-Vallejo, M. and Mujtaba, S.A.},
+  Booktitle                = {Conference Record of the Thirty-Ninth Asilomar Conference on Signals, Systems and Computers, 2005.},
+  Year                     = {2005},
+  Month                    = oct # {--} # nov,
+  Pages                    = {1356--1360},
+
+  File                     = {itulop_05.pdf:itulop_05.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.06}
+}
+
+@Article{iwa_09,
+  Title                    = {{R}oadmap for 22nm and beyond},
+  Author                   = {Iwai, HIROSHI},
+  Journal                  = {Microelectronic Engineering},
+  Year                     = {2009},
+  Number                   = {7},
+  Pages                    = {1520--1528},
+  Volume                   = {86},
+
+  Owner                    = {Brugger},
+  Publisher                = {Elsevier},
+  Timestamp                = {2014.06.15}
+}
+
+@Article{iyekal_07,
+  Title                    = {{T}oward {A}pplication-{A}ware {S}ecurity and {R}eliability},
+  Author                   = {Iyer, R. K. and Kalbarczyk, Z. and Karthik Pattabiraman and Healey, W. and Hwu, W.-M. W. and Klemperer, P. and Farivar, R.},
+  Journal                  = {IEEE Security Privacy},
+  Year                     = {2007},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {57--62},
+  Volume                   = {5},
+
+  Doi                      = {10.1109/MSP.2007.23},
+  File                     = {iyekal_07.pdf:iyekal_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.20}
+}
+
+@Article{jac_01,
+  Title                    = {{D}istribution de la flore alpine dans le bassin des {D}ranses et dans quelques r{\'e}gions voisines},
+  Author                   = {Paul Jaccard},
+  Journal                  = {Bulletin de la Soci{\'e}t{\'e} Vaudoise des Sciences Naturelles},
+  Year                     = {1901},
+  Pages                    = {241--272},
+  Volume                   = {37},
+
+  Owner                    = {Ninasnet},
+  Timestamp                = {2014.11.28}
+}
+
+@InProceedings{jacadk_19,
+  Title                    = {{C}apacity over {C}apacitance for {R}eliable {E}nergy {H}arvesting {S}ensors},
+  Author                   = {Jackson, Neal and Adkins, Joshua and Dutta, Prabal},
+  Booktitle                = {Proceedings of the 18th International Conference on Information Processing in Sensor Networks},
+  Year                     = {2019},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {193--204},
+  Publisher                = {ACM},
+  Series                   = {IPSN '19},
+
+  Acmid                    = {3310400},
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Jackson:2019:COC:3302506.3310400},
+  Ccr_keywords             = {study further!},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1145/3302506.3310400},
+  ISBN                     = {978-1-4503-6284-9},
+  Keywords                 = {TCS},
+  Keywords_original        = {battery, capacity, energy harvesting, sensor network},
+  Location                 = {Montreal, Quebec, Canada},
+  Numpages                 = {12},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/3302506.3310400}
+}
+
+@InProceedings{jacjee_11,
+  Title                    = {{A} new architecture for the generation of picture based {CAPTCHA}: {D}ouble binary convolutional turbo decoder using low power memory reduced traceback {MAP} decoding},
+  Author                   = {Jackuline, S. and Jeevitha, J. and Nidhi, M. A. },
+  Booktitle                = {Proc. 3rd Int Electronics Computer Technology (ICECT) Conf},
+  Year                     = {2011},
+  Pages                    = {382--385},
+  Volume                   = {6},
+
+  Doi                      = {10.1109/ICECTECH.2011.5942120},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@Book{jac_09,
+  Title                    = {{T}he {M}emory {S}ystem: {Y}ou {C}an'{T} {A}void {I}t, {Y}ou {C}an'{T} {I}gnore {I}t, {Y}ou {C}an'{T} {F}ake {I}t},
+  Author                   = {Jacob, Bruce},
+  Publisher                = {Morgan and Claypool Publishers},
+  Year                     = {2009},
+
+  ISBN                     = {159829587X, 9781598295870},
+  Owner                    = {MJ},
+  Timestamp                = {2016-10-30}
+}
+
+@Book{jacng_10,
+  Title                    = {{M}emory {S}ystems: {C}ache, {DRAM}, {D}isk},
+  Author                   = {Jacob, Bruce and Ng, S. and Wang, D.},
+  Publisher                = {Elsevier Science},
+  Year                     = {2010},
+
+  ISBN                     = {9780080553849},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.12}
+}
+
+@InProceedings{jacjac_11,
+  Title                    = {{V}erification of {T}imed-{A}rc {P}etri {N}ets},
+  Author                   = {Jacobsen, Lasse and Jacobsen, Morten and M{\o}ller, Mikael H. and Srba, Ji{\v{r}}{\'i}},
+  Booktitle                = {SOFSEM 2011: Theory and Practice of Computer Science},
+  Year                     = {2011},
+
+  Address                  = {Berlin, Heidelberg},
+  Editor                   = {{\v{C}}ern{\'a}, Ivana
+and Gyim{\'o}thy, Tibor
+and Hromkovi{\v{c}}, Juraj
+and Jefferey, Keith
+and Kr{\'a}lovi{\'{c}}, Rastislav
+and Vukoli{\'{c}}, Marko
+and Wolf, Stefan},
+  Pages                    = {46--72},
+  Publisher                = {Springer Berlin Heidelberg},
+
+  Abstract                 = {Timed-Arc Petri Nets (TAPN) are an extension of the classical P/T nets with continuous time. Tokens in TAPN carry an age and arcs between places and transitions are labelled with time intervals restricting the age of tokens available for transition firing. The TAPN model posses a number of interesting theoretical properties distinguishing them from other time extensions of Petri nets. We shall give an overview of the recent theory developed in the verification of TAPN extended with features like read/transport arcs, timed inhibitor arcs and age invariants. We will examine in detail the boundaries of automatic verification and the connections between TAPN and the model of timed automata. Finally, we will mention the tool TAPAAL that supports modelling, simulation and verification of TAPN and discuss a small case study of alternating bit protocol.},
+  ISBN                     = {978-3-642-18381-2},
+  Owner                    = {MJ},
+  Timestamp                = {2018-07-15}
+}
+
+@Booklet{jae_03,
+  Title                    = {{K}analcodierung mittels {BCH}-{C}ode},
+  Author                   = {Martin Jaensch},
+  Month                    = nov,
+  Year                     = {2003},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {BCH codes, Kanalcodierung, Syndrome, Channel Code, Key Equation, Chien Search},
+  Cds_read                 = {2008-09},
+  Date-added               = {2008-09-15 16:06:29 +0200},
+  Date-modified            = {2008-09-15 16:07:33 +0200},
+  File                     = {jae_03.pdf:jae_03.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InBook{jafbag_11,
+  Title                    = {{ASIP design and prototyping for wireless communication applications}},
+  Author                   = {Atif Raza Jafri and Amer Baghdadi and Michel Jezequel},
+  Chapter                  = {Advanced Applications of Rapid Prototyping Technology in Modern Engineering},
+  Publisher                = {InTech - Open Access Publisher},
+  Year                     = {2011}
+}
+
+@InProceedings{jafbag_10,
+  Title                    = {{R}apid design and prototyping of universal soft demapper},
+  Author                   = {Atif Raza Jafri and Amer Baghdadi and Michel Jezequel},
+  Booktitle                = {IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2010},
+  Month                    = {May},
+  Pages                    = {3769-3772},
+
+  Keywords                 = {application specific integrated circuits;field programmable gate arrays;quadrature amplitude modulation;radiocommunication;software prototyping;telecommunication computing;ADL;ASIP;Gray mapped 16-QAM constellation;LISA;Virtex LX330 FPGA;frequency 156 MHz;modulation;non-turbo context;prototyping;time-to-market constraints;turbo context;universal soft demapper;wireless communication standardization;Application specific processors;Design methodology;Emulation;Field programmable gate arrays;Logic;Prototypes;Standardization;Throughput;Time to market;Wireless communication}
+}
+
+@Article{jafbag_09,
+  Title                    = {{ASIP}-{B}ased {U}niversal {D}emapper for {M}ultiwireless {S}tandards},
+  Author                   = {Atif Raza Jafri and Amer Baghdadi and Michel Jezequel},
+  Journal                  = {IEEE Embedded Systems Letters},
+  Year                     = {2009},
+
+  Month                    = {May},
+  Number                   = {1},
+  Pages                    = {9-13},
+  Volume                   = {1},
+
+  ISSN                     = {1943-0663},
+  Keywords                 = {demodulation;microprocessor chips;quadrature amplitude modulation;quadrature phase shift keying;radio receivers;256-QAM rotated constellation;ASIP;QPSK Gray-mapped constellation;application specific instruction-set processor;flexible radio platform;iterative receiver;multiwireless standard;noniterative receiver;turbo demodulation;universal demapper;Application specific instruction-set processor (ASIP);demapper;modulation;multiwireless standards}
+}
+
+@InProceedings{jafkar_09,
+  Title                    = {{ASIP}-based flexible {MMSE}-{IC} {L}inear {E}qualizer for {MIMO} turbo-equalization applications},
+  Author                   = {Jafri, A. R. and Karakolah, D. and Baghdadi, A. and Jezequel, M. },
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conf. \& Exhibition},
+  Year                     = {2009},
+  Pages                    = {1620--1625},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.07.23}
+}
+
+@InProceedings{jagdie_16,
+  Title                    = {{E}xploring {S}ystem {P}erformance using {E}lastic {T}races: {F}ast, {A}ccurate and {P}ortable},
+  Author                   = {Jagtap, Radhika and Diestelhorst, Stephan and Hansson, Andreas and Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-05-14}
+}
+
+@Conference{jagjun_17,
+  Title                    = {{I}ntegrating {DRAM} {P}ower-{D}own {M}odes in gem5 and {Q}uantifying their {I}mpact},
+  Author                   = {Jagtap, Radhika and Jung, Matthias and Elsasser, Wendy and Weis, Christian and Hansson, Andreas and Wehn, Norbert},
+  Booktitle                = {International Symposium on Memory Systems (MEMSYS17)},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-29}
+}
+
+@InProceedings{jahjun_18,
+  Title                    = {{A} {F}ramework for {N}on-{I}ntrusive {T}race-driven {S}imulation of {M}anycore {A}rchitectures with {D}ynamic {T}racing {C}onfiguration},
+  Author                   = {Jahić, Jasmin and Jung, Matthias and Kuhn, Thomas and Kestel, Claus and Wehn, Norbert},
+  Booktitle                = {The 18th International Conference on Runtime Verification (RV 2018)},
+  Year                     = {2018},
+  Month                    = {November},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-21}
+}
+
+@Conference{jahjun_17,
+  Title                    = {{S}upervised {T}esting of {C}oncurrent {S}oftware in {E}mbedded {S}ystems},
+  Author                   = {Jahić, Jasmin and Jung, Matthias and Kuhn, Thomas and Wehn, Norbert},
+  Booktitle                = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
+  Year                     = {2017},
+  Month                    = {July},
+  Pages                    = {233-238},
+
+  Doi                      = {10.1109/SAMOS.2017.8344633},
+  Keywords                 = {Computer bugs;Concurrent computing;Instruction sets;Synchronization;Task analysis;Testing;Concurrency;Data Races;FERAL;LLVM;Scheduling;Testing;Virtual Prototyping},
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-10}
+}
+
+@InProceedings{jahkuh_18,
+  Title                    = {{BOSMI}: {A} {F}ramework for {N}on-intrusive {M}onitoring and {T}esting of {E}mbedded {M}ultithreaded {S}oftware on the {L}ogical {L}evel},
+  Author                   = {Jahić, Jasmin and Kuhn, Thomas and Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation},
+  Year                     = {2018},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {131--138},
+  Publisher                = {ACM},
+  Series                   = {SAMOS '18},
+
+  Acmid                    = {3229641},
+  Doi                      = {10.1145/3229631.3229641},
+  ISBN                     = {978-1-4503-6494-2},
+  Keywords                 = {LLVM, concurrency, coverage, execution control, execution monitoring},
+  Location                 = {Pythagorion, Greece},
+  Numpages                 = {8},
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-25},
+  Url                      = {http://doi.acm.org/10.1145/3229631.3229641}
+}
+
+@InProceedings{jahkum_19,
+  Title                    = {{R}apid {I}dentification of {S}hared {M}emory in {M}ultithreaded {E}mbedded {S}ystems with {S}tatic {S}cheduling},
+  Author                   = {Jahic, Jasmin and Kumar, Varun and Jung, Matthias and Wirrer, Gerhard and Wehn, Norbert and Kuhn, Thomas},
+  Booktitle                = {Proceedings of the 48th International Conference on Parallel Processing: Workshops},
+  Year                     = {2019},
+
+  Address                  = {New York, NY, USA},
+  Publisher                = {Association for Computing Machinery},
+  Series                   = {ICPP 2019},
+
+  Articleno                = {Article 15},
+  Doi                      = {10.1145/3339186.3339195},
+  ISBN                     = {9781450371964},
+  Keywords                 = {static scheduling, Data races, Lockset, embedded systems},
+  Location                 = {Kyoto, Japan},
+  Numpages                 = {8},
+  Owner                    = {MJ},
+  Timestamp                = {2020-02-03},
+  Url                      = {https://doi.org/10.1145/3339186.3339195}
+}
+
+@Article{jahsha_09a,
+  Title                    = {{A}n {A}nalytical {M}odel for {S}oft {E}rror {C}ritical {C}harge of {N}anometric {SRAM}s},
+  Author                   = {Jahinuzzaman, S.M. and Sharifkhani, M. and Sachdev, M.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2009},
+
+  Month                    = {sept. },
+  Number                   = {9},
+  Pages                    = {1187 -1195},
+  Volume                   = {17},
+
+  Doi                      = {10.1109/TVLSI.2008.2003511},
+  ISSN                     = {1063-8210},
+  Keywords                 = {CMOS process;MIM capacitor;NMOS transistor;PMOS transistor;SPICE simulations;critical charge model;manufacturing defects;nanometric SRAMs;nonlinearly coupled storage nodes;resistive contacts;size 90 nm;soft error critical charge;storage node decoupling;transistor size scaling;vias;CMOS memory circuits;MIM devices;SPICE;SRAM chips;}
+}
+
+@Article{jahsha_09,
+  Title                    = {{D}esign and {A}nalysis of {A} 5.3-p{J} 64-kb {G}ated {G}round {SRAM} {W}ith {M}ultiword {ECC}},
+  Author                   = {Jahinuzzaman, S. M. and Shah, J. S. and Rennie, D. J. and Sachdev, M. },
+  Journal                  = {Solid-State Circuits, IEEE Journal of},
+  Year                     = {2009},
+  Number                   = {9},
+  Pages                    = {2543--2553},
+  Volume                   = {44},
+
+  Doi                      = {10.1109/JSSC.2009.2021088},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{jalott_05,
+  Title                    = {{P}arallel {I}mplementation of a {S}oft {O}utput {S}phere {D}ecoder},
+  Author                   = {Jalden, J. and Ottersten, B.},
+  Booktitle                = {Signals, Systems and Computers, 2005. Conference Record of the Thirty-Ninth Asilomar Conference on},
+  Year                     = {2005},
+  Pages                    = {581-585},
+
+  Doi                      = {10.1109/ACSSC.2005.1599816},
+  File                     = {jalott_05.pdf:jalott_05.pdf:PDF},
+  ISSN                     = {1058-6393},
+  Keywords                 = {antenna arrays;approximation theory;block codes;channel coding;concatenated codes;fading channels;space-time codes;concatenating inner codes;fading multiple antenna channels;log-likelihood ratios;max-log approximation;parallel implementation;soft output sphere decoder;space-time block codes;Capacitive sensors;Concurrent computing;Data models;Demodulation;Error correction codes;Fading;Iterative decoding;MIMO;Parity check codes;Vectors},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.02}
+}
+
+@InBook{janklu_11,
+  Title                    = {{S}tatistical {T}ools for {F}inance and {I}nsurance},
+  Author                   = {Agnieszka Janek and Tino Kluge and Rafał Weron and Uwe Wystup},
+  Chapter                  = {FX smile in the Heston model},
+  Editor                   = {Pavel Cizek and Wolfgang Karl Härdle and Rafał Weron},
+  Pages                    = {133-162},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2011},
+
+  Abstract                 = {The Heston model stands out from the class of stochastic volatility (SV) models mainly for two reasons. Firstly, the process for the volatility is non-negative and mean-reverting, which is what we observe in the markets. Secondly, there exists a fast and easily implemented semi-analytical solution for European options. In this article we adapt the original work of Heston (1993) to a foreign exchange (FX) setting. We discuss the computational aspects of using the semi-analytical formulas, performing Monte Carlo simulations, checking the Feller condition, and option pricing with FFT. In an empirical study we show that the smile of vanilla options can be reproduced by suitably calibrating three out of five model parameters.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Feller condition},
+  Comment                  = {eBook ISBN 978-3-642-18062-0},
+  Doi                      = {10.1007/978-3-642-18062-0_4},
+  File                     = {janklu_11.pdf:janklu_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.11}
+}
+
+@InCollection{janklu_11a,
+  Title                    = {{FX} smile in the {H}eston model},
+  Author                   = {Janek, Agnieszka and Kluge, Tino and Weron, Rafa{\l} and Wystup, Uwe},
+  Booktitle                = {Statistical Tools for Finance and Insurance},
+  Publisher                = {Springer},
+  Year                     = {2011},
+  Pages                    = {133--162},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.08.21}
+}
+
+@MastersThesis{MTjaque02,
+  Title                    = {{Eine kommunikationsorientierte Multiprozessor-Architektur für High-Throughput Turbo-Decoder Systeme}},
+  Author                   = {D. Jaquet},
+  School                   = {Microelectronic System Design Reseach Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2002},
+  Month                    = dec,
+  Note                     = {In German},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{jasped_10,
+  Title                    = {{A}n {I}mproved {GF}(2) {M}atrix {I}nverter with {L}inear {T}ime {C}omplexity},
+  Author                   = {Jasinski, R.P. and Pedroni, V.A. and Gortan, A. and Godoy, W.},
+  Booktitle                = {Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on},
+  Year                     = {2010},
+  Month                    = {dec.},
+  Pages                    = {322 -327},
+
+  Doi                      = {10.1109/ReConFig.2010.86},
+  File                     = {jasped_10.pdf:jasped_10.pdf:PDF},
+  Owner                    = {Scholl},
+  Review                   = {verbesserter SMITH},
+  Timestamp                = {2013.02.04}
+}
+
+@PhdThesis{Phdjason03,
+  Title                    = {{S}ystem {A}rchitecture for {W}ireless {S}ensor {N}etworks},
+  Author                   = {Jason Lester Hill, David E. Culler, Chair, Kris Pister, Paul Wright},
+  School                   = {UC Berkeley},
+  Year                     = {2003},
+
+  Abstract                 = {In this thesis we present and operating system and three generations of a hardware
+platform designed to address the needs of wireless sensor networks. Our operating
+system, called TinyOS uses an event based execution model to provide support for finegrained
+concurrency and incorporates a highly efficient component model. TinyOS
+enables us to use a hardware architecture that has a single processor time shared between
+both application and protocol processing. We show how a virtual partitioning of
+computational resources not only leads to efficient resource utilization but allows for a
+rich interface between application and protocol processing. This rich interface, in turn,
+allows developers to exploit application specific communication protocols that
+significantly improve system performance.
+The hardware platforms we develop are used to validate a generalized architecture
+that is technology independent. Our general architecture contains a single central
+controller that performs both application and protocol-level processing. For flexibility,
+this controller is directly connected to the RF transceiver. For efficiency, the controller is
+supported by a collection of hardware accelerators that provide basic communication
+primitives that can be flexibility composed into application specific protocols.
+The three hardware platforms we present are instances of this general architecture
+with varying degrees of hardware sophistication. The Rene platform serves as a baseline
+and does not contain any hardware accelerators. It allows us to develop the TinyOS
+operating system concepts and refine its concurrency mechanisms. The Mica node
+incorporates hardware accelerators that improve communication rates and
+synchronization accuracy within the constraints of current microcontrollers. As an
+approximation of our general architecture, we use Mica to validate the underlying
+architectural principles. The Mica platform has become the foundation for hundreds of
+wireless sensor network research efforts around the world. It has been sold to more than
+250 organizations.
+Spec is the most advanced node presented and represents the full realization of
+our general architecture. It is a 2.5 mm x 2.5 mm CMOS chip that includes processing,
+storage, wireless communications and hardware accelerators. We show how the careful
+selection of the correct accelerators can lead to orders-of-magnitude improvements in
+efficiency without sacrificing flexibility. In addition to performing a theoretical analysis
+on the strengths of our architecture, we demonstrate its capabilities through a collection
+of real-world application deployments.},
+  File                     = {Phdjason03.pdf:Phdjason03.pdf:PDF},
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21}
+}
+
+@InProceedings{jayrah_16,
+  Title                    = {{E}nergy-{A}ware {M}emory {M}apping for {H}ybrid {FRAM}-{SRAM} {MCU}s in {IoT} {E}dge {D}evices},
+  Author                   = {H. Jayakumar and A. Raha and V. Raghunathan},
+  Booktitle                = {2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)},
+  Year                     = {2016},
+  Month                    = {Jan},
+  Pages                    = {264-269},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7434963},
+  Ccr_keywords             = {"QuickRecall 2"},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/VLSID.2016.52},
+  Keywords                 = {TCS},
+  Keywords_original        = {Internet of Things;SRAM chips;circuit optimisation;energy conservation;energy consumption;energy harvesting;ferroelectric storage;integrated circuit reliability;low-power electronics;microcontrollers;HW-SW technique;Internet of Things;IoT edge devices;MSP430FR5739 microcontroller;SRAM-based system;eM-map;energy consumption;energy efficiency;energy reduction;energy sources;energy-aware memory mapping technique;environmental energy harvesting;ferroelectric RAM;hybrid FRAM-SRAM MCUs;in-situ check pointing;nonvolatile memory;power loss;power supply;Checkpointing;Ferroelectric films;Nonvolatile memory;Performance evaluation;Power supplies;Random access memory;Reliability;Internet of things;Low power design;Non-volatile;energy harvesting;transiently powered system},
+  Owner                    = {CCR}
+}
+
+@InProceedings{jayrah_14,
+  Title                    = {{QUICKRECALL}: {A} {L}ow {O}verhead {HW}/{SW} {A}pproach for {E}nabling {C}omputations across {P}ower {C}ycles in {T}ransiently {P}owered {C}omputers},
+  Author                   = {H. Jayakumar and A. Raha and V. Raghunathan},
+  Booktitle                = {2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems},
+  Year                     = {2014},
+  Month                    = {Jan},
+  Pages                    = {330-335},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {6733152},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/VLSID.2014.63},
+  ISSN                     = {1063-9667},
+  Keywords                 = {TCS},
+  Keywords_original        = {checkpointing;computer power supplies;flash memories;FRAM;QUICKRECALL;flash memory;in-situ checkpointing technique;low overhead HW-SW;power cycles;transiently powered computers;Ash;Checkpointing;Ferroelectric films;Microcontrollers;Nonvolatile memory;Random access memory;Registers;Embedded Systems;Energy Harvesting;FRAM;Low power design;Non-volatile memory;Transiently Powered Computers},
+  Owner                    = {CCR}
+}
+
+@Article{jayrah_17,
+  Title                    = {{E}nergy-{A}ware {M}emory {M}apping for {H}ybrid {FRAM}-{SRAM} {MCU}s in {I}ntermittently-{P}owered {IoT} {D}evices},
+  Author                   = {Jayakumar, Hrishikesh and Raha, Arnab and Stevens, Jacob R. and Raghunathan, Vijay},
+  Journal                  = {ACM Trans. Embed. Comput. Syst.},
+  Year                     = {2017},
+
+  Month                    = apr,
+  Number                   = {3},
+  Pages                    = {65:1--65:23},
+  Volume                   = {16},
+
+  Acmid                    = {2983628},
+  Address                  = {New York, NY, USA},
+  Articleno                = {65},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Jayakumar:2017:EMM:3072970.2983628},
+  Ccr_keywords             = {journal version of QuickRecall 2},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/2983628},
+  ISSN                     = {1539-9087},
+  Issue_date               = {July 2017},
+  Keywords                 = {TCS},
+  Keywords_original        = {Intermittently powered systems, batteryless systems, checkpointing, energy harvesting, ferroelectric RAM, internet of things},
+  Numpages                 = {23},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/2983628}
+}
+
+@InProceedings{jayrod_15,
+  Title                    = {{T}he {P}otential and {P}erils of {M}ulti-{L}evel {M}emory},
+  Author                   = {Jayaraj, Jagan and Rodrigues, Arun F. and Hammond, Simon D. and Voskuilen, Gwendolyn R.},
+  Booktitle                = {Proceedings of the 2015 International Symposium on Memory Systems},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {191--196},
+  Publisher                = {ACM},
+  Series                   = {MEMSYS '15},
+
+  Acmid                    = {2818976},
+  Doi                      = {10.1145/2818950.2818976},
+  ISBN                     = {978-1-4503-3604-8},
+  Keywords                 = {Application Analysis, Multi-Level Memory, Simulation},
+  Location                 = {Washington DC, DC, USA},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-08},
+  Url                      = {http://doi.acm.org/10.1145/2818950.2818976}
+}
+
+@Misc{jayrod_15b,
+  Title                    = {{T}he {P}otential and {P}erils of {M}ulti-{L}evel {M}emory},
+
+  Author                   = {Jayaraj, Jagan and Rodrigues, Arun F. and Hammond, Simon D. and Voskuilen, Gwendolyn R.},
+  Year                     = {2015},
+
+  Booktitle                = {Presentation at the 2015 International Symposium on Memory Systems},
+  Timestamp                = {2016-12-08}
+}
+
+@Electronic{jed_nvdimm_p,
+  Title                    = {{JEDEC} {DDR}5 \& {NVDIMM}-{P} {S}tandards {U}nder {D}evelopment},
+  Author                   = {JEDEC},
+  Url                      = {https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-08-29}
+}
+
+@Article{jed_17,
+  Title                    = {{JESD}79-4{B}, {JEDEC} {S}tandard, {DDR}4 {SDRAM}},
+  Author                   = {JEDEC},
+  Year                     = {2017},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-26}
+}
+
+@Misc{jedhigh15,
+  Title                    = {{H}igh {B}andwidth {M}emory {DRAM} ({JESD}235{A})},
+
+  Author                   = {JEDEC},
+  Month                    = {November},
+  Year                     = {2015},
+
+  Owner                    = {DMM},
+  Timestamp                = {2016-08-15}
+}
+
+@Book{jefrei_13,
+  Title                    = {{I}ntel {X}eon {P}hi {C}oprocessor {H}igh-{P}erformance {P}rogramming},
+  Author                   = {Jim Jeffers and James Reinders},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2013},
+
+  Address                  = {Waltham, MA, USA},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.17}
+}
+
+@Misc{jegfpga09,
+  Title                    = {{FPGA} {P}rototypes for {T}urbo {C}ommunication {A}pplications},
+
+  Author                   = {Christophe Jego and Amer Baghdadi and Camille Leroux and Hazem Moussa and Olivier Muller and Atif Raza Jafri and Omar Al Assil and Patrick Adde and G�rald Le Mestre and Michel Jezequel},
+  HowPublished             = {DATE 2009 University Booth},
+  Month                    = apr,
+  Year                     = {2009},
+
+  File                     = {jegfpga09.pdf:jegfpga09.pdf:PDF},
+  Key                      = {3gpp},
+  Keywords                 = {Turbo},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Url                      = {http://www.date-conference.com/conference/date09-ubooth-session-1}
+}
+
+@Misc{Jego2009,
+  Title                    = {{FPGA} {P}rototypes for {T}urbo {C}ommunication {A}pplications},
+
+  Author                   = {Christophe Jego and Amer Baghdadi and Camille Leroux and Hazem Moussa and Olivier Muller and Atif Raza Jafri and Omar Al Assil and Patrick Adde and G�rald Le Mestre and Michel Jezequel},
+  HowPublished             = {DATE 2009 University Booth},
+  Month                    = apr,
+  Year                     = {2009},
+
+  File                     = {jegfpga09.pdf:jegfpga09.pdf:PDF},
+  Key                      = {3gpp},
+  Keywords                 = {Turbo},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Url                      = {http://www.date-conference.com/conference/date09-ubooth-session-1}
+}
+
+@InProceedings{jegbag_09,
+  Title                    = {{FPGA prototypes for turbo communication applications}},
+  Author                   = {Jego, Christophe and Baghdadi, Amer and Leroux, Camille and Muller, Olivier and Al Assil, Omar and Le Mestre, G{\'e}rald and Jezequel, Michel and Adde, Patrick and Jafri, Atif Raza and Moussa, Hazem},
+  Booktitle                = {University Booth of DATE 09 : Design, Automation \& Test in Europe Conference \& Exhibition},
+  Year                     = {2009}
+}
+
+@InProceedings{Jensen2008,
+  Title                    = {{N}on-{D}ata {A}ided {C}arrier {O}ffset {C}ompensation for {SDR} {I}mplementation},
+  Author                   = {Jensen, A.R. and Jorgensen, N.T.K. and Laugesen, K. and Le Moullec, Y.},
+  Booktitle                = {NORCHIP, 2008.},
+  Year                     = {2008},
+  Month                    = {Nov},
+  Pages                    = {158-161},
+
+  Doi                      = {10.1109/NORCHP.2008.4738302},
+  Keywords                 = {computational complexity;field programmable gate arrays;quadrature phase shift keying;synchronisation;FPGA-accelerated implementation;QPSK communication system;SDR;Simulink;computational complexity;frequency synchronization;modulation removal algorithm;nondata aided carrier offset compensation;Additive white noise;Algorithm design and analysis;Bandwidth;Baseband;Bit error rate;Frequency estimation;Frequency synchronization;Gaussian noise;Quadrature phase shift keying;Radio transmitters},
+  Owner                    = {ali},
+  Timestamp                = {2015.03.26}
+}
+
+@Article{jeooh_16,
+  Title                    = {{A}n e{DRAM}-{B}ased {A}pproximate {R}egister {F}ile for {GPU}s},
+  Author                   = {Jeong, D. and Oh, Y. H. and Lee, J. W. and Park, Y.},
+  Journal                  = {IEEE Design \& Test},
+  Year                     = {2016},
+
+  Month                    = {February},
+  Number                   = {1},
+  Pages                    = {23-31},
+  Volume                   = {33},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-05}
+}
+
+@InProceedings{jeohsi_99,
+  Title                    = {{Optimal Quantization for Soft-Decision Turbo Decoder}},
+  Author                   = {G. Jeong and D. Hsia},
+  Booktitle                = {Proc. 1999-Fall Vehicular Technology Conference (VTC '99 Fall)},
+  Year                     = {1999},
+
+  Address                  = {Amsterdam, The Netherlands},
+  Month                    = sep,
+  Pages                    = {1620--1624},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{jeodrsim,
+  Title                    = {{D}r{S}im: {A} {P}latform for {F}lexible {DRAM} {S}ystem {R}esearch},
+
+  Author                   = {Min Kyu Jeong and Doe Hyun Yoon and Mattan Erez},
+  HowPublished             = {http://lph.ece.utexas.edu/public/DrSim},
+  Year                     = {(Last Access: 15.08.2019)},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-08-15}
+}
+
+@InProceedings{jercon_12,
+  Title                    = {{T}owards a fixed point {QP} solver for predictive control},
+  Author                   = {J. L. Jerez and G. A. Constantinides and E. C. Kerrigan},
+  Booktitle                = {2012 IEEE 51st IEEE Conference on Decision and Control (CDC)},
+  Year                     = {2012},
+  Month                    = {Dec},
+  Pages                    = {675-680},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [6]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/CDC.2012.6427015},
+  ISSN                     = {0191-2216},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {aircraft control;fixed point arithmetic;iterative methods;predictive control;quadratic programming;fixed point {QP} solver;convex quadratic programming;model predictive control;{MPC};linear equations;fixed-point implementation;iterative linear solver;parallel hardware;fixed point arithmetic;Lanczos process;iterative linear solving algorithms;mixed precision interior-point controller;Boeing 747 aircraft;control quality;Symmetric matrices;Dynamic range;Mathematical model;Hardware;Optimization;Equations;Heuristic algorithms},
+  Owner                    = {CCR}
+}
+
+@InProceedings{jercon_11,
+  Title                    = {{A}n {FPGA} {I}mplementation of a {S}parse {Q}uadratic {P}rogramming {S}olver for {C}onstrained {P}redictive {C}ontrol},
+  Author                   = {Jerez, Juan Luis and Constantinides, George Anthony and Kerrigan, Eric C.},
+  Booktitle                = {Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
+  Year                     = {2011},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {209--218},
+  Publisher                = {ACM},
+  Series                   = {{FPGA} '11},
+
+  Acmid                    = {1950454},
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [5]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1145/1950413.1950454},
+  ISBN                     = {978-1-4503-0554-9},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {interior-point, model predictive control, optimization},
+  Location                 = {Monterey, CA, USA},
+  Numpages                 = {10},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/1950413.1950454}
+}
+
+@Article{jercon_11a,
+  Title                    = {{P}arallel {MPC} for {R}eal-{T}ime {FPGA}-based {I}mplementation},
+  Author                   = {Juan L. Jerez and George A. Constantinides and Eric C. Kerrigan and Keck-Voon Ling},
+  Journal                  = {IFAC Proceedings Volumes},
+  Year                     = {2011},
+  Note                     = {18th IFAC World Congress},
+  Number                   = {1},
+  Pages                    = {1338 - 1343},
+  Volume                   = {44},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [7]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {https://doi.org/10.3182/20110828-6-IT-1002.01392},
+  ISSN                     = {1474-6670},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {Parallel Algorithms, Parallel Computation, Pipelined Architectures VLSI, Optimization Problems, Optimal Control, Computer Architecture},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S147466701643795X}
+}
+
+@InProceedings{jergou_13,
+  Title                    = {{E}mbedded {P}redictive {C}ontrol on an {FPGA} using the {F}ast {G}radient {M}ethod},
+  Author                   = {J. L. Jerez and P. J. Goulart and S. Richter and G. A. Constantinides and E. C. Kerrigan and M. Morari},
+  Booktitle                = {2013 European Control Conference (ECC)},
+  Year                     = {2013},
+  Month                    = {July},
+  Pages                    = {3614-3620},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [8]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.23919/ECC.2013.6669598},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {control engineering computing;convex programming;embedded systems;field programmable gate arrays;gradient methods;linear quadratic control;predictive control;satisfactory control performance;AFM;industrial atomic force microscope;arithmetic errors;fixed-point arithmetic;linear-quadratic {MPC} problems;fast gradient solver;field programmable gate array;convex programs;resource-constrained embedded platforms;model predictive control;fast gradient method;{FPGA};embedded predictive control;Gradient methods;Hardware;Computer architecture;Vectors;Field programmable gate arrays;Convergence;Upper bound},
+  Owner                    = {CCR}
+}
+
+@Article{jerlin_12,
+  Title                    = {{M}odel predictive control for deeply pipelined field-programmable gate array implementation: algorithms and circuitry},
+  Author                   = {J. L. Jerez and K. -. Ling and G. A. Constantinides and E. C. Kerrigan},
+  Journal                  = {IET Control Theory Applications},
+  Year                     = {2012},
+
+  Month                    = {May},
+  Number                   = {8},
+  Pages                    = {1029-1041},
+  Volume                   = {6},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [9]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1049/iet-cta.2010.0441},
+  ISSN                     = {1751-8644},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {field programmable gate arrays;pipeline processing;predictive control;quadratic programming;model predictive control;deeply pipelined field-programmable gate array implementation;optimisation-based scheme;real-time constraint;quadratic programming problem;fast embedded systems;customised {QP} solver;optimal control;linear processes;general purpose microprocessor;primal-dual interior-point method;parallel computational channels;pipelined architecture;digital system design},
+  Owner                    = {CCR}
+}
+
+@Article{jersin_04,
+  Title                    = {{A} polynomial-time approximation algorithm for the permanent of a matrix with nonnegative entries},
+  Author                   = {Jerrum, Mark and Sinclair, Alistair and Vigoda, Eric},
+  Journal                  = {Journal of the ACM (JACM)},
+  Year                     = {2004},
+  Number                   = {4},
+  Pages                    = {671--697},
+  Volume                   = {51},
+
+  Owner                    = {Brugger},
+  Publisher                = {ACM},
+  Timestamp                = {2015.08.09}
+}
+
+@Article{jezpen_99,
+  Title                    = {{T}urbo4: a high bit-rate chip for turbo code encoding and decoding},
+  Author                   = {Jezequel, M and Penard, P},
+  Year                     = {1999},
+
+  Owner                    = {StW},
+  Publisher                = {IET},
+  Timestamp                = {2017.07.04}
+}
+
+@InProceedings{jiki_02,
+  Title                    = {{F}ast parallel {CRC} algorithm and implementation on a configurable processor},
+  Author                   = {Ji, H. Michael and Killian, Earl},
+  Booktitle                = {{C}ommunications, 2002. {ICC} 2002. {IEEE} {I}nternational {C}onference on},
+  Year                     = {2002},
+  Organization             = {IEEE},
+  Pages                    = {1813--1817},
+  Volume                   = {3},
+
+  Keywords                 = {CRC, SMAP, LTE},
+  Owner                    = {weithoffer}
+}
+
+@InProceedings{gen_par_turbo,
+  Title                    = {{T}he {G}enerator and {P}arity-{C}heck {M}atrices of {T}urbo {C}odes},
+  Author                   = {Jiang, F. and Psota, E. and Perez, L.C.},
+  Booktitle                = {Information Sciences and Systems, 2006 40th Annual Conference on},
+  Year                     = {2006},
+  Month                    = mar,
+  Pages                    = {1451-1454},
+
+  Owner                    = {punekar}
+}
+
+@InProceedings{jiahon_16,
+  Title                    = {{A} simulation analytics approach to dynamic risk monitoring},
+  Author                   = {Guangxin Jiang and L. Jeff Hong and Barry L. Nelson},
+  Booktitle                = {2016 Winter Simulation Conference (WSC)},
+  Year                     = {2016},
+  Month                    = {Dec.},
+  Pages                    = {437-447},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.08}
+}
+
+@PhdThesis{jia_07,
+  Title                    = {{A}dvanced {C}hannel {C}oding {T}echniques using {B}it-{L}evel {S}oft {I}nformation},
+  Author                   = {Jing Jiang},
+  School                   = {Texas A\&M University},
+  Year                     = {2007},
+  Month                    = {August},
+  Type                     = {Dissertation},
+
+  Keywords                 = {ABP, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {adaptive BP dissertation},
+  Timestamp                = {2013.02.11}
+}
+
+@Article{jianar_08,
+  Title                    = {{A}lgebraic {S}oft-{D}ecision {D}ecoding of {R}eed--{S}olomon {C}odes {U}sing {B}it-{L}evel {S}oft {I}nformation},
+  Author                   = {Jing Jiang and Narayanan, K. R. },
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2008},
+  Number                   = {9},
+  Pages                    = {3907--3928},
+  Volume                   = {54},
+
+  Doi                      = {10.1109/TIT.2008.928238},
+  File                     = {jianar_08.pdf:jianar_08.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ASD},
+  Owner                    = {Scholl},
+  Review                   = {bit level GMD},
+  Timestamp                = {2011.07.20}
+}
+
+@Article{jianar_06,
+  Title                    = {{I}terative {S}oft-{I}nput {S}oft-{O}utput {D}ecoding of {R}eed--{S}olomon {C}odes by {A}dapting the {P}arity-{C}heck {M}atrix},
+  Author                   = {Jing Jiang and Narayanan, K. R.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2006},
+  Number                   = {8},
+  Pages                    = {3746--3756},
+  Volume                   = {52},
+
+  Doi                      = {10.1109/TIT.2006.878176},
+  File                     = {jianar_06.pdf:jianar_06.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ABP},
+  Owner                    = {Scholl},
+  Review                   = {ausfuehrliches Paper zum ABP},
+  Timestamp                = {2011.06.21}
+}
+
+@Article{jianar_04,
+  Title                    = {{I}terative soft decoding of {R}eed-{S}olomon codes},
+  Author                   = {Jing Jiang and Narayanan, K. R.},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2004},
+  Number                   = {4},
+  Pages                    = {244--246},
+  Volume                   = {8},
+
+  Doi                      = {10.1109/LCOMM.2004.827977},
+  File                     = {jianar_04.pdf:jianar_04.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {BP für RS Codes mit zyklischem Verschieben des Codeworts},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{jianar_04a,
+  Title                    = {{I}terative soft decision decoding of {R}eed {S}olomon codes based on adaptive parity check matrices},
+  Author                   = {Jiang, J. and Narayanan, K. R.},
+  Booktitle                = {Proc. Int. Symp. Information Theory ISIT 2004},
+  Year                     = {2004},
+
+  Doi                      = {10.1109/ISIT.2004.1365295},
+  File                     = {jianar_04a.pdf:jianar_04a.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ABP},
+  Owner                    = {Scholl},
+  Review                   = {Urpaper adaptive belief propagation},
+  Timestamp                = {2011.06.21}
+}
+
+@InProceedings{jiatan_02,
+  Title                    = {{A trace-back free Viterbi decoder using a new survival path management algorithm}},
+  Author                   = {Y. Jiang and Y. Tang and Y. Wang and M. N. S. Swamy},
+  Booktitle                = {Proc. 2002 IEEE International Symposium on Circuits and Systems (ISCAS '02)},
+  Year                     = {2002},
+
+  Address                  = {Phoenix, Arizona, USA},
+  Month                    = may,
+  Pages                    = {261--264},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{jiatan_02a,
+  Title                    = {{A DSP-based Turbo Codec for 3G Communication System}},
+  Author                   = {Y. Jiang and Y. Tang and Y. Wang and D. Zhou},
+  Booktitle                = {Proc. 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing},
+  Year                     = {2002},
+
+  Address                  = {Orlando, Florida},
+  Month                    = may,
+  Pages                    = {2685--2688},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{jimsod_16,
+  Title                    = {{I}ntel {X}eon {P}hi {P}rocessor {H}igh {P}erformance {P}rogramming},
+  Author                   = {Jim Jeffers, James Reinders and Avinash Sodani},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2016},
+  Edition                  = {2nd - {Knights Landing}},
+  Month                    = {June},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.11.02}
+}
+
+@InProceedings{jinkha_00,
+  Title                    = {{Irregular Repeat-Accumulate Codes}},
+  Author                   = {H. Jin and A. Khandekar and R. McEliece},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {1--8},
+
+  File                     = {jinkha_00.pdf:jinkha_00.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{jintsu_07,
+  Title                    = {{Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition}},
+  Author                   = {J. Jin AND C. Tsui},
+  Journal                  = {IEEE Transactions on VLSI Systems},
+  Year                     = {2007},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {1172--1176},
+  Volume                   = {16},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2007.11.06}
+}
+
+@InProceedings{jinbec_12,
+  Title                    = {{O}ptimising explicit finite difference option pricing for dynamic constant reconfiguration},
+  Author                   = {Qiwei Jin and Becker, T. and Luk, W. and Thomas, D.},
+  Booktitle                = {Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on},
+  Year                     = {2012},
+  Month                    = {Aug},
+  Pages                    = {165-172},
+
+  Doi                      = {10.1109/FPL.2012.6339256},
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.02}
+}
+
+@InBook{jindon_12,
+  Title                    = {{R}econfigurable {C}omputing: {A}rchitectures, {T}ools and {A}pplications: 8th {I}nternational {S}ymposium, {A}rc 2012, {H}ongkong, {C}hina, {M}arch 19-23, 2012, {P}roceedings},
+  Author                   = {Jin, Q. and Dong, D. and Tse, A. and Chow, G. and Thomas, D. and Luk, W. and Weston, S.},
+  Chapter                  = {Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations},
+  Editor                   = {Choy, O. and Cheung, R. and Athanas, P. and Sano, K.},
+  Pages                    = {187--201},
+  Publisher                = {Springer-Verlag New York Incorporated},
+  Year                     = {2012},
+  Month                    = mar,
+  Volume                   = {7199},
+
+  Cds_grade                = {0},
+  File                     = {jindon_12.pdf:jindon_12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.08.29}
+}
+
+@InProceedings{jinluk_11,
+  Title                    = {{O}n {C}omparing {F}inancial {O}ption {P}rice {S}olvers on {FPGA}},
+  Author                   = {Qiwei Jin and Wayne Luk and David B. Thomas},
+  Booktitle                = {Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on},
+  Year                     = {2011},
+
+  Address                  = {Salt Lake City, Utah, USA},
+  Month                    = may,
+  Pages                    = {89--92},
+
+  Abstract                 = {A number of different numerical methods for accelerating financial option pricing using FPGAs have recently been investigated, such as Monte-Carlo, finite-difference, quadrature, and binomial trees. However, these papers only compare acceleration of each method against the same method in software, and do not consider a more important practical question, which is to identify the method that provides the best FPGA performance for a given option pricing application, regardless of raw speed-up over software. This paper proposes a framework for comparing the performance of numerical option pricing methods using FPGAs, taking into account both speed (time to solution) and accuracy (quality of solution), and examines how the speed-accuracy trade-off curve varies for each method. We apply the framework to European and American option pricing problems using Virtex-4 parts, and show that the quadrature solver converges fastest for both European and American options, and is also the most accurate in terms of root mean squared error for European options. However, when very accurate American results are needed the finite-difference solver is the most efficient method. Our results also show that the Monte-Carlo solver is at least 100 times less accurate in log scale than those based on other pricing methodologies, this drawback outweighs its benefit of having large raw speed-ups found in previous papers.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Benchmarking, Metrics, Option Pricing, Black-Scholes},
+  Cds_read                 = {2011-06-22
+2011-11-29},
+  Cds_review               = {proposes a framework for FPGA comparison of Black-Scholes implementations
+comprehensive overview about solver methods: binomial, trinomial, finite difference, quadrature, Monte Carlo
+metrics for different solver types are proposed
+
+future work similar to what we target: multi-asset options, barrier options, Asian options
+- no metrics for energy
+
+? how to compare to CPU / GPU with the proposed metrics},
+  Doi                      = {10.1109/FCCM.2011.30},
+  File                     = {jinluk_11.pdf:jinluk_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-04-22}
+}
+
+@InProceedings{jinluk_11a,
+  Title                    = {{U}nifying {F}inite {D}ifference {O}ption-{P}ricing for {H}ardware {A}cceleration},
+  Author                   = {Qiwei Jin and Wayne Luk and David B. Thomas},
+  Booktitle                = {Field Programmable Logic and Applications (FPL), 2011 International Conference on},
+  Year                     = {2011},
+  Month                    = sep,
+  Pages                    = {6--9},
+
+  Abstract                 = {Explicit finite difference method is widely used in finance for pricing many kinds of options. Its regular computational pattern makes it an ideal candidate for acceleration using reconfigurable hardware. However, because the corresponding hardware designs must be optimised both for the specific option and for the target platform, it is challenging and time consuming to develop designs efficiently and productively. This paper presents a unifying framework for describing and automatically implementing financial explicit finite difference procedures in reconfigurable hardware, allowing parallelised and pipelined implementations to be created from high-level mathematical expressions. The proposed framework is demonstrated using three option pricing problems. Our results show that an implementation from our framework targeting a Virtex-6 device at 310MHz is more than 24 times faster than a software implementation fully optimised by the Intel compiler on a four-core Xeron CPU at 2.66GHz. In addition, the latency of the FPGA solvers is up to 90 times lower than the corresponding software solvers.},
+  Cds_grade                = {0},
+  Cds_keywords             = {FPGA, option pricing, finite difference,},
+  Doi                      = {10.1109/FPL.2011.12},
+  File                     = {jinluk_11a.pdf:jinluk_11a.pdf:PDF},
+  Keywords                 = {finance, Review},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.09}
+}
+
+@InProceedings{jintho_09a,
+  Title                    = {{E}xploring {R}econfigurable {A}rchitectures for {E}xplicit {F}inite {D}ifference {O}ption {P}ricing {M}odels},
+  Author                   = {Qiwei Jin and Thomas, D.B. and Luk, W.},
+  Booktitle                = {Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on},
+  Year                     = {2009},
+  Month                    = sep,
+  Pages                    = {73--78},
+
+  Abstract                 = {This paper explores the application of reconfigurable hardware and graphics processing units (GPUs) to the acceleration of financial computation using the finite difference (FD) method. A parallel pipelined architecture has been developed to support concurrent valuation of independent options with high pricing throughput. Our FPGA implementation running at 106 MHz on an xc4vlx160 device demonstrates a speed up of 12 times over a Pentium 4 processor at 3.6 GHz in single-precision arithmetic; while the FPGA is 3.6 times slower than a Tesla C1060 240-Core GPU at 1.3 GHz, it is 9 times more energy efficient.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPL.2009.5272549},
+  File                     = {jintho_09a.pdf:jintho_09a.pdf:PDF},
+  ISSN                     = {1946-1488},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.09.10}
+}
+
+@Article{jintho_09,
+  Title                    = {{E}xploring {R}econfigurable {A}rchitectures for {T}ree-{B}ased {O}ption {P}ricing {M}odels},
+  Author                   = {Jin, Qiwei and Thomas, David B. and Luk, Wayne and Cope, Benjamin},
+  Journal                  = {ACM Trans. Reconfigurable Technol. Syst.},
+  Year                     = {2009},
+
+  Month                    = sep,
+  Number                   = {4},
+  Pages                    = {21:1--21:17},
+  Volume                   = {2},
+
+  Acmid                    = {1575781},
+  Address                  = {New York, NY, USA},
+  Articleno                = {21},
+  Cds_grade                = {0},
+  Doi                      = {10.1145/1575779.1575781},
+  File                     = {jintho_09.pdf:jintho_09.pdf:PDF},
+  ISSN                     = {1936-7406},
+  Issue_date               = {September 2009},
+  Keywords                 = {finance},
+  Numpages                 = {17},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2012.09.10}
+}
+
+@Article{jinyi_05,
+  Title                    = {{P}rediction of data retention time distribution of {DRAM} by physics-based statistical {S}imulation},
+  Author                   = {Seonghoon Jin and Jeong-Hyong Yi and Jae Hoon Choi and Dae Gwan Kang and Y. J. Park and Hong Shick Min},
+  Journal                  = {IEEE Transactions on Electron Devices},
+  Year                     = {2005},
+
+  Month                    = {Nov},
+  Number                   = {11},
+  Pages                    = {2422-2429},
+  Volume                   = {52},
+
+  Doi                      = {10.1109/TED.2005.857185},
+  ISSN                     = {0018-9383},
+  Keywords                 = {DRAM chips;Green's function methods;Monte Carlo methods;circuit simulation;integrated circuit modelling;leakage currents;statistical analysis;technology CAD (electronics);128 Mbit;DRAM cells;DRAM chips;Green function methods;Monte Carlo methods;Shockley-Read-Hall process;TCAD framework;cell transistor;coupled physics-based device simulation;cumulative distribution function;data retention time distribution;dynamic random access memory chip;gate-induced drain leakage;leakage currents;physics-based statistical simulation;statistical analysis;trap-assisted tunneling;DRAM chips;Distribution functions;Energy states;Green's function methods;Land surface temperature;Leakage current;Photonic band gap;Predictive models;Random access memory;Tunneling;Data retention time;Green's function methods;Monte Carlo methods;dynamic random access memory (DRAM);gate-induced drain leakage (GIDL);leakage currents;statistical analysis;stress (mechanical);trap-assisted tunneling (TAT)},
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-14}
+}
+
+@PhdThesis{Phdjoere95,
+  Title                    = {{VLSI-Implementierung des Soft-Output Viterbi-Algorithmus}},
+  Author                   = {O. Joeressen},
+  School                   = {RWTH Aachen},
+  Year                     = {1995},
+
+  Address                  = {VDI-Verlag, Düsseldorf, Germany},
+  Note                     = {In German},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{joe_94,
+  Title                    = {{Terminating the Trellis of Turbo-Codes}},
+  Author                   = {O. Joeressen},
+  Journal                  = {Electronics Letters},
+  Year                     = {1994},
+
+  Month                    = aug,
+  Number                   = {16},
+  Pages                    = {1285--1286},
+  Volume                   = {30},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{joevau_94,
+  Title                    = {{High-Speed VLSI Architectures for Soft-Output Viterbi Decoding}},
+  Author                   = {Joeressen, O. J. and M. Vaupel and H. Meyr},
+  Journal                  = {Journal of VLSI Signal Processing Systems},
+  Year                     = {1994},
+  Note                     = {Kluwer Academic Publishers, Boston},
+  Pages                    = {169--181},
+  Volume                   = {8},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{johzig_98,
+  Title                    = {{A} simple one-sweep algorithm for optimal {APP} symbol decoding of linear block codes},
+  Author                   = {Johansson, T. and Zigangirov, K.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1998},
+  Number                   = {7},
+  Pages                    = {3124--3129},
+  Volume                   = {44},
+
+  Doi                      = {10.1109/18.737541},
+  File                     = {johzig_98.pdf:johzig_98.pdf:PDF},
+  Keywords                 = {BCH, InfTheory},
+  Owner                    = {Scholl},
+  Review                   = {Map with only forward recursion for linear block codes},
+  Timestamp                = {2011.04.27}
+}
+
+@MastersThesis{BTjohn15,
+  Title                    = {{C}luster {I}mplementation for the {L}ink {A}ssessment {P}roblem: {F}inding a {H}euristic to {E}stimate the {N}umber of {S}waps},
+  Author                   = {Alexandre Flores John},
+  School                   = {Universidade Federal Do Rio Grande Do Sul, Supervisor: R. Galante, C. Brugger},
+  Year                     = {2015},
+  Month                    = Mar,
+  Type                     = {Bachelor Thesis},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.23}
+}
+
+@Misc{johagile11,
+  Title                    = {{A}gile hardware development – nonsense or necessity?},
+
+  Author                   = {Neil Johnson},
+  HowPublished             = {EE Times, \url{http://www.eetimes.com/document.asp?doc_id=1279137}},
+  Month                    = oct,
+  Note                     = {last access 2015-06-26},
+  Year                     = {2011},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.26}
+}
+
+@Misc{johwhy09,
+  Title                    = {{W}hy {A}gile {I}s {A} {G}ood {F}it {F}or {ASIC} and {FPGA} {D}evelopment},
+
+  Author                   = {Neil Johnson and Bryan Morris},
+  HowPublished             = {AgileSoC, \url{http://www.agilesoc.com/articles/why-agile-is-a-good-fit-for-asic-and-fpga-development/}},
+  Note                     = {last access 2015-06-26},
+  Year                     = {2009},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.26}
+}
+
+@InProceedings{jokmag_17,
+  Title                    = {{P}owering smart wearable systems with flexible solar energy harvesting},
+  Author                   = {P. Jokic and M. Magno},
+  Booktitle                = {2017 IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2017},
+  Month                    = {May},
+  Pages                    = {1-4},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8050615},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/ISCAS.2017.8050615},
+  Keywords                 = {TCS},
+  Keywords_original        = {Bluetooth;biomedical electronics;biomedical measurement;energy harvesting;flexible electronics;geriatrics;health care;low-power electronics;patient monitoring;polymer films;solar cell arrays;thin film devices;wearable computers;Bluetooth;blood oxygenation measurement;elderly people monitoring;energy conversion efficiency maximization;energy source;flexible devices;flexible plastic substrates;flexible solar energy harvesting;healthcare;long term patient monitoring;low power design;polyamide film;self-sustainable wireless wearable system;smart wearable systems;thin-film small form factor flexible photovoltaic panels;wearable smart bracelet design;Batteries;Biomedical monitoring;Energy harvesting;Monitoring;Photovoltaic cells;Solar energy;Solar panels;Ultra-low power device;e-health;energy harvesting;flexible electronics;long term monitoring;wearable devices},
+  Owner                    = {CCR}
+}
+
+@InProceedings{jonval_04,
+  Title                    = {{Approximate-Min Constraint Node Updating for LDPC Code Decoding}},
+  Author                   = {C. Jones and E. Valles and Michael Smith and John Villasenor},
+  Booktitle                = {Proc. 2004 IEEE Military Communications Conference (MILCOM)},
+  Year                     = {2004},
+
+  Address                  = {Boston, Massachusetts},
+  Month                    = oct,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{jonspr_11,
+  Title                    = {auto{VHDL}: a domain-specific modeling language for the auto-generation of {VHDL} core wrappers},
+  Author                   = {Jones, Erica and Sprinkle, Jonathan},
+  Booktitle                = {Proceedings of the compilation of the co-located workshops on DSM'11, TMC'11, AGERE!'11, AOOPES'11, NEAT'11, \& VMIL'11},
+  Year                     = {2011},
+  Organization             = {ACM},
+  Pages                    = {71--76},
+
+  Cds_grade                = {0},
+  File                     = {jonspr_11.pdf:jonspr_11.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@InProceedings{jonsim_14,
+  Title                    = {{FPGA}-accelerated {M}onte-{C}arlo {I}ntegration using {S}tratified {S}ampling and {B}rownian {B}ridges},
+  Author                   = {Mark de Jong and Vlad-Mihai Sima and Koen Bertels and David Thomas},
+  Booktitle                = {Proceedings of the 2014 International Conference on Field Programmable Technologies (FPT 2014)},
+  Year                     = {2014},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.03.25}
+}
+
+@InProceedings{jornic_96,
+  Title                    = {{The Effects of Channel Characteristics on Turbo Code Performance}},
+  Author                   = {M. Jordan and R. Nichols},
+  Booktitle                = {Proc. 1996 Military Communications Conference (Milcom '96)},
+  Year                     = {1996},
+
+  Address                  = {McLean, Virginia, USA},
+  Month                    = oct,
+  Pages                    = {17--21},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{jourog_97,
+  Title                    = {{F}ast, accurate and inelegant valuation of {A}merican options},
+  Author                   = {Adriaan Joubert and {L.C.G. Rogers}},
+  Booktitle                = {Proceedings of the Numerical Methods Workshop at the Isaac Newton Institute, April 1995},
+  Year                     = {1997},
+  Editor                   = {{L.C.G. Rogers} and D. Talay},
+  Pages                    = {88-92},
+  Publisher                = {Cambridge University Press},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.01.30},
+  Url                      = {http://www.statslab.cam.ac.uk/~chris/papers/aj2.pdf}
+}
+
+@InProceedings{jouyou_17b,
+  Title                    = {{I}n-{D}atacenter {P}erformance {A}nalysis of a {T}ensor {P}rocessing {U}nit},
+  Author                   = {Jouppi, Norman P. and Young, Cliff and Patil, Nishant and others},
+  Booktitle                = {Proceedings of the 44th Annual International Symposium on Computer Architecture},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {1--12},
+  Publisher                = {ACM},
+  Series                   = {ISCA '17},
+
+  Acmid                    = {3080246},
+  Doi                      = {10.1145/3079856.3080246},
+  ISBN                     = {978-1-4503-4892-8},
+  Keywords                 = {CNN, DNN, GPU, LSTM, MLP, RNN, TPU, TensorFlow, accelerator, deep learning, domain-specific architecture, neural network},
+  Location                 = {Toronto, ON, Canada},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-17},
+  Url                      = {http://doi.acm.org/10.1145/3079856.3080246}
+}
+
+@InProceedings{jouyou_17,
+  Title                    = {{I}n-{D}atacenter {P}erformance {A}nalysis of a {T}ensor {P}rocessing {U}nit},
+  Author                   = {Jouppi, Norman P. and Young, Cliff and Patil, Nishant and Patterson, David and Agrawal, Gaurav and Bajwa, Raminder and Bates, Sarah and Bhatia, Suresh and Boden, Nan and Borchers, Al and Boyle, Rick and Cantin, Pierre-luc and Chao, Clifford and Clark, Chris and Coriell, Jeremy and Daley, Mike and Dau, Matt and Dean, Jeffrey and Gelb, Ben and Ghaemmaghami, Tara Vazir and Gottipati, Rajendra and Gulland, William and Hagmann, Robert and Ho, C. Richard and Hogberg, Doug and Hu, John and Hundt, Robert and Hurt, Dan and Ibarz, Julian and Jaffey, Aaron and Jaworski, Alek and Kaplan, Alexander and Khaitan, Harshit and Killebrew, Daniel and Koch, Andy and Kumar, Naveen and Lacy, Steve and Laudon, James and Law, James and Le, Diemthu and Leary, Chris and Liu, Zhuyuan and Lucke, Kyle and Lundin, Alan and MacKean, Gordon and Maggiore, Adriana and Mahony, Maire and Miller, Kieran and Nagarajan, Rahul and Narayanaswami, Ravi and Ni, Ray and Nix, Kathy and Norrie, Thomas and Omernick, Mark and Penukonda, Narayana and Phelps, Andy and Ross, Jonathan and Ross, Matt and Salek, Amir and Samadiani, Emad and Severn, Chris and Sizikov, Gregory and Snelham, Matthew and Souter, Jed and Steinberg, Dan and Swing, Andy and Tan, Mercedes and Thorson, Gregory and Tian, Bo and Toma, Horia and Tuttle, Erick and Vasudevan, Vijay and Walter, Richard and Wang, Walter and Wilcox, Eric and Yoon, Doe Hyun},
+  Booktitle                = {Proceedings of the 44th Annual International Symposium on Computer Architecture},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {1--12},
+  Publisher                = {ACM},
+  Series                   = {ISCA '17},
+
+  Acmid                    = {3080246},
+  Doi                      = {10.1145/3079856.3080246},
+  ISBN                     = {978-1-4503-4892-8},
+  Keywords                 = {CNN, DNN, GPU, LSTM, MLP, RNN, TPU, TensorFlow, accelerator, deep learning, domain-specific architecture, neural network},
+  Location                 = {Toronto, ON, Canada},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-17},
+  Url                      = {http://doi.acm.org/10.1145/3079856.3080246}
+}
+
+@Article{joz_95,
+  Title                    = {{M}odern concepts of quality and their relationship to design reuse and model libraries},
+  Author                   = {Jozwiak, Lech},
+  Journal                  = {Hardware component modeling/Ed. J.-M. Berge, O. Levia, J. Rouillard},
+  Year                     = {1995},
+  Pages                    = {107},
+  Volume                   = {5},
+
+  Owner                    = {Brugger},
+  Publisher                = {Kluwer Academic Publishers},
+  Timestamp                = {2015.04.29}
+}
+
+@Article{joz_01,
+  Title                    = {{Q}uality-driven design in the system-on-a-chip era: {W}hy and how?},
+  Author                   = {Lech Jóźwiak},
+  Journal                  = {Journal of Systems Architecture},
+  Year                     = {2001},
+  Note                     = {Modern methods and tools in digital system design },
+  Number                   = {34},
+  Pages                    = {201 - 224},
+  Volume                   = {47},
+
+  Doi                      = {http://dx.doi.org/10.1016/S1383-7621(00)00046-1},
+  ISSN                     = {1383-7621},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.29},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S1383762100000461}
+}
+
+@InProceedings{jozjan_10,
+  Title                    = {{Q}uality-driven methodology for demanding accelerator design},
+  Author                   = {Jozwiak, L. and Jan, Y.},
+  Booktitle                = {Quality Electronic Design (ISQED), 2010 11th International Symposium on},
+  Year                     = {2010},
+  Month                    = {March},
+  Pages                    = {380-389},
+
+  Doi                      = {10.1109/ISQED.2010.5450546},
+  ISSN                     = {1948-3287},
+  Keywords                 = {decoding;nanoelectronics;nanotechnology;parity check codes;LDPC code decoders;communication system standards;demanding accelerator design;hardware accelerators;nanoelectronic technology;quality-driven methodology;Code standards;Communication standards;Computer architecture;Concurrent computing;Decoding;Design methodology;Hardware;Parallel processing;Parity check codes;Power system reliability;architecture design;combined macro- and micro-architecture design;design-space exploration;hardware accelerators},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.29}
+}
+
+@Article{jozned_10,
+  Title                    = {{M}odern development methods and tools for embedded reconfigurable systems: {A} survey },
+  Author                   = {Lech Jóźwiak and Nadia Nedjah and Miguel Figueroa},
+  Journal                  = {Integration, the \{VLSI\} Journal },
+  Year                     = {2010},
+  Number                   = {1},
+  Pages                    = {1 - 33},
+  Volume                   = {43},
+
+  Doi                      = {http://dx.doi.org/10.1016/j.vlsi.2009.06.002},
+  ISSN                     = {0167-9260},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.29},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0167926009000285}
+}
+
+@InProceedings{jozong_96,
+  Title                    = {{Q}uality-driven decision making methodology for system-level design},
+  Author                   = {Jozwiak, L. and Ong, S.A.},
+  Booktitle                = {EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference},
+  Year                     = {1996},
+  Month                    = {Sep},
+  Pages                    = {8-18},
+
+  Doi                      = {10.1109/EURMIC.1996.546360},
+  ISSN                     = {1089-6503},
+  Keywords                 = {real-time systems;systems analysis;application oriented embedded systems;decision making methodology;decision models;design space exploration;quality-driven decision making;system-level design;Decision making;Design methodology;Digital systems;Embedded system;Explosions;Information processing;Power generation economics;Psychology;Space exploration;System-level design},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.29}
+}
+
+@Other{JPMorganChase2017,
+  Title                    = {2016 {A}nnual {R}eport},
+  Author                   = {{JPMorgan Chase \& Co.}},
+  Note                     = {\url{https://www.jpmorganchase.com/corporate/investor-relations/document/2016-annualreport.pdf}. Last access: 05 Nov 2017},
+  Url                      = {https://www.jpmorganchase.com/corporate/investor-relations/document/2016-annualreport.pdf},
+  Year                     = {2017}
+}
+
+@InProceedings{jrban_02,
+  Title                    = {{A comparison of low complexity turbo-like codes}},
+  Author                   = {D. J. Costello Jr and A. Banerjee and C. He and P. C. Massey},
+  Booktitle                = {Proc. of the 36th Asilomar Conference on Signals, Systems, and ComputersProc},
+  Year                     = {2002},
+
+  Address                  = {San Diego, USA},
+  Month                    = nov,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{jun_17,
+  Title                    = {{S}ystem-{L}evel {M}odeling, {A}nalysis and {O}ptimization of {DRAM} {M}emories and {C}ontroller {A}rchitectures},
+  Author                   = {Jung, Matthias},
+  Publisher                = {University of Kaiserslautern},
+  Year                     = {2017},
+
+  ISBN                     = {978-3-95974-051-7},
+  Owner                    = {MJ},
+  School                   = {University of Kaiserslautern},
+  Timestamp                = {2017-06-30}
+}
+
+@PhdThesis{Phdjung17,
+  Title                    = {{S}ystem-{L}evel {M}odeling, {A}nalysis and {O}ptimization of {DRAM} {M}emories and {C}ontroller {A}rchitectures},
+  Author                   = {Jung, Matthias},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2017},
+
+  ISBN                     = {978-3-95974-051-7},
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-08}
+}
+
+@Misc{junicewrapper15,
+  Title                    = {{I}ce{W}rapper - {A} {S}ystem{C} {W}rapper for 3{D}-{ICE}},
+
+  Author                   = {Matthias Jung},
+  HowPublished             = {\url{http://www.uni-kl.de/3d-dram/tools/icewrapper/}},
+  Month                    = {October},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.10.29}
+}
+
+@InProceedings{junbre_12,
+  Title                    = {{A} {S}calable {M}ulti-{C}ore {ASIP} {V}irtual {P}latform {F}or {S}tandard-{C}ompliant {T}rellis {D}ecoding},
+  Author                   = {Jung, Matthias and Brehm, Christian and Wehn, Norbert},
+  Booktitle                = {Synopsys User Group Conference (SNUG)},
+  Year                     = {2012},
+
+  Address                  = {Munich, Germany},
+  Month                    = {May},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {schlaefer},
+  Timestamp                = {2017-07-05}
+}
+
+@InProceedings{junfel_20,
+  Title                    = {{F}ast and {A}ccurate {DRAM} {S}imulation: {C}an we {F}urther {A}ccelerate it?},
+  Author                   = {Jung, Matthias and Feldmann, Johannes and Kraft, Kira and Steiner, Lukas and Wehn, Norbert},
+  Booktitle                = {2020 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2020},
+  Pages                    = {364-369},
+
+  Owner                    = {jung},
+  Timestamp                = {2020-09-19}
+}
+
+@InProceedings{junhei_16,
+  Title                    = {{C}on{G}en: {A}n {A}pplication {S}pecific {DRAM} {M}emory {C}ontroller {G}enerator},
+  Author                   = {Jung, Matthias and Heinrich, Irene and Natale, Marco and Mathew, Deepak M. and Weis, Christian and Krumke, Sven and Wehn, Norbert},
+  Booktitle                = {Proceedings of the Second International Symposium on Memory Systems},
+  Year                     = {2016},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {257--267},
+  Publisher                = {ACM},
+  Series                   = {MEMSYS '16},
+
+  Acmid                    = {2989131},
+  Doi                      = {10.1145/2989081.2989131},
+  ISBN                     = {978-1-4503-4305-3},
+  Keywords                 = {Address Mapping, Application Specific Memory Controller, Combinatorics, DRAM, Graph Theory, Optimization},
+  Location                 = {Alexandria, VA, USA},
+  Numpages                 = {11},
+  Owner                    = {MJ},
+  Timestamp                = {2016-07-07},
+  Url                      = {http://doi.acm.org/10.1145/2989081.2989131}
+}
+
+@Article{junhuo_20,
+  Title                    = {{M}oderne {S}peicherarchitekturen f{\"u}r leistungsf{\"a}hige {I}nfotainmentsysteme und autonomes {F}ahren},
+  Author                   = {Jung, Matthias
+and Huonker, Michael
+and Kalmar, Ralf
+and Wehn, Norbert},
+  Journal                  = {ATZelektronik},
+  Year                     = {2020},
+
+  Month                    = {Nov},
+  Number                   = {11},
+  Pages                    = {16-21},
+  Volume                   = {15},
+
+  Day                      = {01},
+  Doi                      = {10.1007/s35658-020-0269-0},
+  ISSN                     = {2192-8878},
+  Owner                    = {MJ},
+  Timestamp                = {2020-11-06},
+  Url                      = {https://doi.org/10.1007/s35658-020-0269-0}
+}
+
+@InProceedings{junkra_19,
+  Title                    = {{F}ast {V}alidation of {DRAM} {P}rotocols with {T}imed {P}etri {N}ets},
+  Author                   = {Jung, Matthias and Kraft, Kira and Soliman, Taha and Sudarshan, Chirag and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {Proceedings of the International Symposium on Memory Systems},
+  Year                     = {2019},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {133--147},
+  Publisher                = {ACM},
+  Series                   = {MEMSYS '19},
+
+  Acmid                    = {3357556},
+  Doi                      = {10.1145/3357526.3357556},
+  ISBN                     = {978-1-4503-7206-0},
+  Keywords                 = {DRAM, memory controller, petri net, validation},
+  Location                 = {Washington, District of Columbia},
+  Numpages                 = {15},
+  Owner                    = {MJ},
+  Timestamp                = {2019-11-14},
+  Url                      = {http://doi.acm.org/10.1145/3357526.3357556}
+}
+
+@Conference{junkra_17,
+  Title                    = {{A} {N}ew {S}tate {M}odel for {DRAM}s {U}sing {P}etri {N}ets},
+  Author                   = {Jung, Matthias and Kraft, Kira and Wehn, Norbert},
+  Booktitle                = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
+  Year                     = {2017},
+  Month                    = {July},
+  Pages                    = {221-226},
+
+  Doi                      = {10.1109/SAMOS.2017.8344631},
+  Keywords                 = {Computer architecture;Concurrent computing;Inhibitors;Parallel processing;Petri nets;Random access memory;Standards},
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-29}
+}
+
+@Article{junmat_17,
+  Title                    = {{A} {P}latform to {A}nalyze {DDR}3 {DRAM}’s {P}ower and {R}etention {T}ime},
+  Author                   = {Jung, Matthias and Mathew, Deepak and Rheinländer, Carl and Weis, Christian and Wehn, Norbert},
+  Journal                  = {IEEE Design \& Test},
+  Year                     = {2017},
+
+  Month                    = {Aug},
+  Number                   = {4},
+  Pages                    = {52-59},
+  Volume                   = {34},
+
+  Doi                      = {10.1109/MDAT.2017.2705144},
+  ISSN                     = {2168-2356},
+  Keywords                 = {DRAM chips;integrated circuit reliability;logic design;power consumption;DDR3;DRAM;power consumption;reliability;Current measurement;Heating systems;Power demand;Random access memory;Temperature measurement;Temperature sensors;Time measurement;Approximate DRAM;Currents;DDR3;DDR4;DRAM;Measurement Platform;Power;Retention Time},
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17}
+}
+
+@InProceedings{junmat_16a,
+  Title                    = {{A}pproximate {C}omputing with {P}artially {U}nreliable {D}ynamic {R}andom {A}ccess {M}emory - {A}pproximate {DRAM}},
+  Author                   = {Jung, Matthias and Mathew, Deepak and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {Proceedings of the 53rd Annual Design Automation Conference},
+  Year                     = {2016},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {100:1--100:4},
+  Publisher                = {ACM},
+  Series                   = {DAC '16},
+
+  Acmid                    = {2905002},
+  Articleno                = {100},
+  Doi                      = {10.1145/2897937.2905002},
+  ISBN                     = {978-1-4503-4236-0},
+  Keywords                 = {approximate computing, approxmiate DRAM, refresh, retention time},
+  Location                 = {Austin, Texas},
+  Numpages                 = {4},
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-03}
+}
+
+@InProceedings{junmat_16,
+  Title                    = {{E}fficient {R}eliability {M}anagement in {S}o{C}s - {A}n {A}pproximate {DRAM} {P}erspective},
+  Author                   = {Jung, Matthias and Mathew, Deepak M. and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {21st Asia and South Pacific Design Automation Conference (ASP-DAC)},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.11.11}
+}
+
+@InProceedings{junmat_16b,
+  Title                    = {{A} {N}ew {B}ank {S}ensitive {DRAMP}ower {M}odel for {E}fficient {D}esign {S}pace {E}xploration},
+  Author                   = {Jung, Matthias and Mathew, Deepak M. and Zulian, \'Eder F. and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016)},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-15}
+}
+
+@InProceedings{junmck_18,
+  Title                    = {{D}riving into the {M}emory {W}all: {T}he {R}ole of {M}emory for {A}dvanced {D}river {A}ssistance {S}ystems and {A}utonomous {D}riving},
+  Author                   = {Jung, Matthias and McKee, Sally A. and Sudarshan, Chirag and Dropmann, Christoph and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {Proceedings of the International Symposium on Memory Systems},
+  Year                     = {2018},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {377--386},
+  Publisher                = {ACM},
+  Series                   = {MEMSYS '18},
+
+  Acmid                    = {3240322},
+  Doi                      = {10.1145/3240302.3240322},
+  ISBN                     = {978-1-4503-6475-1},
+  Keywords                 = {ADAS, DRAM, autonomous driving},
+  Location                 = {Alexandria, Virginia},
+  Numpages                 = {10},
+  Owner                    = {MJ},
+  Timestamp                = {2018-06-05}
+}
+
+@Article{junpia_15,
+  Title                    = {{V}irtual {D}evelopment on {M}ixed {A}bstraction {L}evels: an {A}gricultural {V}ehicle {C}ase {S}tudy},
+  Author                   = {Jung, Matthias and Piao, Songlin and Purusothaman, Thiyagarajan and Pan, Xiao and Kuhn, Thomas and Grimm, Christoph and Berns, Karsten and Wehn, Norbert},
+  Journal                  = {Synopsys Usergroup Conference (SNUG)},
+  Year                     = {2015},
+
+  Month                    = {June},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.08.11}
+}
+
+@InProceedings{junrhe_16,
+  Title                    = {{R}everse {E}ngineering of {DRAM}s: {R}ow {H}ammer with {C}rosshair},
+  Author                   = {Jung, Matthias and Rheinl{\"a}nder, Carl and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {International Symposium on Memory Systems (MEMSYS 2016)},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-07-07}
+}
+
+@InCollection{junsad_14,
+  Title                    = {{T}hermal {M}odelling of 3{D} {S}tacked {DRAM} with {V}irtual {P}latforms},
+  Author                   = {Jung, Matthias and Sadri, MohammadSadegh and Wehn, Norbert},
+  Booktitle                = {Tenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES14)},
+  Publisher                = {Academia Press, Ghent, Belgium},
+  Year                     = {2014},
+  Volume                   = {10},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.08.11}
+}
+
+@InCollection{junsad_13,
+  Title                    = {{V}irtual {P}latforms for {F}ast {M}emory {S}ubsystem {E}xploration {U}sing gem5 and {TLM}2.0},
+  Author                   = {Jung, Matthias and Sadri, MohammadSadegh and Wehn, Norbert},
+  Booktitle                = {Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES13)},
+  Publisher                = {Academia Press, Ghent, Belgium},
+  Year                     = {2013},
+  Pages                    = {153--156},
+  Volume                   = {9},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.08.11}
+}
+
+@InProceedings{junsch_19,
+  Title                    = {{S}peculative {T}emporal {D}ecoupling {U}sing \texttt{fork()}},
+  Author                   = {Jung, Matthias and Schnicke, Frank and Damm, Markus and Kuhn, Thomas and Wehn, Norbert},
+  Booktitle                = {IEEE Conference on Design, Automation and Test in Europe (DATE)},
+  Year                     = {2019},
+  Month                    = {March},
+  Pages                    = {1721-1726},
+
+  Doi                      = {10.23919/DATE.2019.8714823},
+  ISSN                     = {1558-1101},
+  Keywords                 = {Synchronization;Checkpointing;Kernel;Analytical models;Prototypes;Hardware;Temporal Decoupling;Fork;SystemC;Time Quantum;Virtual Prototyping},
+  Owner                    = {MJ},
+  Timestamp                = {2019-05-21}
+}
+
+@Conference{junweh_18,
+  Title                    = {{D}riving {A}gainst the {M}emory {W}all: {T}he {R}ole of {M}emory for {A}utonomous {D}riving},
+  Author                   = {Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {Workshop on New Platforms for Future Cars: Current and Emerging Trends at IEEE Conference Design, Automation and Test in Europe (DATE)},
+  Year                     = {2018},
+  Month                    = {March},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-02-11}
+}
+
+@InProceedings{junweh_15,
+  Title                    = {{C}oupling gem5 with {S}ystem{C} {TLM} 2.0 {V}irtual {P}latforms},
+  Author                   = {Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {gem5 User Workshop, International Symposium on Computer Architecture (ISCA)},
+  Year                     = {2015},
+
+  Address                  = {Portland, OR, USA.},
+  Month                    = {June},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.08.11}
+}
+
+@InProceedings{junwei_13a,
+  Title                    = {{P}ower {M}odelling of 3{D}-{S}tacked {M}emories with {TLM}2.0 based {V}irtual {P}latforms},
+  Author                   = {Jung, Matthias and Weis, Christian and Bertram, Patrick and Wehn, Norbert},
+  Booktitle                = {Synopsys User Group Conference (SNUG), May, 2013, Munich, Germany.},
+  Year                     = {2013}
+}
+
+@Book{junwei_21,
+  Title                    = {{T}he {D}ynamic {R}andom {A}ccess {M}emory {C}hallenge in {E}mbedded {C}omputing {S}ystems ({B}ook {C}hapter in: {A} {J}ourney of {E}mbedded and {C}yber-{P}hysical {S}ystems: {E}ssays {D}edicated to {P}eter {M}arwedel on the {O}ccasion of {H}is 70th {B}irthday)},
+  Author                   = {Jung, Matthias
+and Weis, Christian
+and Wehn, Norbert},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2021},
+
+  Doi                      = {10.1007/978-3-030-47487-4_3},
+  ISBN                     = {978-3-030-47487-4},
+  Timestamp                = {2020-10-31},
+  Url                      = {https://doi.org/10.1007/978-3-030-47487-4_3}
+}
+
+@Article{junwei_15a,
+  Title                    = {{A} cross layer approach for efficient thermal management in 3{D} stacked {S}o{C}s },
+  Author                   = {Matthias Jung and Christian Weis and Norbert Wehn},
+  Journal                  = {Microelectronics Reliability},
+  Year                     = {2016},
+  Note                     = {ICMAT 2015 Symposium},
+  Pages                    = {43 - 47},
+  Volume                   = {61},
+
+  Abstract                 = {Abstract 3D stacking of silicon dies via Through Silicon Vias (TSVs) is an emerging technology to increase performance, energy efficiency and integration density of today's and future System-on-Chips (SoCs). Especially the stacking of Wide I/O \{DRAMs\} on top of a logic die is a very promising approach to tackle the memory wall and energy efficiency challenge. The potential of this type of stacking is currently under investigation by many research groups and companies in particular for mobile devices. There, for instance, the baseband processing and the application processor can be implemented on the same single logic die. On top of this die one or several Wide I/O \{DRAMs\} are stacked. An example of such a SoC is the \{WIOMING\} chip [15]. However, new challenges emerge, especially thermal management, which is already a very demanding challenge in current 2D SoCs. With 3D SoCs this problem exacerbates due to reliability issues such as the temperature sensitivity of DRAMs, i.e., the retention time of a \{DRAM\} cell largely decreases with increasing temperature. In this paper, we show a holistic cross layer reliability approach for efficient reliability management starting from measuring and modeling of \{DRAM\} retention errors, which finally leads to optimizations for specific applications. These optimizations exploit the data lifetime and the inherent error resilience of the application, which is for instance given in the probabilistic behavior of wireless communications.},
+  Doi                      = {10.1016/j.microrel.2015.12.025},
+  ISSN                     = {0026-2714},
+  Keywords                 = {DRAM},
+  Owner                    = {MJ},
+  Timestamp                = {2016-10-20}
+}
+
+@Article{junwei_15,
+  Title                    = {{DRAMS}ys: {A} flexible {DRAM} {S}ubsystem {D}esign {S}pace {E}xploration {F}ramework},
+  Author                   = {Jung, Matthias and Weis, Christian and Wehn, Norbert},
+  Journal                  = {IPSJ Transactions on System LSI Design Methodology (T-SLDM)},
+  Year                     = {2015},
+
+  Month                    = {August},
+
+  Doi                      = {10.2197/ipsjtsldm.8.63},
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-02}
+}
+
+@InProceedings{junwei_13,
+  Title                    = {{TLM} modelling of 3{D} stacked wide {I}/{O} {DRAM} subsystems: a virtual platform for memory controller design space exploration},
+  Author                   = {Jung, Matthias and Weis, Christian and Wehn, Norbert and Chandrasekar, Karthik},
+  Booktitle                = {Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
+  Year                     = {2013},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {5:1--5:6},
+  Publisher                = {ACM},
+  Series                   = {RAPIDO '13},
+
+  Acmid                    = {2432521},
+  Articleno                = {5},
+  Doi                      = {10.1145/2432516.2432521},
+  File                     = {junwei_13.pdf:junwei_13.pdf:PDF},
+  ISBN                     = {978-1-4503-1539-5},
+  Keywords                 = {AGWehn},
+  Location                 = {Berlin, Germany},
+  Numpages                 = {6},
+  Url                      = {http://doi.acm.org/10.1145/2432516.2432521}
+}
+
+@InProceedings{junwei_14,
+  Title                    = {{O}ptimized active and power-down mode refresh control in 3{D}-{DRAM}s},
+  Author                   = {Jung, Matthias and Weis, Christian and Wehn, Norbert and Sadri, MohammadSadegh and Benini, Luca},
+  Booktitle                = {Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on},
+  Year                     = {2014},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/VLSI-SoC.2014.7004159},
+  Keywords                 = {DRAM chips;integrated circuit design;integrated circuit modelling;three-dimensional integrated circuits;3D integration;3D stacked systems;3D structure;3D-DRAMs;DRAM cells;DRAM controller model;DRAM refresh power;SystemC TLM-2.0;bank-wise refresh;energy reduction;future density optimized mobile computing platforms;lateral temperature variations;optimized active mode refresh control;per DRAM array hotspot detector;power density;power estimation;power-down mode policy;power-down mode refresh control;temperature variation aware bank-wise refresh;thermal dissipation;transaction level modeling;vertical temperature variations;virtual hardware platform;Arrays;Benchmark testing;Detectors;Energy consumption;Random access memory;Temperature sensors;Three-dimensional displays},
+  Owner                    = {MJ},
+  Timestamp                = {2017-07-05}
+}
+
+@InProceedings{junzul_15,
+  Title                    = {{O}mitting {R}efresh - {A} {C}ase {S}tudy for {C}ommodity and {W}ide {I}/{O} {DRAM}s},
+  Author                   = {Jung, Matthias and Zulian, \'Eder and Mathew, Deepak and Herrmann, Matthias and Brugger, Christian and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {1st International Symposium on Memory Systems (MEMSYS 2015)},
+  Year                     = {2015},
+
+  Address                  = {Washington, DC, USA},
+  Month                    = {October},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.08.11}
+}
+
+@Article{jun_96,
+  Title                    = {{Comparison of Turbo-Code Decoders Applied to Short Frame Transmission Systems}},
+  Author                   = {P. Jung},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {1996},
+
+  Month                    = apr,
+  Number                   = {3},
+  Pages                    = {530--537},
+  Volume                   = {14},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{jun_95,
+  Title                    = {{Novel Low Complexity Decoder for Turbo-Codes}},
+  Author                   = {P. Jung},
+  Journal                  = {Electronics Letters},
+  Year                     = {1995},
+
+  Month                    = jan,
+  Number                   = {2},
+  Pages                    = {86--87},
+  Volume                   = {31},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{junna_95,
+  Title                    = {{Comprehensive Comparison of Turbo-Code Decoders}},
+  Author                   = {P. Jung and M. Na{\ss}han},
+  Booktitle                = {{Proc. 1995 Vehicular Technology Conference (VTC '95)}},
+  Year                     = {1995},
+
+  Address                  = {Chicago, Illinois, USA},
+  Month                    = jul,
+  Pages                    = {624--628},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{junna_94b,
+  Title                    = {{Application of Turbo-Codes to a CDMA Mobile Radio System Using Joint Detection and Antenna Diversity}},
+  Author                   = {P. Jung and M. Na{\ss}han and J. Blanz},
+  Booktitle                = {{Proc. 1994 Vehicular Technology Conference (VTC '94)}},
+  Year                     = {1994},
+
+  Address                  = {Stockholm, Sweden},
+  Month                    = jun,
+  Pages                    = {770--774},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{junna_97,
+  Title                    = {{Results on Turbo-Codes for Speech Transmission in a Joint Detection CDMA Mobile Radio System with Coherent Receiver Antenna Diversity}},
+  Author                   = {P. Jung and M. Naßhan},
+  Journal                  = {IEEE Transactions of Vehicular Technology},
+  Year                     = {1997},
+
+  Month                    = nov,
+  Number                   = {4},
+  Pages                    = {862--870},
+  Volume                   = {46},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{junna_94,
+  Title                    = {{Dependence of the Error Performance of Turbo-Codes on the Interleaver Structure in Short Frame Transmission Systems}},
+  Author                   = {P. Jung and M. Naßhan},
+  Journal                  = {Electronics Letters},
+  Year                     = {1994},
+
+  Month                    = feb,
+  Number                   = {4},
+  Pages                    = {287--288},
+  Volume                   = {30},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{junna_94a,
+  Title                    = {{Performance Evaluation of Turbo Codes for Short Frame Transmission Systems}},
+  Author                   = {P. Jung and M. Naßhan},
+  Journal                  = {Electronics Letters},
+  Year                     = {1994},
+
+  Month                    = jan,
+  Number                   = {2},
+  Pages                    = {111--113},
+  Volume                   = {30},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{junple_99,
+  Title                    = {{CDMA Techniques for Third Generation Mobile Systems}},
+  Author                   = {P. Jung and J. Plechinger and M. Doetsch},
+  Chapter                  = {Turbo-Codes for Future Mobile Radio Applications},
+  Pages                    = {239--256},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {1999},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{junple_97,
+  Title                    = {{Advances on the Application of Turbo-Codes to Data-Services in Third Generation Mobile Networks}},
+  Author                   = {P. Jung and J. Plechinger and M. Doetsch and F. M. Berens},
+  Booktitle                = {Proc. International Symposium on Turbo-Codes \& Related Topics},
+  Year                     = {1997},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {135--142},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Jung2012,
+  Title                    = {{F}requency {E}stimation for {Non-pilot} {M}ode of {DVB-S2} {S}ystem},
+  Author                   = {S. Jung and D-G. Oh},
+  Booktitle                = {World Congress on Engineering and Computer Science},
+  Year                     = {2012},
+
+  Address                  = {San Francisco, USA},
+  Month                    = {October},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.03.06}
+}
+
+@InProceedings{koezim_06,
+  Title                    = {{Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures}},
+  Author                   = {St. K\"{o}hler and M. Zimmerling and M. Zabel and R. G. Spallek},
+  Booktitle                = {19th International Conference on Architecture of Computing Systems ARCS'06},
+  Year                     = {2006},
+
+  Address                  = {Frankfurt am Main, Germany},
+
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.05}
+}
+
+@InProceedings{kaesue_14,
+  Title                    = {{A} synthesis strategy for nonlinear model predictive controller on {FPGA}},
+  Author                   = {B. K\"apernick and S. S\"u\ss and E. Schubert and K. Graichen},
+  Booktitle                = {2014 UKACC International Conference on Control (CONTROL)},
+  Year                     = {2014},
+  Month                    = {July},
+  Pages                    = {662-667},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [59]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/CONTROL.2014.6915218},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {control engineering computing;field programmable gate arrays;fixed point arithmetic;high level synthesis;integration;iterative methods;nonlinear control systems;parallel processing;predictive control;nonlinear model predictive controller synthesis strategy;{FPGA};high-level synthesis;real-time {MPC} algorithm;MATLAB HDL Coder;Vivado HLS tool;parallel processing;integration schemes;fixed-point iteration approach;Field programmable gate arrays;Hardware design languages;MATLAB;Real-time systems;Cranes;Hardware;Chemical reactors},
+  Owner                    = {CCR}
+}
+
+@TechReport{kab_00,
+  Title                    = {{G}enerating {G}aussian {P}seudo-{R}andom {D}eviates},
+  Author                   = {Peter Kabal},
+  Institution              = {Department of Electrical \& Computer Engineering, McGill University},
+  Year                     = {2000},
+  Month                    = oct,
+
+  Cds_keywords             = {random number generator, normal distribution, transformation method},
+  Cds_read                 = {2012-03-22},
+  File                     = {kab_00.pdf:kab_00.pdf:PDF},
+  Journal                  = {Department of Electrical and Computer Engineering, McGill University, Tech. Rep},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22},
+  Url                      = {http://www-mmsp.ece.mcgill.ca/Documents/Reports/2000/KabalR2000c.pdf}
+}
+
+@InProceedings{kadkan_02,
+  Title                    = {{An integer linear programming approach for parallelizing applications in on-chip multiprocessors}},
+  Author                   = {I. Kadayif and M. Kandemir and U. Sezer},
+  Booktitle                = {Proc. 2002 Design Automation Conference (DAC '02)},
+  Year                     = {2002},
+
+  Address                  = {New Orleans, LA, USA},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kaeako_11,
+  Title                    = {{T}he {C}onvergence of {HPC} and {E}mbedded {S}ystems in our {H}eterogeneous {C}omputing {F}uture},
+  Author                   = {Kaeli, D. and Akodes, D.},
+  Booktitle                = {Computer Design (ICCD), 2011 IEEE 29th International Conference on},
+  Year                     = {2011},
+  Month                    = oct,
+  Pages                    = {9--11},
+
+  Abstract                 = {Recently we have seen two exciting trends that have been flooding the market: 1) the movement of graphics processing units into mainstream general-purpose platforms, and 2) the movement of multi-core embedded systems into tablet computing and smartphone spaces. These trends are forcing application developers to rethink how they are going to best utilize these many-core and multi-core heterogeneous platforms to provide new levels of cost/performance/power in a range of emerging application domains. A key driver in this movement is the recognition that traditional graphics devices can play a larger role in computation than was ever considered before. The high performance computing community has fueled this development, and has demonstrated that Graphics Processing Units can be utilized in a range of general purpose and embedded systems applications. By making this class of devices programmable, a new era in heterogeneous computing has begun. We will discuss some of the catalysts behind these changes, and consider what lies ahead in the future for heterogeneous computing. We will touch on current trends in computing core architectures and programming frameworks, as well as discuss what new classes of applications will be possible as we arrive at the intersection of these two vastly different computing domains.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ICCD.2011.6081368},
+  File                     = {kaeako_11.pdf:kaeako_11.pdf:PDF},
+  ISSN                     = {1063-6404},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Book{kaemis_15,
+  Title                    = {{H}eterogeneous {C}omputing with {O}pen{CL} 2.0},
+  Author                   = {David Kaeli and Perhaad Mistry and Dana Schaa and Dong Ping Zhang},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2015},
+
+  Address                  = {Waltham, MA, USA},
+  Edition                  = {3rd},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.16}
+}
+
+@InProceedings{kagcho_08,
+  Title                    = {{FPGA} {A}cceleration of {M}onte-{C}arlo based {C}redit {D}erivative {P}ricing},
+  Author                   = {Alexander Kaganov and Paul Chow and Asif Lakhany},
+  Booktitle                = {Proc. Int. Conf. Field Programmable Logic and Applications FPL 2008},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {329--334},
+
+  Abstract                 = {In recent years the financial world has seen an increasing demand for faster risk simulations, driven by growth in client portfolios. Traditionally many financial models employ Monte-Carlo simulation, which can take excessively long to compute in software. This paper describes a hardware implementation for collateralized debt obligations (CDOs) pricing, using the one-factor Gaussian copula (OFGC) model. We explore the precision requirements and the resulting resource utilization for each number representation. Our results show that our hardware implementation mapped onto a Xilinx XC5VSX50T is over 63 times faster than a software implementation running on a 3.4 GHz Intel Xeon processor.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPL.2008.4629953},
+  File                     = {kagcho_08.pdf:kagcho_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.23}
+}
+
+@InProceedings{kahkan_10,
+  Title                    = {{R}ecovery-driven design: {A} power minimization methodology for error-tolerant processor modules},
+  Author                   = {Kahng, A. B. and Seokhyeong Kang and Kumar, R. and Sartori, J.},
+  Booktitle                = {Proc. 47th ACM/IEEE Design Automation Conf. (DAC)},
+  Year                     = {2010},
+  Pages                    = {825--830},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- 
+- Recovery, Processor, Monitor},
+  File                     = {kahkan_10.pdf:kahkan_10.pdf:PDF},
+  Keywords                 = {Reliability PMF Probability Mass Function},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{kahliu_07,
+  Title                    = {{S}tatistical {T}iming {A}nalysis in the {P}resence of {S}ignal-{I}ntegrity {E}ffects},
+  Author                   = {Kahng, A. B. and Bao Liu and Xu Xu},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2007},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {1873--1877},
+  Volume                   = {26},
+
+  Doi                      = {10.1109/TCAD.2007.895771},
+  File                     = {kahliu_07.pdf:kahliu_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{kahcel_12,
+  Title                    = {{C}ode based efficient maximum-likelihood decoding of short polar codes},
+  Author                   = {S. Kahraman and M. E. Çelebi},
+  Booktitle                = {Information Theory Proceedings (ISIT), 2012 IEEE International Symposium on},
+  Year                     = {2012},
+  Month                    = {July},
+  Pages                    = {1967-1971},
+
+  Doi                      = {10.1109/ISIT.2012.6283643},
+  ISSN                     = {2157-8095},
+  Keywords                 = {information theory;maximum likelihood decoding;Shannon capacity;arbitrary symmetric binary-input channels;code based efficient maximum-likelihood decoding;code construction;decoding complexity;optimum ML decoder;polar coding;short polar codes;sphere decoding algorithm;sub-optimal decoders;Binary phase shift keying;Complexity theory;Decoding;Encoding;Maximum likelihood estimation;Measurement;ML estimation;Polar codes;Reed-Muller codes;Sphere Decoding}
+}
+
+@InProceedings{kahvit_14,
+  Title                    = {{F}olded successive cancelation decoding of polar codes},
+  Author                   = {S. Kahraman and E. Viterbo and M. E. Celebi},
+  Booktitle                = {Communications Theory Workshop (AusCTW), 2014 Australian},
+  Year                     = {2014},
+  Month                    = {Feb},
+  Pages                    = {57-61},
+
+  Doi                      = {10.1109/AusCTW.2014.6766428},
+  Keywords                 = {AWGN channels;computational complexity;maximum likelihood decoding;additive white Gaussian noise channel;folded successive cancelation decoding;folded tree maximum-likelihood decoding;nonbinary SC decoder;polar codes;quasilinear complexity;suboptimal decoder;Bit error rate;Complexity theory;Maximum likelihood decoding;Power capacitors;Simulation;Vegetation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Article{kahvit_14a,
+  Title                    = {{M}ultiple {F}olding for {S}uccessive {C}ancelation {D}ecoding of {P}olar {C}odes},
+  Author                   = {S. Kahraman and E. Viterbo and M. E. Çelebi},
+  Journal                  = {IEEE Wireless Communications Letters},
+  Year                     = {2014},
+
+  Month                    = {Oct},
+  Number                   = {5},
+  Pages                    = {545-548},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/LWC.2014.2343970},
+  ISSN                     = {2162-2337},
+  Keywords                 = {binary codes;maximum likelihood decoding;Kronecker product based codes;SCD;capacity achieving coding scheme;code length;conventional decoder;decoding latency;error correction capability;finite length polar codes;maximum-likelihood decoder;multiple folding;quasilinear complexity;standard binary polar codes;successive cancelation decoding;Channel coding;Complexity theory;Maximum likelihood decoding;Memory management;Vectors;Polar codes;SC decoder;folding operation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{kaishe_12,
+  Title                    = {{E}rror {R}esilient {MIMO} {D}etector for {M}emory-{D}ominated {W}ireless {C}ommunication {S}ystems},
+  Author                   = {Muhammad S. Kairy and Chung-An Shen and Ahmed M. Eltawil and Fadi Kurdahi},
+  Booktitle                = {Proceedings of IEEE Global Communications Conference (Globecom)},
+  Year                     = {2012},
+  Month                    = {December},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.05.13}
+}
+
+@Article{kaizhe_09,
+  Title                    = {{A}n {O}verview of {U}ltra-{W}ide-{B}and {S}ystems {W}ith {MIMO}},
+  Author                   = {Kaiser, T. and Feng Zheng and Dimitrov, E.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2009},
+  Number                   = {2},
+  Pages                    = {285-312},
+  Volume                   = {97},
+
+  Doi                      = {10.1109/JPROC.2008.2008784},
+  ISSN                     = {0018-9219},
+  Keywords                 = {MIMO communication;antenna arrays;array signal processing;channel capacity;receiving antennas;space-time codes;transmitting antennas;ultra wideband communication;MIMO system;beamforming;channel capacity;dense multipath propagation;optimal beamformer;space-time coding;spatial multiplexing gain;transmit and multiple receive antennas;ultrawide-band systems;wireless communications;Array signal processing;Channel capacity;Data communication;Indoor communication;MIMO;Receiving antennas;Space technology;Transmitting antennas;Ultra wideband technology;Wireless communication;Beamforming;MIMO;channel capacity;space–time coding;ultra-wide-band communications},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.08.28}
+}
+
+@Article{Kaleh1994,
+  Title                    = {{J}oint parameter estimation and symbol detection for linear or nonlinear unknown channels},
+  Author                   = {Kaleh, G.K. and Vallet, R.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1994},
+
+  Month                    = {Jul},
+  Number                   = {7},
+  Pages                    = {2406-2413},
+  Volume                   = {42},
+
+  Doi                      = {10.1109/26.297849},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Markov processes;iterative methods;parameter estimation;signal detection;Baum-Welch algorithm;EM algorithm;Markovian properties;channel identification;channel parameters;channel state sequence;expectation-maximization algorithm;forward-backward algorithm;information symbols;iterative method;likelihood functions;linear unknown channels;maximum likelihood criterion;noise variance;nonlinear unknown channels;parameter estimation;receiver;simulation results;symbol detection;symbol error probability;symbol selection;system throughput;Convergence;Dispersion;Error probability;Hidden Markov models;Iterative algorithms;Maximum likelihood detection;Maximum likelihood estimation;Modems;Parameter estimation;Throughput},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.23}
+}
+
+@MastersThesis{MTkamde15,
+  Title                    = {{A}ccelerating {B}ig {D}ata: {F}inding an {A}uto-{T}uning {M}ethodology for the {L}ink-{A}ssessment {P}roblem},
+  Author                   = {Kamdem Foudji, Brice},
+  School                   = {University of Kaiserslautern, Supervisor: N. Wehn, C. Brugger},
+  Year                     = {2015},
+  Month                    = Aug,
+  Type                     = {Master Thesis},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.23}
+}
+
+@MastersThesis{MTkamra13,
+  Title                    = {{S}cale-{O}ut {P}rocessors},
+  Author                   = {Pejman Lotfi Kamran},
+  School                   = {École Polytechnique Fédérale de Lausanne, Switzerland},
+  Year                     = {2013},
+  Note                     = {last access 2014-02-07},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {cloud},
+  File                     = {MTkamra13.pdf:MTkamra13.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07},
+  Url                      = {\url{http://infoscience.epfl.ch/record/188550/files/EPFL_TH5906.pdf}}
+}
+
+@InProceedings{kanoka_08,
+  Title                    = {{H}ardware implementation of soft-decision decoding for {R}eed-{S}olomon code},
+  Author                   = {Kan, M. and Okada, S. and Maehara, T. and Oguchi, K. and Yokokawa, T. and Miyauchi, T.},
+  Booktitle                = {Proc. 5th Int Turbo Codes and Related Topics Symp},
+  Year                     = {2008},
+  Pages                    = {73--77},
+
+  Doi                      = {10.1109/TURBOCODING.2008.4658675},
+  File                     = {kanoka_08.pdf:kanoka_08.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ABP},
+  Owner                    = {Scholl},
+  Review                   = {Hardwareimplementation eines ABP für einen grossen RS Code},
+  Timestamp                = {2011.06.21}
+}
+
+@InProceedings{kanli_05,
+  Title                    = {{S}tudying storage-recomputation tradeoffs in memory-constrained embedded processing},
+  Author                   = {Kandemir, Mahmut and Li, Feihul and Chen, Guilin and Chen, Guangyu and Ozturk, Ozcan},
+  Booktitle                = {Design, Automation and Test in Europe, 2005. Proceedings},
+  Year                     = {2005},
+  Organization             = {IEEE},
+  Pages                    = {1026--1031},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.09.17}
+}
+
+@Article{kantis_94,
+  Title                    = {{A}n efficient maximum-likelihood-decoding algorithm for linear block codes with algebraic decoder},
+  Author                   = {T. Kaneko and T. Nishijima and H. Inazumi and S. Hirasawa},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1994},
+
+  Month                    = {Mar},
+  Number                   = {2},
+  Pages                    = {320-327},
+  Volume                   = {40},
+
+  Doi                      = {10.1109/18.312155},
+  ISSN                     = {0018-9448},
+  Keywords                 = {block codes;decoding;maximum likelihood estimation;Chase algorithm;SNR;Tanaka-Kakigahara algorithm;algebraic decoder;computer simulation;decoding complexity;linear block codes;maximum-likelihood-decoding algorithm;performance;received sequence;signal-to-noise ratios;soft decoding algorithm;Block codes;Computer simulation;Industrial engineering;Information systems;Information theory;Laboratories;Maximum likelihood decoding;Research and development;Signal to noise ratio;Systems engineering and theory}
+}
+
+@Article{kanjr._98,
+  Title                    = {{Low-Power Viterbi Decoder for CDMA Mobile Terminals}},
+  Author                   = {I. Kang and Willson Jr., A. N.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {1998},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {473--482},
+  Volume                   = {33},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{kantet_99,
+  Title                    = {{S}imple {M}arkov-chain algorithms for generating bipartite graphs and tournaments},
+  Author                   = {Kannan, Ravi and Tetali, Prasad and Vempala, Santosh},
+  Journal                  = {Random Structures and Algorithms},
+  Year                     = {1999},
+  Number                   = {4},
+  Pages                    = {293--308},
+  Volume                   = {14},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.08.09}
+}
+
+@Article{kaozhu_18,
+  Title                    = {{A} {S}tudy of the {V}ariability in {C}ontact {R}esistive {R}andom {A}ccess {M}emory by {S}tochastic {V}acancy {M}odel},
+  Author                   = {Kao, Yun-Feng
+and Zhuang, Wei Cheng
+and Lin, Chrong-Jung
+and King, Ya-Chin},
+  Journal                  = {Nanoscale Research Letters},
+  Year                     = {2018},
+
+  Month                    = {Jul},
+  Number                   = {1},
+  Pages                    = {213},
+  Volume                   = {13},
+
+  Abstract                 = {Variability in resistive random access memory cell has been one of the critical challenges for the development of high-density RRAM arrays. While the sources of variability during resistive switching vary for different transition metal oxide films, the stochastic oxygen vacancy generation/recombination is generally believed to be the dominant cause. Through analyzing experimental data, a stochastic model which links the subsequent switching characteristics with its initial states of contact RRAM cells is established. By combining a conduction network model and the trap-assisted tunneling mechanism, the impacts of concentration and distribution of intrinsic oxygen vacancies in RRAM dielectric film are demonstrated with Monte Carlo Simulation. The measurement data on contact RRAM arrays agree well with characteristics projected by the model based on the presence of randomly distributed intrinsic vacancies. A strong correlation between forming characteristics and initial states is verified, which links forming behaviors to preforming oxygen vacancies. This study provides a comprehensive understanding of variability sources in contact RRAM devices and a reset training scheme to reduce the variability behavior in the subsequent RRAM states.},
+  Day                      = {16},
+  Doi                      = {10.1186/s11671-018-2619-x},
+  ISSN                     = {1556-276X},
+  Timestamp                = {2018-08-29},
+  Url                      = {https://doi.org/10.1186/s11671-018-2619-x}
+}
+
+@InProceedings{kapnol_06,
+  Title                    = {{A}pplication specific instruction processor based implementation of a {GNSS} receiver on an {FPGA}},
+  Author                   = {Kappen, G. and Noll, T. G.},
+  Booktitle                = {Proc. Design, Automation and Test in Europe DATE '06},
+  Year                     = {2006},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/DATE.2006.243749},
+  File                     = {kapnol_06.pdf:kapnol_06.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2010.10.05}
+}
+
+@InProceedings{kapcha_02,
+  Title                    = {{Power Estimation in Global Interconnect and its Reduction Using a Novel Repeater Optimization Methodology}},
+  Author                   = {P. Kapur and G. Chandra and K.C. Saraswat},
+  Booktitle                = {Proc. 2002 Design Automation Conference (DAC '02)},
+  Year                     = {2002},
+
+  Address                  = {New Orleans, USA},
+  Month                    = jun,
+  Pages                    = {461--466},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{karban_10,
+  Title                    = {{P}rocess-{V}ariation {R}esilient and {V}oltage-{S}calable {DCT} {A}rchitecture for {R}obust {L}ow-{P}ower {C}omputing},
+  Author                   = {Karakonstantis, G. and Banerjee, N. and Roy, K.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2010},
+  Number                   = {10},
+  Pages                    = {1461--1470},
+  Volume                   = {18},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/TVLSI.2009.2025279},
+  File                     = {karban_10.pdf:karban_10.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.26}
+}
+
+@InProceedings{karban_07,
+  Title                    = {{D}esign {M}ethodology to {T}rade {O}ff {P}ower, {O}utput {Q}uality and {E}rror {R}esiliency: {A}pplication to {C}olor {I}nterpolation {F}iltering},
+  Author                   = {G. Karakonstantis and N. Banerjee and K. Roy and C. Chakrabarti},
+  Booktitle                = {Proc. IEEE/ACM International Conference on Computer-Aided Design ICCAD 2007},
+  Year                     = {2007},
+  Month                    = nov,
+  Pages                    = {199--204},
+
+  Doi                      = {10.1109/ICCAD.2007.4397266},
+  File                     = {karban_07.pdf:karban_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.20}
+}
+
+@Article{karcha_11,
+  Title                    = {{C}ontaining the {N}anometer ``{P}andora-{B}ox'': {C}ross-{L}ayer {D}esign {T}echniques for {V}ariation {A}ware {L}ow {P}ower {S}ystems},
+  Author                   = {Karakonstantis, G. and Chatterjee, A. and Roy, K.},
+  Journal                  = {Emerging and Selected Topics in Circuits and Systems, IEEE Journal on},
+  Year                     = {2011},
+  Number                   = {1},
+  Pages                    = {19--29},
+  Volume                   = {1},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Empfehlung Norbert},
+  Doi                      = {10.1109/JETCAS.2011.2135590},
+  File                     = {karcha_11.pdf:karcha_11.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.15}
+}
+
+@InProceedings{karpan_10,
+  Title                    = {{HERQULES}: {S}ystem level cross-layer design exploration for efficient energy-quality trade-offs},
+  Author                   = {Karakonstantis, G. and Panagopoulos, G. and Roy, K.},
+  Booktitle                = {Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on},
+  Year                     = {2010},
+  Pages                    = {117-122},
+
+  File                     = {karpan_10.pdf:karpan_10.pdf:PDF},
+  Keywords                 = {Adders;Algorithm design and analysis;Computer architecture;Delay;Discrete cosine transforms;Energy efficiency;Tuning;Energy efficient systems;optimal design criteria;voltage-scaling},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.05.17}
+}
+
+@InProceedings{karrot_12,
+  Title                    = {{O}n the {E}xploitation of the {I}nherent {E}rror {R}esilience of {W}ireless {S}ystems under {U}nreliable {S}ilicon},
+  Author                   = {G. Karakonstantis and C. Roth and C. Benkeser and A. Burg},
+  Booktitle                = {Proc. IEEE Design Automation Conference},
+  Year                     = {2012},
+  Month                    = jun,
+
+  File                     = {karrot_12.pdf:karrot_12.pdf:PDF},
+  Keywords                 = {Turbo, Reliability},
+  Owner                    = {May},
+  Timestamp                = {2012.02.21}
+}
+
+@Article{karcha_12,
+  Title                    = {{H}igh-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver},
+  Author                   = {S. M. Karim and I. Chakrabarti},
+  Journal                  = {IET Communications},
+  Year                     = {2012},
+
+  Month                    = {July},
+  Number                   = {11},
+  Pages                    = {1416-1424},
+  Volume                   = {6},
+
+  Doi                      = {10.1049/iet-com.2011.0713},
+  File                     = {karcha_12.pdf:karcha_12.pdf:PDF},
+  ISSN                     = {1751-8628},
+  Keywords                 = {maximum likelihood decoding;parallel architectures;pipeline processing;telecommunication computing;telecommunication network reliability;turbo codes;3GPP LTE;ACSO unit;MAP decoder core;add compare select offset unit;bit rate 1.138 Gbit/s;frequency 486 MHz;global overflow protection logic;high-throughput turbo decoder;low-complexity contention-free interleaver;maximum a posteriori probability decoder core;modern wireless communication standards;normalisation process;parallel processing;pipelined parallel architecture;size 90 nm;third-generation partnership project long-term evolution},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{karcha_10,
+  Title                    = {{A}n improved low-power high-throughput log-{MAP} turbo decoder},
+  Author                   = {Karim, S. M. and Chakrabarti, I. },
+  Journal                  = {Consumer Electronics, IEEE Transactions on},
+  Year                     = {2010},
+  Number                   = {2},
+  Pages                    = {450--457},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TCE.2010.5505954},
+  File                     = {karcha_10.pdf:karcha_10.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@Article{kardic_10,
+  Title                    = {{A} {P}erformance {C}omparison of {CUDA} and {O}pen{CL}},
+  Author                   = {Kamran Karimi and Neil G. Dickson and Firas Hamze},
+  Journal                  = {CoRR},
+  Year                     = {2010},
+  Volume                   = {abs/1005.2581},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.04.06},
+  Url                      = {http://arxiv.org/abs/1005.2581}
+}
+
+@InProceedings{karcav_04,
+  Title                    = {{Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding}},
+  Author                   = {M. Karkooti and J. Cavallaro},
+  Booktitle                = {International Conference on Information Technology(ITCC'04)},
+  Year                     = {2004},
+  Month                    = apr,
+  Pages                    = {579--585},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{kar_84,
+  Title                    = {{A} new polynomial-time algorithm for linear programming},
+  Author                   = {Karmarkar, N.~},
+  Journal                  = {Combinatorica},
+  Year                     = {1984},
+  Pages                    = {373-395},
+  Volume                   = {4},
+
+  No                       = {4},
+  Owner                    = {scholl},
+  Timestamp                = {2016.05.31}
+}
+
+@Electronic{karmat_11,
+  Title                    = {{Tutorial: OpenCL - Introduction for HPC Programmers}},
+  Author                   = {Vadim Kartoshkin and Timothy Mattson},
+  Month                    = {Mar},
+  Note                     = {last access: 31 Aug 2017},
+  Organization             = {Intel},
+  Url                      = {https://software.intel.com/en-us/articles/tutorial-opencl-introduction-for-hpc-programmers},
+  Year                     = {2011},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.12.03}
+}
+
+@InProceedings{karben_18,
+  Title                    = {{S}mart {W}earable {W}ristband for {EMG} based {G}esture {R}ecognition {P}owered by {S}olar {E}nergy {H}arvester},
+  Author                   = {V. Kartsch and S. Benatti and M. Mancini and M. Magno and L. Benini},
+  Booktitle                = {2018 IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2018},
+  Month                    = {May},
+  Pages                    = {1-5},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8351727},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/ISCAS.2018.8351727},
+  Keywords                 = {TCS},
+  Keywords_original        = {Batteries;Biomedical monitoring;Discrete wavelet transforms;Electromyography;Power demand;Sensors;Support vector machines},
+  Owner                    = {CCR}
+}
+
+@InCollection{kas_01,
+  Title                    = {{R}eal {T}ime {M}orphological {I}mage {C}ontrast {E}nhancement in {V}irtex {FPGA}},
+  Author                   = {Kasperek, Jerzy},
+  Booktitle                = {Field-Programmable Logic and Applications},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2001},
+  Editor                   = {Brebner, Gordon and Woods, Roger},
+  Pages                    = {430-440},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {2147},
+
+  Abstract                 = {This paper describes the implementation of the real time local image contrast enhancement method. The system is based on Virtex FPGA chip and enhances the angiocardiographic data using the modified mathematical morphology multiscale TopHat transform. The morphological TopHat transform proved its effectiveness but the direct real time pipeline implementation of the multiscale version requires too many memory blocks. The author proposes a slight modification of the algorithm and presents satisfactory image contrast enhancement results and an efficient FPGA implementation. Proposed pipeline architecture uses the structural element decomposition and employs the Virtex BlockRam modules effectively. The processing kernel realises the contrast enhancement for the 512 × 512 image data with 8 bits/pixel representation in the real time in one XCV-800 Virtex chip.},
+  Cds_grade                = {3},
+  Cds_keywords             = {morphological filter, FPGA, top-hat},
+  Cds_read                 = {2014-07-15},
+  Cds_review               = {general introduction to top-hat
+very high-level hardware architecture description},
+  Doi                      = {10.1007/3-540-44687-7_44},
+  File                     = {kas_01.pdf:kas_01.pdf:PDF},
+  ISBN                     = {978-3-540-42499-4},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Timestamp                = {2014.07.15},
+  Url                      = {http://dx.doi.org/10.1007/3-540-44687-7_44}
+}
+
+@Electronic{kasthi_06,
+  Title                    = {{Z}itieren in wissenschaftlichen {A}rbeiten},
+  Author                   = {Susanne Kassel and Martina Thiele and Margit Böck},
+  HowPublished             = {\url{www.daf.tu-berlin.de/fileadmin/fg75/PDF/Zitieren.pdf‎}},
+  Language                 = {de},
+  Month                    = oct,
+  Note                     = {last access 2014-01-24},
+  Url                      = {\url{www.daf.tu-berlin.de/fileadmin/fg75/PDF/Zitieren.pdf‎}},
+  Year                     = {2006},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {citation, zitieren},
+  File                     = {kasthi_06.pdf:kasthi_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24}
+}
+
+@InProceedings{katstu_99,
+  Title                    = {{F}ault-tolerant refresh power reduction of {DRAM}s for quasi-nonvolatile data retention},
+  Author                   = {Katayama, Y. and Stuckey, E.J. and Morioka, S. and Wu, Z.},
+  Booktitle                = {Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on},
+  Year                     = {1999},
+  Month                    = {Nov},
+  Pages                    = {311-318},
+
+  Doi                      = {10.1109/DFTVS.1999.802898},
+  ISSN                     = {1550-5774},
+  Keywords                 = {DRAM chips;Reed-Solomon codes;error correction codes;fault tolerance;DRAMs;adaptive refresh rate controller;data integrity;data pattern sensitivity;fault-tolerant refresh power reduction;memory system power usage;one-shot Reed-Solomon error correction code;part-to-part variations;perturbation effects;quasi-nonvolatile data retention;Adaptive control;DRAM chips;Error correction codes;Fault tolerance;Power system reliability;Programmable control;Random access memory;Reed-Solomon codes;Robust control;Standards development},
+  Owner                    = {MJ},
+  Timestamp                = {2015.12.02}
+}
+
+@Article{kavpat_08,
+  Title                    = {{T}he {R}ead {C}hannel},
+  Author                   = {Kavcic, A. and Patapoutian, Ara},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2008},
+  Number                   = {11},
+  Pages                    = {1761-1774},
+  Volume                   = {96},
+
+  Doi                      = {10.1109/JPROC.2008.2004310},
+  ISSN                     = {0018-9219},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.04.24}
+}
+
+@InProceedings{kavazg_08,
+  Title                    = {{D}esign of {R}obust and {H}igh-{P}erformance 1-{B}it {CMOS} {F}ull {A}dder for {N}anometer {D}esign},
+  Author                   = {Kavehei, O. and Azghadi, M. R. and Navi, K. and Mirbaha, A.-P.},
+  Booktitle                = {Proc. IEEE Computer Society Annual Symposium on VLSI ISVLSI '08},
+  Year                     = {2008},
+  Month                    = apr,
+  Pages                    = {10--15},
+
+  Doi                      = {10.1109/ISVLSI.2008.16},
+  File                     = {kavazg_08.pdf:kavazg_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{Kay1989,
+  Title                    = {{A} {F}ast and {A}ccurate {S}ingle {F}requency {E}stimator},
+  Author                   = {Kay, S.},
+  Journal                  = {IEEE Transactions on Acoustics, Speech and Signal Processing},
+  Year                     = {1989},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {1987-1990},
+  Volume                   = {37},
+
+  Doi                      = {10.1109/29.45547},
+  ISSN                     = {0096-3518},
+  Keywords                 = {filtering and prediction theory;random noise;Cramer-Rao bound;complex white Gaussian noise;linear prediction estimator;maximum-likelihood estimator;prediction theory;single frequency estimator;Frequency estimation;Gaussian noise;Gaussian processes;High performance computing;Least squares approximation;Maximum likelihood estimation;Phase estimation;Random variables;Signal processing;Signal to noise ratio},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.25}
+}
+
+@InProceedings{kayabd_14,
+  Title                    = {{A} {N}ovel {A}pproach for {SVA} {G}eneration of {DDR} {M}emory {P}rotocols {B}ased on {TDML}},
+  Author                   = {M. O. {Kayed} and M. {Abdelsalam} and R. {Guindi}},
+  Booktitle                = {2014 15th International Microprocessor Test and Verification Workshop},
+  Year                     = {2014},
+  Month                    = {Dec},
+  Pages                    = {61-66},
+
+  Doi                      = {10.1109/MTV.2014.15},
+  ISSN                     = {1550-4093},
+  Keywords                 = {DRAM chips;hardware description languages;memory protocols;SVA generation;TDML;System Verilog Assertions;Assertion Based Verification methodology;ABV methodology;hardware design specifications;general memory protocol standard;DDR memory protocols;timing diagram tool;Timing Diagram Markup Language;JEDEC LPDDR3 memory protocol standard;Standards;XML;Protocols;Hardware;Unified modeling language;Delays;Timing Diagrams;TDML;Functional Verification;SVA;DDR memories},
+  Owner                    = {MJ},
+  Timestamp                = {2019-05-30}
+}
+
+@Patent{kazyu_12,
+  Title                    = {{S}ystems and methods for improving digital system simulation speed by clock phase gating},
+  Year                     = {2012},
+  Author                   = {Kazi, Tauseef and Yu, Haobo and Cai, Lukai and Sridharan, Mahesh and Chaiyakul, Viraphol},
+  Note                     = {US Patent 8,140,316},
+
+  Owner                    = {MJ},
+  Publisher                = {Google Patents},
+  Timestamp                = {2019-08-08}
+}
+
+@InBook{keabri_99,
+  Title                    = {{Reuse Methodology Manual For System on Chip Designs Second Edition}},
+  Author                   = {M. Keating and P. Bricaud},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {1999},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{keb_05,
+  Title                    = {{S}tatistical {R}omberg {E}xtrapolation: {A} {N}ew {V}ariance {R}eduction {M}ethod and {A}pplications to {O}ption {P}ricing},
+  Author                   = {Ahmed Kebaier},
+  Journal                  = {The Annals of Applied Probability},
+  Year                     = {2005},
+  Number                   = {4},
+  Pages                    = {2681--2705},
+  Volume                   = {15},
+
+  Abstract                 = {We study the approximation of $Ef(X_{T})$ by a Monte Carlo algorithm, where X is the solution of a stochastic differential equation and f is a given function. We introduce a new variance reduction method, which can be viewed as a statistical analogue of Romberg extrapolation method. Namely, we use two Euler schemes with steps $\delta$ and $\delta^{\beta}, 0 < \beta < 1$ . This leads to an algorithm which, for a given level of the statistical error, has a complexity significantly lower than the complexity of the standard Monte Carlo method. We analyze the asymptotic error of this algorithm in the context of general (possibly degenerate) diffusions. In order to find the optimal $\beta$ (which turns out to be $\beta = 1/2$ ), we establish a central limit type theorem, based on a result of Jacod and Protter for the asymptotic distribution of the error in the Euler scheme. We test our method on various examples. In particular, we adapt it to Asian options. In this setting, we have a CLT and, as a by-product, an explicit expansion of the discretization error.},
+  Cds_grade                = {0},
+  Copyright                = {Copyright © 2005 Institute of Mathematical Statistics},
+  File                     = {keb_05.pdf:keb_05.pdf:PDF},
+  ISSN                     = {10505164},
+  Jstor_articletype        = {research-article},
+  Jstor_formatteddate      = {Nov., 2005},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Publisher                = {Institute of Mathematical Statistics},
+  Url                      = {http://www.jstor.org/stable/30038520}
+}
+
+@Book{keebak_07,
+  Title                    = {{DRAM} {C}ircuit {D}esign: {F}undamental and {H}igh-{S}peed {T}opics},
+  Author                   = {Keeth, Brent and Baker, R. Jacob and Johnson, Brian and Lin, Feng},
+  Publisher                = {Wiley-IEEE Press},
+  Year                     = {2007},
+  Edition                  = {2nd},
+
+  ISBN                     = {0470184752, 9780470184752},
+  Timestamp                = {2018-09-08}
+}
+
+@Article{keiweh_01,
+  Title                    = {{Embedded DRAM Development: Technology, Physical Design, and Application Issues}},
+  Author                   = {D. Keitel-Schulz and N. Wehn},
+  Journal                  = {IEEE Design \& Test of Computers},
+  Year                     = {2001},
+
+  Month                    = may # {--} # jun,
+  Pages                    = {7--15},
+  Volume                   = {18},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@InProceedings{keiweh_98,
+  Title                    = {{Issues in Embedded DRAM Development and Applications}},
+  Author                   = {D. Keitel-Schulz and N. Wehn},
+  Booktitle                = {Proc. 11th International Symposium on System Synthesis},
+  Year                     = {1998},
+
+  Address                  = {Taiwan},
+  Month                    = dec,
+  Note                     = {Invited Paper},
+  Pages                    = {23--28},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{keiweh_01a,
+  Title                    = {{E}mbedded {M}emories in {S}ystem {D}esign: {T}echnology, {A}pplication, {D}esign and {T}ools},
+  Author                   = {D. Keitel-Schulz and N. Wehn and F. Catthoor and P.R. Panda and N.Dutt},
+  Booktitle                = {14th International Conference on VLSI Design (tutorial)},
+  Year                     = {2001},
+
+  Address                  = {Bangalore, India},
+  Month                    = jan,
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@Book{kelham_13,
+  Title                    = {{S}mart {M}achines: {IBM}'s {W}atson and the {E}ra of {C}ognitive {C}omputing},
+  Author                   = {Kelly, J. and Hamm, S.},
+  Publisher                = {Columbia University Press},
+  Year                     = {2013},
+  Series                   = {Columbia Business School Publishing},
+
+  ISBN                     = {9780231168564},
+  Lccn                     = {2013026154},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01},
+  Url                      = {https://books.google.de/books?id=U9arAgAAQBAJ}
+}
+
+@InProceedings{kelcha_93,
+  Title                    = {{A flexible constraint length, foldable Viterbi decoder}},
+  Author                   = {P. H. Kelly and P. M. Chau},
+  Booktitle                = {Proc. 1993 Global Telecommunications Conference (GLOBECOM '93)},
+  Year                     = {1993},
+
+  Address                  = {Houston, Texas},
+  Month                    = nov # {--} # dec,
+  Pages                    = {631--635},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{kengoe_13,
+  Title                    = {{E}nergy {M}anagement for {S}mart {G}rids {W}ith {E}lectric {V}ehicles {B}ased on {H}ierarchical {MPC}},
+  Author                   = {F. {Kennel} and D. {G\"orges} and S. {Liu}},
+  Journal                  = {IEEE Transactions on Industrial Informatics},
+  Year                     = {2013},
+
+  Month                    = {Aug},
+  Number                   = {3},
+  Pages                    = {1528-1537},
+  Volume                   = {9},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/TII.2012.2228876},
+  ISSN                     = {1551-3203},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {electric vehicles;energy management systems;frequency control;load regulation;smart power grids;smart grids;electric vehicles;hierarchical MPC;energy management system;hierarchical model predictive control;HiMPC;time scales;power ratings;renewable generation;systematic model;optimization-based design;electric vehicle integration;electric vehicles availability;current mobility demand;statistical mobility behavior;Electric vehicles;System-on-a-chip;Batteries;Smart grids;Energy management;Power system stability;Aggregator;electric vehicles;energy management;hierarchical model predictive control (HiMPC);load-frequency control (LFC);smart grid;vehicle-to-grid (V2G)},
+  Owner                    = {CCR}
+}
+
+@InProceedings{kerwon_13,
+  Title                    = {{E}mbedded reconfigurable computing: the {ERA} approach},
+  Author                   = {Keramidas, G. and Wong, S. and Anjam, F. and Brandon, A. and Seedorf, R. and Scordino, C. and Carro, L. and Matos, D. and Giorgi, R. and Kavvadias, S. and McKee, S. and Goel, B. and Spiliopoulos, V.},
+  Booktitle                = {Industrial Informatics (INDIN), 2013 11th IEEE International Conference on},
+  Year                     = {2013},
+  Month                    = {July},
+  Pages                    = {827-832},
+
+  Doi                      = {10.1109/INDIN.2013.6889116},
+  Keywords                 = {embedded systems;hardware-software codesign;operating systems (computers);program compilers;ERA approach;adaptive compiler;custom operating system;custom runtime system;embedded reconfigurable computing;hardware-software codesign;high-efficiency embedded system designs;inter-synergism;intra-synergism;structured approach;Benchmark testing;Fabrics;Hardware;Memory management;Multicore processing;Software;VLIW;adaptive embedded platform;hardware-software codesign;reconfigurable computing},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@Misc{kerlod_06,
+  Title                    = {{N}ear {ML} {P}erformance for {L}inear {B}lock {C}odes {U}sing an {I}terative {V}ector {SISO} {D}ecoder},
+
+  Author                   = {Kerr, Ron and Lodge, John},
+  Note                     = {Turbo Codes\&Related Topics; 6th International ITG-Conference on Source and Channel Coding (TURBOCODING), 2006 4th International Symposium on},
+  Year                     = {2006},
+
+  File                     = {kerlod_06.pdf:kerlod_06.pdf:PDF},
+  Owner                    = {Scholl},
+  Pages                    = {1--6},
+  Timestamp                = {2011.07.21}
+}
+
+@Misc{Kerr2006,
+  Title                    = {{N}ear {ML} {P}erformance for {L}inear {B}lock {C}odes {U}sing an {I}terative {V}ector {SISO} {D}ecoder},
+
+  Author                   = {Kerr, Ron and Lodge, John},
+  Note                     = {Turbo Codes\&Related Topics; 6th International ITG-Conference on Source and Channel Coding (TURBOCODING), 2006 4th International Symposium on},
+  Year                     = {2006},
+
+  File                     = {kerlod_06.pdf:kerlod_06.pdf:PDF},
+  Owner                    = {Scholl},
+  Pages                    = {1--6},
+  Timestamp                = {2011.07.21}
+}
+
+@InProceedings{kerlod_04,
+  Title                    = {{V}ector {S}oft-in-soft-out {D}ecoding {A}pplied to {N}on-binary {L}inear {B}lock {C}odes},
+  Author                   = {R. Kerr and J. Lodge},
+  Booktitle                = {Proceedings of the 22nd Biennial Symposium on Communications},
+  Year                     = {2004},
+  Pages                    = {376-378},
+
+  File                     = {kerlod_04.pdf:kerlod_04.pdf:PDF},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.21}
+}
+
+@Misc{ker_18,
+  Title                    = {{L}inux {P}rogrammer's {M}anual: {FORK}(2)},
+
+  Author                   = {Michael Kerrisk},
+  HowPublished             = {http://man7.org/linux/man-pages/man2/fork.2.html},
+  Month                    = {April},
+  Year                     = {2018},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-13}
+}
+
+@Book{kes_12,
+  Title                    = {{M}odellierung von digitalen {S}ystemen mit {S}ystem{C}: {V}on der {RTL}- zur {T}ransaction-{L}evel-{M}odellierung},
+  Author                   = {Kesel, Frank},
+  Publisher                = {Oldenbourg Wissenschaftsverlag},
+  Year                     = {2012},
+
+  ISBN                     = {9783486705812},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.23}
+}
+
+@InProceedings{kessti_09,
+  Title                    = {{RMS-TM}: {A} {T}ransactional {M}emory {B}enchmark for {R}ecognition, {M}ining and {S}ynthesis {A}pplications},
+  Author                   = {Kestor, Gokcen and Stipic, Srdjan and Unsal, Osman S. and Cristal, Adri\'{a}n and Valero, Mateo},
+  Booktitle                = {TRANSACT\~{}'09: 4th Workshop on Transactional Computing},
+  Year                     = {2009},
+  Month                    = feb,
+
+  Citeulike-article-id     = {5856062},
+  File                     = {kessti_09.pdf:kessti_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Posted-at                = {2009-09-29 20:16:16},
+  Priority                 = {0},
+  Timestamp                = {2009.12.16}
+}
+
+@InProceedings{kesdav_10,
+  Title                    = {{BLAS} {C}omparison on {FPGA}, {CPU} and {GPU}},
+  Author                   = {Kestur, S. and Davis, J.D. and Williams, O.},
+  Booktitle                = {VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on},
+  Year                     = {2010},
+  Pages                    = {288-293},
+
+  Abstract                 = {High Performance Computing (HPC) or scientific codes are being executed across a wide variety of computing platforms from embedded processors to massively parallel GPUs. We present a comparison of the Basic Linear Algebra Subroutines (BLAS) using double-precision floating point on an FPGA, CPU and GPU. On the CPU and GPU, we utilize standard libraries on state-of-the-art devices. On the FPGA, we have developed parameterized modular implementations for the dot-product and Gaxpy or matrix-vector multiplication. In order to obtain optimal performance for any aspect ratio of the matrices, we have designed a high-throughput accumulator to perform an efficient reduction of floating point values. To support scalability to large data-sets, we target the BEE3 FPGA platform. We use performance and energy efficiency as metrics to compare the different platforms. Results show that FPGAs offer comparable performance as well as 2.7 to 293 times better energy efficiency for the test cases that we implemented on all three platforms.},
+  Cds_grade                = {4},
+  Cds_keywords             = {GPU, FPGA, Energy},
+  Cds_read                 = {2011-11-11},
+  Cds_review               = {energy comparison
+metrics exactly as we use them
+massive potential of energy saving using FPGAs over GPUs},
+  Doi                      = {10.1109/ISVLSI.2010.84},
+  File                     = {kesdav_10.pdf:kesdav_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@InProceedings{kesdav_10a,
+  Title                    = {{BLAS} {C}omparison on {FPGA}, {CPU} and {GPU}},
+  Author                   = {S. Kestur and J. D. Davis and O. Williams},
+  Booktitle                = {2010 IEEE Computer Society Annual Symposium on VLSI},
+  Year                     = {2010},
+  Month                    = {July},
+  Pages                    = {288-293},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [33]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/ISVLSI.2010.84},
+  ISSN                     = {2159-3469},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {field programmable gate arrays;matrix multiplication;high performance computing;scientific codes;embedded processors;massively parallel {GPU};basic linear algebra subroutines;double-precision floating point;{CPU};parameterized modular implementations;matrix-vector multiplication;dot-product multiplication;floating point values;energy efficiency;{FPGA} optimizations;Field programmable gate arrays;Adders;Random access memory;Kernel;Pipelines;Graphics processing unit;Libraries},
+  Owner                    = {CCR}
+}
+
+@Article{keunew_00,
+  Title                    = {{S}ystem-level design: orthogonalization of concerns and platform-based design},
+  Author                   = {Keutzer, K. and Newton, A.R. and Rabaey, J.M. and Sangiovanni-Vincentelli, A.},
+  Journal                  = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
+  Year                     = {2000},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {1523-1543},
+  Volume                   = {19},
+
+  Doi                      = {10.1109/43.898830},
+  ISSN                     = {0278-0070},
+  Keywords                 = {circuit CAD;embedded systems;integrated circuit design;program compilers;architecture-function co-design;communication-based design;compilers;complex integrated circuits;concurrent architectures;design methodology;design tools;embedded systems;platform-based design;software programmable architecture;system-level design;wireless system design;Application software;Computer architecture;Design methodology;Embedded system;Integrated circuit technology;Process design;Productivity;Silicon;System-level design;Time to market},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.27}
+}
+
+@Article{keyzeb_00,
+  Title                    = {{F}ault-tolerant evolvable hardware using field-programmable transistor arrays},
+  Author                   = {Keymeulen, D. and Zebulum, R. S. and Jin, Y. and Stoica, A.},
+  Journal                  = {IEEE Transactions on Reliability},
+  Year                     = {2000},
+
+  Month                    = sep,
+  Number                   = {3},
+  Pages                    = {305--316},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/24.914547},
+  File                     = {keyzeb_00.pdf:keyzeb_00.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{khashe_12,
+  Title                    = {{E}rror resilient {MIMO} detector for memory-dominated wireless communication systems},
+  Author                   = {Khairy, M.S. and Chung-An Shen and Eltawil, A.M. and Kurdahi, F.},
+  Booktitle                = {Global Communications Conference (GLOBECOM), 2012 IEEE},
+  Year                     = {2012},
+  Pages                    = {3566-3571},
+
+  Doi                      = {10.1109/GLOCOM.2012.6503668},
+  File                     = {khashe_12.pdf:khashe_12.pdf:PDF},
+  ISSN                     = {1930-529X},
+  Keywords                 = {3G mobile communication;Long Term Evolution;MIMO communication;OFDM modulation;radio receivers;3GPP LTE;MIMO-OFDM receiver;aggressive voltage scaling;broadband MIMO-OFDM systems;channel noise;chip area;dense structure;embedded buffering memories;error resilient MIMO detector;hardware errors;memory error;memory power savings;memory-dominated wireless communication systems;modified MIMO detection algorithm;near-optimal performance;power consumption;process variation;receiver buffering memory;reduced voltage overhead;scaling effects;tree-searching structure;wireless channel},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@InProceedings{khaami_10,
+  Title                    = {{A} {U}nified {H}ardware and {C}hannel {N}oise {M}odel for {C}ommunication {S}ystems},
+  Author                   = {Khajeh, A. and Amiri, K. and Khairy, M. S. and Eltawil, A. M. and Kurdahi, F. J.},
+  Booktitle                = {Proc. IEEE Global Telecommunications Conf. GLOBECOM 2010},
+  Year                     = {2010},
+  Pages                    = {1--5},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Kurdahi, Turbo(?)
+- Modified Channel Model, Correction by Adjusting the BMU},
+  Doi                      = {10.1109/GLOCOM.2010.5683123},
+  File                     = {khaami_10.pdf:khaami_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{khakim_12,
+  Title                    = {{E}rror-{A}ware {A}lgorithm/{A}rchitecture {C}oexploration for {V}ideo {O}ver {W}ireless {A}pplications},
+  Author                   = {Khajeh, Amin and Kim, Minyoung and Dutt, Nikil and Eltawil, Ahmed M. and Kurdahi, Fadi J.},
+  Journal                  = {ACM Trans. Embed. Comput. Syst.},
+  Year                     = {2012},
+
+  Month                    = jun,
+  Number                   = {1},
+  Pages                    = {15:1--15:23},
+  Volume                   = {11S},
+
+  Acmid                    = {2180892},
+  Address                  = {New York, NY, USA},
+  Articleno                = {15},
+  Doi                      = {10.1145/2180887.2180892},
+  ISSN                     = {1539-9087},
+  Issue_date               = {June 2012},
+  Keywords                 = {Error resilience, cross-layer, video, wireless communication},
+  Numpages                 = {23},
+  Owner                    = {Gimmler},
+  Publisher                = {ACM},
+  Timestamp                = {2013.05.17},
+  Url                      = {http://doi.acm.org/10.1145/2180887.2180892}
+}
+
+@InProceedings{khakim_08,
+  Title                    = {{C}ross-{L}ayer {C}o-{E}xploration of {E}xploiting {E}rror {R}esilience for {V}ideo over {W}ireless {A}pplications},
+  Author                   = {Khajeh, A. and Minyoung Kim and Dutt, N. and Eltawil, A. M. and Kurdahi, F. J.},
+  Booktitle                = {Proc. IEEE/ACM/IFIP Workshop Embedded Systems for Real-Time Multimedia ESTImedia 2008},
+  Year                     = {2008},
+  Pages                    = {13--18},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Kurdahi
+- Cross Layer, Video},
+  Doi                      = {10.1109/ESTMED.2008.4696987},
+  File                     = {khakim_08.pdf:khakim_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{kharao_19,
+  Title                    = {{A} {R}eview of {H}uman-{P}owered {E}nergy {H}arvesting for {S}mart {E}lectronics: {R}ecent {P}rogress and {C}hallenges},
+  Author                   = {Khalid, Salman and Raouf, Izaz and Khan, Asif and Kim, Nayeon and Kim, Heung Soo},
+  Journal                  = {International Journal of Precision Engineering and Manufacturing-Green Technology},
+  Year                     = {2019},
+
+  Month                    = {Aug},
+  Number                   = {4},
+  Pages                    = {821--851},
+  Volume                   = {6},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Khalid2019},
+  Ccr_keywords             = {wearableEH},
+  Ccr_relevance            = {high},
+  Ccr_topic                = {ATC, TCW},
+  Day                      = {01},
+  Doi                      = {10.1007/s40684-019-00144-y},
+  ISSN                     = {2198-0810},
+  Keywords                 = {TCS},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27},
+  Url                      = {https://doi.org/10.1007/s40684-019-00144-y}
+}
+
+@InProceedings{khasal_15,
+  Title                    = {{I}mplementation and verification of a generic universal memory controller based on {UVM}},
+  Author                   = {K. {Khalifa} and K. {Salah}},
+  Booktitle                = {2015 10th International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS)},
+  Year                     = {2015},
+  Month                    = {April},
+  Pages                    = {1-2},
+
+  Doi                      = {10.1109/DTIS.2015.7127364},
+  Keywords                 = {DRAM chips;flash memories;low-power electronics;power consumption;generic universal memory controller;universal verification methodology;power consumption;FLASH;DRAM;Memory management;Monitoring;Random access memory;Time-varying systems;Time-domain analysis;Memory architecture;Protocols;Universal Memory Controller;low power Memory Controller;Flash;DRAM;UVM;eMMC;ONFI;One-NAND;UFS;HMC;WideIO;SSD;Verification Environment},
+  Owner                    = {MJ},
+  Timestamp                = {2019-05-30}
+}
+
+@InProceedings{kha_17,
+  Title                    = {{E}nergy-efficient {H}uman {A}ctivity {R}ecognition for {S}elf-powered {W}earable {D}evices},
+  Author                   = {Khalifa, Sara},
+  Booktitle                = {Proceedings of the Australasian Computer Science Week Multiconference},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {78:1--78:2},
+  Publisher                = {ACM},
+  Series                   = {ACSW '17},
+
+  Acmid                    = {3018840},
+  Articleno                = {78},
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Khalifa:2017:EHA:3014812.3018840},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3014812.3018840},
+  ISBN                     = {978-1-4503-4768-6},
+  Keywords                 = {TCS},
+  Keywords_original        = {accelerometer, human activity recognition, kinetic energy harvesting, self-powered wearables},
+  Location                 = {Geelong, Australia},
+  Numpages                 = {2},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/3014812.3018840}
+}
+
+@InProceedings{khakun_09,
+  Title                    = {{A} self-adaptive system architecture to address transistor aging},
+  Author                   = {Khan, Omer and Kundu, Sandip},
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conference \& Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {81--86},
+
+  File                     = {khakun_09.pdf:khakun_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.01}
+}
+
+@InProceedings{khalee_14,
+  Title                    = {{T}he {E}fficacy of {E}rror {M}itigation {T}echniques for {DRAM} {R}etention {F}ailures: {A} {C}omparative {E}xperimental {S}tudy},
+  Author                   = {Khan, Samira and Lee, Donghyuk and Kim, Yoongu and Alameldeen, Alaa R. and Wilkerson, Chris and Mutlu, Onur},
+  Booktitle                = {The 2014 ACM International Conference on Measurement and Modeling of Computer Systems},
+  Year                     = {2014},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {519--532},
+  Publisher                = {ACM},
+  Series                   = {SIGMETRICS '14},
+
+  Acmid                    = {2592000},
+  Doi                      = {10.1145/2591971.2592000},
+  ISBN                     = {978-1-4503-2789-3},
+  Keywords                 = {dram, ecc, error correction, fault tolerance, memory scaling, retention failures, system-level detection and mitigation},
+  Location                 = {Austin, Texas, USA},
+  Numpages                 = {14},
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-08},
+  Url                      = {http://doi.acm.org/10.1145/2591971.2592000}
+}
+
+@PhdThesis{Phdkhand02,
+  Title                    = {{Graph-based Codes and Iterative Decoding}},
+  Author                   = {A. Khandekar},
+  School                   = {California Institute of Technology},
+  Year                     = {2002},
+
+  Address                  = {Pasadena, California, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{khuzam_16,
+  Title                    = {{Q}uality {C}ontrol for {A}pproximate {A}ccelerators by {E}rror {P}rediction},
+  Author                   = {Khudia, D. S. and Zamirai, B. and Samadi, M. and Mahlke, S.},
+  Journal                  = {IEEE Design \& Test},
+  Year                     = {2016},
+
+  Month                    = {February},
+  Number                   = {1},
+  Pages                    = {43-50},
+  Volume                   = {33},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-05}
+}
+
+@PhdThesis{Phdkhusa18,
+  Title                    = {{C}o-design of {FPGA} {I}mplementations for {M}odel {P}redictive {C}ontrol},
+  Author                   = {Bulat Khusainov},
+  School                   = {Imperial College London},
+  Year                     = {2018},
+  Type                     = {dissertation},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {HETEROGENEOUS PLATFORMS; cite number in presentation [59]},
+  Ccr_topic                = {NetControl Paper},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR},
+  Url                      = {https://spiral.imperial.ac.uk/bitstream/10044/1/58953/1/Khusainov-B-2018-PhD-Thesis.pdf}
+}
+
+@Article{khuker_18,
+  Title                    = {{N}onlinear predictive control on a heterogeneous computing platform},
+  Author                   = {Bulat Khusainov and Eric Kerrigan and Andrea Suardi and George Constantinides},
+  Journal                  = {Control Engineering Practice},
+  Year                     = {2018},
+  Pages                    = {105 - 115},
+  Volume                   = {78},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {HETEROGENEOUS PLATFORMS; cite number in presentation [38]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {https://doi.org/10.1016/j.conengprac.2018.06.016},
+  ISSN                     = {0967-0661},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {Predictive control, Hardware–software co-design, Scheduling, {FPGA}, Optimization-based control},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0967066118301977}
+}
+
+@PhdThesis{Phdkienl14,
+  Title                    = {{A}rchitectures for {B}aseband {S}ignal {P}rocessing},
+  Author                   = {Frank Kienle},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+  Type                     = {Habilitation},
+
+  Owner                    = {Schläfer},
+  Timestamp                = {2014.07.23}
+}
+
+@InProceedings{kie_09,
+  Title                    = {{O}n {L}ow-{D}ensity {MIMO} {C}odes},
+  Author                   = {Kienle, F.},
+  Booktitle                = {Proc. IEEE International Conference on Communications ICC '09},
+  Year                     = {2009},
+  Month                    = jun,
+  Pages                    = {1--6},
+
+  Doi                      = {10.1109/ICC.2009.5199242},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.08.12}
+}
+
+@InProceedings{kie_08,
+  Title                    = {{Low-Density MIMO Codes}},
+  Author                   = {F. Kienle},
+  Booktitle                = {Proc. 5th International Symposium on Turbo Codes and Related Topics},
+  Year                     = {2008},
+
+  Address                  = {Lausanne, Switzerland},
+  Month                    = sep,
+  Pages                    = {107--112},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{Phdkienl06,
+  Title                    = {{Implementation Issues of Low-Density Parity-Check Decoders}},
+  Author                   = {F. Kienle},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2006},
+  Note                     = {ISBN 978-3-939432-06-7},
+
+  Cds_grade                = {0},
+  Date-added               = {2008-10-15 09:36:04 +0200},
+  Date-modified            = {2008-10-15 09:37:54 +0200},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InBook{kie_11,
+  Title                    = {{E}rror {C}ontrol {C}oding for {B}3{G}/4{G} {W}ireless {S}ystems},
+  Author                   = {Frank Kienle and Torben Brack and Timo Vogt},
+  Chapter                  = {Architecture and Hardware Requirements for Turbo and LDPC decoders},
+  Pages                    = {113--188},
+  Publisher                = {WILEY},
+  Year                     = {2011},
+
+  ISBN                     = {0471648000},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.07.07}
+}
+
+@InProceedings{kiebra_06,
+  Title                    = {{Design of Irregular LDPC Codes for Flexible Encoder and Decoder Hardware Realizations}},
+  Author                   = {F. Kienle and T. Brack and N. Wehn},
+  Booktitle                = {Proc. International Conference on Software in Telecommunications and Computer Networks SoftCOM 2006},
+  Year                     = {2006},
+
+  Address                  = {Dubrovnik, Croatia},
+  Month                    = oct,
+  Pages                    = {296--300},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{kiemethods06,
+  Title                    = {{Methods and device for decoding LDPC encoded codewords with a fast convergence speed}},
+
+  Author                   = {F. Kienle and T. Brack and N. Wehn},
+  HowPublished             = {European Patent Application No.06006521.6},
+  Year                     = {2006},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Kienle2006b,
+  Title                    = {{Methods and device for decoding LDPC encoded codewords with a fast convergence speed}},
+
+  Author                   = {F. Kienle and T. Brack and N. Wehn},
+  HowPublished             = {European Patent Application No.06006521.6},
+  Year                     = {2006},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kiebra_05,
+  Title                    = {{A} {S}ynthesizable {IP} {C}ore for {DVB}-{S}2 {LDPC} {C}ode {D}ecoding},
+  Author                   = {F. Kienle and T. Brack and N. Wehn},
+  Booktitle                = {Proc. Design, Automation and Test in Europe},
+  Year                     = {2005},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+  Pages                    = {1530--1535},
+
+  File                     = {kiebra_05.pdf:kiebra_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kiegim_10,
+  Title                    = {{S}pace-time bit trellis codes},
+  Author                   = {Kienle, F. and Gimmler, C.},
+  Booktitle                = {Proc. Int Source and Channel Coding (SCC) ITG Conf},
+  Year                     = {2010},
+  Pages                    = {1--6},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.05.16}
+}
+
+@InProceedings{kiekre_03,
+  Title                    = {{VLSI}-{I}mplementation {I}ssues of {T}urbo {T}rellis-{C}oded {M}odulation},
+  Author                   = {F. Kienle and G. Kreiselmaier and N. Wehn},
+  Booktitle                = {Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '03)},
+  Year                     = {2003},
+
+  Address                  = {Hong Kong, P.R.China},
+  Month                    = apr,
+  Pages                    = {633--636},
+
+  File                     = {kiekre_03.pdf:kiekre_03.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Kienle2006c,
+  Title                    = {{T}urbo-{C}odes vs. {LDPC} {C}odes ({I}nvited {T}alk)},
+
+  Author                   = {F. Kienle and T. Lehnigk-Emden and T. Brack and M. Alles and T. Vogt and N. Wehn},
+  HowPublished             = {Workshop on VLSI-Architectures for LDPC Decoders, Pisa, Italy
+{{http://vlsi.iet.unipi.it/~ldpcatwork/}}},
+  Month                    = oct,
+  Year                     = {2006},
+
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.06}
+}
+
+@Misc{kieturbo-codes06,
+  Title                    = {{T}urbo-{C}odes vs. {LDPC} {C}odes ({I}nvited {T}alk)},
+
+  Author                   = {F. Kienle and T. Lehnigk-Emden and T. Brack and M. Alles and T. Vogt and N. Wehn},
+  HowPublished             = {Workshop on VLSI-Architectures for LDPC Decoders, Pisa, Italy
+{{http://vlsi.iet.unipi.it/~ldpcatwork/}}},
+  Month                    = oct,
+  Year                     = {2006},
+
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.06}
+}
+
+@InProceedings{kieweh_06,
+  Title                    = {{F}ast convergence algorithm for {LDPC} {C}odes},
+  Author                   = {F. Kienle and T. Lehnigk-Emden and N. Wehn},
+  Booktitle                = {Proc. VTC 2006-Spring Vehicular Technology Conference IEEE 63rd},
+  Year                     = {2006},
+
+  Address                  = {Melbourne, Australia},
+  Month                    = may # { 7--10,},
+  Pages                    = {2393--2397},
+  Volume                   = {5},
+
+  File                     = {kieweh_06.pdf:kieweh_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kiemic_02,
+  Title                    = {{Efficient MAP-Algorithm Implementation on Programmable Architectures}},
+  Author                   = {F. Kienle and H. Michel and F. Gilbert and N. Wehn},
+  Booktitle                = {Advances in Radio Science},
+  Year                     = {2002},
+
+  Address                  = {Miltenberg, Germany},
+  Month                    = oct,
+  Pages                    = {259--263},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{kiesch_12,
+  Title                    = {100\% {G}reen {C}omputing {A}t {T}he {W}rong {L}ocation?},
+  Author                   = {Frank Kienle and Christian de Schryver},
+  Institution              = {University of Kaiserslautern},
+  Year                     = {2012},
+  Month                    = oct,
+  Note                     = {Submission to IEC-IEEE Challenge 2012: How does electrotechnology impact economic, social and environmental development?},
+
+  Abstract                 = {Modern society relies on convenience services and mobile communication. Cloud computing is the current trend to make data and applications available at any time on every device. Data centers concentrate computation and storage at central locations, while they claim themselves green due to their optimized maintenance and increased energy efficiency. The key enabler for this evolution is the microelectronics industry. The trend to power efficient mobile devices has forced this industry to change its design dogma to: ”keep data locally and reduce data communication whenever possible”. Therefore we ask: is cloud computing repeating the aberrations of its enabling industry?},
+  Cds_grade                = {5},
+  Cds_keywords             = {Embedded Systems; Energy Efficiency; Green Computing; High-Performance Computing (HPC); Low-Power, Cloud Computing; Eingebettetes System; Embedded System; Energieffizienz; Green-IT; Hochleistungsrechnen; Smart Grid; Supercomputer; Topologie},
+  Cds_read                 = {2012-10},
+  File                     = {kiesch_12.pdf:kiesch_12.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2013.03.06},
+  Url                      = {http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:hbz:386-kluedo-33241}
+}
+
+@InProceedings{kiethu_03,
+  Title                    = {{Implementation Issues of Scalable LDPC Decoders}},
+  Author                   = {F. Kienle and M. J. Thul and N. Wehn},
+  Booktitle                = {Proc. 3rd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {291--294},
+
+  File                     = {kiethu_03.pdf:kiethu_03.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kieweh_08,
+  Title                    = {{Macro Interleaver Design for Bit Interleaved Coded Modulation with Low-Density Parity-Check Codes}},
+  Author                   = {F. Kienle and N. Wehn},
+  Booktitle                = {Proc. IEEE Vehicular Technology Conference VTC Spring 2008},
+  Year                     = {2008},
+
+  Address                  = {Singapore, Singapore},
+  Month                    = may,
+  Pages                    = {763 -- 766},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.31}
+}
+
+@InProceedings{kieweh_05,
+  Title                    = {{Low Complexity Stopping Criterion for LDPC Code Decoders}},
+  Author                   = {F. Kienle and N. Wehn},
+  Booktitle                = {Proc. VTC 2005-Spring Vehicular Technology Conference 2005 IEEE 61st},
+  Year                     = {2005},
+
+  Address                  = {Stockholm, Schweden},
+  Month                    = may,
+  Pages                    = {606--609},
+
+  File                     = {kieweh_05.pdf:kieweh_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kieweh_04,
+  Title                    = {{E}fficient {H}ardware {R}ealization of {IRA} {C}ode {D}ecoders},
+  Author                   = {F. Kienle and N. Wehn},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems SIPS 2004},
+  Year                     = {2004},
+
+  Address                  = {Austin,USA},
+  Month                    = oct,
+  Pages                    = {286--291},
+
+  File                     = {kieweh_04.pdf:kieweh_04.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kieweh_04a,
+  Title                    = {{Joint Graph-Decoder Design of IRA-Codes on Scalable Architectures}},
+  Author                   = {F. Kienle and N. Wehn},
+  Booktitle                = {Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '04)},
+  Year                     = {2004},
+
+  Address                  = {Montreal, Canada},
+  Month                    = may,
+  Pages                    = {IV-673--676},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kieweh_04b,
+  Title                    = {{D}esign {M}ethodology for {IRA} {C}odes},
+  Author                   = {F. Kienle and N. Wehn},
+  Booktitle                = {Proc. Asia and South Pacific Design Automation Conference the ASP-DAC 2004},
+  Year                     = {2004},
+
+  Address                  = {Yokohama, Japan},
+  Month                    = jan,
+  Pages                    = {459--462},
+
+  File                     = {kieweh_04b.pdf:kieweh_04b.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{kieweh_11,
+  Title                    = {{O}n {C}omplexity, {E}nergy- and {I}mplementation-{E}fficiency of {C}hannel {D}ecoders},
+  Author                   = {Kienle, F. and Wehn, N. and Meyr, H.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2011},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {3301--3310},
+  Volume                   = {59},
+
+  Abstract                 = {Future wireless communication systems require efficient and flexible baseband receivers. Meaningful efficiency metrics are key for design space exploration to quantify the algorithmic and the implementation complexity of a receiver. Most of the current established efficiency metrics are based on counting operations, thus neglecting important issues like data and storage complexity. In this paper we introduce suitable energy and area efficiency metrics which resolve the afore-mentioned disadvantages. These are decoded information bit per energy and throughput per area unit. Efficiency metrics are assessed by various implementations of turbo decoders, LDPC decoders and convolutional decoders. An exploration approach is presented, which permit an appropriate benchmarking of implementation efficiency, communications performance, and flexibility trade-offs. Two case studies demonstrate this approach and show that design space exploration should result in various efficiency evaluations rather than a single snapshot metric as done often in state-of-the-art approaches.},
+  Doi                      = {10.1109/TCOMM.2011.092011.100157},
+  File                     = {kieweh_11.pdf:kieweh_11.pdf:PDF},
+  ISSN                     = {0090-6778}
+}
+
+@InProceedings{kimkwo_00,
+  Title                    = {{A modified Two-Step SOVA-based Turbo Decoder with a fixed Scaling Factor}},
+  Author                   = {D. W. Kim and T. W. Kwon and J. R. Choi and J. J. Kong},
+  Booktitle                = {{Proc. 2000 International Symposium on Circuits and Systems (ISCAS '00)}},
+  Year                     = {2000},
+
+  Address                  = {Geneva, Switzerland},
+  Month                    = may,
+  Pages                    = {37--40},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kimsha_12,
+  Title                    = {{E}nergy-{E}fficient {LDPC} {D}ecoders {B}ased on {E}rror-{R}esiliency},
+  Author                   = {Kim, E.P. and Shanbhag, N.R.},
+  Booktitle                = {Signal Processing Systems (SiPS), 2012 IEEE Workshop on},
+  Year                     = {2012},
+  Pages                    = {149-154},
+
+  Doi                      = {10.1109/SiPS.2012.60},
+  ISSN                     = {2162-3562},
+  Keywords                 = {circuit simulation;error compensation;error statistics;iterative methods;parity check codes;BER;circuit simulations;communication standards;energy-efficient LDPC decoders;error-resiliency;iterations/block;low density parity check codes;sign bit protected LDPC decoder;size 45 nm;statistical error compensation;Bit error rate;Decoding;Delay;Parity check codes;Signal to noise ratio;Wires;Error resiliency;LDPC;low power},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@Article{kimcho_15,
+  Title                    = {{D}istributed {CRC} {A}rchitecture for {H}igh-{R}adix {P}arallel {T}urbo {D}ecoding in {LTE}-{A}dvanced {S}ystems},
+  Author                   = {Hyeji Kim and Injun Choi and Wooseok Byun and Jong-Yeol Lee and Ji-Hoon Kim},
+  Journal                  = {Circuits and Systems II: Express Briefs, IEEE Transactions on},
+  Year                     = {2015},
+
+  Month                    = {Sept},
+  Number                   = {9},
+  Pages                    = {906-910},
+  Volume                   = {62},
+
+  Doi                      = {10.1109/TCSII.2015.2435131},
+  File                     = {kimcho_15.pdf:kimcho_15.pdf:PDF},
+  ISSN                     = {1549-7747},
+  Keywords                 = {CMOS integrated circuits;Long Term Evolution;decode and forward communication;turbo codes;CMOS process;Galois field arithmetic;LTE-advanced systems;LTE/LTE-advanced communication systems;SISO decoding process;distributed CRC architecture;distributed cyclic redundancy check architecture;high radix parallel turbo decoding;high-radix SISO decoder;soft-input soft-output decoding process;Clocks;Computer architecture;Decoding;Energy consumption;Galois fields;Long Term Evolution;Parallel processing;Distributed cyclic redundancy check (CRC);Galois fields;early stopping criteria;parallel turbo decoder},
+  Owner                    = {StW},
+  Timestamp                = {2015.12.08}
+}
+
+@InProceedings{kimkim_13,
+  Title                    = {{D}esign of early stopping unit in parallel turbo decoder based on galois field operation},
+  Author                   = {Hyeji Kim and Ji-Hoon Kim},
+  Booktitle                = {SoC Design Conference (ISOCC), 2013 International},
+  Year                     = {2013},
+  Month                    = {Nov},
+  Pages                    = {050-051},
+
+  Doi                      = {10.1109/ISOCC.2013.6863983},
+  File                     = {kimkim_13.pdf:kimkim_13.pdf:PDF},
+  Keywords                 = {Galois fields;Long Term Evolution;cyclic redundancy check codes;decoding;turbo codes;CRC based stopping criterion;GF operations;Galois field operation;LTE-LTE-Advanced systems;cyclic redundancy check;early stopping unit design;multiple SISO decoders;next generation mobile communication systems;parallel CRC architecture;parallel turbo decoder;soft-input soft-output decoders;timing overhead;Decoding;Galois fields;Hardware;Iterative decoding;Long Term Evolution;Polynomials;Timing;GF multiplication and addition;parallel CRC;parallel turbo decoder;stopping criteria},
+  Owner                    = {StW},
+  Timestamp                = {2015.12.08}
+}
+
+@Article{kimlee_15,
+  Title                    = {{L}ow-complexity {CRC}-aided early stopping unit for parallel turbo decoder},
+  Author                   = {H. Kim and Y. Lee and J. H. Kim},
+  Journal                  = {Electronics Letters},
+  Year                     = {2015},
+  Number                   = {21},
+  Pages                    = {1660-1662},
+  Volume                   = {51},
+
+  Doi                      = {10.1049/el.2015.2262},
+  File                     = {kimlee_15.pdf:kimlee_15.pdf:PDF},
+  ISSN                     = {0013-5194},
+  Keywords                 = {CMOS integrated circuits;Galois fields;Long Term Evolution;cyclic redundancy check codes;shift registers;turbo codes;CMOS process;LTE-advanced;general high-order Galois field multiplier;linear feedback shift register;low-complexity CRC-aided early stopping unit;low-complexity distributed cyclic redundancy check architecture;optimal CRC unit;parallel turbo decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.13}
+}
+
+@Article{kimoh_11a,
+  Title                    = {{C}haracterization of the {V}ariable {R}etention {T}ime in {D}ynamic {R}andom {A}ccess {M}emory},
+  Author                   = {H. Kim and B. Oh and Y. Son and K. Kim and S. Y. Cha and J. G. Jeong and S. J. Hong and H. Shin},
+  Journal                  = {IEEE Transactions on Electron Devices},
+  Year                     = {2011},
+
+  Month                    = {Sept},
+  Number                   = {9},
+  Pages                    = {2952-2958},
+  Volume                   = {58},
+
+  Doi                      = {10.1109/TED.2011.2160066},
+  ISSN                     = {0018-9383},
+  Keywords                 = {leakage currents;random-access storage;dynamic random access memory;leakage current fluctuation;variable retention time;Current measurement;Leakage current;Logic gates;Random access memory;Semiconductor device measurement;Temperature measurement;Time measurement;Dynamic random access memory (DRAM);gate-induced drain leakage (GIDL);leakage current;location of trap;random telegraph noise (RTN);variable retention time (VRT)},
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-14}
+}
+
+@InProceedings{kimvij_03,
+  Title                    = {{E}stimating influence of data layout optimizations on {SDRAM} energy consumption},
+  Author                   = {H. S. Kim and N. Vijaykrishnan and M. Kandemir and E. Brockmeyer and F. Catthoor and M. J. Irwin},
+  Booktitle                = {Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on},
+  Year                     = {2003},
+  Month                    = {Aug},
+  Pages                    = {40-43},
+
+  Doi                      = {10.1109/LPE.2003.1231832},
+  Keywords                 = {low-power electronics;optimisation;optimising compilers;paged storage;random-access storage;storage management;Ehrhart polynomials;Presburger arithmetic;SDRAM energy consumption;compile time estimation;data layout influence;data layout optimization;data page switching;memory access efficiency;memory latency;page granularity data locality;static page break estimation;video codes;Arithmetic;Bandwidth;Computer science;Data engineering;Delay;Energy consumption;Permission;Polynomials;Power engineering and energy;SDRAM},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11}
+}
+
+@InProceedings{kimhar_07,
+  Title                    = {{M}ulti-bit {E}rror {T}olerant {C}aches {U}sing {T}wo-{D}imensional {E}rror {C}oding},
+  Author                   = {Jangwoo Kim and Hardavellas, N. and Ken Mai and Falsafi, B. and Hoe, J. C. },
+  Booktitle                = {Proc. 40th Annual IEEE/ACM International Symposium on Microarchitecture MICRO 2007},
+  Year                     = {2007},
+  Month                    = dec,
+  Pages                    = {197--209},
+
+  Doi                      = {10.1109/MICRO.2007.19},
+  File                     = {kimhar_07.pdf:kimhar_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.23}
+}
+
+@InProceedings{kimpar_09,
+  Title                    = {{A} unified parallel radix-4 turbo decoder for mobile {W}i{MAX} and 3{GPP}-{LTE}},
+  Author                   = {Kim, Ji-Hoon and Park, In-Cheol},
+  Booktitle                = {Proc. IEEE Custom Integrated Circuits Conference CICC '09},
+  Year                     = {2009},
+  Month                    = sep,
+  Pages                    = {487--490},
+
+  Doi                      = {10.1109/CICC.2009.5280790},
+  File                     = {kimpar_09.pdf:kimpar_09.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.10.27}
+}
+
+@Article{kimpar_08,
+  Title                    = {{D}ouble-{B}inary {C}ircular {T}urbo {D}ecoding {B}ased on {B}order {M}etric {E}ncoding},
+  Author                   = {Ji-Hoon Kim and In-Cheol Park},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2008},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {79--83},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCSII.2007.907803},
+  File                     = {kimpar_08.pdf:kimpar_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.10.29}
+}
+
+@InProceedings{kimpar_07,
+  Title                    = {{E}nergy-{E}fficient {D}ouble-{B}inary {T}ail-{B}iting {T}urbo {D}ecoder {B}ased on {B}order {M}etric {E}ncoding},
+  Author                   = {Ji-Hoon Kim and In-Cheol Park},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2007},
+  Year                     = {2007},
+  Month                    = may,
+  Pages                    = {1325--1328},
+
+  Doi                      = {10.1109/ISCAS.2007.378416},
+  File                     = {kimpar_07.pdf:kimpar_07.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{kimoh_11,
+  Title                    = {{A} 1.2{V} 12.8{GB}/s 2{G}b mobile {W}ide-{I}/{O} {DRAM} with 4x128 {I}/{O}s using {TSV}-based stacking},
+  Author                   = {Jung-Sik Kim and Chi Sung Oh and Hocheol Lee and Donghyuk Lee and Hyong-Ryol Hwang and Sooman Hwang and Byongwook Na and Joungwook Moon and Jin-Guk Kim and Hanna Park and Jang-Woo Ryu and Kiwon Park and Sang-Kyu Kang and So-Young Kim and Hoyoung Kim and Jong-Min Bang and Hyunyoon Cho and Minsoo Jang and Cheolmin Han and Jung-Bae Lee and Kyehyun Kyung and Joo-Sun Choi and Young-Hyun Jun},
+  Booktitle                = {Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International},
+  Year                     = {2011},
+  Month                    = {Feb},
+  Pages                    = {496-498},
+
+  Doi                      = {10.1109/ISSCC.2011.5746413},
+  ISSN                     = {0193-6530},
+  Keywords                 = {DRAM chips;low-power electronics;three-dimensional integrated circuits;TSV-based stacking;byte rate 12.8 GByte/s;low power consumption;mobile wide-I/O DRAM;portable electronic devices;single data rate;storage capacity 1 Gbit;storage capacity 2 Gbit;voltage 1.2 V;wide-I/O mobile SDRAM;Arrays;Clocks;Mobile communication;Pins;Random access memory;Registers;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2015.04.13}
+}
+
+@Article{kimlee_09,
+  Title                    = {{A} {N}ew {I}nvestigation of {D}ata {R}etention {T}ime in {T}ruly {N}anoscaled {DRAM}s},
+  Author                   = {Kim, Kinam and Jooyoung Lee},
+  Journal                  = {Electron Device Letters, IEEE},
+  Year                     = {2009},
+
+  Month                    = {Aug},
+  Number                   = {8},
+  Pages                    = {846-848},
+  Volume                   = {30},
+
+  Doi                      = {10.1109/LED.2009.2023248},
+  ISSN                     = {0741-3106},
+  Keywords                 = {DRAM chips;leakage currents;nanoelectronics;data retention time;full chip retention failure curve;gate-induced drain leakage current;interface trap density;nanoscaled DRAM;scaled-down cell size;trap energy dispersion;DRAM;Data retention time;gate-induced drain leakage (GIDL) currents;recess channel array transistor (RCAT);trap-assisted tunneling (TAT)},
+  Owner                    = {MJ},
+  Timestamp                = {2015.10.28}
+}
+
+@Article{kimkwa_06,
+  Title                    = {{G}eneral {L}og-{L}ikelihood {R}atio {E}xpression and its {I}mplementation {A}lgorithm for {G}ray-{C}oded {QAM} {S}ignals},
+  Author                   = {Ki Seol Kim and Kwangmin Hyun and Chang Wahn Yu and Youn Ok Park and Dongweon Yoon and Sang Kyu Park},
+  Journal                  = {ETRI Journal},
+  Year                     = {2006},
+
+  Month                    = {June},
+  Number                   = {3},
+  Pages                    = {291-300},
+  Volume                   = {28},
+
+  Owner                    = {Imran},
+  Timestamp                = {2014.11.05}
+}
+
+@InProceedings{kimhyu_00,
+  Title                    = {{C}oupling-driven signal encoding scheme for low-power interface design},
+  Author                   = {Ki-Wook Kim and Kwang-Hyun-Baek and Shanbhag, N. and Liu, C.L. and Sung-Mo Kang},
+  Booktitle                = {Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on},
+  Year                     = {2000},
+  Month                    = nov,
+  Pages                    = {318--321},
+
+  Doi                      = {10.1109/ICCAD.2000.896492},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@InProceedings{kimlee_18,
+  Title                    = {{A}n analysis of energy consumption under various memory mappings for {FRAM}-based {I}o{T} devices},
+  Author                   = {M. {Kim} and J. {Lee} and Y. {Kim} and Y. H. {Song}},
+  Booktitle                = {2018 IEEE 4th World Forum on Internet of Things (WF-IoT)},
+  Year                     = {2018},
+  Month                    = {Feb},
+  Pages                    = {574-579},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {good},
+  Ccr_key_original         = {8355212},
+  Ccr_keywords             = {Energy consumption wrt general memory mapping},
+  Ccr_relevance            = {medium},
+  Ccr_topic                = {ATC, CP},
+  Doi                      = {10.1109/WF-IoT.2018.8355212},
+  Keywords                 = {TCS},
+  Keywords_original        = {embedded systems;energy harvesting;ferroelectric storage;Internet of Things;random-access storage;telecommunication power management;independent power supply;energy consumption pattern;low-power mode;proper memory mapping;battery;energy harvesters;power failure problems;energy savings;Internet of Things devices;average IoT device energy consumption;FRAM-based embedded device;FRAM-based IoT devices;Task analysis;Random access memory;Energy consumption;Nonvolatile memory;Memory management;Ferroelectric films;Batteries;IoT;Non-volatile memory;FRAM;Memory mapping;Low-power consumption;Real time operating system},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27}
+}
+
+@InProceedings{kimoh_12,
+  Title                    = {{L}ow complexity carrier phase recovery for {DVB}-{RCS}2 standard},
+  Author                   = {Pansoo Kim and Deock-Gil Oh},
+  Booktitle                = {International Conference on ICT Convergence (ICTC), 2012},
+  Year                     = {2012},
+  Month                    = {Oct},
+  Pages                    = {607-609},
+
+  Doi                      = {10.1109/ICTC.2012.6387123},
+  Keywords                 = {digital video broadcasting;modulation;phase noise;satellite ground stations;CPM modulation;DVB-RCS2 standard;Ku/Ka band;linear modulation;low complexity carrier phase recovery;next generation satellite VSAT;phase noise effect;very small aperture terminal system;Digital video broadcasting;Iterative decoding;Phase modulation;Phase noise;Standards;CPM;DVB-RCS;Linear modulation;Phase noise;VSAT},
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-07}
+}
+
+@Conference{Kim2005,
+  Title                    = {{E}nhanced {D}emodulator {I}mplementation for {M}obile {S}atellite {I}nternet {S}ystems},
+  Author                   = {P. Kim and Y. Song and B. Kim and D. Oh and H. Lee},
+  Booktitle                = {14th IST Mobile and Wireless Communications Summit},
+  Year                     = {2005},
+
+  Address                  = {Dresden, Germany},
+  Month                    = {June},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27}
+}
+
+@InProceedings{kimlee_12,
+  Title                    = {{S}elector devices for cross-point {R}e{RAM}},
+  Author                   = {S. Kim and W. Lee and H. Hwang},
+  Booktitle                = {2012 13th International Workshop on Cellular Nanoscale Networks and their Applications},
+  Year                     = {2012},
+  Month                    = {Aug},
+  Pages                    = {1-2},
+
+  Doi                      = {10.1109/CNNA.2012.6331466},
+  ISSN                     = {2165-0152},
+  Keywords                 = {current density;electronic switching systems;memory architecture;niobium compounds;random-access storage;thermal stability;varistors;cross-point ReRAM;varistor-type bidirectional selector device;ultrathin NbO2device;threshold switching characteristics;TS characteristics;nonlinear VBS;current density;selectivity;temperature stability;switching uniformity;scalability;recently-resistive switching memory;NbO2;Switches;Thermal stability;Scalability;Films;Temperature;Temperature measurement;Current density;selector;cross-point memroy;varistor;threshold switching;selectivity},
+  Timestamp                = {2018-08-29}
+}
+
+@InProceedings{Kim2003,
+  Title                    = {{B}lock {T}urbo {C}odes {U}sing {M}ultiple {S}oft {O}utputs},
+  Author                   = {Kim, S. and Ryoo, S. and Lee, S.},
+  Booktitle                = {Proceedings of the 3rd ISTC},
+  Year                     = {2003},
+
+  Address                  = {Brest},
+  Pages                    = {247-250},
+  Volume                   = {1},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2013.12.12}
+}
+
+@InProceedings{kimsob_08,
+  Title                    = {{F}lexible {LDPC} {D}ecoder {A}rchitecture for {H}igh-{T}hroughput {A}pplications},
+  Author                   = {Kim, Sangmin and Sobelman, Gerald E. and Lee, Hanho},
+  Booktitle                = {Proc. IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008},
+  Year                     = {2008},
+  Month                    = nov,
+  Pages                    = {45--48},
+
+  Doi                      = {10.1109/APCCAS.2008.4745956},
+  File                     = {kimsob_08.pdf:kimsob_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.01.29}
+}
+
+@InProceedings{kimsob_02,
+  Title                    = {{Parallel VLSI Architectures for a Class of LDPC Codes}},
+  Author                   = {S. Kim and G. E. Sobelman and J. Moon},
+  Booktitle                = {Proc. 2002 IEEE International Symposium on Circuits and Systems (ISCAS '02)},
+  Year                     = {2002},
+
+  Address                  = {Phoenix, Arizona, USA},
+  Month                    = may,
+  Pages                    = {93--96},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kimtan_05,
+  Title                    = {{Quasi-Cyclic Low-Density Parity-Check Coded Multiband-OFDM UWB Systems}},
+  Author                   = {Sang-Min Kim and Jun Tang and Keshab K. Parhi},
+  Booktitle                = {IEEE International Symposium on Circuits and Systems},
+  Year                     = {2005},
+  Month                    = may,
+  Pages                    = {65-68},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kimdal_14,
+  Title                    = {{F}lipping bits in memory without accessing them: {A}n experimental study of {DRAM} disturbance errors},
+  Author                   = {Yoongu Kim and R. Daly and J. H. Kim and C. Fallin and Ji Hye Lee and Donghyuk Lee and C. Wilkerson and K. Lai and O. Mutlu},
+  Booktitle                = {ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)},
+  Year                     = {2014},
+  Month                    = {June},
+  Pages                    = {361-372},
+
+  Doi                      = {10.1109/ISCA.2014.6853210},
+  Keywords                 = {DRAM chips;field programmable gate arrays;AMD systems;DRAM accesses;DRAM cells;DRAM chips;DRAM disturbance errors;DRAM modules;DRAM process technology;FPGA-based testing platform;Intel;charge leakage;intercell coupling effects;malicious program;memory address;memory bit flipping;memory isolation;reliable computing system;secure computing system;Acceleration;Artificial intelligence;DRAM chips;Organizations;Testing;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-18}
+}
+
+@InProceedings{kimhan_10,
+  Title                    = {{ATLAS}: {A} scalable and high-performance scheduling algorithm for multiple memory controllers},
+  Author                   = {Y. Kim and D. Han and O. Mutlu and M. Harchol-Balter},
+  Booktitle                = {HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture},
+  Year                     = {2010},
+  Month                    = {Jan},
+  Pages                    = {1-12},
+
+  Doi                      = {10.1109/HPCA.2010.5416658},
+  ISSN                     = {1530-0897},
+  Keywords                 = {Pareto distribution;digital storage;microprocessor chips;multiprocessing systems;scheduling;ATLAS memory scheduling;Pareto workload distribution;adaptive per-thread least-attained-service;chip multiprocessor;multiple memory controllers;multiprogrammed SPEC 2006 workloads;scheduling algorithm;single-server queue;Adaptive control;Algorithm design and analysis;Bandwidth;Control systems;Feeds;Programmable control;Queueing analysis;Scheduling algorithm;Throughput;Yarn},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-02}
+}
+
+@InProceedings{kimpap_10,
+  Title                    = {{T}hread {C}luster {M}emory {S}cheduling: {E}xploiting {D}ifferences in {M}emory {A}ccess {B}ehavior},
+  Author                   = {Kim, Yoongu and Papamichael, Michael and Mutlu, Onur and Harchol-Balter, Mor},
+  Booktitle                = {Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture},
+  Year                     = {2010},
+
+  Address                  = {Washington, DC, USA},
+  Pages                    = {65--76},
+  Publisher                = {IEEE Computer Society},
+  Series                   = {MICRO '43},
+
+  Acmid                    = {1935012},
+  Doi                      = {10.1109/MICRO.2010.51},
+  ISBN                     = {978-0-7695-4299-7},
+  Keywords                 = {memory scheduling, memory access behavior, fairness, system throughput, thread cluster, niceness},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-02},
+  Url                      = {http://dx.doi.org/10.1109/MICRO.2010.51}
+}
+
+@Article{kimyan_15,
+  Title                    = {{R}amulator: {A} {F}ast and {E}xtensible {DRAM} {S}imulator},
+  Author                   = {Kim, Yoongu and Yang, Weikun and Mutlu, Onur},
+  Journal                  = {IEEE Computer Architecture Letters},
+  Year                     = {2015},
+  Number                   = {99},
+  Pages                    = {1-1},
+  Volume                   = {PP},
+
+  Doi                      = {10.1109/LCA.2015.2414456},
+  ISSN                     = {1556-6056},
+  Keywords                 = {Hardware design languages;Nonvolatile memory;Proposals;Random access memory;Runtime;Standards;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2016-05-17}
+}
+
+@Article{kimnem_05,
+  Title                    = {{S}pace radiation environment and its effects on satellites: analysis of the first data from {TEDA} on board {ADEOS}-{II}},
+  Author                   = {Kimoto, Y. and Nemoto, N. and Matsumoto, H. and Ueno, K. and Goka, T. and Omodaka, T.},
+  Journal                  = {IEEE Transactions on Nuclear Science},
+  Year                     = {2005},
+
+  Month                    = oct,
+  Number                   = {5},
+  Pages                    = {1574--1578},
+  Volume                   = {52},
+
+  Doi                      = {10.1109/TNS.2005.855822},
+  File                     = {kimnem_05.pdf:kimnem_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Part                     = {2},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{kinmon_77,
+  Title                    = {{C}omputer {G}eneration of {R}andom {V}ariables {U}sing the {R}atio of {U}niform {D}eviates},
+  Author                   = {Kinderman, AJ and Monahan, J.F.},
+  Journal                  = {ACM Transactions on Mathematical Software (TOMS)},
+  Year                     = {1977},
+  Number                   = {3},
+  Pages                    = {257--260},
+  Volume                   = {3},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation},
+  File                     = {kinmon_77.pdf:kinmon_77.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2012.03.22}
+}
+
+@Book{kirw._13,
+  Title                    = {{P}rogramming {M}assively {P}arallel {P}rocessors},
+  Author                   = {David Kirk and {Wen-mei} W. Hwu},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2013},
+  Edition                  = {2nd},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.05.27}
+}
+
+@Article{kirgel_83,
+  Title                    = {{Optimization by Simulated Annealing}},
+  Author                   = {S. Kirkpatrick and Gelatt, C. D. and Vecchi, M. P.},
+  Journal                  = {Science, Number 4598, 13 May 1983},
+  Year                     = {1983},
+  Pages                    = {671--680},
+  Volume                   = {220, 4598},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{kitthe_03,
+  Title                    = {{A}n efficient reconfigurable multiplier architecture for {G}alois field {GF} (2m)},
+  Author                   = {Kitsos, P. and Theodoridis, G. and Koufopavlou, O.},
+  Journal                  = {Microelectronics Journal},
+  Year                     = {2003},
+  Number                   = {10},
+  Pages                    = {975--980},
+  Volume                   = {34},
+
+  Abstract                 = {This paper describes an efficient architecture of a reconfigurable bit-serial polynomial basis multiplier for Galois field GF(2m), where 1<m?M. The value m, of the irreducible polynomial degree, can be changed and so, can be configured and programmed. The value of M determines the maximum size that the multiplier can support. The advantages of the proposed architecture are (i) the high order of flexibility, which allows an easy configuration for different field sizes, and (ii) the low hardware complexity, which results in small area. By using the gated clock technique, significant reduction of the total multiplier power consumption is achieved.},
+  Cds_grade                = {0},
+  Cds_keywords             = {FPGA, Galois Field Multiplier, FFM, Finite Field Multiplier},
+  File                     = {kitthe_03.pdf:kitthe_03.pdf:PDF},
+  Owner                    = {CdS},
+  Publisher                = {Elsevier},
+  Timestamp                = {2009.10.27}
+}
+
+@TechReport{klo_81,
+  Title                    = {{E}rror correcting codes for the asymmetric channel},
+  Author                   = {Kl{\o}ve, Torleiv},
+  Institution              = {Department of Pure Mathematics, University of Bergen},
+  Year                     = {1981},
+
+  Owner                    = {kraft},
+  Timestamp                = {2017-09-16}
+}
+
+@Article{klopin_12,
+  Title                    = {{P}y{CUDA} and {P}y{O}pen{CL}: {A} {S}cripting-based {A}pproach to {GPU} {R}un-time {C}ode {G}eneration},
+  Author                   = {Andreas Kl\"{o}ckner and Nicolas Pinto and Yunsup Lee and Bryan Catanzaro and Paul Ivanov and Ahmed Fasih},
+  Journal                  = {Parallel Computing},
+  Year                     = {2012},
+
+  Month                    = {mar},
+  Number                   = {3},
+  Pages                    = {157--174},
+  Volume                   = {38},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22}
+}
+
+@Article{Kleeberger2013,
+  Title                    = {{A} {C}ross-{L}ayer {T}echnology-{B}ased {S}tudy of the {I}mpact of {M}emory {E}rrors on {S}ystem {R}esilience},
+  Author                   = {Veit Kleeberger and Christina Gimmler-Dumont and Christian Weis and Andreas Herkersdorf and Daniel Mueller-Gritschneder and Sani Nassif and Ulf Schlichtmann and Norbert Wehn},
+  Journal                  = {accepted for publication in IEEE Micro},
+  Year                     = {2013},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.29}
+}
+
+@Article{klegim_13,
+  Title                    = {{A} {C}ross-{L}ayer {T}echnology-{B}ased {S}tudy of the {I}mpact of {M}emory {E}rrors on {S}ystem {R}esilience},
+  Author                   = {Veit Kleeberger and Christina Gimmler-Dumont and Christian Weis and Andreas Herkersdorf and Daniel Mueller-Gritschneder and Sani Nassif and Ulf Schlichtmann and Norbert Wehn},
+  Journal                  = {IEEE Micro},
+  Year                     = {2013},
+
+  Month                    = {July},
+  Number                   = {4},
+  Pages                    = {46-55},
+  Volume                   = {33},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.29}
+}
+
+@MastersThesis{MTklein05,
+  Title                    = {{Hardware Decoder for irregular Low-Density Parity-Check Codes}},
+  Author                   = {M. Klein},
+  School                   = {Microelectronic System Design Reseach Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2005},
+  Month                    = mar,
+
+  Optnote                  = {Diplomarbeit},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{kletar_06,
+  Title                    = {{A}lgorithm {D}esign},
+  Author                   = {Jon Kleinberg and Eva Tardos},
+  Publisher                = {Pearson/Addison Wesley},
+  Year                     = {2006},
+
+  Address                  = {Boston, MA, USA},
+  Edition                  = {International},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.02.01}
+}
+
+@Article{klecan_07,
+  Title                    = {{L}atch {D}esign {T}echniques for {M}itigating {S}ingle {E}vent {U}psets in 65 nm {SOI} {D}evice {T}echnology},
+  Author                   = {KleinOsowski, A. J. and Cannon, E. H. and Gordon, M. S. and Heidel, D. F. and Oldiges, P. and Plettner, C. and Rodbell, K. P. and Rose, R. D. and Tang, H. H. K. },
+  Journal                  = {Nuclear Science, IEEE Transactions on},
+  Year                     = {2007},
+  Number                   = {6},
+  Pages                    = {2021--2027},
+  Volume                   = {54},
+
+  Doi                      = {10.1109/TNS.2007.909707},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Book{klopla_10,
+  Title                    = {{N}umerical {S}olution of {S}tochastic {D}ifferential {E}quations ({S}tochastic {M}odelling and {A}pplied {P}robability)},
+  Author                   = {Peter E. Kloeden and Eckhard Platen},
+  Publisher                = {Springer},
+  Year                     = {2010},
+  Month                    = {12},
+
+  ISBN                     = {9783642081071},
+  Keywords                 = {finance},
+  Owner                    = {Brugger},
+  Price                    = {109.00},
+  Timestamp                = {2013.11.04},
+  Totalpages               = {636}
+}
+
+@Article{kno_69,
+  Title                    = {{R}emark on algorithm 334 [{G}5]: normal random deviates},
+  Author                   = {Knop, R.},
+  Journal                  = {Commun. ACM},
+  Year                     = {1969},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {281--},
+  Volume                   = {12},
+
+  Acmid                    = {362996},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Doi                      = {10.1145/362946.362996},
+  ISSN                     = {0001-0782},
+  Issue_date               = {May 1969},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2012.03.22},
+  Url                      = {http://doi.acm.org/10.1145/362946.362996}
+}
+
+@InProceedings{knurie_10,
+  Title                    = {{I}mproved adaptive belief propagation decoding using edge-local complementation},
+  Author                   = {Knudsen, J. G. and Riera, C. and Danielsen, L. E. and Parker, M. G. and Rosnes, E.},
+  Booktitle                = {Proc. (ISIT) Symp. IEEE Int Information Theory},
+  Year                     = {2010},
+  Pages                    = {774--778},
+
+  Doi                      = {10.1109/ISIT.2010.5513625},
+  File                     = {knurie_10.pdf:knurie_10.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ABP},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.07}
+}
+
+@Book{knu_98,
+  Title                    = {{S}eminumerical {A}lgorithms},
+  Author                   = {Donald E. Knuth},
+  Publisher                = {Addison-Wesley},
+  Year                     = {1997},
+
+  Address                  = {Reading, Massachusetts},
+  Edition                  = {3rd},
+  Series                   = {The Art of Computer Programming},
+  Volume                   = {2},
+
+  File                     = {knu_98.pdf:knu_98.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {Schmidt},
+  Timestamp                = {2010.08.04}
+}
+
+@Article{knu_76,
+  Title                    = {{B}ig {O}micron and big {O}mega and big {T}heta},
+  Author                   = {Knuth, Donald E.},
+  Journal                  = {SIGACT News},
+  Year                     = {1976},
+  Number                   = {2},
+  Pages                    = {18--24},
+  Volume                   = {8},
+
+  Address                  = {New York, NY, USA},
+  Doi                      = {http://doi.acm.org/10.1145/1008328.1008329},
+  ISSN                     = {0163-5700},
+  Publisher                = {ACM}
+}
+
+@InProceedings{kobkaw_09,
+  Title                    = {{A}lpha particle and neutron-induced soft error rates and scaling trends in {SRAM}},
+  Author                   = {Kobayashi, H. and Kawamoto, N. and Kase, J. and Shiraish, K.},
+  Booktitle                = {Proc. IEEE Int. Reliability Physics Symp},
+  Year                     = {2009},
+  Pages                    = {206--211},
+
+  Cb_grade                 = {- gelesen
+- Reliability
+- Technology
+- Alpha and Neutron particle measurement for SRAM},
+  Doi                      = {10.1109/IRPS.2009.5173252},
+  File                     = {kobkaw_09.pdf:kobkaw_09.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.11.07}
+}
+
+@InProceedings{kockan_07,
+  Title                    = {{R}educing off-chip memory access costs using data recomputation in embedded chip multi-processors},
+  Author                   = {Koc, Hakduran and Kandemir, Mahmut and Ercanli, Ehat and Ozturk, Ozcan},
+  Booktitle                = {Proceedings of the 44th annual Design Automation Conference},
+  Year                     = {2007},
+  Organization             = {ACM},
+  Pages                    = {224--229},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.09.17}
+}
+
+@InProceedings{kocbai_90,
+  Title                    = {{Optimum and sub-optimum detection of coded data disturbed by time-varying inter-symbol interference}},
+  Author                   = {W. Koch and A. Baier},
+  Booktitle                = {Proc. 1990 Global Telecommunications Conference (GLOBECOM '90)},
+  Year                     = {1990},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = dec,
+  Pages                    = {1679--1694},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{koec_12,
+  Title                    = {{M}ehrgittermethoden},
+  Author                   = {Norbert Köckler},
+  Publisher                = {Vieweg+Teubner Verlag | Springer Fachmedien Wiesbaden},
+  Year                     = {2012},
+
+  Comment                  = {eBook, ISBN 978-3-8348-2081-5},
+  Doi                      = {10.1007/978-3-8348-2081-5},
+  File                     = {koec_12.pdf:koec_12.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.10}
+}
+
+@Article{koema_11,
+  Title                    = {{T}he {R}e-{E}ncoding {T}ransformation in {A}lgebraic {L}ist-{D}ecoding of {R}eed--{S}olomon {C}odes},
+  Author                   = {Koetter, R. and Jun Ma and Vardy, A. },
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2011},
+  Number                   = {2},
+  Pages                    = {633--647},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TIT.2010.2096034},
+  File                     = {koema_11.pdf:koema_11.pdf:PDF},
+  Keywords                 = {ASD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.27}
+}
+
+@Article{koevar_03,
+  Title                    = {{A}lgebraic soft-decision decoding of {R}eed-{S}olomon codes},
+  Author                   = {Koetter, R. and Vardy, A.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2003},
+  Number                   = {11},
+  Pages                    = {2809--2825},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/TIT.2003.819332},
+  File                     = {koevar_03.pdf:koevar_03.pdf:PDF},
+  Keywords                 = {Reed-Solomon, KV, ASD},
+  Owner                    = {Scholl},
+  Review                   = {der berühmt berüchtigte Koetter Vardy Algorithmus},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{koevon_03,
+  Title                    = {{Graph-covers and iterative decoding of finite length codes}},
+  Author                   = {R. Koetter and P.O. Vontobel},
+  Booktitle                = {Proc. 3rd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {75--82},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{koggenerating10,
+  Title                    = {{Generating Workload Models from TLM-2.0-based Virtual Prototypes for Efficient Architecture Performance Analysis}},
+
+  Author                   = {Kogel, Tim},
+  HowPublished             = {\url{http://www.nascug.org/events/13th/tlm20_workload_models.pdf}},
+  Month                    = {Jun.},
+  Year                     = {2010, Last Access: 19.02.2015},
+
+  Booktitle                = {{talk NASCUG 13}},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20}
+}
+
+@Article{kog_16,
+  Title                    = {{O}ptimizing {DDR} {M}emory {S}ubsystem {E}fficiency - {T}he {U}npredictable {M}emory {B}ottleneck},
+  Author                   = {Kogel, Tim},
+  Journal                  = {\mbox{Synopsys Inc.}},
+  Year                     = {2016},
+
+  Month                    = {January},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11}
+}
+
+@Electronic{kog_06,
+  Title                    = {{TLM} {P}eripheral {M}odeling for {P}latform-{D}riven {ESL} {D}esign {U}sing the {S}ystem{C} {M}odeling {L}ibrary},
+  Author                   = {Tim Kogel},
+  HowPublished             = {Website},
+  Language                 = {english},
+  Organization             = {CoWare Inc.},
+  Url                      = {www.coware.com/PDF/TLMPeripheralModeling.PDF},
+  Year                     = {2006},
+
+  Abstract                 = {This article provides an overview of a SystemC-based
+Transaction Level Modeling (TLM) methodology for the
+rapid creation of SoC platform models. First a brief overview
+of the ESL design tasks and the corresponding modeling
+requirements is given. The main topic is a methodology
+for the efficient creation of transaction-level peripheral
+models. Those are usually specific for a particular SoC
+platform and have to be created by the ESL user.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Transaction-Level-Modeling, TLM, OSCI},
+  Cds_read                 = {2009-10-22},
+  Cds_review               = {Short overview of TLM design methodology},
+  File                     = {kog_06.pdf:kog_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.10.23}
+}
+
+@Electronic{Kogel2006,
+  Title                    = {{TLM} {P}eripheral {M}odeling for {P}latform-{D}riven {ESL} {D}esign {U}sing the {S}ystem{C} {M}odeling {L}ibrary},
+  Author                   = {Tim Kogel},
+  HowPublished             = {Website},
+  Language                 = {english},
+  Organization             = {CoWare Inc.},
+  Url                      = {www.coware.com/PDF/TLMPeripheralModeling.PDF},
+  Year                     = {2006},
+
+  Abstract                 = {This article provides an overview of a SystemC-based
+Transaction Level Modeling (TLM) methodology for the
+rapid creation of SoC platform models. First a brief overview
+of the ESL design tasks and the corresponding modeling
+requirements is given. The main topic is a methodology
+for the efficient creation of transaction-level peripheral
+models. Those are usually specific for a particular SoC
+platform and have to be created by the ESL user.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Transaction-Level-Modeling, TLM, OSCI},
+  Cds_read                 = {2009-10-22},
+  Cds_review               = {Short overview of TLM design methodology},
+  File                     = {kog_06.pdf:kog_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.10.23}
+}
+
+@Electronic{Kogel,
+  Title                    = {{OCP} {TLM} for {A}rchitectural {M}odeling},
+  Author                   = {Tim Kogel and Anssi Haverinen and James Aldis},
+  Url                      = {www.ocpip.org/.../OCP_TLM_for_Architectural_Modeling.pdf},
+
+  Abstract                 = {Over the last years Transaction Level Modeling has established itself as a valuable strategy to
+solve system-level design problems prior to the implementation phase. The System-Level Design
+Working Group of the OCP-IP consortium has contributed SystemC TLM channel packages and
+methodology guidelines to help the proliferation of this modeling paradigm since 2002 
[6].
+Meanwhile, SystemC in general and TLM in particular have been improved and standardized by
+Open SystemC Initiative 
[1], 
[2], 
[3].
+The predominant use models for SystemC based Transaction Level Modeling (TLM) are the
+highly abstract Programmers View (PV) 
[7], 
[8], 
[9] as well as fully cycle accurate modeling for
+verification and HDL co-simulation. However, so far no methodology for abstract performance
+modeling has been established addressing HW/SW partitioning and architectural exploration.
+We propose an Architects View (AV) TLM use-model, which is based on the revised OCP
+Transaction Level 2 (TL2) and TL3 APIs. The goal is to allow SoC architects to identify and
+resolve bottlenecks in the organization of the SW and HW infrastructure. Questions to answer are
+the number of processors, how different pieces of SW and algorithms will access main memory
+and what interconnect approach can deliver the required communication bandwidth. The potential
+of the revised OCP TL2 and TL3 Channels goes clearly beyond modeling of systems, which will
+eventually lead to an OCP based implementation. Instead the new TL2 and TL3 APIs enable the
+unified modeling of arbitrary applications and architecture platforms above cycle accuracy.
+We first give the overall picture of ESL design tasks and the corresponding TLM use-cases. The
+following chapters provide some technical background information on data-handling in TLM
+models and the OSCI TLM standard. The main body of this document is on the OCP based AV
+design methodology itself, introducing the revised OCP API, demonstrating compliance with
+OSCI TLM standard, and in particular explaining in detail the AV performance model. The last
+two chapters deal with the widely used Programmers View use-model and the interoperability of
+PV and AV.
+This methodology document is accompanied by an extensive example package, which provides
+the source code of all mentioned components, transactors as well as numerous examples. Please
+refer to the html documentation in the package for more details on its contents and usage.},
+  Cds_grade                = {5},
+  Cds_keywords             = {TLM, Transaction-Level-Modeling, OSCI},
+  Cds_read                 = {2009-10-21},
+  Cds_review               = {Overview of TLM modeling elements and views (Functional, Architectural, Programmer's and Verification) as well as implementation styles},
+  File                     = {koghav_.pdf:koghav_.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.10.23}
+}
+
+@Electronic{koghav_,
+  Title                    = {{OCP} {TLM} for {A}rchitectural {M}odeling},
+  Author                   = {Tim Kogel and Anssi Haverinen and James Aldis},
+  Url                      = {www.ocpip.org/.../OCP_TLM_for_Architectural_Modeling.pdf},
+
+  Abstract                 = {Over the last years Transaction Level Modeling has established itself as a valuable strategy to
+solve system-level design problems prior to the implementation phase. The System-Level Design
+Working Group of the OCP-IP consortium has contributed SystemC TLM channel packages and
+methodology guidelines to help the proliferation of this modeling paradigm since 2002 
[6].
+Meanwhile, SystemC in general and TLM in particular have been improved and standardized by
+Open SystemC Initiative 
[1], 
[2], 
[3].
+The predominant use models for SystemC based Transaction Level Modeling (TLM) are the
+highly abstract Programmers View (PV) 
[7], 
[8], 
[9] as well as fully cycle accurate modeling for
+verification and HDL co-simulation. However, so far no methodology for abstract performance
+modeling has been established addressing HW/SW partitioning and architectural exploration.
+We propose an Architects View (AV) TLM use-model, which is based on the revised OCP
+Transaction Level 2 (TL2) and TL3 APIs. The goal is to allow SoC architects to identify and
+resolve bottlenecks in the organization of the SW and HW infrastructure. Questions to answer are
+the number of processors, how different pieces of SW and algorithms will access main memory
+and what interconnect approach can deliver the required communication bandwidth. The potential
+of the revised OCP TL2 and TL3 Channels goes clearly beyond modeling of systems, which will
+eventually lead to an OCP based implementation. Instead the new TL2 and TL3 APIs enable the
+unified modeling of arbitrary applications and architecture platforms above cycle accuracy.
+We first give the overall picture of ESL design tasks and the corresponding TLM use-cases. The
+following chapters provide some technical background information on data-handling in TLM
+models and the OSCI TLM standard. The main body of this document is on the OCP based AV
+design methodology itself, introducing the revised OCP API, demonstrating compliance with
+OSCI TLM standard, and in particular explaining in detail the AV performance model. The last
+two chapters deal with the widely used Programmers View use-model and the interoperability of
+PV and AV.
+This methodology document is accompanied by an extensive example package, which provides
+the source code of all mentioned components, transactors as well as numerous examples. Please
+refer to the html documentation in the package for more details on its contents and usage.},
+  Cds_grade                = {5},
+  Cds_keywords             = {TLM, Transaction-Level-Modeling, OSCI},
+  Cds_read                 = {2009-10-21},
+  Cds_review               = {Overview of TLM modeling elements and views (Functional, Architectural, Programmer's and Verification) as well as implementation styles},
+  File                     = {koghav_.pdf:koghav_.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.10.23}
+}
+
+@InProceedings{koehzim_06,
+  Title                    = {{Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures}},
+  Author                   = {St. Köhler and M. Zimmerling and M. Zabel and R. G. Spallek},
+  Booktitle                = {19th International Conference on Architecture of Computing Systems ARCS'06},
+  Year                     = {2006},
+
+  Address                  = {Frankfurt am Main, Germany},
+
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.05}
+}
+
+@InProceedings{koljam_02,
+  Title                    = {{A} {R}eal-{T}ime {S}imulator for {MIMO} {R}adio {C}hannels},
+  Author                   = {Janne Kolu and Tommi Jämsä},
+  Booktitle                = {Wireless Personal Multimedia Communications, 2002. The 5th International Symposium on},
+  Year                     = {2002},
+  Month                    = oct,
+  Pages                    = {568--572},
+  Volume                   = {2},
+
+  Abstract                 = { A high, number of papers have been published on systems utilizing MIMO (multiple input-multiple output) techniques. Developing hardware real time simulators for MIMO channels is essential in evaluating the performances of signal processing algorithms for MIMO systems. We present a real time simulator platform for MIMO radio channel simulations. Due to real-time requirements a digital hardware-based implementation for an MIMO simulator together with controller software was pursued.},
+  Doi                      = {10.1109/WPMC.2002.1088238},
+  File                     = {koljam_02.pdf:koljam_02.pdf:PDF},
+  ISSN                     = {1347-6890 },
+  Keywords                 = {MIMO},
+  Owner                    = {CdS},
+  Timestamp                = {2012.06.20}
+}
+
+@Article{konpar_04,
+  Title                    = {{L}ow-latency architectures for high-throughput rate {V}iterbi decoders},
+  Author                   = {Jun Jin Kong and K. K. Parhi},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2004},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {642-651},
+  Volume                   = {12},
+
+  Doi                      = {10.1109/TVLSI.2004.827600},
+  File                     = {konpar_04.pdf:konpar_04.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {Viterbi decoding;binary codes;codecs;convolutional codes;trellis codes;K-nested layered look-ahead method;K-trellis steps;add-compare-select computations;decoding latency;encoder constraint length;low latency high throughput rate Viterbi decoders;Clocks;Computer architecture;Concurrent computing;Delay;Distributed computing;Frequency;Iterative decoding;Parallel processing;Throughput;Viterbi algorithm},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.18}
+}
+
+@InProceedings{kweh_92,
+  Title                    = {{ Partitioning on Boltzmann Machines}},
+  Author                   = {A. König and N. Wehn and M. Glesner},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS '92},
+  Year                     = {1992},
+
+  Address                  = {San Diego},
+  Pages                    = {324--327},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{konich_05,
+  Title                    = {{D}esign and {E}valuation of {H}ardware {P}seudo-{R}andom {N}umber {G}enerator {MT}19937},
+  Author                   = {Shiro Konuma and Shuichi Ichikawa},
+  Journal                  = {IEICE Transactions on Information And Systems},
+  Year                     = {2005},
+
+  Month                    = dec,
+  Number                   = {12},
+  Pages                    = {2876},
+  Volume                   = {E88-D},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generator, Mersenne Twister, FPGA},
+  File                     = {konich_05.pdf:konich_05.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {INSTITUTE OF ELECTRONICS, INFORMATION \&},
+  Timestamp                = {2012.03.14}
+}
+
+@InProceedings{koowan_97,
+  Title                    = {{Performance of Turbo-Codes with Short Frame Sizes}},
+  Author                   = {H. Koorapaty and Y.-P. Wang and K. Balachandran},
+  Booktitle                = {Proc. 1997 Vehicular Technology Conference (VTC '97)},
+  Year                     = {1997},
+
+  Address                  = {Phoenix, Arizona, USA},
+  Pages                    = {329--333},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{kopoch_87,
+  Title                    = {{C}lock {S}ynchronization in {D}istributed {R}eal-{T}ime {S}ystems},
+  Author                   = {Kopetz, Hermann and Ochsenreiter, Wilhelm},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {1987},
+
+  Month                    = {Aug},
+  Number                   = {8},
+  Pages                    = {933-940},
+  Volume                   = {C-36},
+
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {5009516},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1109/TC.1987.5009516},
+  ISSN                     = {0018-9340},
+  Keywords                 = {BLE},
+  Keywords_original        = {Central Processing Unit;Clocks;Fault tolerant systems;Length measurement;Position measurement;Real time systems;Synchronization;Time measurement;Upper bound;Very large scale integration;Distributed real-time systems;VLSI clock;external synchronization;fault-tolerant clock synchronization;internal synchronization;synchronization accuracy},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30}
+}
+
+@InProceedings{Korb2010,
+  Title                    = {{LDPC} decoder area, timing, and energy models for early quantitative hardware cost estimates},
+  Author                   = {Korb, M. and Noll, T. G.},
+  Booktitle                = {Proc. Int System Chip (SoC) Symp},
+  Year                     = {2010},
+  Pages                    = {169--172},
+
+  Doi                      = {10.1109/ISSOC.2010.5625546},
+  File                     = {Korb2010.pdf:Korb2010.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.02.01}
+}
+
+@InProceedings{Korb2009,
+  Title                    = {{A}rea and latency optimized high-throughput {M}in-{S}um based {LDPC} decoder architectures},
+  Author                   = {Korb, M. and Noll, T. G.},
+  Booktitle                = {Proc. ESSCIRC ESSCIRC '09},
+  Year                     = {2009},
+  Pages                    = {408--411},
+
+  Doi                      = {10.1109/ESSCIRC.2009.5325964},
+  File                     = {Korb2009.pdf:Korb2009.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.01.26}
+}
+
+@Book{korkor_01,
+  Title                    = {{O}ption {P}ricing and {P}ortfolio {O}ptimization: {M}odern {M}ethods of {F}inancial {M}athematics},
+  Author                   = {Ralf Korn and Elke Korn},
+  Publisher                = {AMS},
+  Year                     = {2001},
+
+  Address                  = {Providence, Rhode Island},
+  Series                   = {Graduate Studies in Mathematics},
+  Volume                   = {31},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@Book{korkor_10,
+  Title                    = {{M}onte {C}arlo {M}ethods and {M}odels in {F}inance and {I}nsurance},
+  Author                   = {Ralf Korn and Elke Korn and Gerald Kroisandt},
+  Publisher                = {Boca Raton, FL: CRC Press.},
+  Year                     = {2010},
+
+  Classmath                = {{*91-02 (Research exposition (Social and behavioral sciences)) 65-02 (Research monographs (numerical analysis)) 65C05 (Monte Carlo methods) 91G60 ( ) }},
+  File                     = {korkor_10.pdf:korkor_10.pdf:PDF},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Timestamp                = {2011.07.04}
+}
+
+@Article{korpup_15,
+  Title                    = {{A} {N}ew {V}ariance {R}eduction {T}echnique for {E}stimating {V}alue-at-{R}isk},
+  Author                   = {Ralf Korn and Mykhailo Pupashenko},
+  Journal                  = {Applied Mathematical Finance},
+  Year                     = {2015},
+  Number                   = {1},
+  Pages                    = {83-98},
+  Volume                   = {22},
+
+  Doi                      = {10.1080/1350486X.2014.962182},
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@InProceedings{kottak_05,
+  Title                    = {{A} comparison of adaptive belief propagation and the best graph algorithm for the decoding of linear block codes},
+  Author                   = {Kothiyal, A. and Takeshita, O. Y. },
+  Booktitle                = {Proc. Int. Symp. Information Theory ISIT 2005},
+  Year                     = {2005},
+  Pages                    = {724--728},
+
+  Doi                      = {10.1109/ISIT.2005.1523431},
+  File                     = {kottak_05.pdf:kottak_05.pdf:PDF},
+  Keywords                 = {ABP, Reed-Solomon, BCH},
+  Owner                    = {Scholl},
+  Review                   = {neuer Algorithmus basierend auf dem ABP: Best Graph Algorithmus},
+  Timestamp                = {2011.06.21}
+}
+
+@Article{kottak_05a,
+  Title                    = {{I}terative reliability-based decoding of linear block codes with adaptive belief propagation},
+  Author                   = {Kothiyal, A. and Takeshita, O. Y. and Jin, W. and Fossorier, M.},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2005},
+  Number                   = {12},
+  Pages                    = {1067--1069},
+  Volume                   = {9},
+
+  Doi                      = {10.1109/LCOMM.2005.1576590},
+  File                     = {kottak_05a.pdf:kottak_05a.pdf:PDF},
+  Keywords                 = {OSD, ABP, BCH, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {Kombination aus OSD und ABP},
+  Timestamp                = {2011.06.21}
+}
+
+@Article{kvar_03,
+  Title                    = {{Algebraic soft-decision decoding of Reed-Solomon codes}},
+  Author                   = {R. Kötter and A. Vardy},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {2003},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {2809--2825},
+  Volume                   = {49},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{koulin_01,
+  Title                    = {{Low-Density Parity-Check Codes Based on Finite Geometries: A Rediscovery and New Results}},
+  Author                   = {Y. Kou and S. Lin and Fossorier, M.P.C.},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {2001},
+
+  Month                    = nov,
+  Number                   = {7},
+  Pages                    = {2711--2736},
+  Volume                   = {47},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kraleu_09,
+  Title                    = {{A} checkpoint/restore framework for systemc-based virtual platforms},
+  Author                   = {S. Kraemer and R. Leupers and D. Petras and T. Philipp},
+  Booktitle                = {2009 International Symposium on System-on-Chip},
+  Year                     = {2009},
+  Month                    = {Oct},
+  Pages                    = {161-167},
+
+  Doi                      = {10.1109/SOCC.2009.5335656},
+  Keywords                 = {checkpointing;graphical user interfaces;software engineering;checkpoint/restore framework;SystemC-based virtual platforms;edit-compile-debug cycle;checkpoint image;interactive GUI;checkpointing;Checkpointing;Hardware;Image restoration;Personal digital assistants;Signal restoration;Productivity;Debugging;Programming;Application software;Signal processing},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-09}
+}
+
+@InProceedings{krajun_18,
+  Title                    = {{I}mproving the {E}rror {B}ehavior of {DRAM} by {E}xploiting its {Z}-{C}hannel {P}roperty},
+  Author                   = {Kraft, Kira and Jung, Matthias and Sudarshan, Chiarg and Mathew, Deepak M. and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {IEEE Conference Design, Automation and Test in Europe (DATE)},
+  Year                     = {2018},
+  Month                    = {March},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-11-05}
+}
+
+@InProceedings{kramat_18,
+  Title                    = {{E}fficient {C}oding {S}cheme for {DDR}4 {M}emory {S}ubsystems},
+  Author                   = {Kraft, Kira and Mathew, Deepak M. and Sudarshan, Chirag and Jung, Matthias and Weis, Christian and Wehn, Norbert and Longnos, Florian},
+  Booktitle                = {ACM International Symposium on Memory Systems (MEMSYS 2018)},
+  Year                     = {2018},
+  Month                    = {October},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-06-05}
+}
+
+@InProceedings{krejoh_14,
+  Title                    = {{A}n adaptive {MMSE}-{SIC} soft detector with error regularization for iterative {MIMO} receivers},
+  Author                   = {A. Krebs and M. Joham and W. Utschick},
+  Booktitle                = {Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on},
+  Year                     = {2014},
+  Month                    = {May},
+  Pages                    = {1961-1965},
+
+  Doi                      = {10.1109/ICASSP.2014.6853941},
+  File                     = {krejoh_14.pdf:krejoh_14.pdf:PDF},
+  Keywords                 = {MIMO communication;adaptive signal detection;antenna arrays;interference suppression;iterative decoding;least mean squares methods;maximum likelihood detection;radio receivers;transmitting antennas;wireless channels;MLD;adaptive MMSE-SIC soft detector;channel iterative decoder;error propagation reduction;error regularization;iterative MIMO receivers;low complexity soft detector;minimum mean square error successive interference cancellation;multiple-input multiple-output channels;regularization mechanism;soft max-log maximum-likelihood detector;transmit antennas;Complexity theory;Decoding;Detectors;MIMO;Modulation;Receivers;Vectors},
+  Owner                    = {MH},
+  Timestamp                = {2016-03-29}
+}
+
+@PhdThesis{Phdkreis03,
+  Title                    = {{Efficient VLSI Architectures for Multi-mode Channel Decoder}},
+  Author                   = {G. Kreiselmaier},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2003},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTkreis98,
+  Title                    = {{Untersuchung geeigneter Architekturalternativen zur effizienten Hardwareimplementierung von Turbo-Code-Decodierern}},
+  Author                   = {G. Kreiselmaier},
+  School                   = {Institute of Microelectronic Systems, Department of Electrical Engineering, University of Kaiserslautern},
+  Year                     = {1998},
+  Month                    = jul,
+  Note                     = {In German},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Kreiselmaier2003a,
+  Title                    = {{Method of blindly detecting a transport format of an incident convolutional encoded signal, and corresponding convolutional code decoder}},
+
+  Author                   = {G. Kreiselmaier and F. Berens},
+  HowPublished             = {Patent Application},
+  Month                    = apr,
+  Year                     = {2003},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{kremethod03,
+  Title                    = {{Method of blindly detecting a transport format of an incident convolutional encoded signal, and corresponding convolutional code decoder}},
+
+  Author                   = {G. Kreiselmaier and F. Berens},
+  HowPublished             = {Patent Application},
+  Month                    = apr,
+  Year                     = {2003},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{krecombined02,
+  Title                    = {{Combined Turbo-Code/Convolutional Code Decoder, in particular for Mobile Radio Systems}},
+
+  Author                   = {G. Kreiselmaier and F. Berens},
+  HowPublished             = {Patent Application},
+  Month                    = sep,
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Kreiselmaier2002,
+  Title                    = {{Combined Turbo-Code/Convolutional Code Decoder, in particular for Mobile Radio Systems}},
+
+  Author                   = {G. Kreiselmaier and F. Berens},
+  HowPublished             = {Patent Application},
+  Month                    = sep,
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{kregil_99,
+  Title                    = {{Implementierung/Technische Spezifikation der Turbo-Decoder-Hardware}},
+  Author                   = {G. Kreiselmaier and F. Gilbert},
+  Institution              = {{Institute of Microelectronic Systems and Center of Microelectronics, Department of Electrical Engineering, University of Kaiserslautern}},
+  Year                     = {1999},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{krevog_02,
+  Title                    = {{Combined Turbo and Convolutional Code Decoder Architecture for UMTS Wireless Applications}},
+  Author                   = {G. Kreiselmaier and T. Vogt and N. Wehn and F. Berens},
+  Booktitle                = {Proc. 15th Symposium on Integrated Circuits and Systems Design},
+  Year                     = {2002},
+
+  Address                  = {Porto Alegre, Brazil},
+  Month                    = sep,
+  Pages                    = {337--342},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{kreweh_00,
+  Title                    = {{Architectural Study of 3GPP Turbo/Convolutional Code Decoder}},
+  Author                   = {G. Kreiselmaier and N. Wehn},
+  Institution              = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2000},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kre_97,
+  Title                    = {{DSP-Oriented Extensions to ANSI C}},
+  Author                   = {B. Krepp},
+  Booktitle                = {Proc. 1997 of the International Conference on Signal Processing Applications and Technology (ICSPAT '97)},
+  Year                     = {1997},
+  Organization             = {DSP Associates},
+  Pages                    = {658--664},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{Phdkretz05,
+  Title                    = {{V}erlustleistungsreduktion durch transitionsmindernde {K}odierung von {S}ystembussen},
+  Author                   = {Claudia Kretzschmar},
+  School                   = {Fakultät für Elektrotechnik und Informationstechnik der Technischen Universität Chemnitz},
+  Year                     = {2005},
+  Month                    = jul,
+
+  File                     = {Phdkretz05.pdf:Phdkretz05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{krieng_07,
+  Title                    = {{Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets}},
+  Author                   = {Gummidipudi Krishnaiah and Nur Engin and Sergei Sawitzki},
+  Booktitle                = {Proc. 2007 Design, Automation and Test in Europe (DATE '07)},
+  Year                     = {2007},
+
+  Owner                    = {vogt},
+  Timestamp                = {2007.05.31}
+}
+
+@InProceedings{krimah_04,
+  Title                    = {{A} {H}ighly-{E}fficient {T}echnique for {R}educing {S}oft {E}rrors in {S}tatic {CMOS} {C}ircuits},
+  Author                   = {Krishnamohan, S. and Mahapatra, N.R.},
+  Booktitle                = {Proc. IEEE International Conference on Computer Design (ICCD 2004)},
+  Year                     = {2004},
+  Month                    = oct,
+  Pages                    = {126--131},
+
+  Doi                      = {10.1109/ICCD.2004.1347911},
+  File                     = {krimah_04.pdf:krimah_04.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@InCollection{krisut_12,
+  Title                    = {{I}mage{N}et {C}lassification with {D}eep {C}onvolutional {N}eural {N}etworks},
+  Author                   = {Alex Krizhevsky and Sutskever, Ilya and Hinton, Geoffrey E},
+  Booktitle                = {Advances in Neural Information Processing Systems 25},
+  Publisher                = {Curran Associates, Inc.},
+  Year                     = {2012},
+  Editor                   = {F. Pereira and C. J. C. Burges and L. Bottou and K. Q. Weinberger},
+  Pages                    = {1097--1105},
+
+  Owner                    = {MG},
+  Timestamp                = {2017-04-24},
+  Url                      = {http://papers.nips.cc/paper/4824-imagenet-classification-with-deep-convolutional-neural-networks.pdf}
+}
+
+@InProceedings{kroowa_13,
+  Title                    = {{O}n the {P}ortability of the {O}pen{CL} {D}warfs on {F}ixed and {R}econfigurable {P}arallel {P}latforms},
+  Author                   = {Konstantinos Krommydas and Muhsen Owaida and Christos D. Antonopoulos and Nikolaos Bellas and {Wu-chun} Feng},
+  Booktitle                = {Proceedings of the 2013 International Conference on Parallel and Distributed Systems},
+  Year                     = {2013},
+  Month                    = {Dec},
+  Pages                    = {432-433},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@InProceedings{krudon_11,
+  Title                    = {{H}ardware/software co-design for energy-efficient seismic modeling},
+  Author                   = {Krueger, J. and Donofrio, D. and Shalf, J. and Mohiyuddin, M. and Williams, S. and Oliker, L. and Pfreundt, F.-J.},
+  Booktitle                = {Proceedings of the 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC)},
+  Year                     = {2011},
+  Pages                    = {1-12},
+
+  Abstract                 = {Reverse Time Migration (RTM) has become the standard for high-quality imaging in the seismic industry. RTM relies on PDE solutions using stencils that are 8th order or larger, which require large-scale HPC clusters to meet the computational demands. However, the rising power consumption of conventional cluster technology has prompted investigation of architectural alternatives that offer higher computational efficiency. In this work, we compare the performance and energy efficiency of three architectural alternatives the Intel Nehalem X5530 multicore processor, the NVIDIA Tesla C2050 GPU, and a general-purpose manycore chip design optimized for high-order wave equations called "Green Wave." We have developed an FPGA-accelerated architectural simulation platform to accurately model the power and performance of the Green Wave design. Results show that across highly-tuned high-order RTM stencils, the Green Wave implementation can offer up to 8× and 3.5× energy efficiency improvement per node respectively, compared with the Nehalem and GPU platforms. These results point to the enormous potential energy advantages of our hardware/software co-design methodology.},
+  File                     = {krudon_11.pdf:krudon_11.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@InProceedings{krudon_11a,
+  Title                    = {{H}ardware/software co-design for energy-efficient seismic modeling},
+  Author                   = {Krueger, J. and Donofrio, D. and Shalf, J. and Mohiyuddin, M. and Williams, S. and Oliker, L. and Pfreundt, F.-J.},
+  Booktitle                = {High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for},
+  Year                     = {2011},
+  Month                    = {Nov},
+  Pages                    = {1-12},
+
+  Keywords                 = {field programmable gate arrays;geophysics computing;graphics processing units;hardware-software codesign;multiprocessing systems;power aware computing;seismology;wave equations;FPGA-accelerated architectural simulation platform;Green Wave design;HPC cluster;Intel Nehalem X5530 multicore processor;NVIDIA Tesla C2050 GPU;PDE;RTM stencil;energy-efficient seismic modeling;general-purpose manycore chip design;hardware-software codesign;high-order wave equation;reverse time migration;seismic imaging;Computer architecture;Graphics processing unit;Green products;Hardware;Propagation;System-on-a-chip;GPU;RTM;co-design;manycore;seismic;stencil},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.10}
+}
+
+@Article{kscfre_01,
+  Title                    = {{Factor Graphs and the Sum-Product Algorithm}},
+  Author                   = {Kschischang, F.R. and Frey, B.J. and Loeliger, H.A.},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {498--519},
+  Volume                   = {47},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{ksc_03,
+  Title                    = {{Codes Defined on Graphs}},
+  Author                   = {Kschischang, F. R.},
+  Journal                  = {IEEE Communications Magazine},
+  Year                     = {2003},
+
+  Month                    = aug,
+  Pages                    = {118--125},
+  Volume                   = {41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kuhfor_13,
+  Title                    = {{FERAL} - {F}ramework for simulator coupling on requirements and architecture level},
+  Author                   = {T. Kuhn and T. Forster and T. Braun and R. Gotzhein},
+  Booktitle                = {2013 Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2013)},
+  Year                     = {2013},
+  Month                    = {Oct},
+  Pages                    = {11-22},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-13}
+}
+
+@Article{kulroy_12,
+  Title                    = {{U}ltralow-{V}oltage {P}rocess-{V}ariation-{T}olerant {S}chmitt-{T}rigger-{B}ased {SRAM} {D}esign},
+  Author                   = {Kulkarni, J. P. and Roy, K.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2012},
+  Number                   = {2},
+  Pages                    = {319--332},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/TVLSI.2010.2100834},
+  File                     = {kulroy_12.pdf:kulroy_12.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2012.03.30}
+}
+
+@Book{kumsaw_06,
+  Title                    = {{I}ntelligent {A}lgorithms in {A}mbient and {B}iomedical {C}omputing, {C}hapter 17: {H}igh {T}hroughput and {L}ow {P}ower {R}eed {S}olomon {D}ecoder for {U}ltra {W}ide {B}and},
+  Author                   = {Akash Kumar and Sergei Sawitzki},
+  Editor                   = {Wim Verhaegh and Emile Aarts and Jan Korst},
+  Publisher                = {Springer Verlag},
+  Year                     = {2006},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {design space exploration},
+  Cds_read                 = {2008-07-03},
+  Date-added               = {2008-07-03 14:55:33 +0200},
+  Date-modified            = {2008-07-03 15:03:18 +0200},
+  File                     = {kumsaw_06.pdf:kumsaw_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{Kumar2002,
+  Title                    = {{A Network on Chip Architecture and Design Methodology}},
+  Author                   = {S. Kumar and A. Jantsch and J. P. Soininen and M. Forsell and M. Millberg and J. Öberg and K. Tiensyrjä and A. Hemani},
+  Booktitle                = {Proc. of IEEE Annual Symposium on VLSI},
+  Year                     = {2002},
+
+  Address                  = {Pittsburg, USA},
+  Pages                    = {117--124},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kumjan_02,
+  Title                    = {{A Network on Chip Architecture and Design Methodology}},
+  Author                   = {S. Kumar and A. Jantsch and J. P. Soininen and M. Forsell and M. Millberg and J. Öberg and K. Tiensyrjä and A. Hemani},
+  Booktitle                = {Proc. of IEEE Annual Symposium on VLSI},
+  Year                     = {2002},
+
+  Address                  = {Pittsburg, USA},
+  Pages                    = {117--124},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kunpra_10,
+  Title                    = {{A}pplication {S}pecific {I}nstruction {A}ccelerator for {M}ultistandard {V}iterbi and {T}urbo {D}ecoding},
+  Author                   = {Kunchamwar, M.K. and Prasad, D.P. and Hegde, P. and Balsara, P.T. and Sangireddy, R.},
+  Booktitle                = {Parallel Processing Workshops (ICPPW), 2010 39th International Conference on},
+  Year                     = {2010},
+  Month                    = {sept.},
+  Pages                    = {34 -43},
+
+  Doi                      = {10.1109/ICPPW.2010.17},
+  ISSN                     = {1530-2016},
+  Keywords                 = {Algorithm design and analysis;Computer architecture;Decoding;Measurement;Programprocessors;Standards;Viterbi algorithm;Viterbi decoding;channel coding;telecommunicationstandards;turbo codes;UMTS turbo decoder;UWB Viterbi decoder;application specificinstruction accelerator;parallelism;radio processor;turbo channel decoding;Multistandard wireless communication system;Turbo decoder;Viterbi decoder;}
+}
+
+@TechReport{kungen_82,
+  Title                    = {{M}atrix triangularization by systolic arrays},
+  Author                   = {Kung, H. T. and Gentleman, W. M},
+  Institution              = {Computer Science Department},
+  Year                     = {1982},
+  Number                   = {Paper 1603},
+
+  File                     = {kungen_82.pdf:kungen_82.pdf:PDF},
+  Keywords                 = {Gauss; Gaussian Elimination; systolic array},
+  Owner                    = {Scholl},
+  Timestamp                = {2013.02.04},
+  Url                      = {http://repository.cmu.edu/compsci/1603}
+}
+
+@InProceedings{kunmat_11,
+  Title                    = {{C}ombining {LDPC}, turbo and {V}iterbi decoders: {B}enefits and costs},
+  Author                   = {Kunze, S. and Matus, E. and Fettweis, G. and Kobori, T.},
+  Booktitle                = {Signal Processing Systems (SiPS), 2011 IEEE Workshop on},
+  Year                     = {Oct.},
+  Pages                    = {216-221},
+
+  Doi                      = {10.1109/SiPS.2011.6088977},
+  ISSN                     = {2162-3562},
+  Keywords                 = {channel coding;decoding;forward error correction;parity check codes;turbo codes;ASIP;LDPC decoders;application-specific instruction set processor;channel code;multicode FEC architectures;multicode forward error correction architectures;performance estimations;turbo decoders;viterbi decoders;Computer architecture;Decoding;Measurement;Merging;Parity check codes;Power demand;Viterbi algorithm;LDPC;Viterbi decoder;channel decoder;multi-standard;turbo decoder}
+}
+
+@InProceedings{kunmat_10,
+  Title                    = {{A} ''multi-user'' approach towards a channel decoder for convolutional, turbo and {LDPC} codes},
+  Author                   = {Kunze, S. and Matus, E. and Fettweis, G. and Kobori, T.},
+  Booktitle                = {Signal Processing Systems (SIPS), 2010 IEEE Workshop on},
+  Year                     = {2010},
+  Month                    = {oct.},
+  Pages                    = {386 -391},
+
+  Doi                      = {10.1109/SIPS.2010.5624878},
+  File                     = {kunmat_10.pdf:kunmat_10.pdf:PDF},
+  ISSN                     = {1520-6130},
+  Keywords                 = {convolutional codes;convolutional turbo codes;high-throughput multimode channel decoder architecture;low-density parity-check codes;multiuser approach;separate decoding processes;channel coding;convolutional codes;decoding;parity check codes;turbo codes;}
+}
+
+@InProceedings{kunmat_09,
+  Title                    = {{ASIP} decoder architecture for convolutional and {LDPC} codes},
+  Author                   = {Kunze, S. and Matus, E. and Fettweis, G. P.},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2009},
+  Year                     = {2009},
+  Month                    = may,
+  Pages                    = {2457--2460},
+
+  Doi                      = {10.1109/ISCAS.2009.5118298},
+  File                     = {kunmat_09.pdf:kunmat_09.pdf:PDF},
+  Keywords                 = {ASIP LDPC},
+  Owner                    = {Alles},
+  Timestamp                = {2009.11.24}
+}
+
+@InProceedings{kuowil_07,
+  Title                    = {{L}ow-latency {M}emory-efficient 150-{M}bps {T}urbo {FEC} {E}ncoder and {D}ecoder},
+  Author                   = {Tzu-Chieh Kuo and Willson, A. N. },
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2007},
+  Year                     = {2007},
+  Month                    = may,
+  Pages                    = {913--916},
+
+  Doi                      = {10.1109/ISCAS.2007.378074},
+  File                     = {kuowil_07.pdf:kuowil_07.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@Article{kuoros_07,
+  Title                    = {{M}easuring the {G}ap {B}etween {FPGA}s and {ASIC}s},
+  Author                   = {Kuon, I. and Rose, J.},
+  Journal                  = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
+  Year                     = {2007},
+  Number                   = {2},
+  Pages                    = {203--215},
+  Volume                   = {26},
+
+  Doi                      = {10.1109/TCAD.2006.884574},
+  File                     = {kuoros_07.pdf:kuoros_07.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.01.24}
+}
+
+@InProceedings{kurdut_08,
+  Title                    = {{C}ross-{L}ayer {A}pproaches to {D}esigning {R}eliable {S}ystems {U}sing {U}nreliable {C}hips},
+  Author                   = {Kurdahi, F. and Dutt, N. and Eltawil, A. and Nassif, S.},
+  Booktitle                = {Proc. 21st International Conference on VLSI Design VLSID 2008},
+  Year                     = {2008},
+  Month                    = jan,
+  Pages                    = {14--15},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Kurdahwhii
+- only Abstract, Reliable, Unreliable},
+  Doi                      = {10.1109/VLSI.2008.135},
+  File                     = {kurdut_08.pdf:kurdut_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm, May},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{kurelt_10,
+  Title                    = {{L}ow-{P}ower {M}ultimedia {S}ystem {D}esign by {A}ggressive {V}oltage {S}caling},
+  Author                   = {Kurdahi, F.J. and Eltawil, A. and Kang Yi and Cheng, S. and Khajeh, A.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2010},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {852--856},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/TVLSI.2009.2016665},
+  File                     = {kurelt_10.pdf:kurelt_10.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {Reliability}
+}
+
+@Article{kurfuj_01,
+  Title                    = {{D}evelopment of {M}ersenne {T}wister using {CPLD}s},
+  Author                   = {T. Kurokawa and S. Fujimoto},
+  Journal                  = {IEICE Trans. Inf. \& Syst. (Japanese Edition)},
+  Year                     = {2001},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {501--504},
+  Volume                   = {J84-D-I},
+
+  Cds_grade                = {0},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.07}
+}
+
+@Article{kurkaj_03,
+  Title                    = {{FPGA} {B}ased {I}mplementation of the {M}ersenne {T}wister},
+  Author                   = {T. Kurokawa and H. Kajisaki},
+  Journal                  = {Scientific and Engineering Reports of the National Defense Academy},
+  Year                     = {2003},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {15--21},
+  Volume                   = {40},
+
+  Cds_grade                = {0},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.07}
+}
+
+@Electronic{kus_16,
+  Title                    = {{A}udi z{FAS} - {E}norme {D}atenmengen bewältigen},
+  Author                   = {Ingo Kuss},
+  Month                    = {07},
+  Url                      = {http://www.elektroniknet.de/elektronik-automotive/assistenzsysteme/enorme-datenmengen-bewaeltigen-131797.html},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-01-17}
+}
+
+@Article{kwalee_02,
+  Title                    = {{Design of dividable interleaver for parallel decoding in turbo codes}},
+  Author                   = {J. Kwak and K. Lee},
+  Journal                  = {Electronics Letters},
+  Year                     = {2002},
+
+  Month                    = oct,
+  Number                   = {22},
+  Pages                    = {1362--1364},
+  Volume                   = {38},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kwapar_03,
+  Title                    = {{Implementation of a parallel turbo decoder with dividable interleaver}},
+  Author                   = {J. Kwak and S. M. Park and S.-S. Yoon and K. Lee},
+  Booktitle                = {Proc. 2003 IEEE International Symposium on Circuits and Systems (ISCAS '03)},
+  Year                     = {2003},
+
+  Address                  = {Bangkok, Thailand},
+  Month                    = may,
+  Pages                    = {65--68},
+  Volume                   = {2},
+
+  File                     = {kwapar_03.pdf:kwapar_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Review                   = {MM: Custom Interleaver},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{kwoseo_17,
+  Title                    = {23.4 {A}n extremely low-standby-power 3.733{G}b/s/pin 2{G}b {LPDDR}4 {SDRAM} for wearable devices},
+  Author                   = {H. J. Kwon and E. Seo and C. Y. Lee and Y. H. Seo and G. H. Han and H. R. Kim and J. H. Lee and M. S. Jang and S. G. Do and S. H. Cho and J. K. Park and S. Y. Doo and J. B. Shin and S. H. Jung and H. J. Kim and I. H. Im and B. R. Cho and J. W. Lee and J. Y. Lee and K. H. Yu and H. K. Kim and C. H. Jeon and H. S. Park and S. S. Kim and S. H. Lee and J. W. Park and S. S. Lee and B. T. Lim and J. y. Park and Y. S. Park and H. J. Kwon and S. J. Bae and J. H. Choi and K. I. Park and S. J. Jang and G. Y. Jin},
+  Booktitle                = {2017 IEEE International Solid-State Circuits Conference (ISSCC)},
+  Year                     = {2017},
+  Month                    = {Feb},
+  Pages                    = {394-395},
+
+  Doi                      = {10.1109/ISSCC.2017.7870427},
+  Keywords                 = {DRAM chips;error correction codes;low-power electronics;DRAM periodic self-refresh;active-mode power efficiency;battery life;data retention;deep-power-down mode;dual-page-size scheme;error-correction-code engine;extremely low-standby-power LPDDR4 SDRAM;high-resolution graphic engines;intensive power gating;leakage current;limited battery capacity;memory bandwidth;power 0.15 mW;self-refresh current reduction;smart glasses;smart watches;storage capacity 2 Gbit;temperature controlled internal power generator;wearable devices},
+  Owner                    = {MJ},
+  Timestamp                = {2017-09-13}
+}
+
+@InProceedings{kwogen_20,
+  Title                    = {{RAMB}leed: {R}eading {B}its in {M}emory {W}ithout {A}ccessing {T}hem},
+  Author                   = {Kwong, Andrew and Genkin, Daniel and Gruss, Daniel and Yarom, Yuval},
+  Booktitle                = {Proceedings of the 41st Annual IEEE Symposium on Security \& Privacy, May 2020},
+  Year                     = {2020},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-06-18}
+}
+
+@Patent{che_02,
+  Title                    = {{Dynamic DRAM Refresh Rate Adjustment Based on Cell Leakage Monitoring}},
+  Year                     = {2002},
+
+  Address                  = {{US Patent 6,483,764}},
+  Author                   = {{L.L. Chen Hsu et al.}},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-15}
+}
+
+@TechReport{le_07,
+  Title                    = {{P}seudorandom {N}umber {G}enerators},
+  Author                   = {Pierre L'Ecuyer},
+  Institution              = {DIRO, Université de Montreal},
+  Year                     = {2007},
+
+  Address                  = {C.P. 6128, Succ. Centre-Ville
+Montréal (Québec), Canada, H3C 3J7},
+  Month                    = aug,
+
+  Abstract                 = {We review the basic principles underlying the design of uniform random number generators, their main quality requirements, their theoretical analysis, and their empirical testing. The main con- struction techniques of algorithmic generators are discussed, with an emphasis on the most com- mon ones, the linear generators. Nonlinear generators, as well as hardware-based generators, are also briefly discussed. For simulation, we explain why we favor generators that can offer multiple streams and substreams, and we recommend specific ones.},
+  Cds_grade                = {0},
+  Cds_keywords             = {RNG, PRNG, stream, substream},
+  Cds_read                 = {2013-12-17},
+  File                     = {le_07.pdf:le_07.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.17},
+  Url                      = {http://www.iro.umontreal.ca/~lecuyer/myftp/papers/eqf.pdf}
+}
+
+@Article{le_96,
+  Title                    = {{M}aximally {E}quidistributed {C}ombined {T}ausworthe {G}enerators},
+  Author                   = {Pierre L'Ecuyer},
+  Journal                  = {Mathematics Of Computation},
+  Year                     = {1996},
+
+  Month                    = jan,
+  Number                   = {213},
+  Pages                    = {203--213},
+  Volume                   = {65},
+
+  Abstract                 = {Tausworthe random number generators based on a primitive trinomial allow an easy and fast implementation when their parameters obey certain restrictions. However, such generators, with those restrictions, have bad statistical properties unless we combine them. A generator is called maximally equidistributed if its vectors of successive values have the best possible equidistribution in all dimensions. This paper shows how to nd maximally equidistributed combinations in an ecient manner, and gives a list of generators with that property. Such generators have a strong theoretical support and lend themselves to very fast software implementations.},
+  Cds_grade                = {0},
+  File                     = {l'e_96.pdf:l'e_96.pdf:PDF},
+  Owner                    = {CdS},
+  Publisher                = {American Mathematical Society},
+  Timestamp                = {2010.08.02}
+}
+
+@Article{le_94,
+  Title                    = {{U}niform {R}andom {N}umber {G}eneration},
+  Author                   = {Pierre L'Ecuyer},
+  Journal                  = {Annals of Operations Research},
+  Year                     = {1994},
+  Note                     = {10.1007/BF02136827},
+  Number                   = {1},
+  Pages                    = {77-120},
+  Volume                   = {53},
+
+  Abstract                 = {In typical stochastic simulations, randomness is produced by generating a sequence of independent uniform variates (usually real-valued between 0 and 1, or integer-valued in some interval) and transforming them in an appropriate way. In this paper, we examine practical ways of generating (deterministic approximations to) such uniform variates on a computer. We compare them in terms of ease of implementation, efficiency, theoretical support, and statistical robustness. We look in particular at several classes of generators, such as linear congruential, multiple recursive, digital multistep, Tausworthe, lagged-Fibonacci, generalized feedback shift register, matrix, linear congruential over fields of formal series, and combined generators, and show how all of them can be analyzed in terms of their lattice structure. We also mention other classes of generators, like non-linear generators, discuss other kinds of theoretical and empirical statistical tests, and give a bibliographic survey of recent papers on the subject.},
+  Cds_grade                = {0},
+  Cds_keywords             = {random numbers},
+  Doi                      = {10.1007/BF02136827},
+  File                     = {l'e_94.pdf:l'e_94.pdf:PDF},
+  ISSN                     = {0254-5330},
+  Issue                    = {1},
+  Keyword                  = {Computer Science},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Springer Netherlands},
+  Timestamp                = {2011.04.18},
+  Url                      = {http://dx.doi.org/10.1007/BF02136827}
+}
+
+@InCollection{lepan_02,
+  Title                    = {{C}onstruction of {E}quidistributed {G}enerators {B}ased on {L}inear {R}ecurrences {M}odulo 2},
+  Author                   = {L'Ecuyer, Pierre and Panneton, François},
+  Booktitle                = {Monte Carlo and Quasi-Monte Carlo Methods 2000},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2002},
+  Editor                   = {Fang, Kai-Tai and Niederreiter, Harald and Hickernell, FredJ.},
+  Pages                    = {318--330},
+
+  Abstract                 = {Random number generators based on linear recurrences modulo 2 are widely used and appear in different forms, such as the simple and combined Tausworthe generators, the GFSR, and the twisted GFSR generators. Low-discrepancy point sets for quasi-Monte Carlo integration can also be constructed based on these linear recurrences. The quality of these generators or point sets is usually measured by certain equidistribution criteria. Combining two or more recurrences and adding linear output transformations can be used to improve the equidistribution properties.
+In this paper, we explore the combination of recurrences of different types, together with different kinds of linear output transformations. We have developed flexible software tools to make computer searches for good generators with respect to equidistribution criteria that consider selected low-dimensional projections. We provide several examples of search results.},
+  Cds_grade                = {0},
+  Cds_keywords             = {mersenne twister},
+  Doi                      = {10.1007/978-3-642-56046-0_21},
+  ISBN                     = {978-3-540-42718-6},
+  Keywords                 = {random numbers},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.07},
+  Url                      = {http://dx.doi.org/10.1007/978-3-642-56046-0_21}
+}
+
+@InProceedings{lepan_05,
+  Title                    = {{F}ast random number generators based on linear recurrences modulo 2: overview and comparison},
+  Author                   = {L'Ecuyer, P. and Panneton, F.},
+  Booktitle                = {Simulation Conference, 2005 Proceedings of the Winter},
+  Year                     = {2005},
+  Pages                    = {110--119},
+
+  Abstract                 = {Random number generators based on linear recurrences modulo 2 are among the fastest long-period generators currently available. The uniformity and independence of the points they produce, over their entire period length, can be measured by theoretical figures of merit that are easy to compute, and those having good values for these figures of merit are statistically reliable in general. Some of these generators can also provide disjoint streams and substreams efficiently. In this paper, we review the most interesting construction methods for these generators, examine their theoretical and empirical properties, and make comparisons.},
+  Cds_grade                = {4},
+  Cds_keywords             = {RNG, PRNG, Well, MT, Mersenne Twister, jump-ahead},
+  Cds_read                 = {2013-12-17},
+  Cds_review               = {performance comparison (CPU) of LFSR, WELL, MT, MRG
+--> jump-ahead time increases exponentially with number of states
+summary of properties of "good" RNGs},
+  Doi                      = {10.1109/WSC.2005.1574244},
+  File                     = {lepan_05.pdf:lepan_05.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.16}
+}
+
+@Article{lesim_07,
+  Title                    = {{T}est{U}01: {A} {C} library for empirical testing of random number generators},
+  Author                   = {Pierre L'Ecuyer and Richard Simard},
+  Journal                  = {ACM Trans. Math. Softw.},
+  Year                     = {2007},
+  Number                   = {4},
+  Pages                    = {22},
+  Volume                   = {33},
+
+  Abstract                 = {We introduce TestU01, a software library implemented in the ANSI C language, and offering a collection of utilities for the empirical statistical testing of uniform random number generators (RNGs). It provides general implementations of the classical statistical tests for RNGs, as well as several others tests proposed in the literature, and some original ones. Predefined tests suites for sequences of uniform random numbers over the interval (0, 1) and for bit sequences are available. Tools are also offered to perform systematic studies of the interaction between a specific test and the structure of the point sets produced by a given family of RNGs. That is, for a given kind of test and a given class of RNGs, to determine how large should be the sample size of the test, as a function of the generator's period length, before the generator starts to fail the test systematically. Finally, the library provides various types of generators implemented in generic form, as well as many specific generators proposed in the literature or found in widely used software. The tests can be applied to instances of the generators predefined in the library, or to user-defined generators, or to streams of random numbers produced by any kind of device or stored in files. Besides introducing TestU01, the article provides a survey and a classification of statistical tests for RNGs. It also applies batteries of tests to a long list of widely used RNGs.},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Doi                      = {http://doi.acm.org/10.1145/1268776.1268777},
+  File                     = {l'esim_07.pdf:l'esim_07.pdf:PDF},
+  ISSN                     = {0098-3500},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2010.07.23}
+}
+
+@InProceedings{lahrag_02,
+  Title                    = {{Fast System-Level Power Profiling for Battery-Efficient System Design}},
+  Author                   = {K. Lahiri and A. Raghunathan and S. Dey},
+  Booktitle                = {Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002 (CODES 2002)},
+  Year                     = {2002},
+  Pages                    = {157--162},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lahrag_01,
+  Title                    = {{Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures}},
+  Author                   = {K. Lahiri and A. Raghunathan and S. Dey},
+  Booktitle                = {Fourteenth International Conference on VLSI Design, 2001},
+  Year                     = {2001},
+  Pages                    = {29--35},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{laiasc_11,
+  Title                    = {{E}fficient {C}hannel-{A}daptive {MIMO} {D}etection {U}sing {J}ust-{A}cceptable {E}rror {R}ate},
+  Author                   = {I-Wei Lai and Ascheid, G. and Meyr, H. and Tzi-Dar Chiueh},
+  Journal                  = {Wireless Communications, IEEE Transactions on},
+  Year                     = {2011},
+  Number                   = {1},
+  Pages                    = {73-83},
+  Volume                   = {10},
+
+  Doi                      = {10.1109/TWC.2010.101810.091129},
+  ISSN                     = {1536-1276},
+  Keywords                 = {MIMO communication;matrix algebra;signal detection;telecommunication switching;CA-MIMO receiver;JAER criterion;SNR;SS detector;average computational cost;channel matrix;channel state information;channel-adaptive MIMO detection;channel-adaptive-MIMO receiver;detector-switching strategy;just-acceptable error rate;multiple-input multiple-output detection;signal-to-noise ratio;sophisticated sphere search MIMO detector;zero-forcing detection;AWGN;Bit error rate;Channel estimation;Detectors;MIMO;Receivers;MIMO detection;OFDM;error probability;just-acceptable error rate (JAER);maximum likelihood;sphere search;zero-forcing},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.07.03}
+}
+
+@InProceedings{lailia_09,
+  Title                    = {{S}earching in the {D}elta {L}attice: {A}n {E}fficient {MIMO} {D}etection for {I}terative {R}eceivers},
+  Author                   = {I-Wei Lai and Chun-Hao Liao and Witte, M. and Kammler, D. and Borlenghi, F. and Nikitopoulos, K. and Ramakrishnan, V. and Dan Zhang and Tzi-Dar Chiueh and Ascheid, G. and Meyr, H.},
+  Booktitle                = {Global Telecommunications Conference, 2009. GLOBECOM 2009. IEEE},
+  Year                     = {2009},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/GLOCOM.2009.5426133},
+  File                     = {lailia_09.pdf:lailia_09.pdf:PDF},
+  ISSN                     = {1930-529X},
+  Keywords                 = {MIMO communication;iterative methods;radio receivers;signal detection;MIMO detection;delta lattice;iterative receivers;multiple-input multiple-output detection;Communication standards;Costs;Decoding;Lattices;MIMO;Multiaccess communication;Signal processing;Space technology;Space time codes;Transmitting antennas},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.02}
+}
+
+@InProceedings{lai_10,
+  Title                    = {{A} high-speed low-power pipelined {V}iterbi {D}ecoder: breaking the {ACS}-bottleneck},
+  Author                   = {K. Y. T. Lai},
+  Booktitle                = {Green Circuits and Systems (ICGCS), 2010 International Conference on},
+  Year                     = {2010},
+  Month                    = {June},
+  Pages                    = {334-337},
+
+  Doi                      = {10.1109/ICGCS.2010.5543044},
+  File                     = {lai_10.pdf:lai_10.pdf:PDF},
+  Keywords                 = {Viterbi decoding;cellular arrays;convolutional codes;field programmable gate arrays;low-power electronics;(3,1,2) convolutional code decoding;FPGA;UMC 1P6M Standard Cell Library;add-compare-select recursion;chip area;close-loop;data rate;high throughput Viterbi decoder;high-speed low-power pipelined add select-compare method;power 15.7 mW;power consumption;voltage 1.8 V;Code standards;Convolutional codes;Decoding;Energy consumption;Field programmable gate arrays;Libraries;Pipelines;Power supplies;Throughput;Viterbi algorithm},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.18}
+}
+
+@InProceedings{lakkor_00,
+  Title                    = {{Synthesis of interconnection networks: A novel approach}},
+  Author                   = {V. Lakamraju and I. Koren and C. Krishna},
+  Booktitle                = {in Proc. 20th International Conference on Dependable Systems and Networks},
+  Year                     = {2000},
+  Month                    = jun,
+  Pages                    = {56-64},
+
+  Opturl                   = {citeseer.nj.nec.com/lakamraju00synthesis.html},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTlamm00,
+  Title                    = {{Implementation of High-Speed MAP Algorithms}},
+  Author                   = {H. Lamm},
+  School                   = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2000},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{lam_10,
+  Title                    = {{T}he {E}ra of {E}rror-{T}olerant {C}omputing},
+  Author                   = {Lammers, D.},
+  Journal                  = {IEEE Spectrum},
+  Year                     = {2010},
+  Number                   = {11},
+  Pages                    = {15},
+  Volume                   = {47},
+
+  Doi                      = {10.1109/MSPEC.2010.5605876},
+  File                     = {lam_10.pdf:lam_10.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.11.22}
+}
+
+@InProceedings{i.lhoe_01,
+  Title                    = {{Using the Mean Reliability as a Design and Stopping Criterion for Turbo Codes}},
+  Author                   = {I. Land and P. Hoeher},
+  Booktitle                = {Proc. Information Theory Workshop (ITW)},
+  Year                     = {2001},
+
+  Address                  = {Cairns, Australia},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lanhoe_00,
+  Title                    = {{Partially Systematic Rate 1/2 Turbo Codes}},
+  Author                   = {I. Land and P. Hoeher},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {287--290},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lanhoe_04,
+  Title                    = {{Computation of Symbol-Wise Mutual Information in Transmission Systems with LogAPP Decoders and Application to EXIT Charts}},
+  Author                   = {I. Land and P. Hoeher and S. Gligorevic},
+  Booktitle                = {Proceedings 5th Int. ITG Conf. on Source and Channel Coding (SCC)},
+  Year                     = {2004},
+  Pages                    = {195-202},
+
+  File                     = {lanhoe_04.pdf:lanhoe_04.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.08.10}
+}
+
+@InProceedings{lanhoe_00a,
+  Title                    = {{On the Interpretation of the APP Algorithm as an LLR Filter}},
+  Author                   = {I. Land and P. Hoeher and U. Sorger},
+  Booktitle                = {Proc. 2000 International Symposium in Information Theory (ISIT '00)},
+  Year                     = {2000},
+
+  Address                  = {Sorrento, Italy},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{Phdlandm94,
+  Title                    = {{Low-Power Architectural Design Methodologies}},
+  Author                   = {P. Landman},
+  School                   = {Electronics Research Laboratory, College of Engineering, University of California},
+  Year                     = {1994},
+
+  Address                  = {Berkeley, CA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lanpir_11,
+  Title                    = {{U}sing {SDRAM}s for two-dimensional accesses of long 2n x 2m-point {FFT}s and transposing},
+  Author                   = {S. Langemeyer and P. Pirsch and H. Blume},
+  Booktitle                = {Embedded Computer Systems (SAMOS), 2011 International Conference on},
+  Year                     = {2011},
+  Month                    = {July},
+  Pages                    = {242-248},
+
+  Doi                      = {10.1109/SAMOS.2011.6045467},
+  Keywords                 = {fast Fourier transforms;random-access storage;2D-FFT processing;SDRAM memories;address mapping scheme;bank interleaving method;double buffering;radar application;transposing;two-dimensional access;two-dimensional index-space;Bandwidth;Clocks;Field programmable gate arrays;Indexes;Pipelines;SDRAM;Throughput}
+}
+
+@InProceedings{lanbri_00,
+  Title                    = {{High level estimation of the area and power consumption of on-chip interconnects}},
+  Author                   = {D. Langen and A. Brinkman and U. R{\"}uckert},
+  Booktitle                = {Proc. 13th Annual IEEE International ASIC/SOC Conference, 2000},
+  Year                     = {2000},
+  Pages                    = {297--301},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Langlais1999,
+  Title                    = {{S}ynchronisation in the carrier recovery of a satellite link using turbo-codes with the help of tentative decisions},
+  Author                   = {Langlais, C. and Helard, M. and Lanoiselee, M.},
+  Booktitle                = {Turbo Codes in Digital Broadcasting - Could It Double Capacity? (Ref. No. 1999/165), IEE Colloquium on},
+  Year                     = {1999},
+  Pages                    = {5/1-5/7},
+
+  Doi                      = {10.1049/ic:19990785},
+  Keywords                 = {satellite links;C/N;S-curve;carrier phase errors;carrier recovery synchronisation;continuous mode transmission;cycle slip rate reduction;demodulator;global system performance;noise equivalent bandwidth;phase detector;satellite link;simulation results;synchronisation errors;tentative decisions;tracking mode;turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.07}
+}
+
+@InProceedings{Langlais1999a,
+  Title                    = {{S}ynchronisation in the carrier recovery of a satellite link using turbo-codes with the help of tentative decisions},
+  Author                   = {Langlais, C. and Helard, M. and Lanoiselee, M.},
+  Booktitle                = {IEE Colloquium on Turbo Codes in Digital Broadcasting - Could It Double Capacity? (Ref. No. 1999/165)},
+  Year                     = {1999},
+  Pages                    = {5/1-5/7},
+
+  Doi                      = {10.1049/ic:19990785},
+  Keywords                 = {satellite links;C/N;S-curve;carrier phase errors;carrier recovery synchronisation;continuous mode transmission;cycle slip rate reduction;demodulator;global system performance;noise equivalent bandwidth;phase detector;satellite link;simulation results;synchronisation errors;tentative decisions;tracking mode;turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.23}
+}
+
+@InProceedings{laneri_12,
+  Title                    = {{E}nd-{U}ser {D}riven {T}echnology {B}enchmarks {B}ased on {M}arket-{R}isk {W}orkloads},
+  Author                   = {Lankford, P. and Ericson, L. and Nikolaev, A.},
+  Booktitle                = {Proceedings of the 2012 SC Companion: High Performance Computing, Networking, Storage and Analysis (SCC)},
+  Year                     = {2012},
+
+  Address                  = {Salt Lake City, Utah, USA},
+  Month                    = nov,
+  Pages                    = {1171-1175},
+
+  Abstract                 = {Market risk management is a critical, resourceintensive task for financial trading firms. The industry relies heavily on innovation in technical infrastructure to increase the quality and quantity of risk management information and to reduce the cost of its production. However, until recently, the industry has lacked an independent standard for gauging the potential of new technologies to help. This changed when the STAC BenchmarkTM Council developed STAC-A2TM, a vendorindependent benchmark suite based on real-world market risk analysis workloads. It was specified by trading firms and made actionable by leading HPC vendors. Unlike vendor-developed benchmarks known to the authors, STAC-A2 satisfies all of the requirements important to end-user firms: relevance, neutrality, scalability, and completeness. Intel has demonstrated the utility of STAC-A2 for comparing successive generations of Intel® Xeon® processors.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/SC.Companion.2012.141},
+  File                     = {laneri_12.pdf:laneri_12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-04-22}
+}
+
+@Book{lap_07,
+  Title                    = {{W}hat {E}very {E}ngineer {S}hould {K}now about {S}oftware {E}ngineering},
+  Author                   = {Laplante, P.A.},
+  Publisher                = {CRC Press},
+  Year                     = {2007},
+  Series                   = {What Every Engineer Should Know},
+
+  ISBN                     = {9781420006742},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.23},
+  Url                      = {https://books.google.de/books?id=pFHYk0KWAEgC}
+}
+
+@InProceedings{lapgog_12,
+  Title                    = {{A}n analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding},
+  Author                   = {Lapotre, V. and Gogniat, G. and Diguet, J. and Haddad, S. and Baghdadi, A.},
+  Booktitle                = {Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on},
+  Year                     = {2012},
+  Month                    = {dec.},
+  Pages                    = {1 -6},
+
+  Doi                      = {10.1109/ReConFig.2012.6416728},
+  Keywords                 = {Computer architecture;Decoding;Equations;Iterative decoding;Programprocessors;Receivers;Throughput;channel coding;computer architecture;instructionsets;iterative decoding;multiprocessing systems;analytical heterogeneous multiprocessorflexible platform sizing approach;channel decoding;design-time;flexible basebandreceivers;flexible multiASIP hardware platform;formal representation;hardwareconfiguration;iterative demapping;multimode multistandard terminals;multiprocessorplatform;optimization potential;run-time;ASIP;Design-time;Multiprocessor;Platformsizing;Run-time;Self-adaptation;Wireless multistandards receiver;}
+}
+
+@Article{larfar_09,
+  Title                    = {{I}mplementation of a {M}arkov {C}hain {M}onte {C}arlo {B}ased {M}ultiuser/{MIMO} {D}etector},
+  Author                   = {Laraway, S. A. and Farhang-Boroujeny, B. },
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2009},
+  Number                   = {1},
+  Pages                    = {246--255},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TCSI.2008.925891},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@InProceedings{larpas_04,
+  Title                    = {{Implementation of a UMTS Turbo-Decoder on a dynamically reconfigurable platform}},
+  Author                   = {A. LaRosa and C. Passerone and F. Gregoretti and L. Lavagno},
+  Booktitle                = {Proc. 2004 Design, Automation and Test in Europe (DATE '04)},
+  Year                     = {2004},
+
+  Address                  = {Paris, France},
+  Month                    = feb,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Electronic{las_16,
+  Title                    = {{P}y{MP}},
+  Author                   = {Christoph Lassner},
+  Url                      = {https://github.com/classner/pymp},
+  Year                     = {2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22}
+}
+
+@Article{latfre_19,
+  Title                    = {{A} {H}ardware {C}ompensation {M}echanism for {E}mbedded {E}nergy {H}arvesting {E}mulation},
+  Author                   = {E. {Lattanzi} and V. {Freschi}},
+  Journal                  = {IEEE Embedded Systems Letters},
+  Year                     = {2019},
+
+  Month                    = {March},
+  Number                   = {1},
+  Pages                    = {25-28},
+  Volume                   = {11},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {low},
+  Ccr_key_original         = {8373685},
+  Ccr_keywords             = {enhancement of system emulators},
+  Ccr_relevance            = {low},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/LES.2018.2844469},
+  ISSN                     = {1943-0663},
+  Keywords                 = {TCS},
+  Keywords_original        = {embedded systems;energy harvesting;hardware-software codesign;power aware computing;networked context;achievable option;reproducible conditions;accurate experimental conditions;low-power device;tight time requirements;hardware-software embedded emulator thanks;hardware compensation circuit;efficient run-time correction;emulated voltage;software-based compensation;hardware compensation mechanism;embedded energy harvesting emulation;autonomous embedded systems;Emulation;Voltage measurement;Hardware;Resistors;Current measurement;Computational modeling;Load modeling;Embedded systems;emulation;energy harvesting (EH)},
+  Owner                    = {CCR}
+}
+
+@Article{latbei_08,
+  Title                    = {{A} {R}econfigurable {B}aseband {P}latform {B}ased on an {A}synchronous {N}etwork-on-{C}hip},
+  Author                   = {Lattard, D. and Beigne, E. and Clermidy, F. and Durand, Y. and Lemaire, R. and Vivet, P. and Berens, F.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2008},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {223--235},
+  Volume                   = {43},
+
+  Doi                      = {10.1109/JSSC.2007.909339},
+  File                     = {latbei_08.pdf:latbei_08.pdf:PDF},
+  Keywords                 = {FAUST},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InProceedings{lauyue_09,
+  Title                    = {{A} comparison of interior point and active set methods for {FPGA} implementation of model predictive control},
+  Author                   = {M. S. K. Lau and S. P. Yue and K. V. Ling and J. M. Maciejowski},
+  Booktitle                = {2009 European Control Conference (ECC)},
+  Year                     = {2009},
+  Month                    = {Aug},
+  Pages                    = {156-161},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [15]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.23919/ECC.2009.7074396},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {computational complexity;convergence;field programmable gate arrays;floating point arithmetic;predictive control;quadratic programming;stability;{FPGA};model predictive control;{MPC};quadratic programming problems;{QP} problem;interior point method;IPM;active set method;ASM;computational complexity;convergence speed;occasional instability;single precision floating point arithmetic;numerical error;Decision support systems;Europe;Field programmable gate arrays},
+  Owner                    = {CCR}
+}
+
+@InProceedings{laugle_91,
+  Title                    = {{ VLSI system design for the Control of high performance Combustion Engines}},
+  Author                   = {A.~Laudenbach and M.~Glesner and N.~Wehn},
+  Booktitle                = { IFIP Transactions A-1: VLSI91 },
+  Year                     = {1991},
+  Pages                    = {247--256},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{laugle_90,
+  Title                    = {{ VLSI-Signal Processing Methodology for the Control of High Performance Combustion Engines}},
+  Author                   = {A.~Laudenbach and M.~Glesner and N.~Wehn},
+  Booktitle                = {VLSI Signal Processing},
+  Year                     = {1990},
+  Pages                    = {73--82},
+  Publisher                = {IEEE Press, San Diego},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Electronic{arm_16,
+  Title                    = {{C}ycle {M}odels},
+  Author                   = {ARM Ldt.},
+  HowPublished             = {\url{https://developer.arm.com/products/system-design/cycle-models}},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-24}
+}
+
+@InProceedings{leber_04,
+  Title                    = {{B}readth first algorithms for {APP} detectors over {MIMO} channels},
+  Author                   = {Le Ruyet, D. and Bertozzi, T. and Ozbek, B.},
+  Booktitle                = {Proc. IEEE International Conference on Communications},
+  Year                     = {2004},
+  Month                    = jun,
+  Pages                    = {926--930},
+  Volume                   = {2},
+
+  Comment                  = {use APP information to reduce explored pathes},
+  File                     = {leber_04.pdf:leber_04.pdf:PDF},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.08.03}
+}
+
+@InProceedings{leawad_90,
+  Title                    = {{DSP/C: A Standard High-Level Language for DSP and Numeric Processing}},
+  Author                   = {K. W. Leary and W. Waddington},
+  Booktitle                = {Proc. of the International Conference on Acoustics, Speech and Signal Processing},
+  Year                     = {1990},
+  Organization             = {IEEE},
+  Pages                    = {1065--1068},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lebfan_00,
+  Title                    = {{P}ower {A}ware {P}age {A}llocation},
+  Author                   = {Lebeck, Alvin R. and Fan, Xiaobo and Zeng, Heng and Ellis, Carla},
+  Booktitle                = {Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems},
+  Year                     = {2000},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {105--116},
+  Publisher                = {ACM},
+  Series                   = {ASPLOS IX},
+
+  Acmid                    = {379007},
+  Doi                      = {10.1145/378993.379007},
+  ISBN                     = {1-58113-317-0},
+  Location                 = {Cambridge, Massachusetts, USA},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-13},
+  Url                      = {http://doi.acm.org/10.1145/378993.379007}
+}
+
+@InProceedings{lebgei_11,
+  Title                    = {{H}igh {F}requency {T}rading {A}cceleration {U}sing {FPGA}s},
+  Author                   = {Leber, Christian and Geib, Benjamin and Litz, Heiner},
+  Booktitle                = {Field Programmable Logic and Applications (FPL), 2011 International Conference on},
+  Year                     = {2011},
+  Month                    = sep,
+  Pages                    = {317-322},
+
+  Abstract                 = {This paper presents the design of an application specific hardware for accelerating High Frequency Trading applications. It is optimized to achieve the lowest possible latency for interpreting market data feeds and hence enable minimal round-trip times for executing electronic stock trades. The implementation described in this work enables hardware decoding of Ethernet, IP and UDP as well as of the FAST protocol which is a common protocol to transmit market feeds. For this purpose, we developed a microcode engine with a corresponding instruction set as well as a compiler which enables the flexibility to support a wide range of applied trading protocols. The complete system has been implemented in RTL code and evaluated on an FPGA. Our approach shows a 4x latency reduction in comparison to the conventional Software based approach.},
+  Cds_grade                = {0},
+  Cds_keywords             = {FPGA, trading},
+  Doi                      = {10.1109/FPL.2011.64},
+  File                     = {lebgei_11.pdf:lebgei_11.pdf:PDF},
+  Keywords                 = {finance, Review},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.09}
+}
+
+@InProceedings{lecsay_04,
+  Title                    = {{Efficient DSP Implementation of an LDPC Decoder}},
+  Author                   = {G. Lechner and J. Sayir and M. Rupp},
+  Booktitle                = {Proc. 2004 Conference on Acoustics, Speech, and Signal Processing (ICASSP '04)},
+  Year                     = {2004},
+  Month                    = may,
+  Pages                    = {IV-665--IV-668},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{leeeom_17,
+  Title                    = {23.2 {A} 5{G}b/s/pin 8{G}b {LPDDR}4{X} {SDRAM} with power-isolated {LVSTL} and split-die architecture with 2-die {ZQ} calibration scheme},
+  Author                   = {C. K. Lee and Y. J. Eom and J. H. Park and J. Lee and H. R. Kim and K. Kim and Y. Choi and H. J. Chang and J. Kim and J. M. Bang and S. Shin and H. Park and S. Park and Y. R. Choi and H. Lee and K. H. Jeon and J. Y. Lee and H. J. Ahn and K. H. Kim and J. S. Kim and S. Chang and H. R. Hwang and D. Kim and Y. H. Yoon and S. H. Hyun and J. Y. Park and Y. G. Song and Y. S. Park and H. J. Kwon and S. J. Bae and T. Y. Oh and I. D. Song and Y. C. Bae and J. H. Choi and K. I. Park and S. J. Jang and G. Y. Jin},
+  Booktitle                = {2017 IEEE International Solid-State Circuits Conference (ISSCC)},
+  Year                     = {2017},
+  Month                    = {Feb},
+  Pages                    = {390-391},
+
+  Doi                      = {10.1109/ISSCC.2017.7870425},
+  Keywords                 = {DRAM chips;calibration;low-power electronics;LPDDR4X SDRAM;LPDDR4X memory;PI-LVSTL;ZQ calibration scheme;enhanced power-efficiency;low-power mobile DRAM;low-power mobile applications;low-power system designs;power-isolated low-voltage-swing terminated logic;split-die architecture;Calibration;Capacitance;Equalizers;Impedance;Mobile applications;SDRAM},
+  Owner                    = {MJ},
+  Timestamp                = {2017-09-13}
+}
+
+@InProceedings{leekim_15,
+  Title                    = {{A}daptive-latency {DRAM}: {O}ptimizing {DRAM} timing for the common-case},
+  Author                   = {D. Lee and Y. Kim and G. Pekhimenko and S. Khan and V. Seshadri and K. Chang and O. Mutlu},
+  Booktitle                = {High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on},
+  Year                     = {2015},
+  Month                    = {Feb},
+  Pages                    = {489-501},
+
+  Doi                      = {10.1109/HPCA.2015.7056057},
+  Keywords                 = {DRAM chips;field programmable gate arrays;integrated circuit reliability;integrated circuit testing;AL-DRAM;DRAM chip;DRAM standard;FPGA-based testing platform;access latency;adaptive-latency DRAM;memory-intensive workloads;minimum latency restrictions;process variation;temperature 55 C;temperature 85 C;timing parameters;DRAM chips;Reliability;Temperature dependence;Temperature measurement;Testing;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-14}
+}
+
+@Article{leeche_09,
+  Title                    = {{H}ierarchical {S}egmentation for {H}ardware {F}unction {E}valuation},
+  Author                   = {Dong-U Lee and Cheung, R.C.C. and Wayne Luk and Villasenor, J.D.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2009},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {103 -116},
+  Volume                   = {17},
+
+  Abstract                 = {This paper presents a method for evaluating functions based on piecewise polynomial approximations (splines) with a hierarchical segmentation scheme targeting hardware implementation. The methodology provides significant reduction in table size compared to traditional uniform segmentation approaches. The use of hierarchies involving uniform splines and splines with size varying by powers of two is particularly well suited for the coverage of nonlinear regions. The segmentation step is automated and supports user-supplied precision requirements and approximation method. Bit-widths of the coefficients and arithmetic operators are optimized to minimize circuit area and enable a guarantee of 1 unit in the last place (ulp) accuracy at the output. A coefficient transformation technique is also described, which significantly reduces the dynamic ranges of the fixed-point polynomial coefficients. The hierarchical segmentation method is illustrated using a set of functions including -(x/2) log2 x, cos-1(x), radic(-ln(x)) , a high-degree rational function, ln(1+x), and 1/(1+x). Various degree-1 and degree-2 approximation results for precisions between 8 to 24 bits are given. Hardware realizations are demonstrated on a Xilinx Virtex-4 field-programmable gate array (FPGA).},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TVLSI.2008.2003165},
+  File                     = {leeche_09.pdf:leeche_09.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.23}
+}
+
+@InProceedings{leeluk_03,
+  Title                    = {{H}ierarchical {S}egmentation {S}chemes for {F}unction {E}valuation},
+  Author                   = {Dong-U Lee and Wayne Luk and John Villasenor and Peter Y.K. Cheung},
+  Booktitle                = {Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on},
+  Year                     = {2003},
+  Month                    = {15-17},
+  Pages                    = { 92 - 99},
+
+  Abstract                 = {This paper presents a method for evaluating functions based on piecewise polynomial approximation with a novel hierarchical segmentation scheme. The use of a novel hierarchy scheme of uniform segments and segments with size varying by powers of two enables us to approximate non-linear regions of a function particularly well. This partitioning is automated: efficient look-up tables and their coefficients are generated for a given function, input range, order of the polynomials, desired accuracy and finite precision constraints. We describe an algorithm to find the optimum number of segments and the placement of their boundaries, which is used to analyze the properties of a function and to benchmark out approach. Our method is illustrated using three non-linear compound functions, radic;-log(x), x log(x) and a high order rational function. We present results for various operand sizes between 8 and 24 bits for first and second order polynomial approximations.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPT.2003.1275736},
+  File                     = {leeway_03.pdf:leeway_03.pdf:PDF;leeluk_03.pdf:leeluk_03.pdf:PDF},
+  ISSN                     = { },
+  Keywords                 = { finite precision constraints; function evaluation; hierarchical segmentation scheme; high order rational function; look-up tables; nonlinear compound functions; optimum segment boundaries; piecewise polynomial approximation; polynomial approximations; function evaluation; piecewise polynomial techniques; rational functions; table lookup;},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.26}
+}
+
+@Article{leeluk_05,
+  Title                    = {{A} {H}ardware {G}aussian {N}oise {G}enerator {U}sing the {W}allace {M}ethod},
+  Author                   = {Dong-U Lee and Luk, W. and Villasenor, J.D. and Guanglie Zhang and Leong, P.H.W.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2005},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = { 911 - 920},
+  Volume                   = {13},
+
+  Abstract                 = {We describe a hardware Gaussian noise generator based on the Wallace method used for a hardware simulation system. Our noise generator accurately models a true Gaussian probability density function even at high sigma; values. We evaluate its properties using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test and 2) an application for decoding of low-density parity-check (LDPC) codes. Our design is implemented on a Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) at 155 MHz; it takes up 3% of the device and produces 155 million samples per second, which is three times faster than a 2.6-GHz Pentium-IV PC. Another implementation on a Xilinx Spartan-III XC3S200E-5 FPGA at 106 MHz is two times faster than the software version. Further improvement in performance can be obtained by concurrent execution: 20 parallel instances of the noise generator on an XC2V4000-6 FPGA at 115 MHz can run 51 times faster than software on a 2.6-GHz Pentium-IV PC.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TVLSI.2005.853615},
+  ISSN                     = {1063-8210},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.20}
+}
+
+@Article{leevil_06,
+  Title                    = {{A} {H}ardware {G}aussian {N}oise {G}enerator {U}sing the {B}ox-{M}uller {M}ethod and {I}ts {E}rror {A}nalysis},
+  Author                   = {Dong-U Lee and Villasenor, J.D. and Wayne Luk and Leong, P.H.W.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {2006},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {659 -671},
+  Volume                   = {55},
+
+  Abstract                 = {We present a hardware Gaussian noise generator based on the Box-Muller method that provides highly accurate noise samples. The noise generator can be used as a key component in a hardware-based simulation system, such as for exploring channel code behavior at very low bit error rates, as low as 10-12 to 10-13. The main novelties of this work are accurate analytical error analysis and bit-width optimization for the elementary functions involved in the Box-Muller method. Two 16-bit noise samples are generated every clock cycle and, due to the accurate error analysis, every sample is analytically guaranteed to be accurate to one unit in the last place. An implementation on a Xilinx Virtex-4 XC4VLX100-12 FPGA occupies 1,452 slices, three block RAMs, and 12 DSP slices, and is capable of generating 750 million samples per second at a clock speed of 375 MHz. The performance can be improved by exploiting concurrent execution: 37 parallel instances of the noise generator at 95 MHz on a Xilinx Virtex-II Pro XC2VP100-7 FPGA generate seven billion samples per second and can run over 200 times faster than the output produced by software running on an Intel Pentium-4 3 GHz PC. The noise generator is currently being used at the Jet Propulsion Laboratory, NASA to evaluate the performance of low-density parity-check codes for deep-space communications},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TC.2006.81},
+  File                     = {leevil_06.pdf:leevil_06.pdf:PDF},
+  ISSN                     = {0018-9340},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.23}
+}
+
+@TechReport{leekub_12,
+  Title                    = {{T}he {T}erra{S}warm {R}esearch {C}enter ({TSRC}) ({A} {W}hite {P}aper)},
+  Author                   = {Edward A. Lee and John D. Kubiatowicz and Jan M. Rabaey and Alberto L. Sangiovanni-Vincentelli and Sanjit A. Seshia and John Wawrzynek and David Blaauw and Prabal Dutta and Kevin Fu and Carlos Guestrin and Roozbeh Jafari and Doug Jones and Vijay Kumar and Richard Murray and George Pappas and Anthony Rowe and Carl M. Sechen and Tajana Simunic Rosing and Ben Taskar and David Wessel},
+  Institution              = {EECS Department, University of California, Berkeley},
+  Year                     = {2012},
+
+  Address                  = {Berkeley},
+  Month                    = nov,
+  Note                     = {\url{http://www.eecs.berkeley.edu/Pubs/TechRpts/2012/EECS-2012-207.html}},
+  Number                   = {UCB/EECS-2012-207},
+  Type                     = {Technical Report},
+
+  Abstract                 = {The TerraSwarm Research Center (TSRC), announced on October 31, 2012, will be addressing the huge potential (and associated risks) of pervasive integration of smart, networked sensors and actuators into our connected world. A five-year grant is being awarded by the industry members of the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA) as a part of the Focus Center Research Program (FCRP).},
+  Cds_grade                = {0},
+  File                     = {leekub_12.pdf:leekub_12.pdf:PDF},
+  Keywords                 = {CHPC},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.07},
+  Url                      = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2012/EECS-2012-207.html}
+}
+
+@Article{leerab_14,
+  Title                    = {{T}he {S}warm at the {E}dge of the {C}loud},
+  Author                   = {Lee, E.A and Rabaey, J. and Hartmann, B. and Kubiatowicz, J. and Pister, K. and Sangiovanni-Vincentelli, A and Seshia, S.A and Wawrzynek, J. and Wessel, D. and Rosing, T.S. and Blaauw, D. and Dutta, P. and Fu, K. and Guestrin, C. and Taskar, B. and Jafari, R. and Jones, D. and Kumar, V. and Mangharam, R. and Pappas, G.J. and Murray, R.M. and Rowe, A},
+  Journal                  = {Design Test, IEEE},
+  Year                     = {2014},
+
+  Month                    = {June},
+  Number                   = {3},
+  Pages                    = {8-20},
+  Volume                   = {31},
+
+  Abstract                 = {The paper explains how to use sensors as the eyes, ears, hands, and feet for the cloud. This paper describes the opportunities and challenges when integrating sensors and cloud computing.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/MDAT.2014.2314600},
+  File                     = {leerab_14.pdf:leerab_14.pdf:PDF},
+  ISSN                     = {2168-2356},
+  Keywords                 = {CHPC},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.07}
+}
+
+@Unpublished{leeyan_09,
+  Title                    = {{R}econfigurable {A}rchitecture {D}esign of {M}otion {C}ompensation for {M}ulti-{S}tandard {V}ideo {C}oding},
+  Author                   = {Gwo-Giun Lee and Wei-Chiaho Yang and Min-Shan Wu and He-Yuan Lin},
+
+  Month                    = nov,
+  Year                     = {2009},
+
+  Abstract                 = {This paper proposes a reconfigurable video decoder architecture of motion compensator of video decoder for multi-standard coding including MPEG-2, MPEG-4 and H.264. Through top-down design methodology, the analysis and commonality extraction of the motion compensation algorithm are performed among the multiple standards. In addition, the bandwidth reduction strategies are also adopted to reduce the memory access times and power consumption of motion compensation operations for high bandwidth requirement. The proposed design is synthesized using TMSC 0.18um technology library and can operate at 108HMz to achieve the real time motion compensation coding of 1920x1088 at 30 frames per second.},
+  Cds_grade                = {3},
+  Cds_keywords             = {H.264, motion compensation, Video, VLSI, implementation, ASIC},
+  Cds_read                 = {2009-11-23},
+  Cds_review               = {All in all, a sophisticated implementation is presented in the paper and the reader is able to understand what you have done. State-of-the-art is presented very well in the introduction. Nevertheless, there are some points that should be either addressed in more detail or be removed completely from the text to further clarify the paper:
+- II A: The tap sequences for H.264 and MPEG-4 do not seem to be similar to me, as you write, and are not even containing the same number of elements - you should remove this comment or elaborate more on that. Unfortunately Figure 1 is very low quality so that I cannot see what is happening there.
+- II B: I am not sure if giving a relative throughput gain (e.g. up to 15 % of data transmission saving) would be more helpful, containing the overlap data reuse.
+- III: In the first paragraph, you reference control signals of the interpolator - you should either give an overview over the possible configurations or rewrite this in an more abstract way.
+- III A: very good explanation of how your implementation works, no more comments on that
+- III B: Compared to e.g. II A, B and C, this paragraph contains too little information, in my opinion. As I think this is hard work you've done implementing the multiplexers in the right way, you should elaborate a bit more on that and at least show different expamples in order to clarify why the multiplexers are at the right positions.
+- IV: You write that you've checked against the C model, but I miss some information about how many frames you've checked and how reliable your testing is - I cannot imagine that you've checked more that a few blocks with Verilog-XL.
+- V: You should write one or more sentence about you top-down methodology and what is meant in detail. Is it starting from algorithm's point of view or does it mean from function software model to working hardware implementation?
+- Table III: should be adder"s" here
+- Table IV: good comparison and evaluation against previous implementations
+
+Altogether a working implementation of MC for different video standards is presented in an understandable way. If you write some more about your validation strategy and the reconfigurable part of your design and therefore omit some points in II, the paper would be even more interesting for implementation guys, I think.},
+  File                     = {leeyan_09.pdf:leeyan_09.pdf:PDF},
+  Keywords                 = {Review},
+  Owner                    = {CdS},
+  Timestamp                = {2009.11.23},
+  Url                      = {http://www.epapers.org/iscas2010/ESR/reviewer_main.php?PHPSESSID=ac823fe5544c9c259f89150d67d5c353}
+}
+
+@Article{lee_03,
+  Title                    = {{H}igh-speed {VLSI} architecture for parallel {R}eed-{S}olomon decoder},
+  Author                   = {Hanho Lee},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2003},
+
+  Month                    = apr,
+  Number                   = {2},
+  Pages                    = {288-294},
+  Volume                   = {11},
+
+  Abstract                 = {This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. A parallel processing architecture results in speed-ups of as much as or more than 10 Gb, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean algorithm block. The parallel RS decoders have been designed and implemented with the 0.13-/spl mu/m CMOS standard cell technology in a supply voltage of 1.1 V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gb/s and beyond, could be implemented. The proposed channel = 4 parallel RS decoder operates at a clock frequency of 770 MHz and has a data processing rate of 26.6 Gb/s.},
+  Cds_grade                = {0},
+  Cds_keywords             = {VLSI, high-speed, high-throughput, Reed-Solomon, RS, parallel, Euclidean Algorithm, Galois field multiplier, FFM},
+  Cds_read                 = {2009-02-13},
+  Cds_review               = {very detailed
+shows pipelined modified Euclidean Algorithm implementation
+shows pipelined fully-parallel implementation of Galois field multiplier (FFM)},
+  Date-added               = {2008-08-08 10:25:12 +0200},
+  Date-modified            = {2008-08-08 10:26:05 +0200},
+  Doi                      = {10.1109/TVLSI.2003.810782},
+  File                     = {lee_03.pdf:lee_03.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Article{lee_01a,
+  Title                    = {{A} {VLSI} design of a high-speed {R}eed-{S}olomon decoder},
+  Author                   = {Hanho Lee},
+  Journal                  = {ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International},
+  Year                     = {2001},
+  Pages                    = {316-320},
+
+  Abstract                 = {Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurred in the transmission process. This paper presents a VLSI implementation of a high-speed 8-error correcting, RS(255,239) decoder architecture using a modified Euclidean algorithm for communication systems. The RS decoder has been designed and implemented with a 0.16-micron CMOS standard cell technology with a supply voltage of 1.5 V. The results show that the proposed RS decoder operates at a clock frequency of 670 MHz and has a data processing rate of 5.36 Gbit/s},
+  Booktitle                = {ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International},
+  Cds_grade                = {0},
+  Cds_keywords             = {BCH, CMOS digital integrated circuits, Reed-Solomon codes, VLSI, decoding, digital signal processing chips, error correction codes, high-speed integrated circuits, integrated circuit design, pipeline processing0.16 micron, 1.5 V, 5.36 Gbit/s, 670 MHz, 8-error correcting decoder architecture, CMOS standard cell technology, Reed-Solomon decoder, VLSI design, VLSI implementation, communication systems, high-speed RS decoder architecture, modified Euclidean algorithm},
+  Doi                      = {10.1109/ASIC.2001.954719},
+  File                     = {lee_01a.pdf:lee_01a.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.06.22}
+}
+
+@Article{leecha_10,
+  Title                    = {{A} {L}ow-{P}ower {DSP} for {W}ireless {C}ommunications},
+  Author                   = {Hyunseok Lee and Chakrabarti, C. and Mudge, T.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2010},
+  Number                   = {9},
+  Pages                    = {1310--1322},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/TVLSI.2009.2023547},
+  File                     = {leecha_10.pdf:leecha_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Review                   = {SODA-II},
+  Timestamp                = {2011.08.19}
+}
+
+@Article{leelee_06,
+  Title                    = {{I}terative detection and decoding with an improved {V}-{BLAST} for {MIMO}-{OFDM} systems},
+  Author                   = {Henuchul Lee and Byeongsi Lee and Inkyu Lee},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2006},
+
+  Month                    = {March},
+  Number                   = {3},
+  Pages                    = {504-513},
+  Volume                   = {24},
+
+  Doi                      = {10.1109/JSAC.2005.862400},
+  File                     = {leelee_06.pdf:leelee_06.pdf:PDF},
+  ISSN                     = {0733-8716},
+  Keywords                 = {MIMO systems;OFDM modulation;antenna arrays;broadband antennas;computational complexity;fading channels;filtering theory;interference suppression;iterative decoding;least mean squares methods;radio receivers;signal detection;space-time codes;turbo codes;wireless channels;IDD;OFDM;V-BLAST;coded layered space-time architecture;computational complexity;frequency-selective fading radio channel;hard decision;iterative detection-decoding scheme;linear minimum mean-square error filtering;multiple-input-multiple-output system;nonlinear interference cancellation;orthogonal frequency-division multiplexing;spectral efficiency;turbo-MIMO approach;vertical Bell Labs layered space-time receiver;wideband transmission;wireless system;Fading;Filtering;Frequency division multiplexing;Interference cancellation;Iterative decoding;MIMO;Nonlinear filters;OFDM;Receivers;Wideband;Iterative detection and decoding (IDD);multiple-input&#8211;multiple-output (MIMO) systems;orthogonal frequency-division multiplexing (OFDM);vertical Bell Labs layered space&#8211;time (V-BLAST)},
+  Owner                    = {MH},
+  Timestamp                = {2016-03-29}
+}
+
+@InProceedings{leecha_15,
+  Title                    = {{P}owering the {I}o{T}: {S}torage-less and converter-less energy harvesting},
+  Author                   = {H. G. {Lee} and N. {Chang}},
+  Booktitle                = {The 20th Asia and South Pacific Design Automation Conference},
+  Year                     = {2015},
+  Month                    = {Jan},
+  Pages                    = {124-129},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7058992},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/ASPDAC.2015.7058992},
+  ISSN                     = {2153-6961},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;Internet of Things;level meters;maximum power point trackers;storage-less energy harvesting;converter-less energy harvesting;Internet of Things;IoT;maximum power point tracking;MPPT;power converters;management technique;ultraviolet level meter;skin protect;SmartPatch;Phasor measurement units;Computer architecture;Energy harvesting;Microprocessors;Switches;Batteries;Radiation detectors},
+  Owner                    = {CCR}
+}
+
+@Article{lee_01,
+  Title                    = {{Modification of the MAP Algorithm for Memory Savings}},
+  Author                   = {I. Lee},
+  Journal                  = {Signal Processing, IEEE Transactions on},
+  Year                     = {2005},
+  Pages                    = {1147--1150},
+  Volume                   = {53},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{leeson_00,
+  Title                    = {{A New Architecture for the Fast Viterbi Algorithm}},
+  Author                   = {I. Lee and J. L. Sonntag},
+  Booktitle                = {Proc. 2000 Global Telecommunications Conference (GLOBECOM '00)},
+  Year                     = {2000},
+
+  Address                  = {San Francisco, CA, USA},
+  Month                    = nov,
+  Pages                    = {1664--1668},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{leetho_05,
+  Title                    = {{Memory-Efficient Decoding of LDPC Codes}},
+  Author                   = {J. Lee and J. Thorpe},
+  Booktitle                = {Proc. 2005 IEEE International Symposium on Information Theory (ISIT'05)},
+  Year                     = {2005},
+
+  Address                  = {Adelaide, Australia},
+  Month                    = sep,
+  Pages                    = {459--463},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{leesun_11,
+  Title                    = {{L}ow complexity soft-decision demapper for {DVB}-{S}2 using phase selection method},
+  Author                   = {Lee, Jea Hack and Sunwoo, Myung Hoon and Kim, Pan Soo and Chang, Dae-Ig},
+  Booktitle                = {Proceedings of the 5th International Conference on Ubiquitous Information Management and Communication},
+  Year                     = {2011},
+  Organization             = {ACM},
+  Pages                    = {45},
+
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-12}
+}
+
+@Article{leepar_10,
+  Title                    = {{A} {M}echanism for {D}ependence of {R}efresh {T}ime on {D}ata {P}attern in {DRAM}},
+  Author                   = {M. J. Lee and K. W. Park},
+  Journal                  = {IEEE Electron Device Letters},
+  Year                     = {2010},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {168-170},
+  Volume                   = {31},
+
+  Doi                      = {10.1109/LED.2009.2038243},
+  ISSN                     = {0741-3106},
+  Keywords                 = {DRAM chips;pattern recognition;DRAM chips;cell leakage mechanism;data pattern;dynamic random access memory;refresh time;Bit-line sense amplifier (BLSA);cell leakage;data pattern;offset;refresh time (tREF);sensing noise},
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-14}
+}
+
+@Article{lee_04,
+  Title                    = {{O}ption pricing by transform methods: extensions, unification and error control},
+  Author                   = {Lee, Roger W},
+  Journal                  = {Journal of Computational Finance},
+  Year                     = {2004},
+  Number                   = {3},
+  Pages                    = {51--86},
+  Volume                   = {7},
+
+  Owner                    = {Brugger},
+  Publisher                = {RISK PUBLICATIONS},
+  Timestamp                = {2014.08.21}
+}
+
+@InProceedings{leesak_00,
+  Title                    = {{Run-Time Voltage Hopping for Low-Power Real-Time Systems}},
+  Author                   = {S. Lee and T. Sakurai},
+  Booktitle                = {Proc. 2000 Design Automation Conference (DAC '00)},
+  Year                     = {2000},
+
+  Address                  = {Los Angeles, California, USA},
+  Month                    = jun,
+  Pages                    = {806--809},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{leegoe_08,
+  Title                    = {{F}orward error correction decoding for {W}i{MAX} and 3{GPP} {LTE} modems},
+  Author                   = {Lee, Seok-Jun and Goel, Manish and Zhu, Yuming and Ren, Jing-Fei and Sun, Yang},
+  Booktitle                = {Proc. 42nd Asilomar Conference on Signals, Systems and Computers},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {1143--1147},
+
+  Doi                      = {10.1109/ACSSC.2008.5074593},
+  File                     = {leegoe_08.pdf:leegoe_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.15}
+}
+
+@Article{leesha_05,
+  Title                    = {{A}rea-efficient high-throughput {MAP} decoder architectures},
+  Author                   = {Seok-Jun Lee and Shanbhag, N. R. and Singer, A. C.},
+  Journal                  = {IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS},
+  Year                     = {2005},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {921--933},
+  Volume                   = {13},
+
+  Doi                      = {10.1109/TVLSI.2005.853604},
+  File                     = {leesha_05.pdf:leesha_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{leesha_03,
+  Title                    = {{A Low-Power VLSI Architecture for Turbo Decoding}},
+  Author                   = {S.-J. Lee and N. R. Shanbhag and A. C. Singer},
+  Booktitle                = {Proc. 2003 International Symposium on Low Power Electronics and Design (ISLPED '03)},
+  Year                     = {2003},
+
+  Address                  = {Seoul, Korea},
+  Month                    = aug,
+  Pages                    = {366--371},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{leesha_03a,
+  Title                    = {{A} low-power {VLSI} architecture for turbo decoding},
+  Author                   = {Seok-Jun Lee and Shanbhag, N. R. and Singer, A. C. },
+  Booktitle                = {Proc. Int. Symp. Low Power Electronics and Design ISLPED '03},
+  Year                     = {2003},
+  Pages                    = {366--371},
+
+  Doi                      = {10.1109/LPE.2003.1231921},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{leekum_08,
+  Title                    = {{S}oft-{D}ecision {D}ecoding of {R}eed-{S}olomon {C}odes {U}sing {S}uccessive {E}rror-and-{E}rasure {D}ecoding},
+  Author                   = {Soo-Woong Lee and Kumar, B. },
+  Booktitle                = {Proc. IEEE Global Telecommunications Conf. IEEE GLOBECOM 2008},
+  Year                     = {2008},
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/GLOCOM.2008.ECP.588},
+  File                     = {leekum_08.pdf:leekum_08.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ASD},
+  Owner                    = {Scholl},
+  Review                   = {Successive Errors and Erasures Decoding Algorithmus, RS(255,239) ca 1,3 db gain, Abschaetzung für kleine FER},
+  Timestamp                = {2011.09.15}
+}
+
+@InProceedings{leecho_10,
+  Title                    = {{ERSA}: {E}rror {R}esilient {S}ystem {A}rchitecture for probabilistic applications},
+  Author                   = {Leem, L. and Cho, H and Bau, J. and Jacobson, Q. A. and Mitra, S.},
+  Booktitle                = {Proc. Design, Automation \& Test in Europe Conf. \& Exhibition (DATE)},
+  Year                     = {2010},
+  Pages                    = {1560--1565},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Mitra
+- ERSA},
+  File                     = {leecho_10.pdf:leecho_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@PhdThesis{Phdlehni11,
+  Title                    = {{I}mplementation and {S}imulation {A}spects of {A}dvanced {N}on-{B}inary {I}terative {C}oding {S}chemes},
+  Author                   = {Timo Lehnigk-Emden},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2011},
+
+  File                     = {Phdlehni11.pdf:Phdlehni11.pdf:PDF},
+  Keywords                 = {LDPC, Turbo, 3D, non-binary, Simulationen, Simulation Acceleration},
+  Owner                    = {Lehnigk},
+  Timestamp                = {2011.09.30}
+}
+
+@MastersThesis{MTlehni05,
+  Title                    = {{Decoding algorithm for Low-Density Parity-Check Codes under quantization effects}},
+  Author                   = {T. Lehnigk-Emden},
+  School                   = {{Microelectronic System Design Reseach Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern}},
+  Year                     = {2005},
+  Month                    = feb,
+
+  Optnote                  = {Diplomarbeit},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{lehall_10,
+  Title                    = {{P}rocessor and {S}ystem-on-{C}hip {S}imulation},
+  Author                   = {Timo Lehnigk-Emden and Matthias Alles and Torben Brack and Norbert Wehn},
+  Chapter                  = {Simulation Acceleration in Wireless Baseband Processing},
+  Editor                   = {Rainer Leupers and Olivier Temam},
+  Pages                    = {309--324},
+  Publisher                = {Springer},
+  Year                     = {2010},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2010.10.20}
+}
+
+@InProceedings{lehall_09,
+  Title                    = {3{D} {D}uo {B}inary {T}urbo {D}ecoder {H}ardware {I}mplementation},
+  Author                   = {Timo Lehnigk-Emden and Matthias Alles and Norbert Wehn},
+  Booktitle                = {Proc. 2009 ICT Mobile and Wireless Communications Summit (ICT-Mobile Summit 2009)},
+  Year                     = {2009},
+
+  Address                  = {Santander, Spain},
+  Month                    = jun,
+
+  File                     = {lehall_09.pdf:lehall_09.pdf:PDF},
+  Owner                    = {lehnigk},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{lehbra_06,
+  Title                    = {{P}erformance and {C}omplexity {A}nalysis of advanced {C}oding {S}chemes in the 4{MORE} {P}roject},
+  Author                   = {T. Lehnigk-Emden and T. Brack and M. Alles and N. Wehn and M. Hamon and P. Penard and R. Legouable and F. Berens},
+  Booktitle                = {Proc. 2006 IST Mobile and Wireless Communication Summit},
+  Year                     = {2006},
+
+  Address                  = {Mykonos, Greece},
+  Month                    = jun,
+
+  File                     = {lehbra_06.pdf:lehbra_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lehbre_07,
+  Title                    = {{E}nergy {C}onsumption of {C}hannel {D}ecoders for {OFDM}-based {UWB} {S}ystems},
+  Author                   = {Timo Lehnigk-Emden and Christian Brehm and Torben Brack and Norbert Wehn and Friedbert Berens and Cem Derdiyok},
+  Booktitle                = {Proc. IEEE International Conference on Ultra-Wideband ICUWB 2007},
+  Year                     = {2007},
+
+  Address                  = {Singapore},
+  Month                    = sep # { 24--26,},
+  Pages                    = {447--452},
+
+  File                     = {lehbre_07.pdf:lehbre_07.pdf:PDF},
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.29}
+}
+
+@InProceedings{lehwas_08,
+  Title                    = {{A}nalysis of {I}teration {C}ontrol for {T}urbo {D}ecoders in {T}urbo {S}ynchronization {A}pplications},
+  Author                   = {Timo Lehnigk-Emden and Uwe Wasenmüller and Christina Gimmler and Norbert Wehn},
+  Booktitle                = {Advances in Radio Science},
+  Year                     = {2008},
+
+  Address                  = {Kleinheubach, Germany},
+  Month                    = sep,
+  Pages                    = {139--144},
+  Volume                   = {7},
+
+  File                     = {lehwas_08.pdf:lehwas_08.pdf:PDF},
+  Owner                    = {lehnigk},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{lehweh_10,
+  Title                    = {{C}omplexity {E}valuation of {N}on-binary {G}alois {F}ield {LDPC} {C}ode {D}ecoders},
+  Author                   = {Timo Lehnigk-Emden and Norbert Wehn},
+  Booktitle                = {Proc. 6th International Symposium on Turbo Codes \& Iterative Information Processing (ISTC'2010)},
+  Year                     = {2010},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+
+  Abstract                 = {Forward error correction is an essential part of digital communication systems. Non-binary low-density parity-check (NB-LDPC) codes have an excellent communications performance for short block lengths. The higher the field size is, the better the communications performance is. Non-binary LDPC codes can outperform all other state-of-the-art code classes.
+However, the algorithmic decoding complexity grows with the field size. For an intended, future use of these codes in real systems, an efficient hardware implementation is mandatory. Hardware architectures for binary LDPC codes are well investigated, but efficient implementation of non-binary LDPC decoders is still an open field.
+To the best of our knowledge, this paper studies for the first time the hardware implementation costs for non-binary LDPC decoders with Galois field sizes of 4, 16 and 256 on FPGA and a 65nm ASIC technology.},
+  Keywords                 = {LDPC; non-binary; implementation; higher field; Galois field; decoder; complexity; hardware; FPGA; ASIC; 65nm}
+}
+
+@InProceedings{lehweh_08,
+  Title                    = {{E}nhanced {I}teration {C}ontrol for {U}ltra {L}ow {P}ower {LDPC} {D}ecoding},
+  Author                   = {Timo Lehnigk-Emden and Norbert Wehn},
+  Booktitle                = {Proc. 2008 ICT Mobile and Wireless Communications Summit (ICT-Mobile Summit 2008)},
+  Year                     = {2008},
+
+  Address                  = {Stockholm, Sweden},
+  Month                    = jun,
+
+  File                     = {lehweh_08.pdf:lehweh_08.pdf:PDF},
+  Owner                    = {lehnigk},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{lehlil_07,
+  Title                    = {{F}ault {T}olerance {A}nalysis of {N}o{C} {A}rchitectures},
+  Author                   = {Lehtonen, T. and Liljeberg, P. and Plosila, J. },
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2007},
+  Year                     = {2007},
+  Month                    = may,
+  Pages                    = {361--364},
+
+  Doi                      = {10.1109/ISCAS.2007.378464},
+  File                     = {lehlil_07.pdf:lehlil_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{lem_54,
+  Title                    = {{T}he dual method of solving the linear programming problem},
+  Author                   = {Lemke, C. E.},
+  Journal                  = {Naval Research Logistics Quarterly},
+  Year                     = {1954},
+  Number                   = {1},
+  Pages                    = {36--47},
+  Volume                   = {1},
+
+  Doi                      = {10.1002/nav.3800010107},
+  ISSN                     = {1931-9193},
+  Publisher                = {Wiley Subscription Services, Inc., A Wiley Company},
+  Url                      = {http://dx.doi.org/10.1002/nav.3800010107}
+}
+
+@Article{lerhem_10,
+  Title                    = {{S}tochastic {C}hase {D}ecoding of {R}eed-{S}olomon {C}odes},
+  Author                   = {C. Leroux and S. Hemati and S. Mannor and W. J. Gross},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2010},
+
+  Month                    = {September},
+  Number                   = {9},
+  Pages                    = {863-865},
+  Volume                   = {14},
+
+  Doi                      = {10.1109/LCOMM.2010.09.100594},
+  ISSN                     = {1089-7798},
+  Keywords                 = {Reed-Solomon codes;probability;stochastic processes;Reed-Solomon codes;probabilistic approach;stochastic chase algorithm;stochastic chase decoding;test patterns;Complexity theory;Iterative decoding;Maximum likelihood decoding;Reed-Solomon codes;Stochastic processes;Chase algorithm;Reed-Solomon codes;Stochastic decoding;soft decision decoding}
+}
+
+@Article{lerjeg_11,
+  Title                    = {{T}urbo {P}roduct {C}ode {D}ecoder {W}ithout {I}nterleaving {R}esource: {F}rom {P}arallelism {E}xploration to {H}igh {E}fficiency {A}rchitecture},
+  Author                   = {Camille Leroux and Christophe J{\'e}go and Patrick Adde and Deepak Gupta and Michel J{\'e}z{\'e}quel},
+  Journal                  = {Signal Processing Systems},
+  Year                     = {2011},
+  Number                   = {1},
+  Pages                    = {17-29},
+  Volume                   = {64},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Ee                       = {http://dx.doi.org/10.1007/s11265-010-0478-5},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.07.18}
+}
+
+@Article{lerray_13,
+  Title                    = {{A} {S}emi-{P}arallel {S}uccessive-{C}ancellation {D}ecoder for {P}olar {C}odes},
+  Author                   = {C. Leroux and A. J. Raymond and G. Sarkis and W. J. Gross},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2013},
+
+  Month                    = {Jan},
+  Number                   = {2},
+  Pages                    = {289-299},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TSP.2012.2223693},
+  ISSN                     = {1053-587X},
+  Keywords                 = {application specific integrated circuits;codes;decoding;field programmable gate arrays;ASIC;FPGA;capacity-achieving codes;coding theory;polar codes;semi-parallel architecture;semi-parallel successive-cancellation decoder;successive cancellation decoding;very low processing complexity;Application specific integrated circuits;Complexity theory;Computer architecture;Decoding;Field programmable gate arrays;Hardware;Vectors;Codes;FPGA;VLSI;decoding;polar codes;successive cancellation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{lertal_11,
+  Title                    = {{H}ardware architectures for successive cancellation decoding of polar codes},
+  Author                   = {C. Leroux and I. Tal and A. Vardy and W. J. Gross},
+  Booktitle                = {Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on},
+  Year                     = {2011},
+  Month                    = {May},
+  Pages                    = {1665-1668},
+
+  Doi                      = {10.1109/ICASSP.2011.5946819},
+  ISSN                     = {1520-6149},
+  Keywords                 = {block codes;channel coding;computational complexity;error correction codes;linear codes;consecutive codeword;hardware architecture;logarithmic domain;polar code;speed-up factor;successive cancellation decoding;Complexity theory;Computer architecture;Decoding;Hardware;Processor scheduling;Registers;Throughput;Polar codes;VLSI;hardware implementation;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Misc{lescontinuing08,
+  Title                    = {{C}ontinuing {E}xperiments of {A}tmospheric {N}eutron {E}ffects on {D}eep {S}ubmicron {I}ntegrated {C}ircuits},
+
+  Author                   = {Lesea, Austin},
+  HowPublished             = {www.xilinx.com},
+  Month                    = mar,
+  Year                     = {2008},
+
+  File                     = {lescontinuing08.pdf:lescontinuing08.pdf:PDF;lescontinuing08_email.txt:lescontinuing08_email.txt:Text},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Misc{Lesea2008,
+  Title                    = {{C}ontinuing {E}xperiments of {A}tmospheric {N}eutron {E}ffects on {D}eep {S}ubmicron {I}ntegrated {C}ircuits},
+
+  Author                   = {Lesea, Austin},
+  HowPublished             = {www.xilinx.com},
+  Month                    = mar,
+  Year                     = {2008},
+
+  File                     = {lescontinuing08.pdf:lescontinuing08.pdf:PDF;lescontinuing08_email.txt:lescontinuing08_email.txt:Text},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{leszim_06,
+  Title                    = {{B}lock-{LDPC} {C}odes vs {D}uo-{B}inary {T}urbo-{C}odes for {E}uropean {N}ext {G}eneration {W}ireless {S}ystems},
+  Author                   = {Lestable, T. and Zimmerman, E. and Hamon, M.-H. and Stiglmayr, S.},
+  Booktitle                = {Proc. VTC-2006 Fall Vehicular Technology Conference 2006 IEEE 64th},
+  Year                     = {2006},
+  Month                    = sep,
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/VTCF.2006.285},
+  File                     = {leszim_06.pdf:leszim_06.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.08}
+}
+
+@InProceedings{leuyue_99,
+  Title                    = {{Reducing Power Consumption of Turbo-Code Decoder Using Adaptive Iteration with Variable Supply Voltage}},
+  Author                   = {Leung and Yue and Tsui and Cheng},
+  Booktitle                = {Proc. 1999 International Symposium on Low Power Electronics and Design (ISLPED '99)},
+  Year                     = {1999},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = aug,
+  Pages                    = {36--41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{leuyue_99a,
+  Title                    = {{Reducing Power Consumption of Turbo Code Decoder Using Adaptive Iteration with Variable Supply Voltage}},
+  Author                   = {O. Y.-H. Leung and C.-W. Yue and C.-y. Tsui and R. S. K. Cheng},
+  Booktitle                = {Proc. 1999 International Symposium on Low Power Electronics and Design (ISLPED '99)},
+  Year                     = {1999},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = aug,
+  Pages                    = {36--41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{leucas_10,
+  Title                    = {{MPS}o{C} programming using the {MAPS} compiler},
+  Author                   = {Rainer Leupers and Jeronimo Castrillon},
+  Booktitle                = {Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific},
+  Year                     = {2010},
+  Month                    = {18-21},
+  Pages                    = {897 -902},
+
+  Abstract                 = {The problem of efficiently programming complex embedded heterogeneous multi-processor systems-on-chip (MPSoCs) continues to be one of the biggest hurdles in the IT community. Extracting parallelism from sequential applications, dealing with different programming models, and handling real time constraints in the presence of multiple concurrent applications are some of the challenges that make MPSoC programming so difficult. In this paper we describe the MAPS tool suite, which tries to tackle these aspects of MPSoC programming in an integrated development environment built upon the Eclipse framework. We give an overview of the MAPS framework, highlighting its differences to the previous work in, and report on experiences using the tool.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ASPDAC.2010.5419677},
+  File                     = {leucas_10.pdf:leucas_10.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.08.05}
+}
+
+@InProceedings{levcal_09,
+  Title                    = {{S}tatistical fault injection: {Q}uantified error and confidence},
+  Author                   = {Leveugle, R. and Calvez, A. and Maistri, P. and Vanhauwaert, P.},
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conference \& Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {502--506},
+
+  File                     = {levcal_09.pdf:levcal_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.01}
+}
+
+@Article{levkor_94,
+  Title                    = {{The {\tt Hyeti} Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis}},
+  Author                   = {R. Leveugle and Z. Koren and I. Koren and G. Saucier and N. Wehn},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {1994},
+
+  Month                    = dec,
+  Number                   = {12},
+  Pages                    = {1398--1406},
+  Volume                   = {43},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{levsou_90,
+  Title                    = {{A Practical Experiment in Defect Tolerance: The HYETI 16-Bit Microprocessor}},
+  Author                   = {R.~Leveugle and M.~Soueidan and N.~Wehn},
+  Booktitle                = {Wafer Scale Integration III},
+  Year                     = {1990},
+  Pages                    = {317--332},
+  Publisher                = {Elsevier Science Publisher},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{levsou_88,
+  Title                    = {{Defect Tolerance in a 16-Bit Microprocessor}},
+  Author                   = {R.~Leveugle and M.~Soueidan and N.~Wehn},
+  Booktitle                = {Defect and Fault Tolerance in VLSI-Systems},
+  Year                     = {1988},
+  Pages                    = {179--190},
+  Publisher                = {Plenum Press},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{levtay_00,
+  Title                    = {{Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware}},
+  Author                   = {B. Levine and R. R. Tayler and H. Schmitt},
+  Booktitle                = {Proc. 2000 Symposium on Field-Programmable Custom Computing Machines (FCCM '00)},
+  Year                     = {2000},
+  Pages                    = {217--226},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{levgir_15,
+  Title                    = {{S}neak{P}ath compensation circuit for programming and read operations in {RRAM}-based {C}ross{P}oint architectures},
+  Author                   = {A. Levisse and B. Giraud and J. P. Noël and M. Moreau and J. M. Portal},
+  Booktitle                = {2015 15th Non-Volatile Memory Technology Symposium (NVMTS)},
+  Year                     = {2015},
+  Month                    = {Oct},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/NVMTS.2015.7457426},
+  Keywords                 = {CMOS memory circuits;flash memories;logic design;resistive RAM;RRAM;crosspoint architectures;passive crossbar memories;resistive switching bit-cells;flash memories;crossbar memory simulations;terminal nonlinear selectors;peripheral circuits;sneak current compensation circuit;multilevel cell programming;CMOS;OxRAM;tunnel barrier-based selector bit-cell;size 130 nm;Programming;Resistance;Nonvolatile memory;Integrated circuit modeling;Arrays;Data models;CrossPoint;Nonvolatile Memory;RRAM;compensation circuit;Multiple Level Cell},
+  Timestamp                = {2018-08-29}
+}
+
+@Article{levgir_16,
+  Title                    = {{C}apacitor based {S}neak{P}ath compensation circuit for transistor-less {R}e{RAM} architectures},
+  Author                   = {A. Levisse and Bastien Giraud and Jean-Philippe Noel and Mathieu Moreau and Jean Michel Portal},
+  Journal                  = {2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},
+  Year                     = {2016},
+  Pages                    = {7-12},
+
+  Timestamp                = {2018-08-29}
+}
+
+@InProceedings{levroy_17,
+  Title                    = {{A}rchitecture, design and technology guidelines for crosspoint memories},
+  Author                   = {A. Levisse and p. Royer and B. Giraud and J. P. Noel and M. Moreau and J. M. Portal},
+  Booktitle                = {2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},
+  Year                     = {2017},
+  Month                    = {July},
+  Pages                    = {55-60},
+
+  Doi                      = {10.1109/NANOARCH.2017.8053733},
+  ISSN                     = {2327-8226},
+  Keywords                 = {dividing circuits;flash memories;leakage currents;memory architecture;NAND circuits;random-access storage;IRdrop;periphery overhead;1 selector-1 resistance device;half metal pitch memory technology nodes;RRAM programming current;RRAM memories;NAND memories;crosspoint memories;resistive switching memories;deeply scaled density RRAM architectures;high density RRAM architectures;voltage drop effects;IR drop;metal lines;array-line charging time;in-array multiple bit-write operation;size 15.0 nm to 50.0 nm;word length 1.0 bit to 32.0 bit;Nanoscale devices;RRAM;crosspoint memory;crossbar memory;1S1R NVM device;NVM},
+  Timestamp                = {2018-08-29}
+}
+
+@Electronic{lev_12,
+  Title                    = {{H}andout on {A}merican vs. {E}uropean {O}ptions},
+  Author                   = {Tal Levy},
+  HowPublished             = {\url{http://www.eecs.harvard.edu/~parkes/cs286r/spring08/reading5/hw3handout2.pdf}},
+  Language                 = {en},
+  Month                    = mar,
+  Year                     = {2012},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {European option, American option},
+  Cds_read                 = {2012-03-21},
+  Cds_review               = {explains the differences between the values of American and European options, in particular why they have the same value for pure calls},
+  File                     = {lev_12.pdf:lev_12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.21}
+}
+
+@Electronic{Levy2012,
+  Title                    = {{H}andout on {A}merican vs. {E}uropean {O}ptions},
+  Author                   = {Tal Levy},
+  HowPublished             = {\url{http://www.eecs.harvard.edu/~parkes/cs286r/spring08/reading5/hw3handout2.pdf}},
+  Language                 = {en},
+  Month                    = mar,
+  Year                     = {2012},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {European option, American option},
+  Cds_read                 = {2012-03-21},
+  Cds_review               = {explains the differences between the values of American and European options, in particular why they have the same value for pure calls},
+  File                     = {lev_12.pdf:lev_12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.21}
+}
+
+@Article{lewpay_73,
+  Title                    = {{G}eneralized {F}eedback {S}hift {R}egister {P}seudorandom {N}umber {A}lgorithm},
+  Author                   = {Lewis, T. G. and Payne, W. H.},
+  Journal                  = {Journal of the ACM},
+  Year                     = {1973},
+
+  Month                    = jul,
+  Number                   = {3},
+  Pages                    = {456--468},
+  Volume                   = {20},
+
+  Acmid                    = {321777},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {4},
+  Cds_keywords             = {random number generation, uniform distribution},
+  Cds_read                 = {2014-02-06},
+  Cds_review               = {GFSR algorithm, reference to Tausworthe},
+  Doi                      = {10.1145/321765.321777},
+  File                     = {lewpay_73.pdf:lewpay_73.pdf:PDF},
+  ISSN                     = {0004-5411},
+  Issue_date               = {July 1973},
+  Keywords                 = {finance},
+  Numpages                 = {13},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2012.03.26},
+  Url                      = {http://doi.acm.org/10.1145/321765.321777}
+}
+
+@Electronic{ley_14,
+  Title                    = {{E}rror {D}etection in {N}on-{U}niform {R}andom {V}ariate {G}enerators},
+  Author                   = {Josef Leydold},
+  HowPublished             = {\url{http://cran.r-project.org/web/packages/rvgtest/vignettes/rvgtest.pdf}},
+  Language                 = {en},
+  Month                    = feb,
+  Note                     = {last access 2014-07-02},
+  Organization             = {Institute for Statistics and Mathematics, WU Vienna, Austria},
+  Url                      = {\url{http://cran.r-project.org/web/packages/rvgtest/vignettes/rvgtest.pdf}},
+  Year                     = {2014},
+
+  Abstract                 = {Non-uniform random variate generators are of fundamental importance in Monte-Carlo methods and stochastic simulation. They are based on the assumption that a source of uniformly distributed random numbers is available that produces real and truely random numbers. In practice, however, we have to use pseudo-random numbers which are gener- ated by means of floating point numbers. Thus there are deviations from the theoretical framework caused by round-off errors which are due to the limitations of floating point arithmetic. In addition algorithm have to developed and implemented. As human can err coding errors or mistakes in the design of algorithm may cause defects in a generated random sample. It is of paramount importance to detect such errors using statistical tools and categorize which tests are sensitive to which errors.
+rvgtest is a collection of routines for testing non-uniform random variate generators. They hopefully should help to detect all kinds of error. Thus it provides routines for goodness-of-fit tests that are based on histograms and routines to estimate approximation errors for numerical inversion.},
+  Cds_grade                = {0},
+  Cds_keywords             = {R, non-uniform random number generator test, quality evaluation, test suite},
+  File                     = {ley_14.pdf:ley_14.pdf:PDF},
+  Keywords                 = {random number},
+  Owner                    = {CdS},
+  Timestamp                = {2014.04.03}
+}
+
+@Article{lihai_16,
+  Title                    = {1.5 {G}bit/s {FPGA} {I}mplementation of a {F}ully-{P}arallel {T}urbo {D}ecoder {D}esigned for {M}ission-{C}ritical {M}achine-{T}ype {C}ommunication {A}pplications},
+  Author                   = {A. Li and P. Hailes and R. G. Maunder and B. M. Al-Hashimi and L. Hanzo},
+  Journal                  = {IEEE Access},
+  Year                     = {2016},
+  Pages                    = {5452-5473},
+  Volume                   = {4},
+
+  Doi                      = {10.1109/ACCESS.2016.2599408},
+  ISSN                     = {2169-3536},
+  Keywords                 = {Long Term Evolution;decoding;error correction codes;field programmable gate arrays;forward error correction;parallel processing;turbo codes;FPTD algorithm;LTE frames;Log-BCJR algorithm;Long Term Evolution;Stratix IV FPGA;bit rate 1.5 Gbit/s;computational resource reduction;decoding frames;field-programmable gate array;frame length;fully-parallel turbo decoder;logarithmic Bahl-Cocke-Jelinek-Raviv algorithm;mission-critical machine-type communication;near-capacity transmission;parallel processing;reliable forward error correction;serial data dependency;turbo codes;wireless communication schemes;Benchmark testing;Decoding;Field programmable gate arrays;Long Term Evolution;Throughput;Turbo codes;Wireless communication;FPGA;Fully-parallel turbo decoder;LTE;turbo decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.10.24}
+}
+
+@Article{lixia_16,
+  Title                    = {{VLSI} {I}mplementation of {F}ully {P}arallel {LTE} {T}urbo {D}ecoders},
+  Author                   = {A. Li and L. Xiang and T. Chen and R. G. Maunder and B. M. Al-Hashimi and L. Hanzo},
+  Journal                  = {IEEE Access},
+  Year                     = {2016},
+  Pages                    = {323-346},
+  Volume                   = {4},
+
+  Doi                      = {10.1109/ACCESS.2016.2515719},
+  File                     = {lixia_16.pdf:lixia_16.pdf:PDF},
+  ISSN                     = {2169-3536},
+  Keywords                 = {Long Term Evolution;VLSI;forward error correction;integrated circuit design;interleaved codes;iterative decoding;parallel processing;turbo codes;Long-Term Evolution frames;TSMC low-power technology;Taiwan Semiconductor Manufacturing Company;additive white Gaussian noise channel;bit rate 21.9 Gbit/s;clock cycles;design flow;energy consumption;error correction decoders;fixed-point FPTD VLSI;floating-point fully parallel turbo decoder algorithm;fully parallel LTE turbo decoders;interleaver patterns;logarithmic Bahl-Cocke-Jelinek-Raviv algorithm;message log-likelihood ratio scaling;near-capacity transmission throughputs;parallel processing;real-time communication schemes;reliable iterative forward error correction;serial data dependence;size 65 nm;state metric normalization;time 0.28 mus;very large scale integration;Algorithm design and analysis;Benchmark testing;Decoding;Error correction;Hardware;Throughput;Very large scale integration;Fully-parallel turbo decoder;LTE turbo code;VLSI design;fully-parallel turbo decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.25}
+}
+
+@Article{ligu_16,
+  Title                    = {{E}xploring the {P}recision {L}imitation for {RRAM}-{B}ased {A}nalog {A}pproximate {C}omputing},
+  Author                   = {Li, B. and Gu, P. and Wang, Y. and Yang, H.},
+  Journal                  = {IEEE Design \& Test},
+  Year                     = {2016},
+
+  Month                    = {February},
+  Number                   = {1},
+  Pages                    = {51-58},
+  Volume                   = {33},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-05}
+}
+
+@Article{lishe_12,
+  Title                    = {{A}n {A}daptive {S}uccessive {C}ancellation {L}ist {D}ecoder for {P}olar {C}odes with {C}yclic {R}edundancy {C}heck},
+  Author                   = {B. Li and H. Shen and D. Tse},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2012},
+
+  Month                    = {December},
+  Number                   = {12},
+  Pages                    = {2044-2047},
+  Volume                   = {16},
+
+  Doi                      = {10.1109/LCOMM.2012.111612.121898},
+  ISSN                     = {1089-7798},
+  Keywords                 = {adaptive codes;cyclic redundancy check codes;decoding;CRC code;FER;adaptive SC list decoder;adaptive successive cancellation list decoder;cyclic redundancy check codes;frame error rate;information theoretic limit;polar codes;word length 24 bit;Complexity theory;Cyclic redundancy check;Error analysis;Iterative decoding;Maximum likelihood decoding;Signal to noise ratio;Polar codes;list decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{lidec_13,
+  Title                    = {{T}rellis-{B}ased {E}xtended {M}in-{S}um {A}lgorithm for {N}on-{B}inary {LDPC} {C}odes and its {H}ardware {S}tructure},
+  Author                   = {Erbao Li and Declercq, D. and Gunnam, K.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2013},
+  Number                   = {7},
+  Pages                    = {2600--2611},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCOMM.2013.050813.120489},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6516166}
+}
+
+@InProceedings{ligun_11,
+  Title                    = {{T}rellis based {E}xtended {M}in-{S}um for decoding nonbinary {LDPC} codes},
+  Author                   = {Erbao Li and Gunnam, K. and Declercq, D.},
+  Booktitle                = {Wireless Communication Systems (ISWCS), 2011 8th International Symposium on},
+  Year                     = {2011},
+  Pages                    = {46--50},
+
+  Doi                      = {10.1109/ISWCS.2011.6125307},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6125307}
+}
+
+@Article{licha_96,
+  Title                    = {{A new architecture for the Viterbi Decoder for code rate k/n}},
+  Author                   = {H. Li and C. Chakrabarti},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1996},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {158--164},
+  Volume                   = {44},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{lizha_13,
+  Title                    = {{T}he {M}athematical {M}orphology {I}mage {E}dge {D}etection {B}ased on {FPGA}},
+  Author                   = {Hui De Li and Lian Yu Zhao},
+  Booktitle                = {Applied Mechanics and Materials},
+  Publisher                = {Scientific.Net},
+  Year                     = {2013},
+  Chapter                  = {5},
+  Editor                   = {Tiantian Zhang and Yuanzhi Wang},
+  Month                    = dec,
+  Pages                    = {599-603},
+  Volume                   = {467},
+
+  Abstract                 = {The image edge detection algorithm is one of the most important steps in the image processing, however, while the large amount of data is need to be dealt with in the detection process, it is difficult to meet real-time requirements by using the software method. In order to improve the speed of digital image processing, An embedded processing systems based on FPGA (field-programmable gate array) detection algorithm is proposed, which takes corrosion expansion algorithm of mathematical morphology as its theoretical basis to achieve the task of image edge detection, experiments result show the method is effective and feasible, and meets the real-time requirement of the image processing.},
+  Cds_grade                = {0},
+  Cds_keywords             = {morphological filter, FPGA, edge detection},
+  Owner                    = {CdS},
+  Timestamp                = {2014.07.15}
+}
+
+@Article{lishi_14,
+  Title                    = {{S}implified {S}oft-output {D}emapper {B}ased on a {L}inear {T}ransformation {T}echnique for {M}-ary {PSK}.},
+  Author                   = {Li, Jianping and Shi, Yameng},
+  Journal                  = {Sensors \& Transducers (1726-5479)},
+  Year                     = {2014},
+  Number                   = {10},
+  Volume                   = {181},
+
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-12}
+}
+
+@Article{lishi_14a,
+  Title                    = {{S}implified {S}oft-output {D}emapper {B}ased on a {L}inear {T}ransformation {T}echnique for {M}-ary {PSK}.},
+  Author                   = {Li, Jianping and Shi, Yameng},
+  Journal                  = {Sensors \& Transducers (1726-5479)},
+  Year                     = {2014},
+  Number                   = {10},
+  Volume                   = {181},
+
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-12}
+}
+
+@InProceedings{libou_08,
+  Title                    = {{S}elective {S}panning with {F}ast {E}numeration: {A} {N}ear {M}aximum-{L}ikelihood {MIMO} {D}etector {D}esigned for {P}arallel {P}rogrammable {B}aseband {A}rchitectures},
+  Author                   = {Min Li and Bougard, B. and Lopez, E. E. and Bourdoux, A. and Novo, D. and Van Der Perre, L. and Catthoor, F. },
+  Booktitle                = {Proc. IEEE Int. Conf. Communications ICC '08},
+  Year                     = {2008},
+  Pages                    = {737--741},
+
+  Doi                      = {10.1109/ICC.2008.144},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@InProceedings{linae_13,
+  Title                    = {{A}n area and energy efficient half-row-paralleled layer {LDPC} decoder for the 802.11{AD} standard},
+  Author                   = {M. Li and F. Naessens and P. Debacker and P. Raghavan and C. Desset and M. Li and A. Dejonghe and L. Van der Perre},
+  Booktitle                = {SiPS 2013 Proceedings},
+  Year                     = {2013},
+  Month                    = {Oct},
+  Pages                    = {112-117},
+
+  Doi                      = {10.1109/SiPS.2013.6674490},
+  File                     = {linae_13.pdf:linae_13.pdf:PDF},
+  ISSN                     = {2162-3562},
+  Keywords                 = {decoding;energy conservation;parity check codes;telecommunication standards;802.11AD standard;LDPC decoder;energy efficient;frequency 500 MHz;half-row-paralleled layer;hardware resources;permutation network;Decoding;Encoding;Iterative decoding;Parallel processing;Pipelines;Throughput;802.11ad;LDPC;layer decoding;multi-gigabit communication},
+  Owner                    = {MH},
+  Timestamp                = {2017-05-22}
+}
+
+@InProceedings{linou_09,
+  Title                    = {{D}esign of rotated {QAM} mapper/demapper for the {DVB}-{T}2 standard},
+  Author                   = {Meng Li and Nour, C.A. and Jego, C. and Douillard, C.},
+  Booktitle                = {IEEE Workshop on Signal Processing Systems, 2009. SiPS 2009.},
+  Year                     = {2009},
+  Month                    = {Oct},
+  Pages                    = {018-023},
+
+  Doi                      = {10.1109/SIPS.2009.5336265},
+  ISSN                     = {1520-6130},
+  Keywords                 = {digital video broadcasting;diversity reception;fading channels;field programmable gate arrays;quadrature amplitude modulation;signal detection;television standards;DVB-T2 standard;FPGA prototyping;fading channel;rotated QAM demapper;rotated QAM mapper;signal detection;signal space diversity;terrestrial digital video broadcasting standard;Constellation diagram;Digital video broadcasting;Fading;Field programmable gate arrays;Interleaved codes;Maximum likelihood detection;Modulation coding;Prototypes;Quadrature amplitude modulation;Telecommunication standards;DVB-T2;FPGA design and prototyping;QAM;demapper architectures;erasure channel;fading channel},
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-12}
+}
+
+@InProceedings{liwei_15,
+  Title                    = {{A}n energy efficient 18{G}bps {LDPC} decoding processor for 802.11ad in 28nm {CMOS}},
+  Author                   = {M. Li and J. W. Weijers and V. Derudder and I. Vos and M. Rykunov and S. Dupont and P. Debacker and A. Dewilde and Y. Huang and L. Van der Perre and W. Van Thillo},
+  Booktitle                = {2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)},
+  Year                     = {2015},
+  Month                    = {Nov},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/ASSCC.2015.7387473},
+  File                     = {liwei_15.pdf:liwei_15.pdf:PDF},
+  Keywords                 = {CMOS integrated circuits;decoding;integrated circuit design;parity check codes;5G mobile communication;CMOS technology;IEEE 802.11ad;LDPC ASIP;bit rate 1.8 Gbit/s to 18.4 Gbit/s;demonstrator silicon;energy efficient LDPC decoding processor;frequency scaling;half layer paralleled architecture;multiGbps LDPC decoder design;multicore management;size 28 nm;voltage scaling;Computer architecture;Decoding;Encoding;Energy efficiency;Parity check codes;Standards;Throughput;802.11ad;LDPC;processor},
+  Owner                    = {MH},
+  Timestamp                = {2017-05-22}
+}
+
+@TechReport{liwan_10,
+  Title                    = {{Design and Implementation of an Accurate Memory Subsystem Model in SystemC}},
+  Author                   = {Li, Nan and Wang, Yi and Zhou, Huisheng and Liang, Lei},
+  Year                     = {2010},
+  Month                    = dec,
+
+  Organization             = {OCP},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.17},
+  Url                      = {http://www.ocpip.org/memory_model.php}
+}
+
+@InProceedings{lizha_15,
+  Title                    = {{C}ompiler {D}irected {A}utomatic {S}tack {T}rimming for {E}fficient {N}on-volatile {P}rocessors},
+  Author                   = {Li, Qingan and Zhao, Mengying and Hu, Jingtong and Liu, Yongpan and He, Yanxiang and Xue, Chun Jason},
+  Booktitle                = {Proceedings of the 52Nd Annual Design Automation Conference},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {183:1--183:6},
+  Publisher                = {ACM},
+  Series                   = {DAC '15},
+
+  Acmid                    = {2744809},
+  Articleno                = {183},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Li:2015:CDA:2744769.2744809},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/2744769.2744809},
+  ISBN                     = {978-1-4503-3520-1},
+  Keywords                 = {TCS},
+  Keywords_original        = {compiler, non-volatile processor, stack},
+  Location                 = {San Francisco, California},
+  Numpages                 = {6},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/2744769.2744809}
+}
+
+@InProceedings{lijac_19,
+  Title                    = {{S}tatistical {DRAM} {M}odeling},
+  Author                   = {Li, Shang and Jacob, Bruce},
+  Booktitle                = {Proceedings of the International Symposium on Memory Systems},
+  Year                     = {2019},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {521–530},
+  Publisher                = {Association for Computing Machinery},
+  Series                   = {MEMSYS ’19},
+
+  Doi                      = {10.1145/3357526.3357576},
+  ISBN                     = {9781450372060},
+  Keywords                 = {DRAM modeling, architecture simulation, cycle accurate simulation},
+  Location                 = {Washington, District of Columbia},
+  Numpages                 = {10},
+  Owner                    = {MJ},
+  Timestamp                = {2020.03.10},
+  Url                      = {https://doi.org/10.1145/3357526.3357576}
+}
+
+@Article{lilu_19,
+  Title                    = {{S}entinel: {B}reaking the {B}ottleneck of {E}nergy {U}tilization {E}fficiency in {RF}-{P}owered {D}evices},
+  Author                   = {S. {Li} and L. {Lu} and M. J. {Hussain} and Y. {Ye} and H. {Zhu}},
+  Journal                  = {IEEE Internet of Things Journal},
+  Year                     = {2019},
+
+  Month                    = {Feb},
+  Number                   = {1},
+  Pages                    = {705-717},
+  Volume                   = {6},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8409282},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/JIOT.2018.2854374},
+  ISSN                     = {2327-4662},
+  Keywords                 = {TCS},
+  Keywords_original        = {Task analysis;Sensors;Energy consumption;Internet of Things;Radio frequency;Software;Planning;Energy;energy efficiency;energy polling;energy trigger;energy utilization efficiency;radio frequency (RF)-powered devices},
+  Owner                    = {CCR}
+}
+
+@InProceedings{liver_19,
+  Title                    = {{R}ethinking {C}ycle {A}ccurate {DRAM} {S}imulation},
+  Author                   = {Li, Shang and Verdejo, Rommel S\'{a}nchez and Radojkovi\'{c}, Petar and Jacob, Bruce},
+  Booktitle                = {Proceedings of the International Symposium on Memory Systems},
+  Year                     = {2019},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {184–191},
+  Publisher                = {Association for Computing Machinery},
+  Series                   = {MEMSYS ’19},
+
+  Doi                      = {10.1145/3357526.3357539},
+  ISBN                     = {9781450372060},
+  Keywords                 = {architecture simulation, cycle accurate simulation, DRAM modeling},
+  Location                 = {Washington, District of Columbia},
+  Numpages                 = {8},
+  Url                      = {https://doi.org/10.1145/3357526.3357539}
+}
+
+@Article{liyan_20,
+  Title                    = {{DRAM}sim3: a {C}ycle-accurate, {T}hermal-{C}apable {DRAM} {S}imulator},
+  Author                   = {S. {Li} and Z. {Yang} and D. {Reddy} and A. {Srivastava} and B. {Jacob}},
+  Journal                  = {IEEE Computer Architecture Letters},
+  Year                     = {2020},
+  Pages                    = {1-1},
+
+  Doi                      = {10.1109/LCA.2020.2973991},
+  ISSN                     = {2473-2575},
+  Keywords                 = {Random access memory;Thermal conductivity;Protocols;Thermal resistance;Computational modeling;Integrated circuit modeling;Three-dimensional displays;DRAM;Cycle-accurate;Simulation;3D-modeling;Thermal Modeling},
+  Owner                    = {MJ},
+  Timestamp                = {2020-03-12}
+}
+
+@InProceedings{lihua_00,
+  Title                    = {{E}ffects of iterative detection and decoding on the performance of},
+  Author                   = {Li, X. and Huang, H. and Foschini, G. J. and Valenzuela, R. A.},
+  Booktitle                = {Proc. IEEE Global Telecommunications Conference GLOBECOM '00},
+  Year                     = {2000},
+  Pages                    = {1061--1066 vol.2},
+  Volume                   = {2},
+
+  Abstract                 = {In BLAST (Bell Labs' Layered Space Time) systems, very high spectral efficiency can be achieved by employing antenna arrays at both transmit and receive sides. Coding for these array systems is an interesting topic, as such, has seen intensive research. We study coding architectures constructed from conventional codes including convolutional codes and Reed Solomon codes. Our main interest is in the performance and complexity trade-offs involved in the design of coding/decoding and signal detection algorithms. We show that iterative detection and decoding (IDD) can significantly improve the performance of coded BLAST. In some cases, IDD allows for very simple detection algorithms to be used at the receiver front end. Therefore, it may in fact reduce the overall receiver complexity. Our results again demonstrate that coded V-BLAST (vertical-BLAST) is a promising architecture to achieve the great potential of BLAST with limited complexity},
+  Doi                      = {10.1109/GLOCOM.2000.891300},
+  File                     = {lihua_00.pdf:lihua_00.pdf:PDF},
+  Grade                    = {0},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Review                   = {CG:
+BLAST},
+  Timestamp                = {2008.10.10}
+}
+
+@InProceedings{lisol_03,
+  Title                    = {{G}ood {LDPC} codes over {GF}(q) for bandwidth efficient transmission},
+  Author                   = {Xiangming Li and Soleymani, M. R. and Lodge, J. and Guinand, P. S. },
+  Booktitle                = {Proc. 4th IEEE Workshop on Signal Processing Advances in Wireless Communications SPAWC 2003},
+  Year                     = {2003},
+  Month                    = jun,
+  Pages                    = {95--99},
+
+  File                     = {lisol_03.pdf:lisol_03.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InProceedings{liake_14,
+  Title                    = {{D}ynamic {C}ommand {S}cheduling for {R}eal-{T}ime {M}emory {C}ontrollers},
+  Author                   = {Y. Li and B. Akesson and K. Goossens},
+  Booktitle                = {2014 26th Euromicro Conference on Real-Time Systems},
+  Year                     = {2014},
+  Month                    = {July},
+  Pages                    = {3-14},
+
+  Doi                      = {10.1109/ECRTS.2014.18},
+  ISSN                     = {1068-3070},
+  Keywords                 = {Bismuth;Dynamic scheduling;Heuristic algorithms;Memory management;Real-time systems;SDRAM;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-29}
+}
+
+@InProceedings{liake_16,
+  Title                    = {{M}odeling and {V}erification of {D}ynamic {C}ommand {S}cheduling for {R}eal-{T}ime {M}emory {C}ontrollers},
+  Author                   = {Y. {Li} and B. {Akesson} and K. {Lampka} and K. {Goossens}},
+  Booktitle                = {2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)},
+  Year                     = {2016},
+  Month                    = {April},
+  Pages                    = {1-12},
+
+  Doi                      = {10.1109/RTAS.2016.7461341},
+  Keywords                 = {automata theory;DRAM chips;multiprocessing systems;processor scheduling;real-time systems;dynamic command scheduling verification;dynamic command scheduling modeling;real-time memory controllers;multicore systems;multiple real-time applications;memory traffic;RT memory controllers;dynamic command scheduling;SDRAM timing constraints;tight bounds;worst-case response time;WCRT;worst-case bandwidth;WCBW;timed automata;TA model;model checking;worst-case transaction traces;SDRAM;Timing;Dynamic scheduling;Clocks;Adaptation models;Analytical models;Model checking},
+  Owner                    = {MJ},
+  Timestamp                = {2019-06-03}
+}
+
+@Article{livuc_95,
+  Title                    = {{Optimum Soft-Output Detection for Channels with Intersymbol Interference}},
+  Author                   = {Y. Li and B. Vucetic and Y. Sato},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1995},
+
+  Month                    = may,
+  Number                   = {3},
+  Pages                    = {704--713},
+  Volume                   = {41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{liates_04,
+  Title                    = {{A} dynamically-reconfigurable, power-efficient turbo decoder},
+  Author                   = {Jian Liang and Tessier, R. and Goeckel, D.},
+  Booktitle                = {Proc. 12th Annual IEEE Symp. Field-Programmable Custom Computing Machines FCCM 2004},
+  Year                     = {2004},
+  Pages                    = {91--100},
+
+  Cb_grade                 = {ASIP},
+  Doi                      = {10.1109/FCCM.2004.3},
+  File                     = {liates_04.pdf:liates_04.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.03.23}
+}
+
+@InProceedings{lialai_09,
+  Title                    = {{C}ombining orthogonalized partial metrics: {E}fficient enumeration for soft-input sphere decoder},
+  Author                   = {Chun-Hao Liao and I-Wei Lai and Nikitopoulos, K. and Borlenghi, F. and Kammler, D. and Witte, M. and Dan Zhang and Tzi-Dar Chiueh and Ascheid, G. and Meyr, H.},
+  Booktitle                = {Personal, Indoor and Mobile Radio Communications, 2009 IEEE 20th International Symposium on},
+  Year                     = {2009},
+  Pages                    = {1287-1291},
+
+  Doi                      = {10.1109/PIMRC.2009.5450104},
+  File                     = {lialai_09.pdf:lialai_09.pdf:PDF},
+  Keywords                 = {MIMO communication;decoding;error statistics;mathematical analysis;orthogonal codes;signal detection;MIMO detection;channel information;constellation point;low-complexity method;mathematical analysis;mathematical simulation;optimal error rate;orthogonalized partial metrics;soft-input sphere decoder;Analytical models;Constellation diagram;Decoding;Error analysis;Iterative algorithms;MIMO;Mathematical analysis;Multidimensional signal processing;Signal processing algorithms;Sorting},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.09}
+}
+
+@InProceedings{liawan_08,
+  Title                    = {{A}n {O}(qlogq) log-domain decoder for non-binary {LDPC} over {GF}(q)},
+  Author                   = {Chun-Hao Liao and Chien-Yi Wang and Chun-Hao Liu and Tzi-Dar Chiueh},
+  Booktitle                = {In Proc. IEEE Asis Pacific Conference on Circuits and Systems, APCCAS 2008},
+  Year                     = {2008},
+  Month                    = dec,
+  Pages                    = {1644--1647},
+
+  Doi                      = {10.1109/APCCAS.2008.4746352},
+  Keywords                 = {BER performance;GF;computational complexity;log-domain decoder;nonbinary LDPC;Galois fields;computational complexity;decoding;error statistics;parity check codes;}
+}
+
+@Article{liawan_10,
+  Title                    = {{A} 74.8 m{W} {S}oft-{O}utput {D}etector {IC} for 8x8 {S}patial-{M}ultiplexing {MIMO} {C}ommunications},
+  Author                   = {Chun-Hao Liao and To-Ping Wang and Tzi-Dar Chiueh},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2010},
+  Number                   = {2},
+  Pages                    = {411--421},
+  Volume                   = {45},
+
+  Doi                      = {10.1109/JSSC.2009.2037292},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@MastersThesis{Liao2011,
+  Title                    = {{P}hase and {F}requency {E}stimation: {H}igh-{A}ccuracy and {L}ow-{C}omplexity {T}echniques},
+  Author                   = {Y. Liao},
+  School                   = {Worcester Polytechnic Institute},
+  Year                     = {2011},
+
+  Address                  = {Massachusetts, USA},
+  Month                    = {May},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.03.03}
+}
+
+@Article{libkle_07,
+  Title                    = {{T}he link-prediction problem for social networks},
+  Author                   = {Liben-Nowell, David and Kleinberg, Jon},
+  Journal                  = {Journal of the American society for information science and technology},
+  Year                     = {2007},
+  Number                   = {7},
+  Pages                    = {1019--1031},
+  Volume                   = {58},
+
+  Owner                    = {Brugger},
+  Publisher                = {Wiley Online Library},
+  Timestamp                = {2015.08.15}
+}
+
+@InProceedings{liehut_11,
+  Title                    = {{FPGA} {C}ommunication {F}ramework},
+  Author                   = {Lieber, P. and Hutchings, B.},
+  Booktitle                = {Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on},
+  Year                     = {2011},
+  Pages                    = {69--72},
+
+  Abstract                 = {FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a host-software library/API. It enables a host PC to transmit data at 120 Mb/s to Xilinx-based FPGA boards via Ethernet using standard internet protocols. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports all ICAP functionality. The core also provides an extensible user-channel interface and provides up to 15, 8-bit user-data channels. The host software API supports both Java and C++ and provides high-level functionality for making connections and transmitting data. The utility of the system is demonstrated by implementing an on-chip test/debug system.},
+  Cds_grade                = {4},
+  Cds_keywords             = {FPGA, Ethernet, hardware-in-the-loop, rapid prototyping, UDP/IP},
+  Cds_read                 = {2013-07-16},
+  Cds_review               = {UDP + FCP (FPGA Communication Protocol) solution maintaining order of data packets and ensuring delivery
+global host + board system
+low-level hardware access},
+  Doi                      = {10.1109/FCCM.2011.39},
+  File                     = {liehut_11.pdf:liehut_11.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2013.07.16}
+}
+
+@Article{limlim_15,
+  Title                    = {3-{D} {S}tacked {DRAM} {R}efresh {M}anagement {W}ith {G}uaranteed {D}ata {R}eliability},
+  Author                   = {J. Lim and H. Lim and S. Kang},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2015},
+
+  Month                    = {Sept},
+  Number                   = {9},
+  Pages                    = {1455-1466},
+  Volume                   = {34},
+
+  Doi                      = {10.1109/TCAD.2015.2413411},
+  ISSN                     = {0278-0070},
+  Keywords                 = {DRAM chips;low-power electronics;reliability;temperature sensors;three-dimensional integrated circuits;3-D stacked DRAM refresh management;data communication power reduction;dynamic random-access memory;guaranteed data reliability;on-chip temperature sensor-dependent adaptive refresh control;temperature-aware refresh management;thermal guard-band set-up method;Computer architecture;Microprocessors;Random access memory;Reliability;Temperature distribution;Temperature sensors;Three-dimensional displays;3-D integration;DRAM refresh;Data reliability;Terms—3D integration;data reliability},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-16}
+}
+
+@InProceedings{limris_08,
+  Title                    = {{A} {R}eal-{T}ime {P}rogramming {M}odel for {H}eterogeneous {MPS}o{C}s},
+  Author                   = {Torsten Limberg and Bastian Ristau and Gerhard Fettweis},
+  Booktitle                = {International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS VIII)},
+  Year                     = {2008},
+  Month                    = {July},
+
+  Abstract                 = {Modern multi-core processors su®er from the lack of a programming
+model which allows e±cient utilization of the available hardware.
+Massive software overhead is required to handle task scheduling
+and synchronization, resulting in power ine±ciencies. In this paper we
+present a C++ based, real-time enabled task level programming model,
+which allows e±cient hardware utilization. Task scheduling and synchronization
+is performed by a hardware unit at run-time. The automated
+scheduler unit is guided by o²ine information extracted from source code
+by a specialized compiler},
+  Cds_grade                = {4},
+  Cds_keywords             = {Multicore, MPSoC, Design, Mapping, C++},
+  Cds_read                 = {2010-06-02},
+  Cds_review               = {overview of TU Dreden programing model
+hardware CoreManager schedules tasks and real-time threads at runtime},
+  File                     = {limris_08.pdf:limris_08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.06.01}
+}
+
+@Conference{limwin_09,
+  Title                    = {{A} {H}eterogeneous {MPS}o{C} with {H}ardware {S}upported {D}ynamic {T}ask {S}cheduling for {S}oftware {D}efined {R}adio},
+  Author                   = {Limberg, T. and Winter, M. and Bimberg, M. and Klemm, R. and Tavares, MBS and Ahlendorf, H. and Matúš, E. and Fettweis, G. and Eisenreich, H. and Ellguth, G. and Schlüssler, J.-U.},
+  Booktitle                = {Design Automation Conference (DAC’09)},
+  Year                     = {2009},
+  Organization             = {Citeseer},
+
+  Cds_grade                = {0},
+  File                     = {limwin_09.pdf:limwin_09.pdf:PDF},
+  Keywords                 = {MPSoC},
+  Owner                    = {CdS},
+  Timestamp                = {2010.12.01}
+}
+
+@Electronic{lim_17,
+  Title                    = {{O}pen {V}irtual {P}latforms - the source of {F}ast {P}rocessor {M}odels \& {P}latforms},
+  Author                   = {Imperas Software Limited},
+  Organization             = {Imperas Software Limited},
+  Url                      = {http://www.ovpworld.org},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-04-05}
+}
+
+@InProceedings{linlin_05,
+  Title                    = {{A 3.33Gb/s (1200,720) low-density parity check code decoder}},
+  Author                   = {C. Lin and K. Lin and H. Chang and C. Lee},
+  Booktitle                = {Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC)},
+  Year                     = {2005},
+
+  Address                  = {Grenoble, France},
+  Month                    = sep,
+  Pages                    = {211--214},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{linshi_06,
+  Title                    = {{A} low power turbo/{V}iterbi decoder for 3{GPP}2 applications},
+  Author                   = {Chien-Ching Lin and Yen-Hsu Shih and Chang, Hsie-Chia and Chen-Yi Lee},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {April},
+  Number                   = {4},
+  Pages                    = {426-430},
+  Volume                   = {14},
+
+  Doi                      = {10.1109/TVLSI.2006.874375},
+  ISSN                     = {1063-8210},
+  Keywords                 = {CMOS integrated circuits;Viterbi decoding;low-power electronics;turbo codes;wearablecomputers;0.18 micron;1 Mbit/s;1.8 V;25.1 mW;3.1 Mbit/s;3GPP2 application;4.25 Mbit/s;83mW;CMOS;Viterbi decoder;cache memories;channel decoder;embedded interleaver memory;errorcorrection;low signal-to-noise ratio;mobile communication;optimized memory;test chip;turbodecoder;wearable device;wireless communication system;CMOS technology;Energyconsumption;Iterative decoding;Power dissipation;Power measurement;Semiconductor devicemeasurement;Signal to noise ratio;Testing;Viterbi algorithm;Wireless communication;Cachememories;Viterbi decoding;error correction;mobile communication;turbo}
+}
+
+@InProceedings{linche_11,
+  Title                    = {{A} 0.16n{J}/bit/iteration 3.38mm2 turbo decoder chip for {W}i{MAX}/{LTE} standards},
+  Author                   = {Cheng-Hung Lin and Chun-Yu Chen and En-Jui Chang and An-Yeu Wu},
+  Booktitle                = {Integrated Circuits (ISIC), 2011 13th International Symposium on},
+  Year                     = {2011},
+  Month                    = {Dec},
+  Pages                    = {168-171},
+
+  Doi                      = {10.1109/ISICir.2011.6131904},
+  Keywords                 = {CMOS integrated circuits;Long Term Evolution;VLSI;WiMax;convolutional codes;interleaved codes;turbo codes;CMOS process;LTE standards;VLSI architecture;WiMAX;contention-free vectorizable dual-standard interleaver;convolutional turbo code;frequency 152 MHz;parallel MAP decoding;power 148.1 mW;size 90 nm;turbo decoder chip design;Bit error rate;Decoding;Iterative decoding;Kernel;Parallel processing;Throughput;WiMAX;LTE;Multi-standard;Turbo Decoder;WiMAX}
+}
+
+@Article{linche_09,
+  Title                    = {{L}ow-{P}ower {M}emory-{R}educed {T}raceback {MAP} {D}ecoding for {D}ouble-{B}inary {C}onvolutional {T}urbo {D}ecoder},
+  Author                   = {Cheng-Hung Lin and Chun-Yu Chen and Tsung-Han Tsai and An-Yeu Wu},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2009},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {1005--1016},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TCSI.2009.2017118},
+  File                     = {linche_09.pdf:linche_09.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.10.29}
+}
+
+@InProceedings{linche_08,
+  Title                    = {{L}ow-power traceback {MAP} decoding for double-binary convolutional turbo decoder},
+  Author                   = {Cheng-Hung Lin and Chun-Yu Chen and An-Yeu Wu},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2008},
+  Year                     = {2008},
+  Month                    = may,
+  Pages                    = {736--739},
+
+  Doi                      = {10.1109/ISCAS.2008.4541523},
+  File                     = {linche_08.pdf:linche_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{linche_08a,
+  Title                    = {{H}igh-throughput 12-mode {CTC} decoder for {W}i{MAX} standard},
+  Author                   = {Cheng-Hung Lin and Chun-Yu Chen and An-Yeu Wu},
+  Booktitle                = {Proc. IEEE International Symposium on VLSI Design, Automation and Test VLSI-DAT 2008},
+  Year                     = {2008},
+  Month                    = apr,
+  Pages                    = {216--219},
+
+  Doi                      = {10.1109/VDAT.2008.4542451},
+  File                     = {linche_08a.pdf:linche_08a.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.10.29}
+}
+
+@InProceedings{linshe_12,
+  Title                    = {{SECRET}: {S}elective error correction for refresh energy reduction in {DRAM}s},
+  Author                   = {Chung-Hsiang Lin and De-Yu Shen and Yi-Jung Chen and Chia-Lin Yang and Wang, M.},
+  Booktitle                = {IEEE 30th International Conference on Computer Design (ICCD)},
+  Year                     = {2012},
+  Month                    = {Sept},
+  Pages                    = {67-74},
+
+  Doi                      = {10.1109/ICCD.2012.6378619},
+  ISSN                     = {1063-6404},
+  Keywords                 = {DRAM chips;energy conservation;error correction;integrated circuit design;low-power electronics;power aware computing;DRAM power reduction;SECRET;dynamic random-access memory;error correction information;hard errors;leaky cells;low-overhead error correction mechanism;low-power DRAM design;main memory;memory cell identification;memory cells;off-line phase;process variation;refresh interval;refresh power reduction;retention errors;retention time variation;selective error correction for refresh energy reduction;single worst-case refresh period;system power consumption;target error rate;DRAM chips;Decoding;Error analysis;Error correction;Error correction codes;Memory management},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@Article{linxia_10,
+  Title                    = {{L}ow {C}omplexity {S}oft {D}ecision {T}echnique for {G}ray {M}apping {M}odulation},
+  Author                   = {Dengsheng Lin and Yue Xiao and Shaoqian Li},
+  Journal                  = {Wireless Personal Communications},
+  Year                     = {2010},
+  Number                   = {2},
+  Pages                    = {383-392},
+  Volume                   = {52},
+
+  ISSN                     = {0929-6212},
+  Keywords                 = {Gray mapping; Soft decision; PAM; PSK; QAM},
+  Language                 = {English},
+  Publisher                = {Springer US}
+}
+
+@InCollection{linshu_90,
+  Title                    = {{Folded Viterbi Decoders for Convolutional Codes}},
+  Author                   = {H.-D. Lin and C. B. Shung and D. G. Messerschmitt},
+  Booktitle                = {{VLSI Signal Processing IV}},
+  Publisher                = {IEEE},
+  Year                     = {1990},
+  Pages                    = {381--391},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{linxio_14,
+  Title                    = {{A} reduced latency list decoding algorithm for polar codes},
+  Author                   = {J. Lin and C. Xiong and Z. Yan},
+  Booktitle                = {Signal Processing Systems (SiPS), 2014 IEEE Workshop on},
+  Year                     = {2014},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/SiPS.2014.6986062},
+  Keywords                 = {cyclic codes;cyclic redundancy check codes;decoding;error correction codes;CRC;LMLD algorithm;RLLD algorithm;SCL decoding algorithm;computational complexity;cyclic redundancy check;decoding clock cycles;decoding latency;list maximum-likelihood decoding;polar codes;reduced latency list decoding algorithm;successive cancellation list;Government},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{liny_15,
+  Title                    = {{A}n {E}fficient {L}ist {D}ecoder {A}rchitecture for {P}olar {C}odes},
+  Author                   = {Jun Lin and Zhiyuan Yan},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2015},
+
+  Month                    = {Nov},
+  Number                   = {11},
+  Pages                    = {2508-2518},
+  Volume                   = {23},
+
+  Doi                      = {10.1109/TVLSI.2014.2378992},
+  ISSN                     = {1063-8210},
+  Keywords                 = {CMOS integrated circuits;cyclic redundancy check codes;memoryless systems;CMOS technology;CRC-aided SCL algorithm;TSMC;Taiwan semiconductor manufacturing company;algorithmic reformulations;arbitrary binary-input discrete memoryless channels;area efficient message memory architecture;cyclic-redundancy-check-aided SC-list-decoding algorithm;efficient list decoder architecture;efficient path pruning unit;low-complexity successive cancellation decoding algorithm;polar codes;symmetric capacity;Approximation algorithms;Computer architecture;Decoding;Degradation;Measurement;Quantization (signal);Random access memory;Hardware implementation;list decoding;polar codes;successive cancelation (SC) decoding;successive cancelation (SC) decoding.},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{liny_15a,
+  Title                    = {{A} hybrid partial sum computation unit architecture for list decoders of polar codes},
+  Author                   = {J. Lin and Z. Yan},
+  Booktitle                = {Acoustics, Speech and Signal Processing (ICASSP), 2015 IEEE International Conference on},
+  Year                     = {2015},
+  Month                    = {April},
+  Pages                    = {1076-1080},
+
+  Doi                      = {10.1109/ICASSP.2015.7178135},
+  Keywords                 = {codes;decoding;SC based list decoding algorithms;hybrid partial sum computation unit architecture;lazy copy partial sum computation algorithm;list decoders;polar codes;successive cancelation algorithm;Clocks;Computer architecture;Decoding;Encoding;Indexes;Registers;TV;Polar codes;list decoding;partial sum computation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{linyan_17,
+  Title                    = {{E}fficient {S}oft {C}ancelation {D}ecoder {A}rchitectures for {P}olar {C}odes},
+  Author                   = {J. Lin and Z. Yan and Z. Wang},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2017},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {87-99},
+  Volume                   = {25},
+
+  Abstract                 = {The flooding belief propagation (FO-BP) and the soft-cancelation (SCAN) algorithms are the two most popular soft-output BP algorithms for the decoding of capacity-achieving polar codes. The FO-BP algorithm has high throughput at the cost of performance degradation in high signal-to-noise ratio (SNR) region or with large block length. The SCAN algorithm has much better decoding performance while suffering from long decoding latency and low throughput. In this paper, an improved BP algorithm, named reduced complexity soft-cancelation (RCSC) algorithm, is proposed. Compared with the SCAN algorithm, the number of memory entries required by the RCSC algorithm is reduced by more than 50% in general, while achieving comparable or even better (e.g., when block size N = 215) decoding performance. When block size is large (e.g., N ≥ 215), the proposed RCSC algorithm reduces the required memory entries by more than 23% compared with the state-of-the-art FO-BP algorithm. The numerical results show that the error performance improvement of the RCSC algorithm is more significant when the SNR increases. For a different tradeoff, a reduced latency soft-cancelation (RLSC) algorithm is proposed to reduce the decoding latency and increase the throughput of the RCSC algorithm while slightly sacrificing decoding performance. Finally, the optimized VLSI architectures are presented for the RCSC and RLSC algorithms, respectively. The synthesis results demonstrate the efficiency of the proposed algorithms and architectures.},
+  Doi                      = {10.1109/TVLSI.2016.2577883},
+  File                     = {linyan_17.pdf:linyan_17.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {VLSI;circuit optimisation;decoding;FO-BP algorithm;RCSC algorithm;RLSC algorithm;SCAN algorithms;SNR;VLSI architectures;decoding latency;flooding belief propagation;memory entries;polar codes;reduced complexity soft-cancellation algorithm;reduced latency soft-cancellation;signal-to-noise ratio;soft cancellation decoder architectures;soft-output BP algorithms;Decoding;Iterative decoding;Memory management;Schedules;Signal to noise ratio;Throughput;Belief propagation (BP);hardware implementation;polar codes},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-27}
+}
+
+@InProceedings{linlee_06a,
+  Title                    = {{H}igh-speed {CRC} design for 10 {G}bps applications},
+  Author                   = {Jing-Shiun Lin and Chung-Kung Lee and Ming-Der Shieh and Jun-Hong Chen},
+  Booktitle                = {Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on},
+  Year                     = {2006},
+  Month                    = {May},
+  Pages                    = {4 pp.-},
+
+  Doi                      = {10.1109/ISCAS.2006.1693300},
+  File                     = {linlee_06a.pdf:linlee_06a.pdf:PDF},
+  Keywords                 = {circuit feedback;cyclic redundancy check codes;integrated circuit design;logic design;shift registers;10 Gbit/s;circuit complexity;cyclic redundancy codes;feedback loop;high-speed CRC design;linear feedback shift registers;parallel CRC circuitry;serial implementation;state-space transformation;Asynchronous transfer mode;Complexity theory;Cyclic redundancy check;Ethernet networks;Feedback circuits;Feedback loop;Hardware;Linear feedback shift registers;Protocols;Throughput},
+  Owner                    = {StW},
+  Timestamp                = {2015.12.08}
+}
+
+@InProceedings{linche_97,
+  Title                    = {{Improvements in SOVA-based decoding of turbo codes}},
+  Author                   = {L. Lin and R. S. Cheng},
+  Booktitle                = {Proc. 1996 International Conference on Communications (ICC '96)},
+  Year                     = {1997},
+  Pages                    = {1473--1478},
+
+  Optaddress               = {Montreal, Canada},
+  Optmonth                 = {#jun#},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{linjr_04,
+  Title                    = {{Error Control Coding 2nd.}},
+  Author                   = {S. Lin and D.J. Costello Jr },
+  Publisher                = {Prentice Hall PTR},
+  Year                     = {2004},
+
+  Address                  = {Upper Saddle River, New Jersey, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{linrei_01,
+  Title                    = {{R}educing {DRAM} latencies with an integrated memory hierarchy design},
+  Author                   = {Wei-Fen Lin and Reinhardt, S.K. and Burger, D.},
+  Booktitle                = {High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on},
+  Year                     = {2001},
+  Pages                    = {301-312},
+
+  Doi                      = {10.1109/HPCA.2001.903272},
+  ISSN                     = {1530-0897},
+  Keywords                 = {cache storage;memory architecture;performance evaluation;DRAM accesses;Rambus channels;benchmarks;cache blocks;integrated memory hierarchy;next-generation memory system;performance;performance gap;Banking;Clocks;Computer science;Degradation;Delay;Dynamic scheduling;Frequency;High performance computing;Prefetching;Random access memory},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.21}
+}
+
+@InProceedings{linlee_05,
+  Title                    = {{A System Solution for High-Performance, Low Power SDR}},
+  Author                   = {Yuan Lin and Hyunseok Lee and Yoav Harel and Mark Woh and Scott Mahlke and Trevor Mudge and Krisztian Flautner},
+  Booktitle                = {Software Defined Radio Technical Conference and Product Exposition},
+  Year                     = {2005},
+  Month                    = nov,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{linlee_06,
+  Title                    = {{SODA}: {A} {L}ow-power {A}rchitecture {F}or {S}oftware {R}adio},
+  Author                   = {Yuan Lin and Hyunseok Lee and Who, M. and Harel, Y. and Mahlke, S. and Mudge, T. and Chakrabarti, C. and Flautner, K.},
+  Booktitle                = {Proc. 33rd International Symposium on Computer Architecture ISCA '06},
+  Year                     = {2006},
+  Pages                    = {89--101},
+
+  Doi                      = {10.1109/ISCA.2006.37},
+  File                     = {linlee_06.pdf:linlee_06.pdf:PDF},
+  Owner                    = {May},
+  Timestamp                = {2009.10.06}
+}
+
+@InProceedings{linmah_06,
+  Title                    = {{D}esign and {I}mplementation of {T}urbo {D}ecoders for {S}oftware {D}efined {R}adio},
+  Author                   = {Yuan Lin and Mahlke, S. and Mudge, T. and Chakrabarti, C. and Reid, A. and Flautner, K.},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems Design and Implementation SIPS '06},
+  Year                     = {2006},
+  Month                    = oct,
+  Pages                    = {22--27},
+
+  Doi                      = {10.1109/SIPS.2006.352549},
+  File                     = {linmah_06.pdf:linmah_06.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@Misc{linsolutions17,
+  Title                    = {{S}olutions for {B}anking and {F}inance – {D}ata {C}enters},
+
+  Author                   = {Hugh Lindsay},
+  HowPublished             = {Data Center World Conference 2017 (Hong Kong) - Keynote. Online: \url{https://www.datacentreworldhk.com/__media/2017-Presentation-Slides/10.-DCW-Keynote/DCW-Keynote-D1-1101-1130-Hugh-Lindsay.pdf}},
+  Month                    = {May},
+  Note                     = {(Hugh Lindsay is a Global Solution Architect at Schneider Electric)},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.11.22},
+  Url                      = {https://www.datacentreworldhk.com/__media/2017-Presentation-Slides/10.-DCW-Keynote/DCW-Keynote-D1-1101-1130-Hugh-Lindsay.pdf}
+}
+
+@InProceedings{lin_00,
+  Title                    = {{Optimal Turbo Decoding Metric Generation in a Pilot Assisted Coherent Wireless Communication System}},
+  Author                   = {F. Ling},
+  Booktitle                = {Proc. 2000-Fall Vehicular Technology Conference (VTC '00 Fall)},
+  Year                     = {2000},
+
+  Address                  = {Boston, Massachusetts, USA},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{lip_01,
+  Title                    = {{M}athematical methods for foreign exchange. {A} financial engineer's approach.},
+  Author                   = {Lipton, Alexander},
+  Publisher                = {World Scientific},
+  Year                     = {2001},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {foreign exchange rate; dynamic stochastic process; discrete and continuous stochastic engines; Black-Scholes paradigm; European options; American options; Asian options},
+  Classmath                = {{*91-02 (Research exposition (Social and behavioral sciences)) 91B28 (Finance etc.) 91B64 (Macro-economic models) }},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Owner                    = {marxen},
+  Reviewer                 = {{C.L.Parihar (Indore)}},
+  Timestamp                = {2011.07.19}
+}
+
+@Article{litweh_04,
+  Title                    = {{Research Center 'Ambient Intelligence' at the University of Kaiserslautern}},
+  Author                   = {L. Litz and N. Wehn and B. Schürmann},
+  Journal                  = {VDE-Kongress 2004},
+  Year                     = {2004},
+  Pages                    = {19-24},
+  Volume                   = {1},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Article{liulin_04,
+  Title                    = {{T}urbo encoding and decoding of {R}eed-{S}olomon codes through binary decomposition and self-concatenation},
+  Author                   = {Liu, C. Y. and Lin, S.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2004},
+  Number                   = {9},
+  Pages                    = {1484--1493},
+  Volume                   = {52},
+
+  Doi                      = {10.1109/TCOMM.2004.833189},
+  File                     = {liulin_04.pdf:liulin_04.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{liuyen_08,
+  Title                    = {{A}n {LDPC} {D}ecoder {C}hip {B}ased on {S}elf-{R}outing {N}etwork for {IEEE} 802.16e {A}pplications},
+  Author                   = {Chih-Hao Liu and Shau-Wei Yen and Chih-Lung Chen and Hsie-Chia Chang and Chen-Yi Lee and Yar-Sun Hsu and Shyh-Jye Jou},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2008},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {684--694},
+  Volume                   = {43},
+
+  Doi                      = {10.1109/JSSC.2007.916610},
+  File                     = {liuyen_08.pdf:liuyen_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@MastersThesis{MTliu14,
+  Title                    = {{A}ccelerating {F}inance: {H}eston model calibration with {FFT} methods},
+  Author                   = {Gongda Liu},
+  School                   = {University of Kaiserslautern, Supervisor: N. Wehn, C. Brugger},
+  Year                     = {2014},
+  Month                    = Dec,
+  Type                     = {Master Thesis},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.23}
+}
+
+@InCollection{liubru_15,
+  Title                    = {{A}ccelerating {C}losed-{F}orm {H}eston {P}ricers for {C}alibration},
+  Author                   = {Gongda Liu and Christian Brugger and Christian De Schryver and Norbert Wehn},
+  Booktitle                = {FPGA Based Accelerators for Financial Applications},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2015},
+  Edition                  = {1st},
+  Editor                   = {De Schryver, Christian},
+  Month                    = jul,
+  Pages                    = {221--242},
+
+  Abstract                 = {Calibrating models against the markets is a crucial step to obtain meaningful results in the subsequent pricing processes. In general, calibration can be seen as a minimization problem that tries to fit modeled product prices to the observed ones on the market (compare Chap. 2 by Sayer and Wenzel). This means that during the calibration process the modeled prices need to be calculated many times, and therefore the run time of the product pricers have the highest impact on the overall calibration run time. Therefore, in general, only products are used for calibration for which closed-form mathematical pricing formulas are known.
+While for the Heston model (semi) closed-form solutions exist for simple products, their evaluation involves complex functions and infinite integrals. So far these integrals can only be solved with time-consuming numerical methods. However, over the time, more and more theoretical and practical subtleties have been revealed for doing this and today a large number of possible approaches are known. Examples are different formulations of closed-formulas and various integration algorithms like quadrature or Fourier methods. Nevertheless, all options only work under specific conditions and depend on the Heston model parameters and the input setting.
+In this chapter we present a methodology how to determine the most appropriate calibration method at run time. For a practical setup we study the available popular closed-form solutions and integration algorithms from literature. In total we compare 14 pricing methods, including adaptive quadrature and Fourier methods. For a target accuracy of 10−3 we show that static Gauss-Legendre are best on Central Processing Units (CPUs) for the unrestricted parameter set. Further we show that for restricted Carr-Madan formulation the methods are 3.6× faster. We also show that Fourier methods are even better when pricing at least 10 options with the same maturity but different strikes.},
+  Doi                      = {10.1007/978-3-319-15407-7_10},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-08-21}
+}
+
+@Article{Liu2010,
+  Title                    = {{O}n the {D}ecomposition {M}ethod for {L}inear {P}rogramming {D}ecoding of {LDPC} {C}odes},
+  Author                   = {Liu, H. and Qu, W. and Liu, B. and Chen, J.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2010},
+  Number                   = {12},
+  Pages                    = {3448--3458},
+  Volume                   = {58},
+
+  Doi                      = {10.1109/TCOMM.2010.102910.090490},
+  File                     = {liuqu_10.pdf:liuqu_10.pdf:PDF},
+  Keywords                 = {LPDecoding, LDPC},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.08},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5628280}
+}
+
+@Article{liujai_13,
+  Title                    = {{A}n {E}xperimental {S}tudy of {D}ata {R}etention {B}ehavior in {M}odern {DRAM} {D}evices: {I}mplications for {R}etention {T}ime {P}rofiling {M}echanisms},
+  Author                   = {Liu, Jamie and Jaiyen, Ben and Kim, Yoongu and Wilkerson, Chris and Mutlu, Onur},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {2013},
+
+  Month                    = jun,
+  Number                   = {3},
+  Pages                    = {60--71},
+  Volume                   = {41},
+
+  Acmid                    = {2485928},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/2508148.2485928},
+  ISSN                     = {0163-5964},
+  Issue_date               = {June 2013},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2015.07.06},
+  Url                      = {http://doi.acm.org/10.1145/2508148.2485928}
+}
+
+@InProceedings{liujai_12,
+  Title                    = {{RAIDR}: {R}etention-{A}ware {I}ntelligent {DRAM} {R}efresh},
+  Author                   = {Liu, Jamie and Jaiyen, Ben and Veras, Richard and Mutlu, Onur},
+  Booktitle                = {Proceedings of the 39th Annual International Symposium on Computer Architecture},
+  Year                     = {2012},
+
+  Address                  = {Washington, DC, USA},
+  Pages                    = {1--12},
+  Publisher                = {IEEE Computer Society},
+  Series                   = {ISCA '12},
+
+  Acmid                    = {2337161},
+  ISBN                     = {978-1-4503-1642-2},
+  Location                 = {Portland, Oregon},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.09},
+  Url                      = {http://dl.acm.org/citation.cfm?id=2337159.2337161}
+}
+
+@InProceedings{liupey_14,
+  Title                    = {{FPGA} implementation of an interior point method for high-speed model predictive control},
+  Author                   = {J. Liu and H. Peyrl and A. Burg and G. A. Constantinides},
+  Booktitle                = {2014 24th International Conference on Field Programmable Logic and Applications (FPL)},
+  Year                     = {2014},
+  Month                    = {Sept},
+  Pages                    = {1-8},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [19]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/FPL.2014.6927473},
+  ISSN                     = {1946-147X},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {control system synthesis;embedded systems;field programmable gate arrays;predictive control;predictor-corrector methods;quadratic programming;velocity control;{FPGA} implementation;interior point method;high-speed model predictive control;hardware architecture;quadratic programs;high-end {CPU};embedded industrial control applications;{MPC}-specific problem structure;direct linear equation solver;predictor-corrector algorithm;modular design;embedded computing platforms;Pipelines;Hardware;Field programmable gate arrays;Equations;Vectors;Optimization;Computer architecture},
+  Owner                    = {CCR}
+}
+
+@Article{liu_84,
+  Title                    = {{A}rchitecture for {VLSI} {D}esign of {R}eed-{S}olomon {D}ecoders},
+  Author                   = {Liu, Kuang Yung},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {1984},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {178-189},
+  Volume                   = {C-33},
+
+  Abstract                 = {In this paper, the known decoding procedures for Reed-Solomon (RS) codes are modified to obtain a repetitive and recursive decoding technique which is suitable for VLSI implementation and pipelining. The chip architectures of two basic building blocks for VLSI RS decoder systems are then presented. It is shown that a VLSI RS decoder has the potential advantage of achieving a high decoding speed through parallel-pipeline processing.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TC.1984.1676409},
+  File                     = {liu_84.pdf:liu_84.pdf:PDF},
+  ISSN                     = {0018-9340},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2009.05.14}
+}
+
+@Article{liu_14,
+  Title                    = {{E}nergy-{E}fficient {S}oft-{I}nput {S}oft-{O}utput {S}ignal {D}etector for {I}terative {MIMO} {R}eceivers},
+  Author                   = {L. Liu},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2014},
+
+  Month                    = {Aug},
+  Number                   = {8},
+  Pages                    = {2422-2432},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCSI.2014.2304657},
+  File                     = {liu_14.pdf:liu_14.pdf:PDF},
+  ISSN                     = {1549-8328},
+  Keywords                 = {MIMO communication;VLSI;computational complexity;decoding;integrated circuit reliability;iterative methods;radio receivers;search problems;signal detection;trees (mathematics);2-iteration modes;4-iteration modes;adaptive tree-travel control scheme;algorithm-level techniques;block-level clock gating;computational complexity;detector core;energy 127.9 pJ;energy 149.5 pJ;energy 98.5 pJ;energy-efficient soft-input soft-output signal detector;frequency 240 MHz;frequency-selective channels;hybrid node enumeration technique;imbalanced fixed complexity sphere decoder;iterative MIMO receivers;multiple-input multiple-output receiver;multistage parallel VLSI architecture;near-optimal detection performance;open-loop modes;post-layout simulation;reliability-dependent log-likelihood ratio correction method;size 65 nm;tree-search space;voltage 1.0 V;Complexity theory;Decoding;Detectors;Iterative decoding;Receivers;Reliability;Vectors;Energy efficient;multiple-input multiple-output (MIMO);signal detector;soft-input soft-output (SISO);very-large scale integration (VLSI)},
+  Owner                    = {MH},
+  Timestamp                = {2017-02-15}
+}
+
+@Article{liuye_10,
+  Title                    = {{A} 1.1-{G}b/s 115-p{J}/bit {C}onfigurable {MIMO} {D}etector {U}sing 0.13- $muhbox{m}$ {CMOS} {T}echnology},
+  Author                   = {L. Liu and F. Ye and X. Ma and T. Zhang and J. Ren},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2010},
+  Number                   = {9},
+  Pages                    = {701--705},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TCSII.2010.2058494},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@InProceedings{liunel_10,
+  Title                    = {{S}imulation on demand for pricing many securities},
+  Author                   = {M. Liu and B. L. Nelson and J. Staum},
+  Booktitle                = {Proceedings of the 2010 Winter Simulation Conference},
+  Year                     = {2010},
+  Month                    = {Dec.},
+  Pages                    = {2782--2789},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.10}
+}
+
+@Article{liuhem_17,
+  Title                    = {3{D}-{S}tacked {M}any-{C}ore {A}rchitecture for {B}iological {S}equence {A}nalysis {P}roblems},
+  Author                   = {Liu, Pei
+and Hemani, Ahmed
+and Paul, Kolin
+and Weis, Christian
+and Jung, Matthias
+and Wehn, Norbert},
+  Journal                  = {International Journal of Parallel Programming},
+  Year                     = {2017},
+  Pages                    = {1--41},
+
+  Abstract                 = {Sequence analysis plays extremely important role in bioinformatics, and most applications of which have compute intensive kernels consuming over 70{\%} of total execution time. By exploiting the compute intensive execution stages of popular sequence analysis applications, we present and evaluate a VLSI architecture with a focus on those that target at biological sequences directly, including pairwise sequence alignment, multiple sequence alignment, database search, and short read sequence mappings. Based on coarse grained reconfigurable array we propose the use of many-core and 3D-stacked technologies to gain further improvement over memory subsystem, which gives another order of magnitude speedup from high bandwidth and low access latency. We analyze our approach in terms of its throughput and efficiency for different application mappings. Initial experimental results are evaluated from a stripped down implementation in a commodity FPGA, and then we scale the results to estimate the performance of our architecture with 9 layers of {\$}{\$}70 {\backslash}hbox {\{} mm{\}}^{\{}2{\}}{\$}{\$} 70 mm 2 stacked wafers in 45-nm process. We demonstrate numerous estimated speedups better than corresponding existed hardware accelerator platforms for at least 40 times for the entire range of applications and datasets of interest. In comparison, the alternative FPGA based accelerators deliver only improvement for single application, while GPGPUs perform not well enough on accelerating program kernel with random memory access and integer addition/comparison operations.},
+  Doi                      = {10.1007/s10766-017-0495-0},
+  ISSN                     = {1573-7640},
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17},
+  Url                      = {http://dx.doi.org/10.1007/s10766-017-0495-0}
+}
+
+@Article{liuhem_16,
+  Title                    = {{A} {C}ustomized {M}any-{C}ore {H}ardware {A}cceleration {P}latform for {S}hort {R}ead {M}apping {P}roblems {U}sing {D}istributed {M}emory {I}nterface with 3{D}--{S}tacked {A}rchitecture},
+  Author                   = {Liu, Pei and Hemani, Ahmed and Paul, Kolin and Weis, Christian and Jung, Matthias and Wehn, Norbert},
+  Journal                  = {Journal of Signal Processing Systems},
+  Year                     = {2016},
+  Pages                    = {1--15},
+
+  Abstract                 = {Rapidly developing Next Generation Sequencing technologies produce huge amounts of short reads that consisting randomly fragmented DNA base pair strings. Assembling of those short reads poses a challenge on the mapping of reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a customized many-core hardware acceleration platform for short read mapping problems based on hash-index method. The processing core is highly customized to suite both 2-hit string matching and banded Smith-Waterman sequence alignment operations, while distributed memory interface with 3D--stacked architecture provides high bandwidth and low access latency for highly customized dataset partitioning and memory access scheduling. Conformal with original BFAST program, our design provides an amazingly 45,012 times speedup over software approach for single-end short reads and 21,102 times for paired-end short reads, while also beats similar single FPGA solution for 1466 times in case of single end reads. Optimized seed generation gives much better sensitivity while the performance boost is still impressive.},
+  Doi                      = {10.1007/s11265-016-1204-8},
+  ISSN                     = {1939-8115},
+  Owner                    = {MJ},
+  Timestamp                = {2017-01-01},
+  Url                      = {http://dx.doi.org/10.1007/s11265-016-1204-8}
+}
+
+@Article{liupar_09,
+  Title                    = {{L}ow-{L}atency {L}ow-{C}omplexity {A}rchitectures for {V}iterbi {D}ecoders},
+  Author                   = {R. Liu and K. K. Parhi},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2009},
+
+  Month                    = {Oct},
+  Number                   = {10},
+  Pages                    = {2315-2324},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TCSI.2008.2012217},
+  File                     = {liupar_09.pdf:liupar_09.pdf:PDF},
+  ISSN                     = {1549-8328},
+  Keywords                 = {Viterbi decoding;computational complexity;Viterbi decoders;binary trellis;branch metric precomputation;complexity reduction;look-ahead level;low-latency low-complexity architectures;nonlinear add-compare-select unit;one-step complex trellis;time sequence;Balanced binary grouping (BBG);Viterbi decoder;look-ahead technique;low latency;precomputation;trellis},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.18}
+}
+
+@InProceedings{liupar_08,
+  Title                    = {{M}inimal complexity low-latency architectures for {V}iterbi decoders},
+  Author                   = {R. Liu and K. K. Parhi},
+  Booktitle                = {2008 IEEE Workshop on Signal Processing Systems},
+  Year                     = {2008},
+  Month                    = {Oct},
+  Pages                    = {140-145},
+
+  Doi                      = {10.1109/SIPS.2008.4671752},
+  File                     = {liupar_08.pdf:liupar_08.pdf:PDF},
+  ISSN                     = {2162-3562},
+  Keywords                 = {Viterbi decoding;trellis codes;Viterbi decoders;add-compare-select unit;binary trellis steps;branch metrics precomputation unit;complex trellis step;computational redundancy;look-ahead techniques;minimal complexity low-latency architectures;Cities and towns;Computer architecture;Convolutional codes;Delay;Iterative decoding;Logic;Mathematical model;System performance;Throughput;Viterbi algorithm;Viterbi decoder;look-ahead technique;low complexity;low latency;pre-computation;trellis},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.18}
+}
+
+@Article{liupat_11,
+  Title                    = {{F}likker: {S}aving {DRAM} {R}efresh-power {T}hrough {C}ritical {D}ata {P}artitioning},
+  Author                   = {Liu, Song and Pattabiraman, Karthik and Moscibroda, Thomas and Zorn, Benjamin G.},
+  Journal                  = {SIGPLAN Not.},
+  Year                     = {2011},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {213--224},
+  Volume                   = {46},
+
+  Acmid                    = {1950391},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/1961296.1950391},
+  ISSN                     = {0362-1340},
+  Issue_date               = {March 2011},
+  Keywords                 = {allocation, critical data, dram refresh, power-savings, soft errors},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2015.07.06},
+  Url                      = {http://doi.acm.org/10.1145/1961296.1950391}
+}
+
+@InProceedings{liuyan_13,
+  Title                    = {{A} 130.7mm lt;sup gt;2 lt;/sup gt; 2-layer 32{G}b {R}e{RAM} memory device in 24nm technology},
+  Author                   = {T. Liu and T. H. Yan and R. Scheuerlein and Y. Chen and J. K. Lee and G. Balakrishnan and G. Yee and H. Zhang and A. Yap and J. Ouyang and T. Sasaki and S. Addepalli and A. Al-Shamma and C. Chen and M. Gupta and G. Hilton and S. Joshi and A. Kathuria and V. Lai and D. Masiwal and M. Matsumoto and A. Nigam and A. Pai and J. Pakhale and C. H. Siau and X. Wu and R. Yin and L. Peng and J. Y. Kang and S. Huynh and H. Wang and N. Nagel and Y. Tanaka and M. Higashitani and T. Minvielle and C. Gorla and T. Tsukamoto and T. Yamaguchi and M. Okajima and T. Okamura and S. Takase and T. Hara and H. Inoue and L. Fasoli and M. Mofidi and R. Shrivastava and K. Quader},
+  Booktitle                = {2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers},
+  Year                     = {2013},
+  Month                    = {Feb},
+  Pages                    = {210-211},
+
+  Doi                      = {10.1109/ISSCC.2013.6487703},
+  ISSN                     = {0193-6530},
+  Keywords                 = {integrated circuit reliability;random-access storage;two layer ReRAM memory device;next-generation nonvolatile memory;multiple-layered architectures;reliability;MeOx-based ReRAM test chip;size 24 nm;storage capacity 32 Gbit;Arrays;Charge pumps;Clocks;Temperature sensors;Leakage currents},
+  Timestamp                = {2018-08-29}
+}
+
+@InProceedings{liurho_06,
+  Title                    = {{L}ow-{P}ower {H}igh-{T}hroughput {BCH} {E}rror {C}orrection {VLSI} {D}esign for {M}ulti-{L}evel {C}ell {NAND} {F}lash {M}emories},
+  Author                   = {Wei Liu and Junrye Rho and Wonyong Sung},
+  Booktitle                = {Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on},
+  Year                     = {2006},
+  Month                    = oct,
+  Pages                    = {303--308},
+
+  Abstract                 = {As the reliability is a critical issue for new generation multi-level cell (MLC) flash memories, there is growing call for fast and compact error correction code (ECC) circuit with minimum impact on memory access time and chip area. This paper presents a high-throughput and low-power ECC scheme for MLC NAND flash memories. The BCH encoder and decoder architecture features byte-wise processing and a low complexity key equation solver using a simplified Berlekamp-Massey algorithm. Resource sharing and power reduction techniques are also applied. Synthesized using 0.25-mum CMOS technology in a supply voltage of 2.5 V, the proposed BCH (4148,4096) encoder/decoder achieves byte-wise processing, and it needs an estimated cell area of 0.2 mm2, and an average power of 3.18 mW with 50 MB/s throughput},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/SIPS.2006.352599},
+  File                     = {liurho_06.pdf:liurho_06.pdf:PDF},
+  ISSN                     = {1520-6130},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.22}
+}
+
+@Article{Liu2012,
+  Title                    = {{A} {C}arrier {E}stimation {M}ethod for {MF}-{TDMA} {S}ignal {M}onitoring},
+  Author                   = {Liu, Xi and Feng, Wenquan and Li, Chunsheng and Ma, Chao},
+  Journal                  = {Journal of Networks},
+  Year                     = {2012},
+  Number                   = {8},
+  Pages                    = {1170--1175},
+  Volume                   = {7},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.03.26}
+}
+
+@InProceedings{liupap_02,
+  Title                    = {{Design of a High-Troughput Low-Power IS95 Viterbi Decoder}},
+  Author                   = {X. Liu and M. C. Papaefthymiou},
+  Booktitle                = {Proc. 2002 Design Automation Conference (DAC '02)},
+  Year                     = {2002},
+
+  Address                  = {New Orleans, Louisiana, USA},
+  Month                    = jun,
+  Pages                    = {263-268},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{liusu_19,
+  Title                    = {{A} 130-nm {F}erroelectric {N}onvolatile {S}ystem-on-{C}hip {W}ith {D}irect {P}eripheral {R}estore {A}rchitecture for {T}ransient {C}omputing {S}ystem},
+  Author                   = {Y. {Liu} and F. {Su} and Y. {Yang} and Z. {Wang} and Y. {Wang} and Z. {Li} and X. {Li} and R. {Yoshimura} and T. {Naiki} and T. {Tsuwa} and T. {Saito} and Z. {Wang} and K. {Taniuchi} and H. {Yang}},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2019},
+
+  Month                    = {March},
+  Number                   = {3},
+  Pages                    = {885-895},
+  Volume                   = {54},
+
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8604003},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/JSSC.2018.2884349},
+  Keywords                 = {TCS},
+  Keywords_original        = {CMOS memory circuits;ferroelectric devices;microprocessor chips;random-access storage;system-on-chip;on-chip power management subsystem;versatile power policies;direct peripheral restore architecture;peripheral devices;power supply;test chip;conventional NVP;system-on-chip;transient computing system;computation progress;power outages;nonvolatile processor;energy-harvesting-powered Internet-of-Things devices;widespread application;system integration issues;configuration overheads;improved integration level;power management flexibility;system wake-up speed;power failures;ferroelectric-CMOS process;size 130 nm;Nonvolatile memory;Power system management;Transient analysis;Computer architecture;Random access memory;Detectors;Voltage control;Energy harvesting;nonvolatile processor (NVP);transient computing},
+  Owner                    = {CCR}
+}
+
+@Article{liuzha_09,
+  Title                    = {{D}esign of {V}oltage {O}verscaled {L}ow-{P}ower {T}rellis {D}ecoders in {P}resence of {P}rocess {V}ariations},
+  Author                   = {Yang Liu and Tong Zhang and Jiang Hu},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2009},
+  Number                   = {3},
+  Pages                    = {439--443},
+  Volume                   = {17},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Viterbi, Turbo
+- Clock skew aware scheduling, Transactions, see liuzha_06},
+  Doi                      = {10.1109/TVLSI.2008.2004545},
+  File                     = {liuzha_09.pdf:liuzha_09.pdf:PDF},
+  Keywords                 = {Reliability, Convolutional},
+  Owner                    = {May},
+  Timestamp                = {2011.10.04}
+}
+
+@Article{livrya_08,
+  Title                    = {{Q}uasi-cyclic generalized ldpc codes with low error floors},
+  Author                   = {Liva, G. and Ryan, W. E. and Chiani, M.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2008},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {49--57},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TCOMM.2008.050600},
+  File                     = {livrya_08.pdf:livrya_08.pdf:PDF},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.08.03}
+}
+
+@Misc{llcstac12,
+  Title                    = {{STAC}-{A}2 {C}entral},
+
+  Author                   = {Securities Technology Analysis Center LLC},
+  HowPublished             = {\url{https://stacresearch.com/a2}},
+  Note                     = {last access 2015-02-14},
+  Year                     = {2012},
+
+  Keywords                 = {finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-02-14}
+}
+
+@InProceedings{lodker_04,
+  Title                    = {{V}ector {S}oft-in-soft-out {D}ecoding of {L}inear {B}lock {C}odes},
+  Author                   = {J. Lodge and R. Kerr},
+  Booktitle                = {Proceedings of the 22nd Biennial Symposium on Communications},
+  Year                     = {2004},
+  Pages                    = {373-375},
+
+  File                     = {lodker_04.pdf:lodker_04.pdf:PDF},
+  Owner                    = {Scholl},
+  Review                   = {Urpaper zum Vector SISO},
+  Timestamp                = {2011.07.21}
+}
+
+@InProceedings{lodyou_93,
+  Title                    = {{Separable MAP ``Filters'' for the Decoding of Product and Concatenated Codes}},
+  Author                   = {J. Lodge and R. Young and P. Hoeher and J. Hagenauer},
+  Booktitle                = {Proc. 1993 International Conference on Communications (ICC '93)},
+  Year                     = {1993},
+
+  Address                  = {Geneva, Switzerland},
+  Month                    = may,
+  Pages                    = {1740--1745},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{lodcap_06,
+  Title                    = {{XiSystem: a XiRisc-based SoC with Reconfigurable IO Module}},
+  Author                   = {Lodi, A. and Cappelli, A. and Bocchi, M. and Mucci, C. and Innocenti, M. and De Bartolomeis, C. and Ciccarelli, L. and Giansante, R. and Deledda, A. and Campi, F. and Toma, M. and Guerrieri, R.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2006},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {85--96},
+  Volume                   = {41},
+
+  Doi                      = {10.1109/JSSC.2005.859319},
+  Owner                    = {vogt},
+  Timestamp                = {2006.08.31}
+}
+
+@Article{loelus_01,
+  Title                    = {{Probability Propagation and Decoding in Analog VLSI}},
+  Author                   = {Loeliger, H.-A. and F. Lustenberger and M. Helfenstein and F. Tarköy},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {837--843},
+  Volume                   = {47},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{loelus_98,
+  Title                    = {{Probability Propagation and Decoding in Analog VLSI}},
+  Author                   = {H.-A. Loeliger and F. Lustenberger and M. Helfenstein and F. Tarköy},
+  Booktitle                = {Proc. 1998 International Symposium in Information Theory (ISIT '98)},
+  Year                     = {1998},
+
+  Address                  = {Cambridge, Massachusetts, USA},
+  Month                    = aug,
+  Pages                    = {146},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{loflod_05,
+  Title                    = {{A}n analysis of {FPGA}-based {UDP}/{IP} stack parallelism for embedded {E}thernet connectivity},
+  Author                   = {Löfgren, A. and Lodesten, L. and Sjöholm, S. and Hansson, H.},
+  Booktitle                = {NORCHIP Conference, 2005. 23rd},
+  Year                     = {2005},
+  Pages                    = {94--97},
+
+  Abstract                 = {When designing FPGA-based Ethernet connected embedded systems the priority and necessity of requirements such as cost, area, flexibility etc. varies for each system. Simplified for most systems, it can be stated that no extra functionality than required is desired. Hence, when designing a UDP/IP stack in an FPGA a single UDP/IP stack "template" design is not suitable to effectively realize the different embedded network system requirements. We present three different UDP/IP stack cores, with different grades of parallelism and suited for various network demands. We show that the UDP/IP core area can be reduced to 1/3 of the original size with an appropriate implementation, accomplished by a trade-off between parallelism/latency and area. Furthermore guidelines are proposed on how to perform the trade-off between parallelism, area (cost), flexibility and functionality when designing an UDP/IP stack for compact embedded network systems.},
+  Cds_grade                = {3},
+  Cds_keywords             = {FPGA, rapid Prototyping, Hardware-in-the-loop, ethernet, UDP},
+  Cds_read                 = {2013-10-02},
+  Cds_review               = {hardware UDP stack implementation},
+  Doi                      = {10.1109/NORCHP.2005.1596997},
+  File                     = {loflod_05.pdf:loflod_05.pdf:PDF}
+}
+
+@InProceedings{loimit_08,
+  Title                    = {{A} low-overhead fault tolerance scheme for {TSV}-based 3{D} network on chip links},
+  Author                   = {Loi, I. and Mitra, S. and Lee, T. H. and Fujita, S. and Benini, L. },
+  Booktitle                = {Proc. IEEE/ACM International Conference on Computer-Aided Design ICCAD 2008},
+  Year                     = {2008},
+  Month                    = nov,
+  Pages                    = {598--602},
+
+  Doi                      = {10.1109/ICCAD.2008.4681638},
+  File                     = {loimit_08.pdf:loimit_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.14}
+}
+
+@InProceedings{loiwed_08,
+  Title                    = {{Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking}},
+  Author                   = {Sacha Loitz and Markus Wedler and Christian Brehm and Timo Vogt and N. Wehn and Wolfgang Kunz},
+  Booktitle                = {Proc. Symposium on Application Specific Processors SASP 2008},
+  Year                     = {2008},
+
+  Address                  = {Anaheim, CA, USA},
+  Month                    = jun,
+  Pages                    = {48--54},
+
+  File                     = {loiwed_08.pdf:loiwed_08.pdf:PDF},
+  Owner                    = {alles},
+  Timestamp                = {2008.09.25}
+}
+
+@Book{loiwed_11,
+  Title                    = {{F}ormal {H}ardware/{S}oftware {C}o-verification of {A}pplication {S}pecific {I}nstruction {S}et {P}rocessors},
+  Author                   = {S. Loitz and M. Wedler and D. Stoffel and C. Brehm and W. Kunz and N. Wehn},
+  Editor                   = {Tom J. Kamierski and Adam Morawiec},
+  Publisher                = {System Specification and Design Languages: Selected Contributions from FDL 2010},
+  Year                     = {2011},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@InProceedings{lonjoh_06,
+  Title                    = {{Iterative BEAST-Decoding of Product Codes}},
+  Author                   = {M. Loncar and R. Johannesson and I.E. Bocharova and B.D. Kudryashov},
+  Booktitle                = {Proc. 4nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2006},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lonker_11,
+  Title                    = {{P}arallel move blocking {M}odel {P}redictive {C}ontrol},
+  Author                   = {S. Longo and E. C. Kerrigan and K. V. Ling and G. A. Constantinides},
+  Booktitle                = {2011 50th IEEE Conference on Decision and Control and European Control Conference},
+  Year                     = {2011},
+  Month                    = {Dec},
+  Pages                    = {1239-1244},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{GPU} PLATFORM; cite number in presentation [16]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/CDC.2011.6160429},
+  ISSN                     = {0191-2216},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {control engineering computing;delays;matrix algebra;optimisation;parallel architectures;predictive control;parallel move blocking model predictive control algorithm;parallel computing architectures;multicore;{FPGA};{GPU};optimization problems;computational delay;closed-loop cost;blocking matrices;Stability analysis;Vectors;Optimization;Hardware;Field programmable gate arrays;Indexes;Transmission line matrix methods},
+  Owner                    = {CCR}
+}
+
+@Article{lonsch_01,
+  Title                    = {{V}aluing {A}merican options by simulation: {A} simple least-squares approach},
+  Author                   = {Longstaff, Francis A and Schwartz, Eduardo S},
+  Journal                  = {Review of Financial studies},
+  Year                     = {2001},
+  Number                   = {1},
+  Pages                    = {113--147},
+  Volume                   = {14},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {Longstaff-Schwartz, American options},
+  File                     = {lonsch_01.pdf:lonsch_01.pdf:PDF},
+  Keywords                 = {fiannce},
+  Owner                    = {CdS},
+  Publisher                = {Soc Financial Studies},
+  Timestamp                = {2014.06.12}
+}
+
+@InProceedings{looalu_03,
+  Title                    = {{H}igh performance parallelised 3{GPP} turbo decoder},
+  Author                   = {Loo, K. K. and Alukaidey, T. and Jimaa, S. A.},
+  Booktitle                = {Proc. 5th European (Conf Personal Mobile Communications Conference Publ. No. 492)},
+  Year                     = {2003},
+  Month                    = apr,
+  Pages                    = {337--342},
+
+  File                     = {looalu_03.pdf:looalu_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.08.14}
+}
+
+@InProceedings{lopbue_16,
+  Title                    = {{T}owards 100 {G}bps wireless communication: energy efficiency of {ARQ}, {FEC}, and {RF}-frontends},
+  Author                   = {Lopacinski, Lukasz and Buechner, Steffen and Nolte, Joerg and Brzozowski, Marcin and Kraemer, Rolf},
+  Booktitle                = {Wireless Communication Systems (ISWCS), 2016 International Symposium on},
+  Year                     = {2016},
+  Organization             = {IEEE},
+  Pages                    = {320--324},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.05.09}
+}
+
+@InProceedings{lopmuj_02,
+  Title                    = {{A} low-power architecture for maximum a posteriori decoding},
+  Author                   = {Lopez-Vallejo, M. and Mujtaba, S. A. and Inkyu Lee},
+  Booktitle                = {Proc. Conf Signals, Systems and Computers Record of the Thirty-Sixth Asilomar Conf},
+  Year                     = {2002},
+  Pages                    = {47--51},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ACSSC.2002.1197147},
+  File                     = {lopmuj_02.pdf:lopmuj_02.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@TechReport{lorkah_06,
+  Title                    = {{O}ptimal {F}ourier inversion in semi-analytical option pricing},
+  Author                   = {Lord, Roger and Kahl, Christian},
+  Institution              = {Tinbergen Institute Discussion Paper},
+  Year                     = {2006},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.08.21}
+}
+
+@Article{lorkoe_10,
+  Title                    = {{A} comparison of biased simulation schemes for stochastic volatility models},
+  Author                   = {Roger Lord and Remmert Koekkoek and Dick van Dijk},
+  Journal                  = {Quantitative Finance},
+  Year                     = {2010},
+  Number                   = {2},
+  Pages                    = {177-194},
+  Volume                   = {10},
+
+  Abstract                 = {Using an Euler discretisation to simulate a mean-reverting CEV process gives rise to the problem that while the process itself is guaranteed to be nonnegative, the discretisation is not. Although an exact and efficient simulation algorithm exists for this process, at present this is not the case for the CEV-SV stochastic volatility model, with the Heston model as a special case, where the variance is modelled as a mean-reverting CEV process. Consequently, when using an Euler discretisation, one must carefully think about how to fix negative variances. Our contribution is threefold. Firstly, we unify all Euler fixes into a single general framework. Secondly, we introduce the new full truncation scheme, tailored to minimise the positive bias found when pricing European options. Thirdly and finally, we numerically compare all Euler fixes to recent quasi-second order schemes of Kahl and Jäckel and Ninomiya and Victoir, as well as to the exact scheme of Broadie and Kaya. The choice of fix is found to be extremely important. The full truncation scheme outperforms all considered biased schemes in terms of bias and root-mean-squared error.},
+  Cds_grade                = {0},
+  Cds_review               = {several stochastic examinations on Heston model},
+  File                     = {lorkoe_10.pdf:lorkoe_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.23}
+}
+
+@Article{lotlui_04,
+  Title                    = {{Embedding Carrier Phase Recovery Into Iterative Decoding of Turbo-Coded Linear Modulations}},
+  Author                   = {V. Lottici and M. Luise},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2004},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {661--669},
+  Volume                   = {52},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{louche_96,
+  Title                    = {{Performance of Punctured Channel Codes with ARQ for Multimedia Transmission in Rayleigh Fading Channels}},
+  Author                   = {Lou, H. and Cheung, A.S.},
+  Booktitle                = {Vehicular Technology Conference, 1996. 'Mobile Technology for the Human Race'., IEEE 46th},
+  Year                     = {1996},
+  Month                    = apr # {--} # may,
+  Pages                    = {282--286vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/VETEC.1996.503453},
+  Owner                    = {vogt},
+  Timestamp                = {2007.01.29}
+}
+
+@Article{loubou_93,
+  Title                    = {{O}n maximum likelihood soft-decision decoding of binary linear codes},
+  Author                   = {N. J. C. Lous and P. A. H. Bours and H. C. A. van Tilborg},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1993},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {197-203},
+  Volume                   = {39},
+
+  Doi                      = {10.1109/18.179358},
+  ISSN                     = {0018-9448},
+  Keywords                 = {decoding;error correction codes;binary linear codes;bounding techniques;branching techniques;codeword;column patterns;error patterns;maximum likelihood soft-decision decoding;Error correction codes;Euclidean distance;Information theory;Linear code;Maximum likelihood decoding;Notice of Violation;Parity check codes;Read only memory;Vectors;Welding}
+}
+
+@Misc{lowgem520,
+  Title                    = {{T}he gem5 {S}imulator: {V}ersion 20.0+},
+
+  Author                   = {Jason Lowe-Power and Abdul Mutaal Ahmad and Ayaz Akram and Mohammad Alian and Rico Amslinger and Matteo Andreozzi and Adrià Armejach and Nils Asmussen and Srikant Bharadwaj and Gabe Black and Gedare Bloom and Bobby R. Bruce and Daniel Rodrigues Carvalho and Jeronimo Castrillon and Lizhong Chen and Nicolas Derumigny and Stephan Diestelhorst and Wendy Elsasser and Marjan Fariborz and Amin Farmahini-Farahani and Pouya Fotouhi and Ryan Gambord and Jayneel Gandhi and Dibakar Gope and Thomas Grass and Bagus Hanindhito and Andreas Hansson and Swapnil Haria and Austin Harris and Timothy Hayes and Adrian Herrera and Matthew Horsnell and Syed Ali Raza Jafri and Radhika Jagtap and Hanhwi Jang and Reiley Jeyapaul and Timothy M. Jones and Matthias Jung and Subash Kannoth and Hamidreza Khaleghzadeh and Yuetsu Kodama and Tushar Krishna and Tommaso Marinelli and Christian Menard and Andrea Mondelli and Tiago Mück and Omar Naji and Krishnendra Nathella and Hoa Nguyen and Nikos Nikoleris and Lena E. Olson and Marc Orr and Binh Pham and Pablo Prieto and Trivikram Reddy and Alec Roelke and Mahyar Samani and Andreas Sandberg and Javier Setoain and Boris Shingarov and Matthew D. Sinclair and Tuan Ta and Rahul Thakur and Giacomo Travaglini and Michael Upton and Nilay Vaish and Ilias Vougioukas and Zhengrong Wang and Norbert Wehn and Christian Weis and David A. Wood and Hongil Yoon and Éder F. Zulian},
+  Year                     = {2020},
+
+  Archiveprefix            = {arXiv},
+  Eprint                   = {2007.03152},
+  Owner                    = {MJ},
+  Primaryclass             = {cs.AR},
+  Timestamp                = {2020-07-08}
+}
+
+@Misc{ltecole,
+  Title                    = {{École Polytechnique Fédérale de Lausanne (EPFL)}},
+
+  Author                   = {{LTHC}},
+  HowPublished             = {{{http://lthcwww.epfl.ch/research/ldpcopt/}}},
+
+  Key                      = {ldpcopt},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{LTHC,
+  Title                    = {{École Polytechnique Fédérale de Lausanne (EPFL)}},
+
+  Author                   = {{LTHC}},
+  HowPublished             = {{{http://lthcwww.epfl.ch/research/ldpcopt/}}},
+
+  Key                      = {ldpcopt},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{lu_82,
+  Title                    = {{W}atchdog {P}rocessors and {S}tructural {I}ntegrity {C}hecking.},
+  Author                   = {Lu, David J.},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {1982},
+  Number                   = {7},
+  Pages                    = {681-685},
+  Volume                   = {31},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de}
+}
+
+@Conference{lu_16,
+  Title                    = {{T}utorial: {DRAM} - {C}ircuits, {O}rganization, {I}nterfaces},
+  Author                   = {Shih-Lien Lu},
+  Booktitle                = {IEEE Microarchitecture Conference (MICRO)},
+  Year                     = {2016},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-05-02},
+  Url                      = {http://people.oregonstate.edu/~sllu/Micro_MT/presentations/Micro2016_Memory_Tutorial_DRAM_Lu.pdf}
+}
+
+@Article{luwal_04,
+  Title                    = {{4G Mobile Communications: Toward Open Wireless Architecture}},
+  Author                   = {Lu, W.W. and Walke, B.H. and X. Shen},
+  Journal                  = {IEEE Wireless Communications},
+  Year                     = {2004},
+
+  Month                    = apr,
+  Number                   = {2},
+  Pages                    = {4--6},
+  Volume                   = {11},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{luqiu_12,
+  Title                    = {{A}n efficient majority-logic based message-passing algorithm for non-binary {LDPC} decoding},
+  Author                   = {Yichao Lu and Nanfan Qiu and Zhixiang Chen and Goto, S.},
+  Booktitle                = {Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on},
+  Year                     = {2012},
+  Pages                    = {479--482},
+
+  Doi                      = {10.1109/APCCAS.2012.6419076},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6419076}
+}
+
+@InProceedings{luyu_10,
+  Title                    = {{D}esign of probabilistic-based {M}arkov {R}andom {F}ield logic gates in 65nm {CMOS} technology},
+  Author                   = {Zhenghao Lu and Xiao Peng Yu and Kiat Seng Yeo},
+  Booktitle                = {SoC Design Conference (ISOCC), 2010 International},
+  Year                     = {2010},
+  Month                    = {nov.},
+  Pages                    = {311 -314},
+
+  Doi                      = {10.1109/SOCDC.2010.5682910},
+  File                     = {luyu_10.pdf:luyu_10.pdf:PDF},
+  Keywords                 = {Reliability}
+}
+
+@InProceedings{lubmit_98,
+  Title                    = {{Analysis of low-density codes and improved designs using irregular graphs}},
+  Author                   = {M. Lubi and M. Mitzenmacher and A. Shokrollahi and D. Spielmann},
+  Booktitle                = {{Proc. 30th ACM Symp. on the Theory of Computing}},
+  Year                     = {1998},
+  Pages                    = {249--258},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{lubmit_01,
+  Title                    = {{Improved low-density parity-check codes using irregular graphs}},
+  Author                   = {Luby, M.G. and M. Mitzenmacher and Shokrollahi, M. A. and Spielman, D. A.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {585--598},
+  Volume                   = {42},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lucalv_14,
+  Title                    = {{S}parkk: {Q}uality-{S}calable {A}pproximate {S}torage in {DRAM}},
+  Author                   = {Jan Lucas and Mauricio Alvarez-Mesa and Michael Andersch and Ben Juurlink},
+  Booktitle                = {The Memory Forum},
+  Year                     = {2014},
+  Month                    = {June},
+
+  Owner                    = {MJ},
+  Projectname              = {LPGPU},
+  Timestamp                = {2015.10.26},
+  Url                      = {http://www.redaktion.tu-berlin.de/fileadmin/fg196/publication/sparkk2014.pdf}
+}
+
+@Article{lucran_15,
+  Title                    = {{A} {S}impler, {S}afer {P}rogramming and {E}xecution {M}odel for {I}ntermittent {S}ystems},
+  Author                   = {Lucia, Brandon and Ransford, Benjamin},
+  Journal                  = {SIGPLAN Not.},
+  Year                     = {2015},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {575--585},
+  Volume                   = {50},
+
+  Acmid                    = {2737978},
+  Address                  = {New York, NY, USA},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Lucia:2015:SSP:2813885.2737978},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/2813885.2737978},
+  ISSN                     = {0362-1340},
+  Issue_date               = {June 2015},
+  Keywords                 = {TCS},
+  Keywords_original        = {Intermittent Computing},
+  Numpages                 = {11},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/2813885.2737978}
+}
+
+@Article{lucnav_18,
+  Title                    = {{O}ptimized {FPGA} {I}mplementation of {M}odel {P}redictive {C}ontrol for {E}mbedded {S}ystems {U}sing {H}igh-{L}evel {S}ynthesis {T}ool},
+  Author                   = {S. Lucia and D. Navarro and {\'{O}}. Luc{\'{i}}a and P. Zometa and R. Findeisen},
+  Journal                  = {IEEE Transactions on Industrial Informatics},
+  Year                     = {2018},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {137-145},
+  Volume                   = {14},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [31]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/TII.2017.2719940},
+  ISSN                     = {1551-3203},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {control system synthesis;embedded systems;field programmable gate arrays;microcontrollers;optimisation;power control;predictive control;microcontroller implementation;optimized {FPGA} implementation;model predictive control;embedded systems;{MPC};high-performance control;increasing interest;optimization problem;multivariable systems;powerful control strategy;field programmable gate arrays;{FPGA}s;automatic tools;resource-constrained systems;optimized implementation;Field programmable gate arrays;Tools;Predictive control;Algorithm design and analysis;Gradient methods;Informatics;Field programmable gate array ({FPGA});high-level synthesis (HLS);model predictive control ({MPC})},
+  Owner                    = {CCR}
+}
+
+@Article{luireg_95,
+  Title                    = {{C}arrier frequency recovery in all-digital modems for burst-mode transmissions},
+  Author                   = {Luise, M. and Reggiannini, R.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1995},
+  Number                   = {234},
+  Pages                    = {1169--1178},
+  Volume                   = {43},
+
+  Booktitle                = {IEEE Transactions on Communications}
+}
+
+@InProceedings{lukcou_09,
+  Title                    = {{A} high-level compilation toolchain for heterogeneous systems},
+  Author                   = {Luk, W. and Coutinho, J. and Todman, T. and Lam, Y.M. and Osborne, W. and Susanto, K.W. and Liu, Q. and Wong, W.S.},
+  Booktitle                = {SOC Conference, 2009. SOCC 2009. IEEE International},
+  Year                     = {2009},
+  Month                    = {Sept},
+  Pages                    = {9-18},
+
+  Doi                      = {10.1109/SOCCON.2009.5398108},
+  Keywords                 = {C language;multiprocessing systems;optimising compilers;Harmonic;data representation optimiser;digital signal processors;field-programmable gate arrays;general-purposed processors;hardware synthesiser;high-level C program;high-level compilation toolchain;mapping selector;multiprocessor heterogeneous systems;program optimisation;task transformation engine;Application software;Control system synthesis;Digital signal processing;Digital signal processors;Educational institutions;Engines;Field programmable gate arrays;Graphical user interfaces;Hardware;Resource management},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@Article{lussan_00,
+  Title                    = {{Advanced Signal-Processing Algorithms for Energy-Efficient Wireless Communications}},
+  Author                   = {C. Luschi and M. Sandell and P. Strauch and J.-J. Wu and C. Ilas and P.-W. Ong and R. Baeriswyl and F. Battaglia and S. Karageorgis and R.-H. Yan},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2000},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {1633--1650},
+  Volume                   = {88},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lushel_99,
+  Title                    = {{An Analog VLSI Decoding Technique for Digital Codes}},
+  Author                   = {F. Lustenberger and M. Helfenstein and H.-A. Loeliger and F. Tarköy and G. S. Moschytz},
+  Booktitle                = {Proc. 1999 IEEE International Symposium on Circuits and Systems (ISCAS '99)},
+  Year                     = {1999},
+  Pages                    = {424--427},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{lusbai_06,
+  Title                    = {{T}he {HPC} {C}hallenge ({HPCC}) {B}enchmark {S}uite},
+  Author                   = {Luszczek, Piotr R and Bailey, David H and Dongarra, Jack J and Kepner, Jeremy and Lucas, Robert F and Rabenseifner, Rolf and Takahashi, Daisuke},
+  Booktitle                = {Proceedings of the 2006 ACM/IEEE Conference on Supercomputing},
+  Year                     = {2006},
+
+  Address                  = {New York, NY, USA},
+  Publisher                = {ACM},
+  Series                   = {SC '06},
+
+  Acmid                    = {1188677},
+  Articleno                = {213},
+  Doi                      = {10.1145/1188455.1188677},
+  ISBN                     = {0-7695-2700-0},
+  Location                 = {Tampa, Florida},
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17},
+  Url                      = {http://doi.acm.org/10.1145/1188455.1188677}
+}
+
+@InProceedings{lyo_93,
+  Title                    = {{Cost, Power and Parallelism in Speech Signal Processing}},
+  Author                   = {R. F. Lyon},
+  Booktitle                = {{Proc. 1993 Custom Integrated Circuits Conference (CICC '93)}},
+  Year                     = {1993},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = may,
+  Pages                    = {15.1.1--15.1.9},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{Monetary2014,
+  Title                    = {{S}tatistical release: {OTC} derivatives statistics at end-{D}ecember 2013},
+  Author                   = {{M}onetary and {E}conomic {D}epartment},
+  Institution              = {{B}ank for {I}nternational {S}ettlements},
+  Year                     = {2014},
+  Month                    = {may},
+
+  Owner                    = {varela},
+  Timestamp                = {2014.12.20},
+  Url                      = {http://www.bis.org/publ/otc_hy1405.pdf}
+}
+
+@Article{mali_18,
+  Title                    = {{NEOF}og: {N}onvolatility-{E}xploiting {O}ptimizations for {F}og {C}omputing},
+  Author                   = {Ma, Kaisheng and Li, Xueqing and Kandemir, Mahmut Taylan and Sampson, Jack and Narayanan, Vijaykrishnan and Li, Jinyang and Wu, Tongda and Wang, Zhibo and Liu, Yongpan and Xie, Yuan},
+  Journal                  = {SIGPLAN Not.},
+  Year                     = {2018},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {782--796},
+  Volume                   = {53},
+
+  Acmid                    = {3177154},
+  Address                  = {New York, NY, USA},
+  Ccr_flags                = {read},
+  Ccr_grade                = {Looks like another foggy work on NVP},
+  Ccr_key_original         = {Ma:2018:NNO:3296957.3177154},
+  Ccr_keywords             = {NVP, NV-RF},
+  Ccr_relevance            = {low},
+  Ccr_topic                = {n.a.},
+  Doi                      = {10.1145/3296957.3177154},
+  ISSN                     = {0362-1340},
+  Issue_date               = {February 2018},
+  Keywords                 = {TCS},
+  Keywords_original        = {distributed fog computing, distributed load balancing, energy harvesting, node virtualization, nonvolatile processor, wireless sensor network},
+  Numpages                 = {15},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/3296957.3177154}
+}
+
+@Article{mali_17a,
+  Title                    = {{D}ynamic {P}ower and {E}nergy {M}anagement for {E}nergy {H}arvesting {N}onvolatile {P}rocessor {S}ystems},
+  Author                   = {Ma, Kaisheng and Li, Xueqing and Liu, Huichu and Sheng, Xiao and Wang, Yiqun and Swaminathan, Karthik and Liu, Yongpan and Xie, Yuan and Sampson, John and Narayanan, Vijaykrishnan},
+  Journal                  = {ACM Trans. Embed. Comput. Syst.},
+  Year                     = {2017},
+
+  Month                    = may,
+  Number                   = {4},
+  Pages                    = {107:1--107:23},
+  Volume                   = {16},
+
+  Acmid                    = {3077575},
+  Address                  = {New York, NY, USA},
+  Articleno                = {107},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Ma:2017:DPE:3092956.3077575},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, NVP},
+  Doi                      = {10.1145/3077575},
+  ISSN                     = {1539-9087},
+  Issue_date               = {September 2017},
+  Keywords                 = {TCS},
+  Keywords_original        = {Nonvolatile processor, dynamic power and energy management, energy harvesting, intermittent power supply},
+  Numpages                 = {23},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/3077575}
+}
+
+@InProceedings{mali_15,
+  Title                    = {{D}ynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile},
+  Author                   = {K. Ma and X. Li and Y. Liu and J. Sampson and Y. Xie and V. Narayanan},
+  Booktitle                = {2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
+  Year                     = {2015},
+  Month                    = {Nov},
+  Pages                    = {670-675},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7372634},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/ICCAD.2015.7372634},
+  Keywords                 = {TCS},
+  Keywords_original        = {learning (artificial intelligence);neural nets;random-access storage;N-stage-pipeline;NSP;OoO cores;baseline NP architecture;dynamic machine learning based matching;dynamic nonvolatile microarchitecture;energy harvesting systems;energy storage device;harvested energy profile;neural network machine learning algorithms;nonvolatile microarchitectures;nonvolatile processor microarchitecture;simpler processor;weak power sources;Computer architecture;Energy storage;Microarchitecture;Nonvolatile memory;Registers;Switches;Dynamic Matching;Energy Harvesting;Machine Learning;Neural Networks;Nonvolatile Processor},
+  Owner                    = {CCR}
+}
+
+@InProceedings{mali_17,
+  Title                    = {{S}pendthrift: {M}achine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors},
+  Author                   = {K. Ma and X. Li and S. R. Srinivasa and Y. Liu and J. Sampson and Y. Xie and V. Narayanan},
+  Booktitle                = {2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)},
+  Year                     = {2017},
+  Month                    = {Jan},
+  Pages                    = {678-683},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7858402},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, NVP},
+  Doi                      = {10.1109/ASPDAC.2017.7858402},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;power aware computing;storage management chips;Spendthrift;ambient energy harvesting nonvolatile processors;batteryless energy harvesting system;frequency scaling;machine learning based resource;out-of-order processor;predictor-driven scheme;resource scaling;static configuration;Biological neural networks;Computer architecture;Energy harvesting;Energy storage;Microarchitecture;Power demand;Program processors;Internet of Things;Nonvolatile processor;energy harvesting;machine learning;power-adaptive microarchitecture},
+  Owner                    = {CCR}
+}
+
+@InProceedings{mazhe_15,
+  Title                    = {{A}rchitecture exploration for ambient energy harvesting nonvolatile processors},
+  Author                   = {K. Ma and Y. Zheng and S. Li and K. Swaminathan and X. Li and Y. Liu and J. Sampson and Y. Xie and V. Narayanan},
+  Booktitle                = {2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)},
+  Year                     = {2015},
+  Month                    = {Feb},
+  Pages                    = {526-537},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7056060},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, NVP},
+  Doi                      = {10.1109/HPCA.2015.7056060},
+  ISSN                     = {1530-0897},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;memory architecture;random-access storage;ambient energy harvesting;battery-less system;nonvolatile processor architecture;power variation tolerance;Clocks;Nonvolatile memory;Pipelines;Program processors;Radio frequency;Registers;Sensors},
+  Owner                    = {CCR}
+}
+
+@Book{mac_03,
+  Title                    = {{Information Theory, Inference, and Learning Algorithms}},
+  Author                   = {D.J.C. MacKay},
+  Publisher                = {Cambridge University Press},
+  Year                     = {2003},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mac_99,
+  Title                    = {{Good error-correcting codes based on very sparse matrices}},
+  Author                   = {MacKay, D.J.C.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1999},
+  Pages                    = {399--431},
+  Volume                   = {45},
+
+  File                     = {mac_99.pdf:mac_99.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{maches_03,
+  Title                    = {{Performance of Low Density Parity Check Codes as a Function of Actual and Assumed Noise Levels}},
+  Author                   = {D. MacKay and C. Hesketh},
+  Journal                  = {Electronic Notes in Theoretical Computer Science},
+  Year                     = {2003},
+  Pages                    = {89--96},
+  Volume                   = {74},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{macnea_96,
+  Title                    = {{Near Shannon limit performance of Low-Density Parity-Check Codes}},
+  Author                   = {MacKay, D.J.C. and R. Neal},
+  Journal                  = {Electronic Letters},
+  Year                     = {1996},
+  Pages                    = {1645--1646},
+  Volume                   = {32},
+
+  File                     = {macnea_96.pdf:macnea_96.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{macwil_99,
+  Title                    = {{Comparison of Construction of Irregular Gallager Codes}},
+  Author                   = {MacKay, D.J.C. and Wilson, S. T. and Davey, M.C.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1999},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {1449--1454},
+  Volume                   = {47},
+
+  File                     = {macwil_99.pdf:macwil_99.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mac_03a,
+  Title                    = {{C}omments on the {M}odied {L}ow-{D}ensity {P}arity-{C}heck {C}odes for the {DVB} {S}tandard},
+  Author                   = {David J.C. MacKay},
+  Year                     = {2003},
+
+  Month                    = {June},
+  Note                     = {Dies ist die Studie von MacKay zu den im DVB-S2 Standard gelandeten LDPC-Codes und deren Mindestdistanzen.},
+
+  Abstract                 = {The original four low-density parity-check codes proposed for DVBS2 have been replaced
+by seven similar codes. In this report I describe some low-weight codewords found in some of
+these codes.},
+  File                     = {mac_03a.pdf:mac_03a.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2010.02.19}
+}
+
+@InProceedings{MacKay03weaknessesof,
+  Title                    = {{W}eaknesses of {M}argulis and {R}amanujan-{M}argulis {L}ow-{D}ensity {P}arity-{C}heck {C}odes},
+  Author                   = {David J.C. MacKay and Michael S. Postol},
+  Booktitle                = {Electronic Notes in Theoretical Computer Science},
+  Year                     = {2003},
+  Pages                    = {2003},
+  Publisher                = {Elsevier},
+
+  Owner                    = {punekar}
+}
+
+@Article{mace.a_03,
+  Title                    = {{Gallager Codes for High Rate Applications}},
+  Author                   = {MacKay, D. J. C. and Ratzer, E. A.},
+  Year                     = {2003},
+
+  Month                    = jan,
+  Note                     = {Auf seiner Webseite, kein Journal gefunden},
+  Pages                    = {1--8},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Url                      = {http://www.inference.phy.cam.ac.uk/mackay/highrate.pdf}
+}
+
+@Article{Macleod1998,
+  Title                    = {{F}ast nearly {ML} estimation of the parameters of real or complex single tones or resolved multiple tones},
+  Author                   = {Macleod, M.D.},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {1998},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {141-148},
+  Volume                   = {46},
+
+  Doi                      = {10.1109/78.651200},
+  ISSN                     = {1053-587X},
+  Keywords                 = {Fourier analysis;Gaussian noise;amplitude estimation;frequency estimation;harmonic analysis;interpolation;iterative methods;maximum likelihood estimation;optimisation;phase estimation;signal sampling;spectral analysis;white noise;AWGN;Cramer-Rao bounds;FFT;amplitude;cisoids;colored noise;complex single tones;discrete Fourier spectrum;fast nearly ML estimation;frequency;frequency separations;interpolator;iterative cyclic descent algorithm;noise;nonGaussian noise;nonlinear optimization;nonzero mean signals;parameter estimation;peak sample;phase;real single tones;resolved multiple tones;sinusoids;unbiased estimates;uniformly spaced samples;Amplitude estimation;Computational efficiency;Frequency estimation;Iterative algorithms;Maximum likelihood estimation;Noise level;Parameter estimation;Phase estimation;Phase noise;Signal processing algorithms},
+  Owner                    = {ali},
+  Timestamp                = {2015.03.03}
+}
+
+@Book{macslo_78,
+  Title                    = {{T}he {T}heory of {E}rror-{C}orrecting {C}odes},
+  Author                   = {MacWilliams, F.J. and Sloane, N.J.A.},
+  Publisher                = {North-holland Publishing Company},
+  Year                     = {1978},
+  Edition                  = {2nd},
+
+  Owner                    = {scholl},
+  Timestamp                = {2015.09.15}
+}
+
+@Article{madban_06,
+  Title                    = {{R}eliability-based coded modulation with low-density parity-check codes},
+  Author                   = {Maddock, R.D. and Banihashemi, A.H.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2006},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {403--406},
+  Volume                   = {54},
+
+  Doi                      = {10.1109/TCOMM.2006.869865},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.02}
+}
+
+@Article{maecol_17,
+  Title                    = {{A}lpaca: {I}ntermittent {E}xecution {W}ithout {C}heckpoints},
+  Author                   = {Maeng, Kiwan and Colin, Alexei and Lucia, Brandon},
+  Journal                  = {Proc. ACM Program. Lang.},
+  Year                     = {2017},
+
+  Month                    = oct,
+  Number                   = {OOPSLA},
+  Pages                    = {96:1--96:30},
+  Volume                   = {1},
+
+  Acmid                    = {3133920},
+  Address                  = {New York, NY, USA},
+  Articleno                = {96},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Maeng:2017:AIE:3152284.3133920},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3133920},
+  ISSN                     = {2475-1421},
+  Issue_date               = {October 2017},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy-harvesting, intermittent computing},
+  Numpages                 = {30},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/3133920}
+}
+
+@InProceedings{maeluc_19,
+  Title                    = {{S}upporting {P}eripherals in {I}ntermittent {S}ystems with {J}ust-in-time {C}heckpoints},
+  Author                   = {Maeng, Kiwan and Lucia, Brandon},
+  Booktitle                = {Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation},
+  Year                     = {2019},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {1101--1116},
+  Publisher                = {ACM},
+  Series                   = {PLDI 2019},
+
+  Acmid                    = {3314613},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Maeng:2019:SPI:3314221.3314613},
+  Ccr_keywords             = {atomic operations},
+  Ccr_relevance            = {in general},
+  Ccr_topic                = {ATC, CP},
+  Doi                      = {10.1145/3314221.3314613},
+  ISBN                     = {978-1-4503-6712-7},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy-harvesting, intermittent computing},
+  Location                 = {Phoenix, AZ, USA},
+  Numpages                 = {16},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27},
+  Url                      = {http://doi.acm.org/10.1145/3314221.3314613}
+}
+
+@InProceedings{maeluc_18,
+  Title                    = {{A}daptive {D}ynamic {C}heckpointing for {S}afe {E}fficient {I}ntermittent {C}omputing},
+  Author                   = {Maeng, Kiwan and Lucia, Brandon},
+  Booktitle                = {Proceedings of the 12th USENIX Conference on Operating Systems Design and Implementation},
+  Year                     = {2018},
+
+  Address                  = {Berkeley, CA, USA},
+  Pages                    = {129--144},
+  Publisher                = {USENIX Association},
+  Series                   = {OSDI'18},
+
+  Acmid                    = {3291178},
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Maeng:2018:ADC:3291168.3291178},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  ISBN                     = {978-1-931971-47-8},
+  Keywords                 = {TCS},
+  Location                 = {Carlsbad, CA, USA},
+  Numpages                 = {16},
+  Owner                    = {CCR},
+  Url                      = {http://dl.acm.org/citation.cfm?id=3291168.3291178}
+}
+
+@InProceedings{magkha_16,
+  Title                    = {{ASIC} {C}louds: {S}pecializing the {D}atacenter},
+  Author                   = {Ikuo Magaki and Moein Khazraee and Luis Vega Gutierrez and Michael Bedford Taylor},
+  Booktitle                = {2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)},
+  Year                     = {2016},
+  Month                    = {June},
+  Pages                    = {178-190},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.22}
+}
+
+@InProceedings{magboy_17,
+  Title                    = {{W}earable {E}nergy {H}arvesting: {F}rom body to battery},
+  Author                   = {M. Magno and D. Boyle},
+  Booktitle                = {2017 12th International Conference on Design Technology of Integrated Systems In Nanoscale Era (DTIS)},
+  Year                     = {2017},
+  Month                    = {April},
+  Pages                    = {1-6},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7930169},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/DTIS.2017.7930169},
+  Keywords                 = {TCS},
+  Keywords_original        = {body sensor networks;energy harvesting;EH wearable systems;in-field measurement;wearable devices;wearable energy harvesting;Industries;Kinetic theory;Microcontrollers;Radio frequency;Sensor phenomena and characterization;Switches;Vibrations;Energy Harvesting;Low Energy Design;Power Management;Wearble Devices;Wireless Sensors Systems},
+  Owner                    = {CCR}
+}
+
+@Article{magbru_16,
+  Title                    = {{I}nfini{T}ime: {M}ulti-sensor wearable bracelet with human body harvesting },
+  Author                   = {Michele Magno and Davide Brunelli and Lukas Sigrist and Renzo Andri and Lukas Cavigelli and Andres Gomez and Luca Benini},
+  Journal                  = {Sustainable Computing: Informatics and Systems },
+  Year                     = {2016},
+  Note                     = {SI: \{IGCC\} 2014 },
+  Pages                    = {38 - 49},
+  Volume                   = {11},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Magno201638},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {http://doi.org/10.1016/j.suscom.2016.05.003},
+  ISSN                     = {2210-5379},
+  Keywords                 = {TCS},
+  Keywords_original        = {Wearable devices},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S2210537916300816}
+}
+
+@InProceedings{magkne_18,
+  Title                    = {{M}icro {K}inetic {E}nergy {H}arvesting for {A}utonomous {W}earable {D}evices},
+  Author                   = {M. {Magno} and D. {Kneub\"{u}hler} and P. {Mayer} and L. {Benini}},
+  Booktitle                = {2018 International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM)},
+  Year                     = {2018},
+  Month                    = {June},
+  Pages                    = {105-110},
+
+  Ccr_flags                = {unread, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8445342},
+  Ccr_keywords             = {MGS26.4},
+  Ccr_relevance            = {high},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/SPEEDAM.2018.8445342},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;piezoelectric transducers;electrical energy;Microkinetic energy harvesting;autonomous wearable devices;microenergy harvesting circuits;wearable applications;kinetic energy harvesting circuits;human motion;high-efficiency energy harvesting system;MicroGenerator System 26.4;kinetic harvesting system;energy conversion efficiency;human body;wearable devices;power 624.0 muW;Kinetic energy;Generators;Energy harvesting;Springs;Performance evaluation;Transducers;Magnetic flux;Energy Harvesting;Kinetic;Wearable devices;Low Power Design;Energy efficiency;Energy Conversion},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27}
+}
+
+@InProceedings{magpor_14,
+  Title                    = {{I}nfini{T}ime: {A} multi-sensor energy neutral wearable bracelet},
+  Author                   = {M. Magno and D. Porcarelli and D. Brunelli and L. Benini},
+  Booktitle                = {International Green Computing Conference},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {1-8},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7039180},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/IGCC.2014.7039180},
+  Keywords                 = {TCS},
+  Keywords_original        = {cameras;data acquisition;energy harvesting;optimisation;power engineering computing;sensors;solar cells;battery powered wearable;data acquisition;energy harvester;energy intake measurements;energy optimization techniques;indoor light levels;infinitime;limited lifetime;multisensor energy neutral wearable bracelet;on-board camera;photovoltaic cells;radio connectivity;sensor-rich smart bracelet;visualization;Abstracts;Decision support systems;Hardware;Microcontrollers;Microelectronics;Sensor phenomena and characterization;Energy Neutral;Indoor energy harvesters;Power Management;Ultra low power;Wearable devices},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-26}
+}
+
+@InProceedings{magsal_16,
+  Title                    = {{A}utonomous smartwatch with flexible sensors for accurate and continuous mapping of skin temperature},
+  Author                   = {M. Magno and G. A. Salvatore and S. Mutter and W. Farrukh and G. Troester and L. Benini},
+  Booktitle                = {2016 IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2016},
+  Month                    = {May},
+  Pages                    = {337-340},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7527239},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/ISCAS.2016.7527239},
+  Keywords                 = {TCS},
+  Keywords_original        = {biomedical measurement;biothermics;patient monitoring;sensor arrays;skin;temperature sensors;wireless sensor networks;autonomous smartwatch;cardiovascular health;communication;data transmission;dermatology;electrophysiology;epidermal temperature sensor array;flexible sensor;flexible solar module;long-term monitoring;low-power wearable device;power management;signal treatment;skin temperature mapping;ultralow-power smartwatch;wireless autonomous system;Epidermis;Microcontrollers;Temperature measurement;Temperature sensors;Wrist;Ultra-low power device;e-health;energy harvesting;epidermal sensors;long term monitoring;wearable devices},
+  Owner                    = {CCR}
+}
+
+@InProceedings{magspa_16,
+  Title                    = {{K}inetic energy harvesting: {T}oward autonomous wearable sensing for {I}nternet of {T}hings},
+  Author                   = {M. Magno and L. Spadaro and J. Singh and L. Benini},
+  Booktitle                = {2016 International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM)},
+  Year                     = {2016},
+  Month                    = {June},
+  Pages                    = {248-254},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7525995},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/SPEEDAM.2016.7525995},
+  Keywords                 = {TCS},
+  Keywords_original        = {Internet of Things;energy harvesting;rectifiers;supercapacitors;wind turbines;Internet of Things;Kinetron microgenerator system;autonomous wearable sensing;direct current conversion;energy sources;high-frequency vibration;human movements;kinetic energy harvesting;off-the-shelf components;outdoor setting;passive rectifier;power autonomous wearable devices;power supply availability;single small human movement;solar panels;supercapacitors;wind turbines;Batteries;Energy harvesting;Generators;Internet of things;Kinetic energy;Magnetic flux;Energy Harvesting;Kinetic energy harvseting;Wearable devices;energy efficiency;low power circuits},
+  Owner                    = {CCR}
+}
+
+@InProceedings{mahbri_04,
+  Title                    = {{Rate-feedback schemes for MIMO-OFDM wireless LANs}},
+  Author                   = {Mahadevappa, R. and ten Brink, S.},
+  Booktitle                = {Vehicular Technology Conference, 2004. VTC2004-Fall. 2004 IEEE 60th},
+  Year                     = {2004},
+  Month                    = sep,
+  Pages                    = {563--567Vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/VETECF.2004.1400070},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Unpublished{mai_10,
+  Title                    = {{T}ime {S}cheduling {S}chemes for {O}nline {L}aboratory {M}anagement {S}ystems},
+  Author                   = {Ananda Maiti},
+
+  Month                    = feb,
+  Year                     = {2010},
+
+  Abstract                 = {Online remotely-controlled educational laboratories are increasingly being deployed in many universities around the world. Such laboratories could help a lot in distance education. As hardware-based remote experiment can only be used by one person or a group of persons at a time, for proper utilization of the resources, an efficient time scheduling scheme is essential. In this work, we discuss some of the possible methods for scheduling of online experiments which may be integrated in online laboratory management systems for optimum resource utilization.},
+  Cds_grade                = {1},
+  Cds_keywords             = {education, scheduling, internet},
+  Cds_read                 = {2010-02-09},
+  Cds_review               = {You introduce the reader into the problems connected with student labs and how to maximize resource utilization in a remote lab. Unfortunately, the schemes mentioned in the paper are not very sophisticated, they are quite primitive approaches to lab scheduling as you would do offline. As you are missing any implementation details or acceptance studies from attending students, I would state that your paper shows a case-study of online lab scheduling at your university, but does not provide any new concept to the reader. I therefore suggest that you include much more information on where the pitfalls in implementation and usage are and how you have managed to solve them, this would in my opinion really be interesting for the reader.},
+  File                     = {mai_10.pdf:mai_10.pdf:PDF},
+  Keywords                 = {Review},
+  Owner                    = {CdS},
+  Timestamp                = {2010.02.09}
+}
+
+@InProceedings{majpat_94,
+  Title                    = {{H}ierarchical {C}hecking of {M}ultiprocessors {U}sing {W}atchdog {P}rocessors},
+  Author                   = {Majzik, I. and Pataricza, A. and Dal Cin, M. and Hohl, W. and Hönig, J. and Sieh, V.},
+  Booktitle                = {Proc. European Dependable Computing Conference},
+  Year                     = {1994},
+  Pages                    = {386-403},
+
+  Url                      = {citeseer.ist.psu.edu/majzik94hierarchical.html}
+}
+
+@InProceedings{malsha_12,
+  Title                    = {{R}ethinking {DRAM} {P}ower {M}odes for {E}nergy {P}roportionality},
+  Author                   = {Krishna T. Malladi and Ian Shaeffer and Liji Gopalakrishnan and David Lo and Benjamin C. Lee and Mark Horowitz},
+  Booktitle                = {MICRO},
+  Year                     = {2012},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-22}
+}
+
+@InProceedings{malsch_18,
+  Title                    = {{T}he transprecision computing paradigm: {C}oncept, design, and applications},
+  Author                   = {A. C. I. {Malossi} and M. {Schaffner} and A. {Molnos} and L. {Gammaitoni} and G. {Tagliavini} and A. {Emerson} and A. {Tomás} and D. S. {Nikolopoulos} and E. {Flamand} and N. {Wehn}},
+  Booktitle                = {2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2018},
+  Month                    = {March},
+  Pages                    = {1105-1110},
+
+  Doi                      = {10.23919/DATE.2018.8342176},
+  ISSN                     = {1558-1101},
+  Keywords                 = {Big Data;Internet of Things;parallel processing;power aware computing;HPC simulations;energy efficiency improvements;transprecision computing paradigm;constant exponential improvement;Internet-of-Things;HPC computing centers;power wall;computational domains;Big Data analytics;European OPRECOMP project;ultraconservative precise computing abstraction;Hardware;Computer architecture;Measurement;Random access memory;Europe;Computational modeling;Software;Approximate Computing;Inexact Computing;Energy-Efficiency;Low Power Computing;Architecture Design}
+}
+
+@InProceedings{man_02,
+  Title                    = {{On Nanoscale Integration and Gigascale Complexity in the Post .com World (Keynote Speach)}},
+  Author                   = {H. De Man},
+  Booktitle                = {{Proc. 2002 Design, Automation and Test in Europe (DATE '02)}},
+  Year                     = {2002},
+
+  Address                  = {Paris, France},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mansha_03,
+  Title                    = {{Architecture-Aware Low-Density Parity-Check Codes}},
+  Author                   = {M. Mansour and N. Shanbhag},
+  Booktitle                = {Proc. 2003 IEEE International Symposium on Circuits and Systems (ISCAS '03)},
+  Year                     = {2003},
+
+  Address                  = {Bangkok, Thailand},
+  Month                    = may,
+
+  File                     = {mansha_03.pdf:mansha_03.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mansha_02,
+  Title                    = {{Low-Power VLSI Decoder Architectures for LDPC Codes}},
+  Author                   = {M. Mansour and N. Shanbhag},
+  Booktitle                = {Proc. 2002 International Symposium on Low Power Electronics and Design (ISLPED '02)},
+  Year                     = {2002},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = aug,
+
+  File                     = {mansha_02.pdf:mansha_02.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mansha_02a,
+  Title                    = {{Memory-Efficient Turbo Decoder Architectures for LDPC Codes}},
+  Author                   = {M. Mansour and N. Shanbhag},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems (SiPS '02)},
+  Year                     = {2002},
+
+  Address                  = {San Diego,USA},
+  Month                    = sep,
+  Pages                    = {159--164},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mansha_02b,
+  Title                    = {{Design Methodology for High-Speed Iterative Decoder Architectures}},
+  Author                   = {M. M. Mansour and N. Shanbhag},
+  Booktitle                = {Proc. 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '02)},
+  Year                     = {2002},
+
+  Address                  = {Orlando, Florida, USA},
+  Month                    = may,
+  Pages                    = {3085--3088},
+
+  File                     = {mansha_02b.pdf:mansha_02b.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mansha_03a,
+  Title                    = {{High-Throughput LDPC Decoders}},
+  Author                   = {Mansour, M. M. and Shanbhag, N. R.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration Systems},
+  Year                     = {2003},
+
+  Month                    = dec,
+  Number                   = {6},
+  Pages                    = {976--996},
+  Volume                   = {11},
+
+  File                     = {mansha_03a.pdf:mansha_03a.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mansha_03b,
+  Title                    = {{VLSI architectures for SISO-APP decoders}},
+  Author                   = {Mansour, M. M. and Shanbhag, N. R.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2003},
+
+  Month                    = aug,
+  Number                   = {4},
+  Pages                    = {627--650},
+  Volume                   = {11},
+
+  File                     = {mansha_03b.pdf:mansha_03b.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mansha_03c,
+  Title                    = {{VLSI} architectures for {SISO}-{APP} decoders},
+  Author                   = {Mansour, M. M. and Shanbhag, N. R. },
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2003},
+  Number                   = {4},
+  Pages                    = {627--650},
+  Volume                   = {11},
+
+  Doi                      = {10.1109/TVLSI.2003.816136},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{maowan_14,
+  Title                    = {{A}n {A}utomatic {N}ews {A}nalysis and {O}pinion {S}haring {S}ystem for {E}xchange {R}ate {A}nalysis},
+  Author                   = {Hongyu Mao and Keqin Wang and Rui Ma and Yifan Gao and Yuanzhi Li and Kun Chen and Dejun Xie and Wei Zhu and Ting Wang and Huaiqing Wang},
+  Booktitle                = {In Proceedings of the 2014 IEEE 11th International Conference on e-Business Engineering (ICEBE)},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {303-307},
+
+  Abstract                 = {In an increasingly competitive global market, exchange rate analysis becomes a key part of financial management for international companies. Although some previous studies have developed various forecasting techniques to predict exchange rate trends based on both numerical data and textual data, a deeper understanding of the underlying economic factors is critical for financial decision making purposes. Driven by the real business requirement, we propose an automatic news analysis and opinion sharing system for exchange rate prediction. The system is comprised of five components, including data collection, event classification, sentiment analysis, prediction, and opinion sharing. Breaking news and other data are gathered from broad Web sources in a real time. These news and data are firstly classified into focal event types, an innovative sentiment analysis method is then used to predict their impacts on exchange rate. A built-in mechanism is provided for users to share their opinions. Finally, feedbacks and human judgment from decisions makers are allowed to improve the accuracy. The proposed system has been used in an international logistic company. A real-world case has been used to test and illustrate the effectiveness of the designed system. The paper concludes with a discussion of potential applications.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ICEBE.2014.59},
+  Keywords                 = {finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-02-05}
+}
+
+@InProceedings{maoban_01,
+  Title                    = {{A Heuristic Search for Good Low-Density Parity-Check Codes at Short Block Lengths}},
+  Author                   = {Y. Mao and A.H. Banihashemi},
+  Booktitle                = {Proc. 2001 International Conference on Communications (ICC '01)},
+  Year                     = {2001},
+  Month                    = jun,
+  Pages                    = {11--14},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{markus_04,
+  Title                    = {{T}he {F}looding {T}ime {S}ynchronization {P}rotocol},
+  Author                   = {Mar\'{o}ti, Mikl\'{o}s and Kusy, Branislav and Simon, Gyula and L{\'e}deczi, \'{A}kos},
+  Booktitle                = {Proceedings of the 2Nd International Conference on Embedded Networked Sensor Systems},
+  Year                     = {2004},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {39--49},
+  Publisher                = {ACM},
+  Series                   = {SenSys '04},
+
+  Acmid                    = {1031501},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Maroti:2004:FTS:1031495.1031501},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1145/1031495.1031501},
+  ISBN                     = {1-58113-879-2},
+  Keywords                 = {BLE},
+  Keywords_original        = {clock drift, clock synchronization, multi-hop, sensor networks, time synchronization},
+  Location                 = {Baltimore, MD, USA},
+  Numpages                 = {11},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30},
+  Url                      = {http://doi.acm.org/10.1145/1031495.1031501}
+}
+
+@InProceedings{marsch_86,
+  Title                    = {{A}pplications of morphological filtering to image analysis and processing},
+  Author                   = {Maragos, P. and Schafer, R.W.},
+  Booktitle                = {Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.},
+  Year                     = {1986},
+  Month                    = {Apr},
+  Pages                    = {2067-2070},
+  Volume                   = {11},
+
+  Abstract                 = {This paper summarizes some applications of morphological erosions, dilations, openings, and closings to image edge-detection, cleaning of impulsive-noise, median-filtering, region-filling, skeletonization, and 2-D shape recognition.},
+  Cds_grade                = {0},
+  Cds_keywords             = {morphological filters, applications},
+  Doi                      = {10.1109/ICASSP.1986.1168861},
+  File                     = {marsch_86.pdf:marsch_86.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.07.15}
+}
+
+@InProceedings{mar_03a,
+  Title                    = {{N}etworks-on-chip: the quest for on-chip fault-tolerant communication},
+  Author                   = {Marculescu, R. },
+  Booktitle                = {Proc. IEEE Computer Society Annual Symposium on VLSI},
+  Year                     = {2003},
+  Month                    = feb,
+  Pages                    = {8--12},
+
+  File                     = {mar_03a.pdf:mar_03a.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{marsha_10,
+  Title                    = {{E}fficient {C}ounting of {N}etwork {M}otifs},
+  Author                   = {Marcus, D. and Shavitt, Y.},
+  Booktitle                = {Proceedings of the 2010 IEEE 30th International Conference on Distributed Computing Systems Workshops (ICDCSW)},
+  Year                     = {2010},
+  Month                    = jun,
+  Pages                    = {92--98},
+
+  Abstract                 = {Counting network motifs has an important role in studying a wide range of complex networks. However, when the network size is large, as in the case of Internet Topology and WWW graphs counting the number of motifs becomes prohibitive. Devising efficient motif counting algorithms thus becomes an important goal. In this paper, we present efficient counting algorithms for 4-nodemotifs. We show how to efficiently count the total number of each type of motif, and the number of motifs adjacent to a node. We further present a new algorithm for node position-aware motif counting, namely partitioning the motif count by the node position in the motif. Since our algorithm is based on motifs, which are non-induced we also show how to calculate the count of induced motifs given the non-induced motif count. Finally, we report on initial implementation performance result using evaluation on a large-scale graph.},
+  Cds_grade                = {0},
+  Cds_keywords             = {motif detection},
+  Doi                      = {10.1109/ICDCSW.2010.41},
+  File                     = {marsha_10.pdf:marsha_10.pdf:PDF},
+  ISSN                     = {1545-0678},
+  Keywords                 = {graphs},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.28}
+}
+
+@Article{margie_11,
+  Title                    = {{C}omputer-{A}ided {A}nalog {C}ircuit {D}esign for {R}eliability in {N}anometer {CMOS}},
+  Author                   = {Maricau, E. and Gielen, G. },
+  Journal                  = {Emerging and Selected Topics in Circuits and Systems, IEEE Journal on},
+  Year                     = {2011},
+  Number                   = {1},
+  Pages                    = {50--58},
+  Volume                   = {1},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Analog},
+  Doi                      = {10.1109/JETCAS.2011.2135470},
+  File                     = {margie_11.pdf:margie_11.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Misc{diehard,
+  Title                    = {{D}iehard {B}attery of {T}ests of {R}andomness},
+
+  Author                   = {George Marsaglia},
+  HowPublished             = {\url{http://stat.fsu.edu/pub/diehard}},
+  Note                     = {last access 2014-07-02},
+  Year                     = {1995},
+
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@Misc{Marsagli1995,
+  Title                    = {{D}iehard {B}attery of {T}ests of {R}andomness},
+
+  Author                   = {George Marsaglia},
+  HowPublished             = {\url{http://stat.fsu.edu/pub/diehard/}},
+  Year                     = {1995},
+
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@Article{marbra_64,
+  Title                    = {{A} convenient method for generating normal variables},
+  Author                   = {Marsaglia, G. and Bray, TA},
+  Journal                  = {Siam Review},
+  Year                     = {1964},
+  Number                   = {3},
+  Pages                    = {260--264},
+  Volume                   = {6},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation},
+  File                     = {marbra_64.pdf:marbra_64.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {JSTOR},
+  Timestamp                = {2012.03.22}
+}
+
+@Article{martsa_84,
+  Title                    = {{A} {F}ast, {E}asily {I}mplemented {M}ethod for {S}ampling from {D}ecreasing or {S}ymmetric {U}nimodal {D}ensity {F}unctions},
+  Author                   = {Marsaglia, G. and Tsang, W.W.},
+  Journal                  = {SIAM Journal on Scientific and Statistical Computing},
+  Year                     = {1984},
+  Pages                    = {349},
+  Volume                   = {5},
+
+  Abstract                 = {The fastest computer methods for sampling from a given density are those based on a mixture of a fast and slow part. This paper describes a new method of this type, suitable for any decreasing or symmetric unimodal density. It differs from others in that it is faster and more easily implemented, thereby providing a standard procedure for developing both the fast and the slow part for many given densities. It is called the ziggurat method, after the shape of a single, convenient density that provides for both the fast and the slow parts of the generating process. Examples are given for REXP and RNOR, subroutines that generate exponential and normal variates that, as assembler routines, are nearly twice as fast as the previous best assembler routines, and that, as Fortran subroutines, approach the limiting possible speed: the time for Fortran subroutine linkage conventions plus the time to generate one uniform variate.},
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation, Ziggurat method},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@Article{martsa_00,
+  Title                    = {{T}he {Z}iggurat {M}ethod for {G}enerating {R}andom {V}ariables},
+  Author                   = {George Marsaglia and Wai Wan Tsang},
+  Journal                  = {Journal of Statistical Software},
+  Year                     = {2000},
+  Number                   = {8},
+  Pages                    = {1--7},
+  Volume                   = {5},
+
+  Abstract                 = {We provide a new version of our ziggurat method for generating a random variable from a given
+decreasing density. It is faster and simpler than the original, and will produce, for example, normal
+or exponential variates at the rate of 15 million per second with a C version on a 400MHz PC. It
+uses two tables, integers ki and reals wi. Some 99% of the time, the required x is produced by:
+Generate a random 32-bit integer j and let i be the index formed from the rightmost 8 bits of j. If
+j < ki return x = j  wi.
+We illustrate with C code that provides for inline generation of both normal and exponential
+variables, with a short procedure for setting up the necessary tables.},
+  Cds_grade                = {0},
+  File                     = {martsa_00.pdf:martsa_00.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.23}
+}
+
+@Article{martsa_00a,
+  Title                    = {{A Simple Method for Generating Gamma Variables}},
+  Author                   = {George Marsaglia and Wai Wan Tsang},
+  Journal                  = {ACM Transactions on Mathematical Software},
+  Year                     = {2000},
+
+  Month                    = {sep},
+  Number                   = {3},
+  Pages                    = {363-372},
+  Volume                   = {26},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.26}
+}
+
+@Article{mar_34,
+  Title                    = {{A} problem in arrangements},
+  Author                   = {Martin, Monroe H},
+  Journal                  = {Bulletin of the American Mathematical Society},
+  Year                     = {1934},
+  Number                   = {12},
+  Pages                    = {859--864},
+  Volume                   = {40},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-09-12}
+}
+
+@Article{marmas_11,
+  Title                    = {{S}tate {M}etric {C}ompression {T}echniques for {T}urbo {D}ecoder {A}rchitectures},
+  Author                   = {Martina, M. and Masera, G.},
+  Journal                  = {Circuits and Systems I: Regular Papers, IEEE Transactions on},
+  Year                     = {2011},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {1119-1128},
+  Volume                   = {58},
+
+  Doi                      = {10.1109/TCSI.2010.2090566},
+  ISSN                     = {1549-8328},
+  Keywords                 = {Hadamard codes;Hadamard transforms;decoding;error correction codes;quantisation (signal);turbo codes;Walsh-Hadamard transform;error correcting performance floor;memory complexity reduction;nonuniform quantization;power consumption;state metric compression;state metric memory area;turbo decoder;Decoding;Measurement;Memory management;Program processors;Quantization;Signal to noise ratio;Turbo decoder;VLSI;data compression},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@Article{marnic_08,
+  Title                    = {{A Flexible UMTS-WiMax Turbo Decoder Architecture}},
+  Author                   = {Maurizio Martina and Mario Nicola and Guido Masera},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2008},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {369-373},
+  Volume                   = {55},
+
+  File                     = {marnic_08.pdf:marnic_08.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{marandroid12,
+  Title                    = {{A}ndroid-powered {C}a-{F}i {D}ashlinq infotainment system coming in {J}anuary},
+
+  Author                   = {Andrew Martonik},
+  HowPublished             = {AndroidCentral, \url{http://www.androidcentral.com/android-powered-ca-fi-dashlinq-infotainment-system-coming-january}},
+  Month                    = dec,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2012},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@InProceedings{mar_03,
+  Title                    = {{A} turbo decoder for high speed downlink packet access},
+  Author                   = {Maru, T. },
+  Booktitle                = {Proc. VTC 2003-Fall Vehicular Technology Conference 2003 IEEE 58th},
+  Year                     = {2003},
+  Month                    = oct,
+  Pages                    = {332--336},
+  Volume                   = {1},
+
+  File                     = {mar_03.pdf:mar_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.15}
+}
+
+@PhdThesis{Phdmarxe12,
+  Title                    = {{A}spects of the {A}pplication of {M}ultilevel {M}onte {C}arlo {M}ethods in the {H}eston {M}odel and in a {L}évy {P}rocess {F}ramework},
+  Author                   = {Henning Marxen},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2012},
+
+  Cds_grade                = {0},
+  File                     = {Phdmarxe12.pdf:Phdmarxe12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.04.02}
+}
+
+@InProceedings{markos_11,
+  Title                    = {{A}lgorithmic {C}omplexity in the {H}eston {M}odel: {A}n {I}mplementation {V}iew},
+  Author                   = {Henning Marxen and Anton Kostiuk and Ralf Korn and Christian de Schryver and Stephan Wurm and Ivan Shcherbakov and Norbert Wehn},
+  Booktitle                = {Proceedings of the fourth workshop on High Performance Computational Finance (WHPCF '11)},
+  Year                     = {2011},
+
+  Address                  = {Seattle, USA},
+  Month                    = nov,
+  Note                     = {ISBN 978-1-4503-1108-3},
+  Pages                    = {5--12},
+  Publisher                = {ACM New York, NY, USA},
+
+  Abstract                 = {In this paper, we present an in-depth investigation of the algorithmic parameter influence for barrier option pricing with the Heston model. For that purpose we focus on single- and multi-level Monte Carlo simulation methods. We investigate the impact of algorithmic variations on simulation time and energy consumption, giving detailed measurement results for a state-of-the-art 8-core CPU server and a Nvidia Tesla C2050 GPU. We particularly show that a naive algorithm on a powerful GPU can even increase the energy consumption and computation time, compared to a better algorithm running on a standard CPU. Furthermore we give preliminary results of a dedicated FPGA implementation and comment on the speedup and energy saving potential of this architecture.},
+  Cds_grade                = {5},
+  Cds_keywords             = {Heston, Monte Carlo, GPU, speed comparison, energy comparison, algorithm, multi-level Monte Carlo, option pricing, FPGA},
+  Cds_read                 = {2011-11-13},
+  Doi                      = {10.1145/2088256.2088261},
+  File                     = {markos_11.pdf:markos_11.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-04-22}
+}
+
+@Electronic{masshe_13,
+  Title                    = {{T}he {E}nergy {E}fficiency {P}otential of {C}loud-{B}ased {S}oftware: {A} {U}.{S}. {C}ase {S}tudy},
+  Author                   = {Eric Masanet and Arman Shehabi and Lavanya Ramakrishnan and Jiaqi Liang and XiaoHui Ma and Benjamin Walker and Valerie Hendrix and Pradeep Mantha},
+  HowPublished             = {\url{http://crd.lbl.gov/assets/pubs_presos/ACS/cloud_efficiency_study.pdf}},
+  Language                 = {en},
+  Month                    = jun,
+  Note                     = {last access 2014-07-02},
+  Organization             = {Lawrence Berkeley National Laboratory},
+  Url                      = {http://crd.lbl.gov/assets/pubs_presos/ACS/cloud_efficiency_study.pdf},
+  Year                     = {2013},
+
+  Cds_grade                = {3},
+  Cds_read                 = {2014-03-24},
+  File                     = {masshe_13.pdf:masshe_13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.24}
+}
+
+@Article{masmaz_02,
+  Title                    = {{Architectural strategies for low-power VLSI turbo decoders}},
+  Author                   = {G. Masera and M. Mazza and G. Piccinini and F. Viglione and M. Zamboni},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2002},
+
+  Month                    = jun,
+  Number                   = {3},
+  Pages                    = {279--285},
+  Volume                   = {10},
+
+  File                     = {masmaz_02.pdf:masmaz_02.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{maspic_99,
+  Title                    = {{VLSI Architectures for Turbo Codes}},
+  Author                   = {G. Masera and G. Piccinini and Ruo Roch, M. and M. Zambonini},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {1999},
+
+  Month                    = sep,
+  Number                   = {3},
+  Pages                    = {369--379},
+  Volume                   = {7},
+
+  File                     = {maspic_99.pdf:maspic_99.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{masqua_06,
+  Title                    = {{Interconnection Structure for a Flexible LDPC Decoder}},
+  Author                   = {G. Masera and F. Quaglio and A. Tarable and F. Vacca},
+  Booktitle                = {{Proceedings of WiRTeP - Wireless Reconfigurable Terminals and Platforms}},
+  Year                     = {2006},
+  Month                    = apr,
+  Pages                    = {58--62},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{masqua_07,
+  Title                    = {{Implementation of a Flexible LDPC Decoder}},
+  Author                   = {Guido Masera and Federico Quaglio and Fabrizio Vacca},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2007},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {542-546},
+  Volume                   = {54},
+
+  File                     = {masqua_07.pdf:masqua_07.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mas_69,
+  Title                    = {{S}hift-register synthesis and {BCH} decoding},
+  Author                   = {Massey, J.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1969},
+  Number                   = {1},
+  Pages                    = {122--127},
+  Volume                   = {15},
+
+  Doi                      = {10.1109/TIT.1969.1054260},
+  File                     = {mas_69.pdf:mas_69.pdf:PDF},
+  Keywords                 = {BCH, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {BCH HDD Paper},
+  Timestamp                = {2013.02.12},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1054260}
+}
+
+@Misc{massoft04,
+  Title                    = {{S}oft {E}rrors' {I}mpact on {S}ystem {R}eliability},
+
+  Author                   = {R. Mastipuram and E. C. Wee},
+  HowPublished             = {http://www.edn.com/article/CA454636.html},
+  Month                    = sep,
+  Year                     = {2004},
+
+  File                     = {massoft04.pdf:massoft04.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Misc{Mastipuram2004,
+  Title                    = {{S}oft {E}rrors' {I}mpact on {S}ystem {R}eliability},
+
+  Author                   = {R. Mastipuram and E. C. Wee},
+  HowPublished             = {http://www.edn.com/article/CA454636.html},
+  Month                    = sep,
+  Year                     = {2004},
+
+  File                     = {massoft04.pdf:massoft04.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{matdol_00,
+  Title                    = {{Stopping Rules for Turbo Decoders}},
+  Author                   = {A. Matache and S. Dolinar and F. Pollara},
+  Journal                  = {TMO Progress Report 42--142},
+  Year                     = {2000},
+
+  Month                    = aug,
+  Note                     = {{http://tda.jpl.nasa.gov/progress\_report/}, Jet Propulsion Laboratory, Pasadena, California},
+  Pages                    = {1--22},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{matmey_04,
+  Title                    = {{S}tochastic modeling of the convergence behavior of concatenated codes},
+  Author                   = {Mathar, R. and Meyr, H.},
+  Booktitle                = {Vehicular Technology Conference, 2004. VTC2004-Fall. 2004 IEEE 60th},
+  Year                     = {2004},
+  Month                    = sep,
+  Pages                    = {1263--1265Vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/VETECF.2004.1400225},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Patent{matmat_18,
+  Title                    = {{U}sing {R}untime {R}everse {E}ngineering to {O}ptimize {DRAM} {R}efresh},
+  Nationality              = {United States},
+  Number                   = {US20190074052A1},
+  Year                     = {2018},
+  Author                   = {Mathew M., Deepak and Jung, Matthias and Weis, Christian and Wehn, Norbert},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-04-26}
+}
+
+@Patent{matmat_18a,
+  Title                    = {使用运行时逆向工程优化{DRAM}刷新},
+  Nationality              = {China},
+  Number                   = {CN109461465A},
+  Year                     = {2018},
+  Author                   = {Mathew M., Deepak and Jung, Matthias and Weis, Christian and Wehn, Norbert},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-04-26}
+}
+
+@Patent{matmat_17,
+  Title                    = {{U}sing {R}untime {R}everse {E}ngineering to {O}ptimize {DRAM} {R}efresh},
+  Nationality              = {European Patent Office},
+  Number                   = {EP3454337A1},
+  Year                     = {2017},
+  Author                   = {Mathew M., Deepak and Jung, Matthias and Weis, Christian and Wehn, Norbert},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-04-26}
+}
+
+@InProceedings{matchi_19,
+  Title                    = {{RRAMS}pec: {A} {D}esign {S}pace {E}xploration {F}ramework for {H}igh {D}ensity {R}esistive {RAM}},
+  Author                   = {Mathew, Deepak and Chinazzo, Andr\'e Lucas and Weis, Christian and Jung, Matthias and Giraud, Bastien and Vivet, Pascal and Levisse, Alexandre and Wehn, Norbert},
+  Booktitle                = {2019 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
+  Year                     = {2019},
+  Month                    = {July},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-04-26}
+}
+
+@InProceedings{matpra_20,
+  Title                    = {{A}n {E}nergy {E}fficient 3{D}-{H}eterogeneous {M}ain {M}emory {A}rchitecture for {M}obile {D}evices},
+  Author                   = {Mathew, Deepak M. and Prado, Felipe S. and Zulian, Éder. F. and Weis, Christian and Ghaffar, Muhammad Mohsin and Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {International Symposium on Memory Systems (MEMSYS 2020)},
+  Year                     = {2020},
+  Month                    = {October},
+  Publisher                = {ACM/IEEE},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-09-19}
+}
+
+@InProceedings{matsch_18,
+  Title                    = {{A}n {A}nalysis on {R}etention {E}rror {B}ehavior and {P}ower {C}onsumption of {R}ecent {DDR}4 {DRAM}s},
+  Author                   = {Mathew, Deepak M. and Schultheis, Martin and Rheinländer, Carl C. and Sudarshan, Chirag and Jung, Matthias and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {IEEE Conference Design, Automation and Test in Europe (DATE)},
+  Year                     = {2018},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-11-05}
+}
+
+@InProceedings{matzul_17,
+  Title                    = {{A} {B}ank-{W}ise {DRAM} {P}ower {M}odel for {S}ystem {S}imulations},
+  Author                   = {Mathew, Deepak M. and Zulian, \'{E}der F. and Kannoth, Subash and Jung, Matthias and Weis, Christian and Wehn, Norbert},
+  Booktitle                = {Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {5:1--5:7},
+  Publisher                = {ACM},
+  Series                   = {RAPIDO '17},
+
+  Acmid                    = {3023978},
+  Articleno                = {5},
+  Doi                      = {10.1145/3023973.3023978},
+  ISBN                     = {978-1-4503-4840-9},
+  Keywords                 = {DRAM, Power, Simulation},
+  Location                 = {Stockholm, Sweden},
+  Numpages                 = {7},
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-15}
+}
+
+@Conference{matzul_17a,
+  Title                    = {{U}sing {R}un-{T}ime {R}everse-{E}ngineering to {O}ptimize {DRAM} {R}efresh},
+  Author                   = {Mathew, Deepak M. and Zulian, Éder F. and Jung, Matthias and Kraft, Kira and Weis, Christian and Jacob, Bruce and Wehn, Norbert},
+  Booktitle                = {International Symposium on Memory Systems (MEMSYS17)},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-29}
+}
+
+@PhdThesis{Phdmathe08,
+  Title                    = {{D}esign {T}echniques for {L}ow {P}ower {O}n {C}hip {E}rror {C}orrection},
+  Author                   = {Jimson Mathew},
+  School                   = {University of Bristol},
+  Year                     = {2008},
+  Month                    = sep,
+
+  Annote                   = {only printed version},
+  Cds_grade                = {0},
+  Cds_keywords             = {Channel Code, low-power, finite field arithmetic, Galois Fields, LDPC, FFM, Finite Field Multiplier, Galois Field Multiplier, Fault Tolerant Logic},
+  Cds_read                 = {2008-11},
+  Date-added               = {2008-11-04 11:03:31 +0100},
+  Date-modified            = {2008-11-04 11:05:59 +0100},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Electronic{Mathworks2017,
+  Title                    = {{MATLAB Coder: Generate C and C++ code from MATLAB code}},
+  Author                   = {Mathworks},
+  Note                     = {\url{https://ch.mathworks.com/help/coder/} Last access: 01 Jan 2018},
+  Url                      = {https://ch.mathworks.com/help/coder/},
+  Year                     = {2017}
+}
+
+@Misc{matmersenne02,
+  Title                    = {{M}ersenne {T}wister {MT}19937 {H}ome {P}age},
+
+  Author                   = {Makoto Matsumoto},
+  HowPublished             = {\url{hhttp://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/MT2002/emt19937ar.html}},
+  Month                    = jan,
+  Note                     = {last access 2015-07-04},
+  Year                     = {2007},
+
+  Keywords                 = {financ},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19},
+  Url                      = {http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html}
+}
+
+@Misc{matmersenne07,
+  Title                    = {{M}ersenne {T}wister {H}ome {P}age},
+
+  Author                   = {Makoto Matsumoto},
+  HowPublished             = {\url{http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html}},
+  Month                    = jan,
+  Note                     = {last access 2014-07-02},
+  Year                     = {2007},
+
+  Keywords                 = {financ},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19},
+  Url                      = {http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html}
+}
+
+@Misc{Matsumoto2007,
+  Title                    = {{M}ersenne {T}wister {H}ome {P}age},
+
+  Author                   = {Makoto Matsumoto},
+  HowPublished             = {\url{http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html}},
+  Month                    = jan,
+  Year                     = {2007},
+
+  Keywords                 = {financ},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19},
+  Url                      = {http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html}
+}
+
+@Misc{matmt05,
+  Title                    = {{MT} for 64-bit {M}achines {W}ebsite},
+
+  Author                   = {Makoto Matsumoto},
+  HowPublished             = {\url{http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt64.html}},
+  Month                    = feb,
+  Note                     = {last access 2014-07-02},
+  Year                     = {2005},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {mersenne twister 64 bit},
+  Cds_read                 = {2014-03-07},
+  Cds_review               = {website with 64 bit MT source code},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.07},
+  Url                      = {http://www.math.sci.hiroshima-u.ac.jp/~m-mat/eindex.html}
+}
+
+@Article{matkur_94,
+  Title                    = {{T}wisted {GFSR} {G}enerators {II}},
+  Author                   = {Matsumoto, Makoto and Kurita, Yoshiharu},
+  Journal                  = {ACM Trans. Model. Comput. Simul.},
+  Year                     = {1994},
+
+  Month                    = jul,
+  Number                   = {3},
+  Pages                    = {254--266},
+  Volume                   = {4},
+
+  Abstract                 = {The twisted GFSR generators proposed in a previous article have a defect in k-distribution for k larger than the order of recurrence. In this follow up article, we introduce and analyze a new TGFSR variant having better k-distribution property. We provide an efficient algorithm to obtain the order of equidistribution, together with a tight upper bound on the order. We discuss a method to search for generators attaining this bound, and we list some of these such generators. The upper bound turns out to be (sometimes far) less than the maximum order of equidistribution for a generator of that period length, but far more than that for a GFSR with a working are of the same size.},
+  Acmid                    = {189445},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Doi                      = {10.1145/189443.189445},
+  File                     = {matkur_94.pdf:matkur_94.pdf:PDF},
+  ISSN                     = {1049-3301},
+  Issue_date               = {July 1994},
+  Keywords                 = {randum numbers},
+  Numpages                 = {13},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2014.03.03},
+  Url                      = {http://doi.acm.org/10.1145/189443.189445}
+}
+
+@Article{matkur_92,
+  Title                    = {{T}wisted {GFSR} {G}enerators},
+  Author                   = {Matsumoto, Makoto and Kurita, Yoshiharu},
+  Journal                  = {ACM Trans. Model. Comput. Simul.},
+  Year                     = {1992},
+
+  Month                    = jul,
+  Number                   = {3},
+  Pages                    = {179--194},
+  Volume                   = {2},
+
+  Abstract                 = {The generalized feed back shift register (GFSR) algorithm suggested by Lewis and Payne is a widely used pseudorandom number generator, but has the following serious drawbacks: (1) an initialization scheme to assure higher order equidistribution is involved and is time consuming; (2) each bit of the generated words constitutes an m-sequence based on a primitive trinomials, which shows poor randomness with respect to weight distribution; (3) a large working area is necessary; (4) the period of sequence is far shorter than the theoretical upper bound. This paper presents the twisted GFSR (TGFSR) algorithm, a slightly but essentially modified version of the GFSR, which solves all the above problems without loss of merit. Some practical TGFSR generators were implemented and passed strict empirical tests. These new generators are most suitable for simulation of a large distributive system, which requires a number of mutually independent pseudorandom number generators with compact size.},
+  Acmid                    = {146383},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {5},
+  Cds_keywords             = {random numbers},
+  Cds_read                 = {2014-02-06},
+  Cds_review               = {GFSR and twisted GFSR (TGFSR) algorithms},
+  Doi                      = {10.1145/146382.146383},
+  File                     = {matkur_92.pdf:matkur_92.pdf:PDF},
+  ISSN                     = {1049-3301},
+  Issue_date               = {July 1992},
+  Keywords                 = {random numbers},
+  Numpages                 = {16},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2014.02.06},
+  Url                      = {http://doi.acm.org/10.1145/146382.146383}
+}
+
+@Misc{matdynamic98,
+  Title                    = {{Dynamic Creation of Pseudorandom Number Generators}},
+
+  Author                   = {Makoto Matsumoto and Takuji Nishimura},
+  HowPublished             = {Online: http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/DC/dgene.pdf},
+  Note                     = {Last access: 20/05/2016},
+  Year                     = {1998},
+
+  Comment                  = {Last access: 20/05/2016},
+  Owner                    = {varela},
+  Timestamp                = {2016.05.20},
+  Url                      = {{http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/DC/dgene.pdf}}
+}
+
+@Article{matnis_98,
+  Title                    = {{M}ersenne {T}wister: {A} 623-{D}imensionally {E}quidistributed {U}niform {P}seudo-{R}andom {N}umber {G}enerator},
+  Author                   = {Makoto Matsumoto and Takuji Nishimura},
+  Journal                  = {ACM Trans. Model. Comput. Simul.},
+  Year                     = {1998},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {3--30},
+  Volume                   = {8},
+
+  Abstract                 = {A new algorithm called Mersenne Twister (MT) is proposed for generating uniform pseudorandom numbers. For a particular choice of parameters, the algorithm provides a super astronomical period of 219937 −1 and 623-dimensional equidistribution up to 32-bit accuracy, while using a working area of only 624 words. This is a new variant of the previously proposed generators, TGFSR, modified so as to admit a Mersenne-prime period. The characteristic polynomial has many terms. The distribution up to v bits accuracy for 1 ≤ v ≤ 32 is also shown to be good. An algorithm is also given that checks the primitivity of the characteristic polynomial of MT with computational complexity O(p2) where p is the degree of the polynomial.We implemented this generator in portable C-code. It passed several stringent statistical tests, including diehard. Its speed is comparable to other modern generators. Its merits are due to the efficient algorithms that are unique to polynomial calculations over the two-element field.},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Doi                      = {http://doi.acm.org/10.1145/272991.272995},
+  File                     = {matnis_98.pdf:matnis_98.pdf:PDF},
+  ISSN                     = {1049-3301},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2010.07.23}
+}
+
+@InProceedings{matsei_06,
+  Title                    = {{A GFLOPS Vector-DSP for Broadband Wireless Applications}},
+  Author                   = {Matu, E. and Seidel, H. and Limberg, T. and Robelly, P. and Fettweis, G.},
+  Booktitle                = {Conference 2006, IEEE Custom Integrated Circuits},
+  Year                     = {2006},
+  Month                    = sep,
+  Pages                    = {543--546},
+
+  Doi                      = {10.1109/CICC.2006.320923},
+  Owner                    = {vogt},
+  Timestamp                = {2007.08.27}
+}
+
+@Article{mau_15,
+  Title                    = {{A} {F}ully-{P}arallel {T}urbo {D}ecoding {A}lgorithm},
+  Author                   = {R. G. Maunder},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2015},
+
+  Month                    = {Aug},
+  Number                   = {8},
+  Pages                    = {2762-2775},
+  Volume                   = {63},
+
+  Doi                      = {10.1109/TCOMM.2015.2450208},
+  File                     = {mau_15.pdf:mau_15.pdf:PDF},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Long Term Evolution;WiMax;computational complexity;decoding;error correction;turbo codes;LTE standards;Log-BCJR algorithm;Logarithmic Bahl-Cocke-Jelinek-Raviv algorithm;WiMAX standards;computational complexity;error correction performance;even-indexed bits;first component code;fully-parallel algorithm;odd-even interleavers;odd-indexed bits;resource requirement;serial forwards-backwards manner;standardized codes;turbo codes;turbo decoding;turbo-encoded bits;Convolutional codes;Decoding;Iterative decoding;Measurement;Throughput;Turbo codes;WiMAX;Iterative decoding;Parallel algorithms;Throughput;Turbo codes;WiMAX;iterative decoding;parallel algorithms;throughput},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.25}
+}
+
+@InProceedings{maveat_02,
+  Title                    = {{S}oft error rate mitigation techniques for modern microcircuits},
+  Author                   = {Mavis, D. G. and Eaton, P. H. },
+  Booktitle                = {Proc. 40th Annual Reliability Physics Symp},
+  Year                     = {2002},
+  Pages                    = {216--225},
+
+  Doi                      = {10.1109/RELPHY.2002.996639},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{maveat_09,
+  Title                    = {{SEE} characterization and mitigation in ultra-deep submicron technologies},
+  Author                   = {Mavis, D. G. and Eaton, P. H. and Sibley, M. D. },
+  Booktitle                = {Proc. IEEE Int. Conf. IC Design and Technology ICICDT '09},
+  Year                     = {2009},
+  Pages                    = {105--112},
+
+  Doi                      = {10.1109/ICICDT.2009.5166276},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Electronic{max_16,
+  Title                    = {{New Amazon EC2 F1 instance bringing Maxeler Maximum Performance Computing to The Cloud}},
+  Author                   = {{Maxeler Technologies}},
+  HowPublished             = {https://www.maxeler.com/f1/},
+  Month                    = {Dec},
+  Note                     = {last access 2016-12-22},
+  Year                     = {2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.12.22}
+}
+
+@Misc{maxxilinx13,
+  Title                    = {{X}ilinx {V}ivado {D}esign {S}uite boasts {IP} integration and {HLS} enhancements},
+
+  Author                   = {Clive Maxfield},
+  HowPublished             = {EE Times, \url{http://www.eetimes.com/document.asp?doc_id=1317631}},
+  Month                    = mar,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2013},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{maxxilinx12,
+  Title                    = {{X}ilinx' {Z}ynq {A}ll {P}rogrammable {S}o{C}s accelerate productivity in industrial automation},
+
+  Author                   = {Clive Maxfield},
+  HowPublished             = {EE Times, \url{http://www.eetimes.com/document.asp?doc_id=1317538}},
+  Month                    = nov,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2012},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{maxaltera11,
+  Title                    = {{A}ltera announces industry’s first {O}pen{CL} program for {FPGA}s},
+
+  Author                   = {Clive Maxfield},
+  HowPublished             = {EE Times, \url{http://www.eetimes.com/author.asp?section_id=14&doc_id=1285594}},
+  Month                    = nov,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2011},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{maxalteras11,
+  Title                    = {{A}ltera’s new {ARM}-based {S}o{C} {FPGA}s},
+
+  Author                   = {Clive Maxfield},
+  HowPublished             = {EE Times, \url{http://www.eetimes.com/author.asp?section_id=14&doc_id=1285475}},
+  Month                    = nov,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2011},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{maxxilinx14,
+  Title                    = {{X}ilinx {A}nnounces {SDA}ccel {D}ev {E}nvironment for {C}, {C}++ \& {O}pen{CL}},
+
+  Author                   = {Max Maxfield},
+  HowPublished             = {EE Times, \url{http://www.eetimes.com/document.asp?doc_id=1324674}},
+  Month                    = nov,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2014},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@PhdThesis{Phdmay13,
+  Title                    = {{A}rchitectures for {H}igh-throughput and {R}eliable {I}terative {C}hannel {D}ecoders},
+  Author                   = {May, Matthias},
+  School                   = {Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2013},
+  Month                    = {may},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.04}
+}
+
+@PhdThesis{Phdmay12,
+  Title                    = {{D}issertation in preparation: {A}rchitectures for {H}igh-throughput and {R}eliable {I}terative {C}hannel {D}ecoders},
+  Author                   = {May, Matthias},
+  School                   = {Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2012},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {May},
+  Timestamp                = {2011.12.16}
+}
+
+@MastersThesis{MTmay04,
+  Title                    = {{Integration and Synthesis of Parallel High-Throughput Turbo-Decoders}},
+  Author                   = {M. May},
+  School                   = {Microelectronic System Design Reseach Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2004},
+  Month                    = may,
+
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mayall_08,
+  Title                    = {{A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder}},
+  Author                   = {M. May and M. Alles and N. Wehn},
+  Booktitle                = {Proc. Design, Automation and Test in Europe DATE '08},
+  Year                     = {2008},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+  Pages                    = {456--461},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- LDPC, AIS, AG, Memory, Controller, Network},
+  File                     = {mayall_08.pdf:mayall_08.pdf:PDF},
+  Keywords                 = {AGWehn, LDPC, Reliability},
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.31}
+}
+
+@InProceedings{mayiln_10,
+  Title                    = {{A} 150{M}bit/s 3{GPP} {LTE} {T}urbo {C}ode {D}ecoder},
+  Author                   = {M. May and T. Ilnseher and N. Wehn and W. Raab},
+  Booktitle                = {Proc. Design, Automation and Test in Europe, 2010 (DATE '10)},
+  Year                     = {2010},
+  Month                    = mar,
+  Pages                    = {1420--1425},
+
+  File                     = {mayiln_10.pdf:mayiln_10.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.12.01}
+}
+
+@InProceedings{maynee_07,
+  Title                    = {{E}valuation of {H}igh {T}hroughput {T}urbo-{D}ecoder {A}rchitectures},
+  Author                   = {M. May and C. Neeb and N. Wehn},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2007},
+  Year                     = {2007},
+
+  Address                  = {New Orleans, USA},
+  Month                    = may,
+  Pages                    = {2770--2773},
+
+  Abstract                 = {The outstanding forward error correction of Turbo-codes made them part of many today's communications standards. For high throughput applications, efficient parallel Turbo-decoder architectures are the key. In this paper, two fundamentally different parallel architectural approaches in terms of performance and implementation complexity were compared. Both architectures exploit the well known windowing scheme. The first architecture template processes several windows in parallel. Each window is executed on a serial Log-MAP decoder which produces one value per clock cycle. In contrast, the second architecture sequentially processes the individual windows on a fast monolithic pipelined MAP decoder which produces several values per clock cycle and is memory-optimized. This is, to the best of the author's knowledge, the first comparison of this totally different architectural approach for high throughput Turbo-decoder architectures. The 3GPP conditions for performance comparisons were applied.},
+  Doi                      = {10.1109/ISCAS.2007.378627},
+  File                     = {maynee_07.pdf:maynee_07.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.10}
+}
+
+@InProceedings{mayweh_10,
+  Title                    = {{A} {R}apid {P}rototyping {S}ystem for {E}rror-{R}esilient {M}ulti-{P}rocessor {S}ystems-on-{C}hip},
+  Author                   = {M. May and N. Wehn and A. Bouajila and J. Zeppenfeld and W. Stechele and A. Herkersdorf and D. Ziener and J. Teich},
+  Booktitle                = {Proc. Design, Automation and Test in Europe, 2010 (DATE '10)},
+  Year                     = {2010},
+  Month                    = mar,
+  Pages                    = {375--380},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- LDPC, AIS, AG, Memory
+
+[10] muealv_99},
+  File                     = {mayweh_10.pdf:mayweh_10.pdf:PDF},
+  Keywords                 = {AGWehn, Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.14}
+}
+
+@InProceedings{mccjoi_01,
+  Title                    = {{S}oft decision decoding of {R}eed-{S}olomon codes using the {F}ano sequential algorithm},
+  Author                   = {J. H. McClure and L. L. Joiner},
+  Booktitle                = {SoutheastCon 2001. Proceedings. IEEE},
+  Year                     = {2001},
+  Pages                    = {131-135},
+
+  Doi                      = {10.1109/SECON.2001.923102},
+  Keywords                 = {Reed-Solomon codes;error correction codes;sequential decoding;Fano sequential algorithm;Reed-Solomon codes;error performance;hard decision decoding;soft decision decoding;Block codes;Correlators;Decoding;Error correction;Error correction codes;Matched filters;Radio access networks;Reed-Solomon codes;Transmitters;Voltage}
+}
+
+@InProceedings{mcclan_03,
+  Title                    = {{H}ardware {A}cceleration of {P}seudo-{R}andom {N}umber {G}eneration for {S}imulation {A}pplications},
+  Author                   = {James M. McCollum and Joseph M. Lancaster and Donald W. Bouldin and Gregory D. Peterson},
+  Booktitle                = {System Theory, 2003. Proceedings of the 35th Southeastern Symposium on},
+  Year                     = {2003},
+  Month                    = {16-18},
+  Pages                    = { 299 - 303},
+
+  Abstract                 = {In modeling and simulation tools, random numbers from a variety of probability distribution functions are generated to simulate the behavior of random events. Inefficient generation of these numbers can be a significant bottleneck for simulation applications. Generating these random numbers imprecisely can skew results. An efficient and scalable fixed-point method for generating random numbers for any probability distribution function in a Field Programmable Gate Array (FPGA) is developed. A Pi estimator, a Monte Carlo integrator, and a stochastic simulator for chemical species are developed in software. Estimates are made regarding their potential to be accelerated using the designed FPGA. Results are presented which examine trade-offs between the number of gates used by the FPGA and the accuracy of the random numbers generated. The work shows that generating random numbers using the designed hardware can significantly increase the performance of simulation applications that require many random numbers.},
+  Cds_grade                = {0},
+  File                     = {mcclan_03.pdf:mcclan_03.pdf:PDF},
+  ISSN                     = {0094-2898 },
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.28}
+}
+
+@Article{mcc_06,
+  Title                    = {{A} {R}eview of {TESTU}01},
+  Author                   = {B. D. McCullough},
+  Journal                  = {Journal of Applied Econometrics},
+  Year                     = {2006},
+  Number                   = {5},
+  Pages                    = {677-682},
+  Volume                   = {21},
+
+  Abstract                 = {The choice of an appropriate social rate of discount is critical in the decision-making process on public investments. In this paper we review the literature on social discounting, and address in particular a recently growing field of related research, that is, individual time preferences. We argue that an explicit consideration and analysis of the behaviour of individuals regarding the concept and the use of an appropriate social discount rate are essential for balanced decision making in the public sector, especially, though not exclusively, in the field of resource or environmental policy.},
+  Cds_grade                = {0},
+  File                     = {mcc_06.pdf:mcc_06.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.18},
+  Url                      = {http://ideas.repec.org/a/jae/japmet/v21y2006i5p677-682.html}
+}
+
+@Article{mcemac_98,
+  Title                    = {{Turbo Decoding as an Instance of Pearl's ``Belief Propagation'' Algorithm}},
+  Author                   = {McEliece, R. J. and MacKay, D. J. C. and Cheng, J.-F.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {1998},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {140--152},
+  Volume                   = {16},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mceony_89,
+  Title                    = {{Truncation Effects in Viterbi Decoding}},
+  Author                   = {R. J. McEliece and I. M. Onyszchuk},
+  Booktitle                = {Proc. 1989 Military Communications Conference (Milcom '89)},
+  Year                     = {1989},
+  Pages                    = {541--545},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mcf_14,
+  Title                    = {{A} modified ziggurat algorithm for generating exponentially- and normally-distributed pseudorandom numbers},
+  Author                   = {Christopher D. McFarland},
+  Journal                  = {CoRR},
+  Year                     = {2014},
+
+  Month                    = mar,
+  Volume                   = {abs/1403.6870},
+
+  Abstract                 = {The Ziggurat Algorithm is a very fast rejection sampling method for generating PseudoRandom Numbers (PRNs) from common statistical distributions. The algorithm divides a distribution into rectangular layers that stack on top of each other (resembling a Ziggurat), subsuming the desired distribution. Random values within these rectangular layers are then sampled by rejection. This implementation splits layers into two types: those constituting the majority that fall completely under the distribution and can be sampled extremely fast without a rejection test, and a few additional layers that encapsulate the fringe of the distribution and require a rejection test. This method offers speedups of 65% for exponentially- and 82% for normally-distributed PRNs when compared to the best available C implementations of these generators. Even greater speedups are obtained when the algorithm is extended to the Python and MATLAB/OCTAVE programing environments.},
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Cds_grade                = {0},
+  Cds_keywords             = {Ziggurat, CPU},
+  Ee                       = {http://arxiv.org/abs/1403.6870},
+  File                     = {mcf_14.pdf:mcf_14.pdf:PDF},
+  Keywords                 = {random numbers}
+}
+
+@Article{mcicon_18,
+  Title                    = {{A} {S}urvey of the {I}mplementation of {L}inear {M}odel {P}redictive {C}ontrol on {FPGAs}},
+  Author                   = {Ian McInerney and George A. Constantinides and Eric C. Kerrigan},
+  Journal                  = {IFAC-PapersOnLine},
+  Year                     = {2018},
+  Note                     = {6th IFAC Conference on Nonlinear Model Predictive Control NMPC 2018},
+  Number                   = {20},
+  Pages                    = {381 - 387},
+  Volume                   = {51},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; NEW STUFF ACCORDING TO THE REVIEWER COMMENTS OF ECC'19},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {https://doi.org/10.1016/j.ifacol.2018.11.063},
+  ISSN                     = {2405-8963},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {linear MPC, embedded optimization, Field Programmable Gate Array (FPGA)},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S2405896318327216}
+}
+
+@PhdThesis{Phdmckeo95,
+  Title                    = {{Scheduling Algorithms for Input-queued Cell Switches}},
+  Author                   = {McKeown, N.W.},
+  School                   = {University of California, Berkeley},
+  Year                     = {1995},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mck_66,
+  Title                    = {{G}eneralized birthday problem},
+  Author                   = {McKinney, Earl H},
+  Journal                  = {American Mathematical Monthly},
+  Year                     = {1966},
+  Pages                    = {385--387},
+
+  Owner                    = {Brugger},
+  Publisher                = {JSTOR},
+  Timestamp                = {2015.09.10}
+}
+
+@Misc{mclcdn_17,
+  Title                    = {{CDND}rive: {C}adence {A}utomotive {IP} {S}olutions},
+
+  Author                   = {McLellan, Paul},
+  HowPublished             = {https://community.cadence.com/cadence\_blogs\_8/b/breakfast-bytes/posts/cdndrive-cadence-automotive-solutions},
+  Month                    = {July},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-01}
+}
+
+@Book{mcnfre_05,
+  Title                    = {{Q}uantitative {R}isk {M}anagement: {C}oncepts, {T}echniques, and {T}ools},
+  Author                   = {Alexander J. McNeil and Rüdiger Frey and Paul Embrechts},
+  Publisher                = {Princeton University Press},
+  Year                     = {2005},
+
+  Address                  = {Princeton and Oxford},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@InProceedings{meddra_07,
+  Title                    = {{C}haracterization of a {F}ault-tolerant {N}o{C} {R}outer},
+  Author                   = {Mediratta, S. D. and Draper, J.},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2007},
+  Year                     = {2007},
+  Month                    = may,
+  Pages                    = {381--384},
+
+  Doi                      = {10.1109/ISCAS.2007.378469},
+  File                     = {meddra_07.pdf:meddra_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InCollection{medsch_09,
+  Title                    = {{C}oding {S}chemes for {A}rithmetic and {L}ogic {O}perations - {H}ow {R}obust {A}re {T}hey?},
+  Author                   = {Medwed, Marcel and Schmidt, Jörn-Marc},
+  Booktitle                = {Information Security Applications},
+  Publisher                = {Springer Berlin / Heidelberg},
+  Year                     = {2009},
+  Editor                   = {Youm, Heung and Yung, Moti},
+  Note                     = {10.1007/978-3-642-10838-9_5},
+  Pages                    = {51-65},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {5932},
+
+  Affiliation              = {Graz University of Technology Institute for Applied Information Processing and Communications Inffeldgasse 16a A–8010 Graz Austria},
+  File                     = {medsch_09.pdf:medsch_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Url                      = {http://dx.doi.org/10.1007/978-3-642-10838-9_5}
+}
+
+@TechReport{mehneu_12,
+  Title                    = {{M}anaging market risk: {T}oday and tomorrow},
+  Author                   = {Amit Mehta and Max Neukirchen and Sonja Pfetsch and Thomas Poppensieker},
+  Institution              = {McKinsey \& Company},
+  Year                     = {2012},
+  Month                    = {may},
+  Number                   = {32},
+  Type                     = {McKinsey Working Papers on Risk},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.28},
+  Url                      = {http://www.mckinsey.com/business-functions/risk/our-insights/managing-market-risk-today-and-tomorrow}
+}
+
+@Article{meilam_05,
+  Title                    = {{Architecture Exploration for a Reconfigurable Architecture Template}},
+  Author                   = {Mei, B. and Lambrechts, A. and Mignolet, J.-Y. and Verkest, D. and Lauwereins, R.},
+  Journal                  = {Design \& Test of Computers, IEEE},
+  Year                     = {2005},
+
+  Month                    = mar # {--} # apr,
+  Number                   = {2},
+  Pages                    = {90--101},
+  Volume                   = {22},
+
+  Doi                      = {10.1109/MDT.2005.27},
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.01}
+}
+
+@InProceedings{meiver_04,
+  Title                    = {{Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: a Case Study}},
+  Author                   = {Mei, B. and Vernalde, S. and Verkest, D. and Lauwereins, R.},
+  Booktitle                = {Proc. Design, Automation and Test in Europe Conference and Exhibition, 2004.},
+  Year                     = {2004},
+  Month                    = feb,
+  Pages                    = {1224--1229Vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/DATE.2004.1269063},
+  Owner                    = {vogt},
+  Timestamp                = {2006.11.30}
+}
+
+@InProceedings{meiver_03,
+  Title                    = {{ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix}},
+  Author                   = {B. Mei and S. Vernalde and Diederik Verkest and H. De Man and Rudy Lauwereins},
+  Booktitle                = {Field-Programmable Logic and Applications, 2003. Proc. 13th International Conference},
+  Year                     = {2003},
+
+  Address                  = {Lisbon, Portugal},
+  Month                    = sep,
+  Pages                    = {61--70},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Unpublished{meieng_10,
+  Title                    = {{L}av{A}: {A}n {O}pen {P}latform for {R}apid {P}rototyping of {MPS}o{C}s},
+  Author                   = {Matthias Meier and Michael Engel and Matthias Steinkamp and Olaf Spinczyk},
+  Note                     = {for FPL 2010 in Milano, Italy},
+
+  Month                    = {May},
+  Year                     = {2010},
+
+  Abstract                 = {Configurable hardware is becoming increasingly powerful and less expensive. This allows embedded system developers to exploit hardware parallelism in order to improve real time properties and energy efficiency. However, hardware design, even if performed using high-level hardware description languages, is error-prone and time consuming, especially when designing complex heterogeneous multiprocessor systems. To reduce the time to market for such systems, it is necessary to support the designer with a flexible work flow and methods for efficient reuse of existing components. In software engineering, this is enabled by using model-driven design flows and tools for configuration. In this paper, we describe LavA, a system which adapts these concepts to hardware design. By providing a streamlined toolchain and workflow to rapidly prototype complex, heterogeneous multiprocessor systems-on-chip based on a model-driven approach, developers can reduce turnaround times in design as well as design space exploration.},
+  Cds_grade                = {4},
+  Cds_keywords             = {MPSoC, Methodology, Tool, Rapid Prototyping, Code Generation, HDL},
+  Cds_read                 = {2010-05-12},
+  Cds_review               = {You present a very-well structured approach for model-based MPSoC design. As you use standard software like Eclipse, XVCL and oAW, in my opinion your methodology provides a good starting point for future and custom extensions, as you show them in the outlook.
+
+Concerning the state-of-the-art section, maybe you should have a look at the MAPS tool from RWTH Aachen published at DAC 2008, even if it's not exactly the same application and does not completely rely on free software.
+
+Furthermore, it seems like your tool only can handle IP written in the system-level common HDL. What about IP that is only available as a netlist? You should at least comment on that.
+
+Section 5 for me seems very good, you clearly explain your meta-model approach and show the possibility of early plausibility checks by assertions, what is very important in my opinion.
+
+Nevertheless, there are some formal issues in the paper, e.g. a wrong line break in the second paragraph and the word "automaton" in the fourth one. You really should re-read the paper and look for spelling errors.
+
+All in all a good overview of your new methodology without giving too much details.},
+  File                     = {meieng_10.pdf:meieng_10.pdf:PDF},
+  Keywords                 = {Review},
+  Owner                    = {CdS},
+  Timestamp                = {2010.05.12}
+}
+
+@InProceedings{memli_17,
+  Title                    = {{B}enchmarking {O}pen{CL}, {O}pen{ACC}, {O}pen{MP}, and {CUDA}: {P}rogramming {P}roductivity, {P}erformance, and {E}nergy {C}onsumption},
+  Author                   = {Suejb Memeti and Lu Li and Sabri Pllana and Joanna Kolodziej and Christoph Kessler},
+  Booktitle                = {Proceedings of the 2017 Workshop on Adaptive Resource Management and Scheduling for Cloud Computing},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {1--6},
+  Publisher                = {ACM},
+  Series                   = {ARMS-CC '17},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.16}
+}
+
+@Conference{menjun_17,
+  Title                    = {{S}ystem {S}imulation with gem5 and {S}ystem{C}: {T}he {K}eystone for {F}ull {I}nteroperability},
+  Author                   = {Menard, Christian and Jung, Matthias and Castrillon, Jeronimo and Wehn, Norbert},
+  Booktitle                = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
+  Year                     = {2017},
+  Month                    = {July},
+  Pages                    = {62-69},
+
+  Doi                      = {10.1109/SAMOS.2017.8344612},
+  Keywords                 = {Couplings;Hardware;Industries;Protocols;Time-domain analysis;Time-varying systems;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17}
+}
+
+@InProceedings{menvyn_11,
+  Title                    = {{F}inding the {R}ight {L}evel of {A}bstraction for {M}inimizing {O}perational {E}xpenditure},
+  Author                   = {Oskar Mencer and Erik Vynckier and James Spooner and Stephen Girdlestone and Oliver Charlesworth},
+  Booktitle                = {High Performance Computational Finance (WHPCF), 2011 IEEE Workshop on},
+  Year                     = {2011},
+  Month                    = nov,
+
+  Abstract                 = {In this paper we are examining the impact of modern programming language abstractions on total cost of ownership (TCO) of a financial computing operation. Our analysis is based on static and dynamic analysis of example financial software, based on our loop-flow graph (LFG) concept and our custom dynamic hotspot tool called MaxSpot. Our results show that, if the required throughput of an application is high enough, then operational expenditure is minimized by minimizing runtime and not programming effort.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Heston, FPGA, option pricing, Monte Carlo},
+  Cds_read                 = {2011-11-13},
+  Cds_review               = {TCO: total cost of ownership <- central metric of the paper
+Heston FPGA pricer presented based on Monte Carlo, extended by jump simulation
+volatility modelling avoiding negative values
+
++ motivation for drastic increase of simulation need in the future: Solvency II, Basel III},
+  File                     = {menvyn_11.pdf:menvyn_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.13}
+}
+
+@Book{menda_97,
+  Title                    = {{Synchronization Techniques for Digital Receivers}},
+  Author                   = {U. Mengali and A. D'Andrea},
+  Publisher                = {Plenum Publishing Corporation},
+  Year                     = {1997},
+
+  Address                  = {New York},
+
+  Optnote                  = {ISBN 0-306-45725-3},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{menmor_97,
+  Title                    = {{D}ata-aided frequency estimation for burst digital transmission.},
+  Author                   = {Mengali, Umberto and Morelli, Michele},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1997},
+  Number                   = {1},
+  Pages                    = {23-25},
+  Volume                   = {45},
+
+  Owner                    = {Imran Ali},
+  Timestamp                = {2013-07-30}
+}
+
+@PhdThesis{Phdmenne10,
+  Title                    = {{A}ufwandsgünstige {D}etektion in {M}ehrantennensystemen mittels komplexitätsreduzierter {B}aumsuchverfahren},
+  Author                   = {Björn Mennenga},
+  School                   = {Technische Universität Dresden},
+  Year                     = {2010},
+
+  File                     = {Phdmenne10.pdf:Phdmenne10.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.03.27}
+}
+
+@InProceedings{menfet_09,
+  Title                    = {{S}earch sequence determination for tree search based detection algorithms},
+  Author                   = {Mennenga, B. and Fettweis, G.},
+  Booktitle                = {Sarnoff Symposium, 2009. SARNOFF '09. IEEE},
+  Year                     = {2009},
+  Pages                    = {1 -6},
+
+  Doi                      = {10.1109/SARNOF.2009.4850294},
+  File                     = {menfet_09.pdf:menfet_09.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.03.30}
+}
+
+@InProceedings{menfri_09,
+  Title                    = {{I}terative {S}oft-{I}n {S}oft-{O}ut {S}phere {D}etection for {MIMO} {S}ystems},
+  Author                   = {Mennenga, B. and Fritzsche, R. and Fettweis, G.},
+  Booktitle                = {Vehicular Technology Conference, 2009. VTC Spring 2009. IEEE 69th},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/VETECS.2009.5073627},
+  File                     = {menfri_09.pdf:menfri_09.pdf:PDF},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.08.03}
+}
+
+@InProceedings{menmat_09,
+  Title                    = {{V}ectorization of the {S}phere {D}etection algorithm},
+  Author                   = {Mennenga, Bjorn and Matus, Emil and Fettweis, Gerhard},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2009},
+  Year                     = {2009},
+  Month                    = may,
+  Pages                    = {2806--2809},
+
+  Doi                      = {10.1109/ISCAS.2009.5118385},
+  File                     = {menmat_09.pdf:menmat_09.pdf:PDF},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.08.03}
+}
+
+@Misc{catapult,
+  Title                    = {{C}atapult {C} {S}ynthesis},
+
+  Author                   = {{Mentor Graphics}},
+  HowPublished             = {www.mentor.com/catapult},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.20}
+}
+
+@Misc{MentorGraphics,
+  Title                    = {{C}atapult {C} {S}ynthesis},
+
+  Author                   = {{Mentor Graphics}},
+  HowPublished             = {www.mentor.com/catapult},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.20}
+}
+
+@InProceedings{mer_16,
+  Title                    = {{I}nvited - {E}nergy {H}arvesting and {T}ransient {C}omputing: {A} {P}aradigm {S}hift for {E}mbedded {S}ystems?},
+  Author                   = {Merrett, Geoff V.},
+  Booktitle                = {Proceedings of the 53rd Annual Design Automation Conference},
+  Year                     = {2016},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {33:1--33:2},
+  Publisher                = {ACM},
+  Series                   = {DAC '16},
+
+  Acmid                    = {2905011},
+  Articleno                = {33},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Merrett:2016:IEH:2897937.2905011},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/2897937.2905011},
+  ISBN                     = {978-1-4503-4236-0},
+  Keywords                 = {TCS},
+  Keywords_original        = {embedded systems, energy harvesting, transient computing},
+  Location                 = {Austin, Texas},
+  Numpages                 = {2},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/2897937.2905011}
+}
+
+@Misc{mermsoft14,
+  Title                    = {{M}'soft {P}lugs {FPGA}s in {D}atacenter},
+
+  Author                   = {Rick Merritt},
+  HowPublished             = {EE Times, \url{http://www.eetimes.com/document.asp?doc_id=1323500}},
+  Month                    = dec,
+  Note                     = {last access 2015-06-02},
+  Year                     = {2014},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.02}
+}
+
+@Electronic{mer_09,
+  Title                    = {{ARM} {CTO}: power surge could create 'dark silicon'},
+  Author                   = {Rick Merritt},
+  Language                 = {en},
+  Month                    = oct,
+  Note                     = {last access 2014-07-02},
+  Url                      = {http://www.eetimes.com/document.asp?doc_id=1172049},
+  Year                     = {2009},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {dark silicon, scaling, power},
+  File                     = {mer_09.pdf:mer_09.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Article{mer_73,
+  Title                    = {{T}heory of {R}ational {O}ption {P}ricing},
+  Author                   = {Robert C. Merton},
+  Journal                  = {The Bell Journal of Economics and Management Science},
+  Year                     = {1973},
+  Number                   = {1},
+  Pages                    = {141--183},
+  Volume                   = {4},
+
+  Cds_grade                = {0},
+  File                     = {mer_73.pdf:mer_73.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {JSTOR},
+  Timestamp                = {2012.04.03}
+}
+
+@Article{metfav_00,
+  Title                    = {{S}elf-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines},
+  Author                   = {Metra, C. and Favalli, M. and Ricco, B.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {2000},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {560--574},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/12.862216},
+  File                     = {metfav_00.pdf:metfav_00.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@Misc{meuadvanced16,
+  Title                    = {{A}dvanced {R}isk and {P}ortfolio {M}anagement ({ARPM}) {B}ootcamp},
+
+  Author                   = {Attilio Meucci},
+  HowPublished             = {Online: \url{https://www.arpm.co/bootcamp/}},
+  Month                    = {Aug.},
+  Note                     = {Last access: 16 Jan. 2018},
+  Year                     = {2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.16},
+  Url                      = {https://www.arpm.co/bootcamp/}
+}
+
+@Electronic{meu_11,
+  Title                    = {‘{T}he {P}rayer’ {T}en-{S}tep {C}hecklist for {A}dvanced {R}isk and {P}ortfolio {M}anagement},
+  Author                   = {Attilio Meucci},
+  HowPublished             = {Online: http://dx.doi.org/10.2139/ssrn.1753788},
+  Month                    = {Feb},
+  Note                     = {Last access: 06 Oct 2017},
+  Year                     = {2011},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.06}
+}
+
+@Article{Meucci2010,
+  Title                    = {{F}actors on {D}emand: {B}uilding a {P}latform for {P}ortfolio {M}anagers, {R}isk {M}anagers and {T}raders},
+  Author                   = {Attilio Meucci},
+  Journal                  = {Risk},
+  Year                     = {2010},
+  Number                   = {7},
+  Pages                    = {84-89},
+  Volume                   = {23},
+
+  Date                     = {2010-04-01},
+  Url                      = {https://ssrn.com/abstract=1565134},
+  Urldate                  = {2017-08-20}
+}
+
+@Book{meu_05,
+  Title                    = {{R}isk and {A}sset {A}llocation},
+  Author                   = {Attilio Meucci},
+  Publisher                = {Springer},
+  Year                     = {2005},
+
+  Address                  = {Berlin Heidelberg},
+  Series                   = {Springer Finance},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.07.07}
+}
+
+@Article{meulor_16,
+  Title                    = {{Neither 'Normal' nor 'Lognormal': Modeling Interest Rates Across All Regimes}},
+  Author                   = {Attilio Meucci and Angela Loregian},
+  Journal                  = {Financial Analysts Journal},
+  Year                     = {2016},
+
+  Month                    = {April},
+  Number                   = {3},
+  Volume                   = {72},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.07.07},
+  Url                      = {https://ssrn.com/abstract=2359117}
+}
+
+@Article{meybae_12,
+  Title                    = {{E}nergy optimization of {A}pplication-{S}pecific {I}nstruction-{S}et {P}rocessors by using hardware accelerators in semicustom {IC}s technology},
+  Author                   = {Uwe Meyer-Baese and Guillermo Botella and Soumak Mookherjee and Encarnación Castillo and Antonio García},
+  Journal                  = {Microprocessors and Microsystems},
+  Year                     = {2012},
+  Note                     = {<ce:title>SPECIAL ISSUE -EXPLOITATION OF HARDWARE ACCELERATORS</ce:title>},
+  Number                   = {2},
+  Pages                    = {127 - 137},
+  Volume                   = {36},
+
+  Doi                      = {10.1016/j.micpro.2011.06.003},
+  File                     = {meybae_12.pdf:meybae_12.pdf:PDF},
+  ISSN                     = {0141-9331},
+  Keywords                 = {Application-Specific Instruction-Set Processors (ASIPs)},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0141933111000780}
+}
+
+@Book{meymoe_97,
+  Title                    = {{Digital Communication Receivers}},
+  Author                   = {H. Meyr and M. Moeneclaey and S. Fechtel},
+  Publisher                = {John Wiley \& Sons, Inc.},
+  Year                     = {1997},
+
+  Address                  = {New York},
+
+  Optnote                  = {ISBN 0-471-50275-8},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{meymoe_98,
+  Title                    = {{Digital Communication Receivers}},
+  Author                   = {H. Meyr AND M. Moeneclaey AND S. A. Fechtel},
+  Publisher                = {John Wiley \& Sons Inc},
+  Year                     = {1998},
+
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.01}
+}
+
+@InProceedings{meynol_02,
+  Title                    = {{Designing Complex SOC's for Wireless Communications (Invited Talk)}},
+  Author                   = {H. Meyr and T. G. Noll},
+  Booktitle                = {Proc. 2002 International Symposium on Low Power Electronics and Design (ISLPED '02)},
+  Year                     = {2002},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = aug,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mezwu_15,
+  Title                    = {{R}evisiting {M}emory {E}rrors in {L}arge-{S}cale {P}roduction {D}ata {C}enters: {A}nalysis and {M}odeling of {N}ew {T}rends from the {F}ield},
+  Author                   = {Meza, Justin and Wu, Qiang and Kumar, Sanjeev and Mutlu, Onur},
+  Booktitle                = {IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.17}
+}
+
+@InProceedings{mifen_10,
+  Title                    = {{S}oftware-hardware {C}ooperative {DRAM} {B}ank {P}artitioning for {C}hip {M}ultiprocessors},
+  Author                   = {Mi, Wei and Feng, Xiaobing and Xue, Jingling and Jia, Yaocang},
+  Booktitle                = {Proceedings of the 2010 IFIP International Conference on Network and Parallel Computing},
+  Year                     = {2010},
+
+  Address                  = {Berlin, Heidelberg},
+  Pages                    = {329--343},
+  Publisher                = {Springer-Verlag},
+  Series                   = {NPC'10},
+
+  Acmid                    = {1882045},
+  ISBN                     = {3-642-15671-1, 978-3-642-15671-7},
+  Keywords                 = {address mapping, cache locality, row buffer locality},
+  Location                 = {Zhengzhou, China},
+  Numpages                 = {15},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11},
+  Url                      = {http://dl.acm.org/citation.cfm?id=1882011.1882045}
+}
+
+@PhdThesis{Phdmiche02,
+  Title                    = {{Implementation of Turbo-Decoders on Programmable Architectures}},
+  Author                   = {H. Michel},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2002},
+  Note                     = {ISBN 3-925178-87-2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{mic_01,
+  Title                    = {{Evaluation of Tensilica Xtensa Core Using a Turbo-Decoder Example}},
+  Author                   = {H. Michel},
+  Institution              = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2001},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{mic_99,
+  Title                    = {{Software-Implementierung eines Turbo-Decoders auf dem DSP Motorola 56603}},
+  Author                   = {H. Michel},
+  Institution              = {Institute of Microelectronic Systems, Department of Electrical Engineering, University of Kaiserslautern},
+  Year                     = {1999},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{micweh_01,
+  Title                    = {{T}urbo-{D}ecoder {Q}uantization for {UMTS}},
+  Author                   = {Heiko Michel and Norbert Wehn},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {55--57},
+  Volume                   = {5},
+
+  Abstract                 = {The use of Turbo-Codes is proposed for high-rate data services
+in third generation wireless communication systems. Bit-true models
+are mandatory for hardware and software implementations. In this paper
+we present to the best of our knowledge the first investigation of a combined
+bit-width optimization of input data and internal data for an 8-state Turbodecoder
+based on parameters relevant for UMTS. Simulation results for
+AWGN and Rayleigh-fading channels show that performance degradation
+can be held below 0.11 dB using a 4-bit input data quantization.},
+  Cds_grade                = {3},
+  Cds_keywords             = {turbo decoding, quantization, umts, simulation},
+  Cds_read                 = {2008-12-18},
+  Cds_review               = {Quantization effects on UMTS turbo decoding
+relies strongly on simulation results, only few theoretical considerations},
+  File                     = {micweh_01.pdf:micweh_01.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{micwor_02,
+  Title                    = {{Hardware/Software Trade-offs for Advanced 3G Channel Coding}},
+  Author                   = {H. Michel and A. Worm and Münch and N. Wehn},
+  Booktitle                = {Proc. Design, Automation and Test in Europe Conference and Exhibition},
+  Year                     = {2002},
+
+  Address                  = {Paris, France},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{micwor_00,
+  Title                    = {{Influence of Quantization on the Bit-Error Performance of Turbo-Decoders}},
+  Author                   = {H. Michel and A. Worm and N. Wehn},
+  Booktitle                = {Proc. IEEE 51st VTC 2000-Spring Tokyo Vehicular Technology},
+  Year                     = {2000},
+
+  Address                  = {Tokyo, Japan},
+  Month                    = may,
+  Pages                    = {581--585},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{miclev_91,
+  Title                    = {{A} {N}ew {A}pproach to {C}ontrol {F}low {C}hecking {W}ithout {P}rogram {M}odification.},
+  Author                   = {T. Michel and Régis Leveugle and Gabriele Saucier},
+  Booktitle                = {Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers., Twenty-First International Symposium},
+  Year                     = {1991},
+  Pages                    = {334-343},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de}
+}
+
+@Misc{micron_ddr3_11,
+  Title                    = {{DDR}3 {SDRAM} {S}ystem {P}ower {C}alculator},
+
+  Author                   = {Micron},
+  Month                    = jul,
+  Note                     = {last access 2014-07-03},
+  Year                     = {2011},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.03},
+  Url                      = {http://www.micron.com/products/support/power-calc}
+}
+
+@Misc{micron_ddr3_11_kopie_ipsj,
+  Title                    = {{DDR}3 {SDRAM} {S}ystem {P}ower {C}alculator,},
+
+  Author                   = {Micron},
+  HowPublished             = {last access 2014-07-03},
+  Month                    = {jul},
+  Year                     = {2011},
+
+  Owner                    = {MJ},
+  Timestamp                = {2014.07.03},
+  Url                      = {http://www.micron.com/products/support/power-calc}
+}
+
+@InProceedings{Mielczarek2002,
+  Title                    = {{P}hase offset estimation using enhanced turbo decoders},
+  Author                   = {Mielczarek, B. and Svensson, A.},
+  Booktitle                = {IEEE International Conference on Communications (ICC 2002)},
+  Year                     = {2002},
+  Pages                    = {1536-1540 vol.3},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/ICC.2002.997107},
+  Keywords                 = {Gaussian distribution;Markov processes;decoding;digital radio;error statistics;phase estimation;state-space methods;synchronisation;turbo codes;Gaussian probability distribution;Markov chain;bit error probability;decoding algorithms;enhanced turbo decoders;phase offset estimation;residual phase error;signal phase;state space;turbo coding system;AWGN channels;Decoding;Fading;Frequency synchronization;Gaussian noise;Phase estimation;Phase noise;Probability distribution;Signal processing;Turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.23}
+}
+
+@InProceedings{miesve_99,
+  Title                    = {{Improved MAP Decoders for Turbo Codes With Non-Perfect Timing and Phase Synchronization}},
+  Author                   = {B. Mielczarek and A. Svensson},
+  Booktitle                = {Proc. 1999-Fall Vehicular Technology Conference (VTC Fall '99)},
+  Year                     = {1999},
+
+  Address                  = {Amsterdam, The Netherlands},
+  Month                    = sep,
+  Pages                    = {1590--1594},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{miknoeg_05,
+  Title                    = {{T}he {B}est of {W}ilmott 1: {I}ncorporating the {Q}uantitative {F}inance {R}eview},
+  Author                   = {Sergei Mikhailov and Ulrich Nögel},
+  Chapter                  = {Heston’s Stochastic Volatility Model Implementation, Calibration and Some Extensions},
+  Editor                   = {Paul Wilmott},
+  Year                     = {2005},
+  Month                    = jul,
+
+  Cds_grade                = {0},
+  Cds_keywords             = {finance, calibration, Heston},
+  File                     = {miknoeg_05.pdf:miknoeg_05.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24},
+  Url                      = {\url{http://www.math.umn.edu/~bemis/IMA/MMI2008/calibrating_heston.pdf}}
+}
+
+@InProceedings{milarc_12,
+  Title                    = {{A} scalable signal processing architecture for massive graph analysis},
+  Author                   = {Miller, B.A. and Arcolano, N. and Beard, M.S. and Kepner, J. and Schmidt, M.C. and Bliss, N.T. and Wolfe, P.J.},
+  Booktitle                = {Proceedings of the 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)},
+  Year                     = {2012},
+  Month                    = {March},
+  Pages                    = {5329-5332},
+
+  Abstract                 = {In many applications, it is convenient to represent data as a graph, and often these datasets will be quite large. This paper presents an architecture for analyzing massive graphs, with a focus on signal processing applications such as modeling, filtering, and signal detection. We describe the architecture, which covers the entire processing chain, from data storage to graph construction to graph analysis and subgraph detection. The data are stored in a new format that allows easy extraction of graphs representing any relationship existing in the data. The principal analysis algorithm is the partial eigendecomposition of the modularity matrix, whose running time is discussed. A large document dataset is analyzed, and we present subgraphs that stand out in the principal eigenspace of the time-varying graphs, including behavior we regard as clutter as well as small, tightly-connected clusters that emerge over time.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ICASSP.2012.6289124},
+  File                     = {milarc_12.pdf:milarc_12.pdf:PDF},
+  ISSN                     = {1520-6149},
+  Keywords                 = {graphs},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.28}
+}
+
+@Article{milwil_12,
+  Title                    = {{I}mplementation of linear model predictive control using a field-programmable gate array},
+  Author                   = {A. Mills and A. G. Wills and S. R. Weller and B. Ninness},
+  Journal                  = {IET Control Theory Applications},
+  Year                     = {2012},
+
+  Month                    = {May},
+  Number                   = {8},
+  Pages                    = {1042-1054},
+  Volume                   = {6},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [14]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1049/iet-cta.2010.0739},
+  ISSN                     = {1751-8644},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {actuators;beams (structures);computer architecture;control engineering computing;field programmable gate arrays;flexible structures;predictive control;structural engineering;linear model predictive control;field-programmable gate array;custom computer architecture solution;primal logarithmic-barrier interior-point algorithm;actuator constraint handling;state observation;data sampling;disturbance rejection control problem;14th-order lightly damped flexible beam structure;frequency 2 kHz},
+  Owner                    = {CCR}
+}
+
+@Article{mil_91,
+  Title                    = {{I}nternet time synchronization: the network time protocol},
+  Author                   = {Mills, D.L.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {1991},
+
+  Month                    = {Oct},
+  Number                   = {10},
+  Pages                    = {1482-1493},
+  Volume                   = {39},
+
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {103043},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1109/26.103043},
+  ISSN                     = {0090-6778},
+  Keywords                 = {BLE},
+  Keywords_original        = {computer networks;protocols;synchronisation;Internet;distributed subnet;hierarchical configuration;large diverse networks;local routing algorithms;national time standards;network time protocol;symmetric architecture;time daemons;time servers;time synchronization;Clocks;IP networks;Internet;Maintenance;Milling machines;Network servers;Protocols;Synchronization;Web server;Wire},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30}
+}
+
+@Article{milshe_02,
+  Title                    = {{N}etwork {M}otifs: {S}imple {B}uilding {B}locks of {C}omplex {N}etworks},
+  Author                   = {Ron Milo and Shai Shen-Orr and Shalev Itzkovitz and Nadav Kashtan and Dmitri Chklovskii and Uri Alon},
+  Journal                  = {Science},
+  Year                     = {2002},
+  Pages                    = {824--827},
+  Volume                   = {298},
+
+  Owner                    = {Nina},
+  Timestamp                = {2006.11.23}
+}
+
+@Article{miltri_14,
+  Title                    = {{S}equential {D}ecoding of {P}olar {C}odes},
+  Author                   = {V. Miloslavkaya and P. Trifonov},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2014},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {1127-1130},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/LCOMM.2014.2323237},
+  ISSN                     = {1089-7798},
+  Keywords                 = {binary codes;block codes;interference suppression;linear codes;sequential decoding;trees (mathematics);code tree;low complexity sequential soft decision decoding algorithm;path selection;polar codes;successive cancellation approach;Arrays;Complexity theory;Decoding;Heuristic algorithms;Iterative decoding;Random variables;Polar codes;sequential decoding;successive cancellation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{miltri_14a,
+  Title                    = {{S}equential decoding of polar codes with arbitrary binary kernel},
+  Author                   = {V. Miloslavskaya and P. Trifonov},
+  Booktitle                = {Information Theory Workshop (ITW), 2014 IEEE},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {376-380},
+
+  Doi                      = {10.1109/ITW.2014.6970857},
+  ISSN                     = {1662-9019},
+  Keywords                 = {BCH codes;binary codes;numerical analysis;sequential decoding;Arikan kernel;BCH kernel;arbitrary binary kernel;near-ML decoding;polar codes;sequential decoding algorithm;soft-decision decoding efficiency;Complexity theory;Decoding;Error probability;Iterative decoding;Kernel;Random variables;Vectors},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Article{min_17,
+  Title                    = {{A}n {I}nnovative {I}ndicator to {E}valuate {DRAM} {C}ell {T}ransistor {L}eakage {C}urrent {D}istribution},
+  Author                   = {MIN HEE CHO, NAMHO JEON},
+  Journal                  = {Journal of the Electron Devices Society},
+  Year                     = {2017},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-05-02}
+}
+
+@InProceedings{mirghe_02,
+  Title                    = {{D}ata transfer and storage exploration for real-time implementation of a digital audio broadcast receiver on a {T}rimedia processor},
+  Author                   = {Miranda, M. and Ghez, C. and Brockmeyer, E. and Op De Beeck, P. and Catthoor, F. },
+  Booktitle                = {Proc. 15th Symposium on Integrated Circuits and Systems Design},
+  Year                     = {2002},
+  Month                    = sep,
+  Pages                    = {373--378},
+
+  Doi                      = {10.1109/SBCCI.2002.1137685},
+  Owner                    = {Kienle},
+  Timestamp                = {2010.01.13}
+}
+
+@Book{mis_10,
+  Title                    = {{T}he economics of money, banking, and financial markets},
+  Author                   = {Frederic S. Mishkin},
+  Publisher                = {Pearson},
+  Year                     = {2010},
+
+  Address                  = {Boston, MA, USA},
+  Edition                  = {{Business school ed., 2. ed., global ed.}},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.15}
+}
+
+@InProceedings{misbri_07,
+  Title                    = {{Cognitive Technology for Ultra-Wideband/WiMax Coexistence}},
+  Author                   = {Mishra, Shridhar Mubaraq and ten Brink, Stephan and Mahadevappa, Ravi and Brodersen, Robert W.},
+  Booktitle                = {New Frontiers in Dynamic Spectrum Access Networks, 2007. DySPAN 2007. 2nd IEEE International Symposium on},
+  Year                     = {2007},
+  Month                    = apr,
+  Pages                    = {179--186},
+
+  Doi                      = {10.1109/DYSPAN.2007.30},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{mit_10,
+  Title                    = {{E}nergy harvesting for human wearable and implantable bio-sensors},
+  Author                   = {P. D. {Mitcheson}},
+  Booktitle                = {2010 Annual International Conference of the IEEE Engineering in Medicine and Biology},
+  Year                     = {2010},
+  Month                    = {Aug},
+  Pages                    = {3432-3436},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {5627952},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/IEMBS.2010.5627952},
+  ISSN                     = {1094-687X},
+  Keywords                 = {TCS},
+  Keywords_original        = {biomedical electronics;body area networks;energy harvesting;power supplies to apparatus;thermoelectric devices;wireless sensor networks;human wearable wireless biosensors;human implantable wireless biosensors;biosensor functionality;biosensor battery lifetime;biosensor battery volume;harvester powered body sensor networks;inertial kinetic energy harvesting devices;thermoelectric devices;walking;running;power density;Generators;Thermal resistance;Energy harvesting;Kinetic energy;Humans;Immune system;Legged locomotion;Bioelectric Energy Sources;Biosensing Techniques;Computer-Aided Design;Electric Power Supplies;Energy Transfer;Equipment Design;Equipment Failure Analysis;Humans;Monitoring, Ambulatory;Prostheses and Implants},
+  Owner                    = {CCR}
+}
+
+@InProceedings{mit_08a,
+  Title                    = {{C}ircuit failure prediction for robust system design in scaled {CMOS}},
+  Author                   = {Mitra, S.},
+  Booktitle                = {Proc. IEEE International Reliability Physics Symposium IRPS 2008},
+  Year                     = {2008},
+  Month                    = apr,
+  Pages                    = {524--531},
+
+  Doi                      = {10.1109/RELPHY.2008.4558940},
+  File                     = {mit_08a.pdf:mit_08a.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.23}
+}
+
+@InProceedings{mit_08b,
+  Title                    = {{G}lobally {O}ptimized {R}obust {S}ystems to {O}vercome {S}caled {CMOS} {R}eliability {C}hallenges},
+  Author                   = {Mitra, S.},
+  Booktitle                = {Proc. Design, Automation and Test in Europe DATE '08},
+  Year                     = {2008},
+  Month                    = mar,
+  Pages                    = {941--946},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Mitra
+- Empfehlung Norbert, Basics},
+  Doi                      = {10.1109/DATE.2008.4484801},
+  File                     = {mit_08b.pdf:mit_08b.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm, May},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{mit_08c,
+  Title                    = {{C}ircuit {F}ailure {P}rediction for {R}obust {S}ystem {D}esign},
+  Author                   = {Mitra, Subhasish},
+  Booktitle                = {Proc. IEEE International Integrated Reliability Workshop Final Report IRW 2008},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {1--51},
+
+  Doi                      = {10.1109/IRWS.2008.4796145},
+  File                     = {mit_08c.pdf:mit_08c.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.23}
+}
+
+@InProceedings{mitaga_07,
+  Title                    = {{C}ircuit failure prediction to overcome scaled {CMOS} reliability challenges},
+  Author                   = {Mitra, S. and Agarwal, M. },
+  Booktitle                = {Proc. IEEE International Test Conference ITC 2007},
+  Year                     = {2007},
+  Month                    = oct,
+  Pages                    = {1--3},
+
+  Doi                      = {10.1109/TEST.2007.4437665},
+  File                     = {mitaga_07.pdf:mitaga_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.23}
+}
+
+@Article{mitbre_11,
+  Title                    = {{R}obust {S}ystem {D}esign to {O}vercome {CMOS} {R}eliability {C}hallenges},
+  Author                   = {Mitra, S. and Brelsford, K. and Young Moon Kim and Hsiao-Heng Kelin Lee and Yanjing Li},
+  Journal                  = {Emerging and Selected Topics in Circuits and Systems, IEEE Journal on},
+  Year                     = {2011},
+  Number                   = {1},
+  Pages                    = {30--41},
+  Volume                   = {1},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Mitra
+- Technology, ???},
+  Doi                      = {10.1109/JETCAS.2011.2135630},
+  File                     = {mitbre_11.pdf:mitbre_11.pdf:PDF},
+  Keywords                 = {reliability SPP},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{mitbre_10,
+  Title                    = {{C}ross-layer resilience challenges: {M}etrics and optimization},
+  Author                   = {Mitra, S. and Brelsford, K. and Sanda, P. N.},
+  Booktitle                = {Proc. Design, Automation \& Test in Europe Conf. \& Exhibition (DATE)},
+  Year                     = {2010},
+  Pages                    = {1029--1034},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Mitra, see mitbre_11},
+  File                     = {mitbre_10.pdf:mitbre_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{mitmcc_00,
+  Title                    = {{W}hich concurrent error detection scheme to choose ?},
+  Author                   = {Mitra, S. and McCluskey, E. J.},
+  Booktitle                = {Proc. Int. Test Conf},
+  Year                     = {2000},
+  Pages                    = {985--994},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Mitra},
+  Doi                      = {10.1109/TEST.2000.894311},
+  File                     = {mitmcc_00.pdf:mitmcc_00.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{mitsei_05,
+  Title                    = {{R}obust system design with built-in soft-error resilience},
+  Author                   = {Mitra, S. and Seifert, N. and Zhang, M. and Shi, Q. and Kim, K. S.},
+  Journal                  = {IEEE Computer},
+  Year                     = {2005},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {43--52},
+  Volume                   = {38},
+
+  Comment                  = {mitra latches, BISER},
+  Doi                      = {10.1109/MC.2005.70},
+  File                     = {mitsei_05.pdf:mitsei_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{mitzha_09,
+  Title                    = {{I}mperfection-immune {VLSI} logic circuits using {C}arbon {N}anotube {F}ield {E}ffect {T}ransistors},
+  Author                   = {Mitra, Subhasish and Zhang, Jie and Patil, Nishant and Hai Wei},
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conference \& Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {436--441},
+
+  File                     = {mitzha_09.pdf:mitzha_09.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.14}
+}
+
+@InProceedings{mitzha_07,
+  Title                    = {{B}uilt-{I}n {S}oft {E}rror {R}esilience for {R}obust {S}ystem {D}esign},
+  Author                   = {Mitra, S. and Ming Zhang and Seifert, N. and Mak, T. M. and Kee Sup Kim},
+  Booktitle                = {Proc. IEEE International Conference on Integrated Circuit Design and Technology ICICDT '07},
+  Year                     = {2007},
+  Month                    = may,
+  Pages                    = {1--6},
+
+  Doi                      = {10.1109/ICICDT.2007.4299587},
+  File                     = {mitzha_07.pdf:mitzha_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.14}
+}
+
+@InProceedings{mitzha_06,
+  Title                    = {{S}oft {E}rror {R}esilient {S}ystem {D}esign through {E}rror {C}orrection},
+  Author                   = {Subhasish Mitra and Ming Zhang and Seifert, N. and Mak, T. M. and Kee Sup Kim},
+  Booktitle                = {Proc. IFIP International Conference on Very Large Scale Integration},
+  Year                     = {2006},
+  Month                    = oct,
+  Pages                    = {332--337},
+
+  Doi                      = {10.1109/VLSISOC.2006.313256},
+  File                     = {mitzha_06.pdf:mitzha_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.14}
+}
+
+@Article{mitvet_14,
+  Title                    = {{A} {S}urvey of {M}ethods {F}or {A}nalyzing and {I}mproving {GPU} {E}nergy {E}fficiency},
+  Author                   = {Mittal, Sparsh and Vetter, Jeffrey S},
+  Journal                  = {arXiv preprint arXiv:1404.4629},
+  Year                     = {2014},
+
+  Month                    = apr,
+
+  Cds_grade                = {3},
+  Cds_keywords             = {GPU survey},
+  Cds_review               = {cites schshc_11},
+  File                     = {mitvet_14.pdf:mitvet_14.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.15}
+}
+
+@Electronic{mit_08,
+  Title                    = {{O}ptimization {S}oftware for {F}inancial {M}athematics},
+  Author                   = {Hans D Mittelmann},
+  HowPublished             = {\url{http://www.mathfinance.de/workshop/2008/papers/mittelmann/slides.pdf}},
+  Language                 = {en},
+  Month                    = mar,
+  Organization             = {Arizona State University},
+  Url                      = {http://www.mathfinance.de/workshop/2008/papers/mittelmann/slides.pdf},
+  Year                     = {2008},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {finance, calibration, optimization},
+  File                     = {mit_08.pdf:mit_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24}
+}
+
+@Book{mitupf_05,
+  Title                    = {{P}robability and {C}omputing},
+  Author                   = {Michael Mitzenmacher and Eli Upfal},
+  Publisher                = {Cambridge University Press},
+  Year                     = {2005},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-23}
+}
+
+@InProceedings{moegab_00,
+  Title                    = {{An Analog 0.25{$\mu$}m BiCMOS Tailbiting MAP Decoder}},
+  Author                   = {M. Moerz and T. Gabara and R. Yan and J. Hagenauer},
+  Booktitle                = {Proc. 2000 IEEE International Solid-State Circuits Conference (ISSCC)},
+  Year                     = {2000},
+
+  Address                  = {San Francisco, California, USA},
+  Month                    = feb,
+  Pages                    = {356--357},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mohtou_03,
+  Title                    = {{C}ost-effective approach for reducing soft error failure rate in logic circuits},
+  Author                   = {Mohanram, K. and Touba, N.A.},
+  Booktitle                = {Test Conference, 2003. Proceedings. ITC 2003. International},
+  Year                     = {2003},
+  Month                    = sep # {--} # oct,
+  Pages                    = {893--901},
+  Volume                   = {1},
+
+  File                     = {mohtou_03.pdf:mohtou_03.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@InProceedings{mohkar_09,
+  Title                    = {{S}ignificance {D}riven {C}omputation: a {V}oltage-{S}calable, {V}ariation-{A}ware, {Q}uality-{T}uning {M}otion {E}stimator},
+  Author                   = {Mohapatra, D. and Karakonstantis, G. and Roy, K.},
+  Booktitle                = {Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design},
+  Year                     = {2009},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {195--200},
+  Publisher                = {ACM},
+  Series                   = {ISLPED '09},
+
+  Acmid                    = {1594282},
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {http://doi.acm.org/10.1145/1594233.1594282},
+  File                     = {mohkar_09.pdf:mohkar_09.pdf:PDF},
+  ISBN                     = {978-1-60558-684-7},
+  Keywords                 = {Reliability, low power, motion estimation, significance driven computation, variation aware, voltage over-scaling},
+  Location                 = {San Fancisco, CA, USA},
+  Numpages                 = {6},
+  Url                      = {http://doi.acm.org/10.1145/1594233.1594282}
+}
+
+@InProceedings{mohcor_05,
+  Title                    = {{A} cross-layer approach for power-performance optimization in distributed mobile systems},
+  Author                   = {Shivajit Mohapatra and Cornea, R. and Oh, H. and Lee, K. and Kim, M. and Nikil Dutt and Rajesh Gupta and Nicolau, A. and Sandeep Shukla and Nalini Venkatasubramanian},
+  Booktitle                = {Proc. 19th IEEE Int. Parallel and Distributed Processing Symp},
+  Year                     = {2005},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- 
+- Video},
+  Doi                      = {10.1109/IPDPS.2005.13},
+  File                     = {mohcor_05.pdf:mohcor_05.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{moh_93,
+  Title                    = {{Decoding via Cross-entropy Minimization}},
+  Author                   = {M. Moher},
+  Booktitle                = {Proc. 1993 Global Telecommunications Conference (GLOBECOM '93)},
+  Year                     = {1993},
+
+  Address                  = {Houston, Texas},
+  Month                    = nov # {--} # dec,
+  Pages                    = {809--813},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mohtru_10,
+  Title                    = {{A} {L}ow-{C}omplexity {M}essage-{P}assing {A}lgorithm for {R}educed {R}outing {C}ongestion in {LDPC} {D}ecoders},
+  Author                   = {Tinoosh Mohsenin and Dean Truong and Bevan Baas},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2010},
+  Number                   = {5},
+  Pages                    = {1048--1061},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TCSI.2010.2046957},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.03.25},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5462985}
+}
+
+@InProceedings{mohtru_09,
+  Title                    = {{M}ulti-{S}plit-{R}ow {T}hreshold decoding implementations for {LDPC} codes},
+  Author                   = {Tinoosh Mohsenin and Dean Truong and Bevan Baas},
+  Booktitle                = {Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on},
+  Year                     = {2009},
+  Pages                    = {2449--2452},
+
+  Doi                      = {10.1109/ISCAS.2009.5118296},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.03.25},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5118296}
+}
+
+@Electronic{mol_12,
+  Title                    = {{N}umerical {C}omputing with {MATLAB}},
+  Author                   = {Cleve Moler},
+  HowPublished             = {\url{http://www.mathworks.de/moler}},
+  Language                 = {en},
+  Month                    = mar,
+  Note                     = {last access 2014-07-02},
+  Organization             = {Mathworks},
+  Url                      = {\url{http://www.mathworks.de/moler}},
+  Year                     = {2012},
+
+  Cds_keywords             = {random number generation, Ziggurat},
+  Cds_read                 = {2012-03-22},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@Electronic{Moler2012,
+  Title                    = {{N}umerical {C}omputing with {MATLAB}},
+  Author                   = {Cleve Moler},
+  HowPublished             = {\url{http://www.mathworks.de/moler/}},
+  Language                 = {en},
+  Month                    = mar,
+  Year                     = {2012},
+
+  Cds_keywords             = {random number generation, Ziggurat},
+  Cds_read                 = {2012-03-22},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@Article{molfoe_03,
+  Title                    = {{Channel Models for Ultrawideband Personal Area Networks}},
+  Author                   = {A. Molisch and J. Foerster and M. Pendergrass},
+  Journal                  = {IEEE WIreless Communications},
+  Year                     = {2003},
+
+  Month                    = dec,
+  Pages                    = {14--21},
+  Volume                   = {10},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{moneng_13,
+  Title                    = {{C}heckpointing for {V}irtual {P}latforms and {S}ystem{C}-{TLM}},
+  Author                   = {M. Monton and J. Engblom and M. Burton},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2013},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {133-141},
+  Volume                   = {21},
+
+  Doi                      = {10.1109/TVLSI.2011.2181881},
+  ISSN                     = {1063-8210},
+  Keywords                 = {checkpointing;formal verification;virtual machines;virtual prototyping;SystemC-TLM;virtual platform;SystemC transaction-level model;full-system simulation environment;Simics checkpoint mechanism;virtual prototyping;QEMU;Bridges;Kernel;Time domain analysis;Time varying systems;Synchronization;Checkpointing;Program processors;SystemC;system-level verification;transaction-level modeling;virtual prototyping},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-09}
+}
+
+@TechReport{moo_05a,
+  Title                    = {{T}he {H}eston {M}odel: {A} {P}ractical {A}pproach with {M}atlab {C}ode},
+  Author                   = {Nimalin Moodley},
+  Institution              = {University of the Witwatersrand, Johannesburg, South Africa,},
+  Year                     = {2005},
+
+  Abstract                 = {This document covers various aspects the Heston model. The structure
+and topics covered is as follows:
+Chapter 1 introduces the model and provides theoretical and graphical
+motivation for its robustness and hence popularity. It also discusses
+pricing using the Partial Differential Equation and Equivalent Martingale
+Measure techniques
+Chapter 2 discusses how the different components of the model can be
+evaluated computationally and how this can be achieved with different
+methods. These methods are then compared to each other.
+Chapter 3 addresses the calibration problem. Different methods are
+presented as well as practical implementation, results thereof, and comparisons.
+All the MATLAB code required to implement the model is provided in
+the appendix},
+  Cds_grade                = {0},
+  Cds_keywords             = {finance, Heston, calibr},
+  File                     = {moo_05a.pdf:moo_05a.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24},
+  Url                      = {\url{http://www.math.nyu.edu/~atm262/fall06/compmethods/a1/nimalinmoodley.pdf}}
+}
+
+@Book{moo_05,
+  Title                    = {{E}rror {C}orrection {C}oding: {M}athematical {M}ethods and {A}lgorithms},
+  Author                   = {Moon, Todd K.},
+  Publisher                = {Wiley-Interscience},
+  Year                     = {2005},
+
+  ISBN                     = {0471648000},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.02.23}
+}
+
+@Misc{Moondanos2008,
+  Title                    = {{S}ystem{C} {T}utorial},
+
+  Author                   = {John Moondanos},
+  Year                     = {2008},
+
+  Cds_grade                = {0},
+  Date-added               = {2008-10-29 17:54:25 +0100},
+  Date-modified            = {2008-10-29 17:55:45 +0100},
+  File                     = {moosystemc08.pdf:moosystemc08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Misc{moosystemc08,
+  Title                    = {{S}ystem{C} {T}utorial},
+
+  Author                   = {John Moondanos},
+  Year                     = {2008},
+
+  Cds_grade                = {0},
+  Date-added               = {2008-10-29 17:54:25 +0100},
+  Date-modified            = {2008-10-29 17:55:45 +0100},
+  File                     = {moosystemc08.pdf:moosystemc08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{Moore1975,
+  Title                    = {{P}rogress in digital integrated electronics},
+  Author                   = {Moore, G.E.},
+  Booktitle                = {International Electron Devices Meeting},
+  Year                     = {1975},
+  Pages                    = {11-13},
+  Volume                   = {21},
+
+  Keywords                 = {Cost function;Geometry;Integrated circuit interconnections;Integrated circuit technology;Logic arrays;Manufacturing processes;Microprocessors;Microstructure;Process design;System performance}
+}
+
+@Misc{moocontinuing,
+  Title                    = {{The continuing silicon technology evolution inside the PC platform}},
+
+  Author                   = {G. E. Moore},
+  HowPublished             = {{{http://developer.intel.com/update/archive/issue2/feature.htm}}},
+
+  Key                      = {moore},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Moore,
+  Title                    = {{The continuing silicon technology evolution inside the PC platform}},
+
+  Author                   = {G. E. Moore},
+  HowPublished             = {{{http://developer.intel.com/update/archive/issue2/feature.htm}}},
+
+  Key                      = {moore},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{moo_06,
+  Title                    = {{C}ramming more components onto integrated circuits, {R}eprinted from {E}lectronics, volume 38, number 8, {A}pril 19, 1965, pp.114 ff.},
+  Author                   = {Moore, Gordon E.},
+  Journal                  = {IEEE Solid-State Circuits Newsletter},
+  Year                     = {2006},
+  Number                   = {3},
+  Pages                    = {33--35},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/N-SSC.2006.4785860},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.03.26}
+}
+
+@Article{moo_65,
+  Title                    = {{C}ramming {M}ore {C}omponents {O}nto {I}ntegrated {C}ircuits},
+  Author                   = {Moore, Gordon Earle},
+  Journal                  = {Electronics},
+  Year                     = {1965},
+
+  Month                    = {April},
+  Pages                    = {114–117},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016.02.07}
+}
+
+@Article{Moore1965,
+  Title                    = {{Cramming More Components onto Integrated Circuits}},
+  Author                   = {Moore, G. E.},
+  Journal                  = {Electronics},
+  Year                     = {1965},
+
+  Month                    = apr,
+  Number                   = {8},
+  Pages                    = {114--117},
+  Volume                   = {38},
+
+  Abstract                 = {{First Page of the Article}},
+  Citeulike-article-id     = {814762},
+  Citeulike-linkout-0      = {http://dx.doi.org/10.1109/jproc.1998.658762},
+  Citeulike-linkout-1      = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=658762},
+  Day                      = {19},
+  Doi                      = {10.1109/jproc.1998.658762},
+  ISSN                     = {0018-9219},
+  Keywords                 = {engineeringindustry, fabrication},
+  Posted-at                = {2007-10-10 14:15:19},
+  Publisher                = {IEEE},
+  Url                      = {http://dx.doi.org/10.1109/jproc.1998.658762}
+}
+
+@InProceedings{morhor_14,
+  Title                    = {{E}nergy-efficient {FPGA} implementation for binomial option pricing using {O}pen{CL}},
+  Author                   = {V. M. Morales and P. H. Horrein and A. Baghdadi and E. Hochapfel and S. Vaton},
+  Booktitle                = {Proceedings of 2014 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
+  Year                     = {2014},
+  Month                    = {March},
+  Pages                    = {1-6},
+
+  Doi                      = {10.7873/DATE.2014.221},
+  Owner                    = {varela},
+  Timestamp                = {2016.05.19}
+}
+
+@Article{Morelli2007,
+  Title                    = {{M}aximum {L}ikelihood {T}iming and {C}arrier {S}ynchronization in {B}urst-{M}ode {S}atellite {T}ransmissions},
+  Author                   = {Morelli, Michele and D'Amico, Antonio A},
+  Journal                  = {EURASIP Journal on Wireless Communications and Networking},
+  Year                     = {2007},
+  Number                   = {1},
+  Pages                    = {065058},
+  Volume                   = {2007},
+
+  Doi                      = {10.1155/2007/65058},
+  ISSN                     = {1687-1499},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27},
+  Url                      = {http://jwcn.eurasipjournals.com/content/2007/1/065058}
+}
+
+@InCollection{Morelli1998,
+  Title                    = {{F}eedforward {E}stimation {T}echniques for {C}arrier {R}ecovery in 16-{QAM} {M}odulation},
+  Author                   = {Morelli, M. and D{’}Andrea, A.N. and Mengali, U.},
+  Booktitle                = {Broadband Wireless Communications},
+  Publisher                = {Springer London},
+  Year                     = {1998},
+  Editor                   = {Luise, Marco and Pupolin, Silvano},
+  Pages                    = {34-45},
+
+  Doi                      = {10.1007/978-1-4471-1570-0_4},
+  ISBN                     = {978-3-540-76237-9},
+  Language                 = {English},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.25},
+  Url                      = {http://dx.doi.org/10.1007/978-1-4471-1570-0_4}
+}
+
+@Article{mormen_98,
+  Title                    = {{F}eedforward {F}requency {E}stimation for {PSK}: {A} {T}utorial {R}eview},
+  Author                   = {Michele Morelli and Umberto Mengali},
+  Journal                  = {European Transactions on Telecommunications},
+  Year                     = {1998},
+  Number                   = {2},
+  Pages                    = {103-116},
+  Volume                   = {9},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Ee                       = {http://dx.doi.org/10.1002/ett.4460090203}
+}
+
+@TechReport{morreu_96,
+  Title                    = {{R}isk{M}etrics: {R}isk{M}etrics {T}echnical {D}ocument},
+  Author                   = {J. P. Morgan and Reuters},
+  Year                     = {1996},
+
+  Address                  = {New York},
+  Month                    = {Dec},
+  Number                   = {4th ed.},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.27}
+}
+
+@TechReport{mor_,
+  Title                    = {{U}niform and {E}xponential {R}andom {F}loating {P}oint {N}umber {G}eneration},
+  Author                   = {Thomas Morgenstern},
+  Institution              = {Hochschule Harz, Friedrichstr. 57-59, D-38855 Wernigerode},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation, floating point},
+  File                     = {mor_.pdf:mor_.pdf:PDF},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24},
+  Url                      = {\url{http://www.home.hs-karlsruhe.de/~moth0001/forschung/Uniform%20and%20Exponential%20Random%20Floating%20OR2007.pdf}}
+}
+
+@InProceedings{morohy_05,
+  Title                    = {{T}he origin of variable retention time in {DRAM}},
+  Author                   = {Y. Mori and K. Ohyu and K. Okonogi and R. i. Yamada},
+  Booktitle                = {IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.},
+  Year                     = {2005},
+  Month                    = {Dec},
+  Pages                    = {1034-1037},
+
+  Doi                      = {10.1109/IEDM.2005.1609541},
+  ISSN                     = {0163-1918},
+  Keywords                 = {DRAM chips;leakage currents;DRAM;VRT;junction leakage current;random telegraph signal;variable retention time;Circuit testing;Current measurement;Fluctuations;Laboratories;Leakage current;Random access memory;Subthreshold current;Telegraphy;Temperature dependence;Time measurement},
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-13}
+}
+
+@InProceedings{Morlet2000,
+  Title                    = {{A} carrier phase estimator for multimedia satellite payloads suited to {RSC} coding schemes},
+  Author                   = {Morlet, C. and Buret, I. and Boucheret, M.-L.},
+  Booktitle                = {Communications, 2000. ICC 2000. 2000 IEEE International Conference on},
+  Year                     = {2000},
+  Pages                    = {455-459 vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ICC.2000.853360},
+  Keywords                 = {convolutional codes;decoding;demodulators;multimedia communication;parameter estimation;phase estimation;quality of service;satellite communication;turbo codes;GEO satellite telecommunication systems;RSC coding schemes;TD estimation;TD estimator;Viterbi estimator;carrier phase estimator;carrier phase recovery;decision directed estimator;demodulation;frequency offset;high QoS performance;low SNR;low cost user terminals;multimedia access services;multimedia satellite payloads;nondata aided estimator;on-board demodulator;power-limited user terminals;recursive systematic convolutional codes;regenerative onboard processing;routing;satellite uplink;turbo codes;turbo decoding;Artificial satellites;Costs;Decoding;Demodulation;Frequency estimation;Multimedia systems;Payloads;Phase estimation;Routing;Turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.07}
+}
+
+@InProceedings{Morlet2000a,
+  Title                    = {{A} carrier phase estimator for multimedia satellite payloads suited to {RSC} coding schemes},
+  Author                   = {Morlet, C. and Buret, I. and Boucheret, M.-L.},
+  Booktitle                = {IEEE International Conference on Communications, 2000. (ICC 2000)},
+  Year                     = {2000},
+  Pages                    = {455-459 vol.1},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ICC.2000.853360},
+  Keywords                 = {convolutional codes;decoding;demodulators;multimedia communication;parameter estimation;phase estimation;quality of service;satellite communication;turbo codes;GEO satellite telecommunication systems;RSC coding schemes;TD estimation;TD estimator;Viterbi estimator;carrier phase estimator;carrier phase recovery;decision directed estimator;demodulation;frequency offset;high QoS performance;low SNR;low cost user terminals;multimedia access services;multimedia satellite payloads;nondata aided estimator;on-board demodulator;power-limited user terminals;recursive systematic convolutional codes;regenerative onboard processing;routing;satellite uplink;turbo codes;turbo decoding;Artificial satellites;Costs;Decoding;Demodulation;Frequency estimation;Multimedia systems;Payloads;Phase estimation;Routing;Turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.23}
+}
+
+@Article{mor_95,
+  Title                    = {{T}he full {M}onte},
+  Author                   = {Boris Moro},
+  Journal                  = {Risk Magazine},
+  Year                     = {1995},
+
+  Month                    = {February},
+  Pages                    = {57-58},
+  Volume                   = {8(2)},
+
+  Owner                    = {Schmidt},
+  Timestamp                = {2010.08.03}
+}
+
+@InProceedings{moraub_07,
+  Title                    = {{D}esign {S}pace {E}xploration of the {E}uropean {O}ption {B}enchmark using {H}yperstreams},
+  Author                   = {Gareth W. Morris and Matt Aubury},
+  Booktitle                = {Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on},
+  Year                     = {2007},
+
+  Address                  = {Amsterdam, Netherlands},
+  Month                    = aug,
+  Pages                    = {5 -10},
+
+  Abstract                 = {The benchmark of pricing a European option via Monte Carlo simulation is commonly used in financial engineering for evaluating the performance of new computational techniques and to tune the parameters of the Monte Carlo simulation for improved convergence. This paper presents a comparison of different FPGA implementations of the European option benchmark against other implementations using GPUs, Cell BE, and a traditional software implementation. Error against a closed form solution is contrasted with relative acceleration for the different implementations. The FPGA approach gives significant performance advantages compared to the alternatives examined. An acceleration of x compared to a reference software implementation can be obtained using FPGAs, compared to only x in the case of the best non-FPGA alternative. Better error performance than a double precision floating point software implementation may also be obtained. In addition, the reconfigurability of an FPGA solution allows tradeoffs between acceleration and error not possible with alternative approaches. The FPGA implementations were produced using 'HyperStreams', a high level abstraction for designing arithmetic pipelines built on the Handel-C programming language.},
+  Cds_grade                = {0},
+  Cds_keywords             = {finance, benchmark},
+  Doi                      = {10.1109/FPL.2007.4380617},
+  File                     = {moraub_07.pdf:moraub_07.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-04-22}
+}
+
+@Misc{morsoftware15,
+  Title                    = {{S}oftware {D}efines {E}verything. {X}ilinx {A}nnounces {SDS}o{C}},
+
+  Author                   = {Kevin Morris},
+  HowPublished             = {Electronic Engineering Journal, \url{http://www.eejournal.com/archives/articles/20150317-sdsoc/}},
+  Month                    = mar,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{morfpgas14,
+  Title                    = {{FPGA}s {C}ool {O}ff the {D}atacenter. {X}ilinx {H}eats {U}p the {R}ace},
+
+  Author                   = {Kevin Morris},
+  HowPublished             = {Electronic Engineering Journal, \url{http://www.eejournal.com/archives/articles/20141118-datacenter}},
+  Month                    = nov,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2014},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Misc{morintel15,
+  Title                    = {{I}ntel {P}lus {A}ltera. {W}hat {W}ould it {M}ean?},
+
+  Author                   = {Kevin Morris and Bruce Kleinman},
+  HowPublished             = {Electronic Engineering Journal, \url{http://eejournal.com/archives/articles/20150331-intel/}},
+  Month                    = mar,
+  Note                     = {last access 2015-10-13},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Article{mosani_10,
+  Title                    = {{A} {D}esign-{O}riented {S}oft {E}rror {R}ate {V}ariation {M}odel {A}ccounting for {B}oth {D}ie-to-{D}ie and {W}ithin-{D}ie {V}ariations in {S}ubmicrometer {CMOS} {SRAM} {C}ells},
+  Author                   = {Mostafa, H. and Anis, M. and Elmasry, M. },
+  Journal                  = {Circuits and Systems I: Regular Papers, IEEE Transactions on},
+  Year                     = {2010},
+  Number                   = {6},
+  Pages                    = {1298--1311},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TCSI.2009.2033528},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{mosani_09,
+  Title                    = {{C}omparative analysis of process variation impact on flip-flops soft error rate},
+  Author                   = {Mostafa, H. and Anis, M. and Elmasry, M. },
+  Booktitle                = {Proc. 1st Asia Symp. Quality Electronic Design ASQED 2009},
+  Year                     = {2009},
+  Pages                    = {103--108},
+
+  Doi                      = {10.1109/ASQED.2009.5206288},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{mosani_11,
+  Title                    = {{A}nalytical {S}oft {E}rror {M}odels {A}ccounting for {D}ie-to-{D}ie and {W}ithin-{D}ie {V}ariations in {S}ub-{T}hreshold {SRAM} {C}ells},
+  Author                   = {Mostafa, H. and Anis, M. H. and Elmasry, M. },
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2011},
+  Number                   = {2},
+  Pages                    = {182--195},
+  Volume                   = {19},
+
+  Doi                      = {10.1109/TVLSI.2009.2033697},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{Motedayen-Aval2003,
+  Title                    = {{P}olynomial-complexity noncoherent symbol-by-symbol detection with application to adaptive iterative decoding of turbo-like codes},
+  Author                   = {Motedayen-Aval, I. and Anastasopoulos, A.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2003},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {197-207},
+  Volume                   = {51},
+
+  Doi                      = {10.1109/TCOMM.2003.809286},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Gaussian noise;adaptive decoding;computational complexity;concatenated codes;convolutional codes;iterative decoding;parity check codes;phase estimation;signal detection;turbo codes;GLRT-based sequence detection;Gaussian noise;LDPC codes;QAM;adaptive iterative decoding;channel parameters;exponential complexity;generalized-likelihood ratio test;hardware implementation;iterative decoding;iterative detection;low-density parity-check codes;parallel concatenated convolutional codes;phase estimation;polynomial-complexity noncoherent detection;quadrature amplitude modulated;sequence length;serially concatenated convolutional codes;symbol-by-symbol detection;symbol-by-symbol soft decision metrics;time-varying carrier-phase offset;turbo-like codes;ultra-fast approximate algorithm;uncoded data sequence detection;Concatenated codes;Convolutional codes;Gaussian noise;Hardware;Iterative algorithms;Iterative decoding;Parity check codes;Phase estimation;Polynomials;Turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.23}
+}
+
+@Article{moulu_04,
+  Title                    = {{Structured Low-Density Parity-Check Codes}},
+  Author                   = {Moura, J.M.F. and J. Lu and H. Zhang},
+  Journal                  = {IEEE Signal Processing Magazine},
+  Year                     = {2004},
+
+  Month                    = jan,
+  Pages                    = {42--55},
+  Volume                   = {21},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{moubag_08,
+  Title                    = {{B}inary de {B}ruijn interconnection network for a flexible {LDPC}/turbo decoder},
+  Author                   = {Moussa, H. and Baghdadi, A. and J\'{e}z\'{e}quel, M.},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2008},
+  Year                     = {2008},
+  Month                    = may,
+  Pages                    = {97--100},
+
+  Doi                      = {10.1109/ISCAS.2008.4541363},
+  File                     = {moubag_08.pdf:moubag_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.08.03}
+}
+
+@InProceedings{moubag_08a,
+  Title                    = {{B}inary de {B}ruijn on-chip network for a flexible multiprocessor {LDPC} decoder},
+  Author                   = {Moussa, H. and Baghdadi, A. and J\'{e}z\'{e}quel, M.},
+  Booktitle                = {Proc. 45th ACM/IEEE Design Automation Conference DAC 2008},
+  Year                     = {2008},
+  Month                    = jun,
+  Pages                    = {429--434},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.08.03}
+}
+
+@InProceedings{moumul_07,
+  Title                    = {{B}utterfly and {B}enes-{B}ased on-{C}hip {C}ommunication {N}etworks for {M}ultiprocessor {T}urbo {D}ecoding},
+  Author                   = {Moussa, H. and Muller, O. and Baghdadi, A. and J\'{e}z\'{e}quel, M.},
+  Booktitle                = {Proc. Design, Automation \& Test in Europe Conference \& Exhibition DATE '07},
+  Year                     = {2007},
+  Month                    = apr,
+  Pages                    = {1--6},
+
+  Doi                      = {10.1109/DATE.2007.364668},
+  File                     = {moumul_07.pdf:moumul_07.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{Mueller2007,
+  Title                    = {{B}uilding a table tennis game for three players},
+  Author                   = {Florian Mueller and Martin R. Gibbs},
+  Booktitle                = {ACE '07: Proceedings of the international conference on Advances in computer entertainment technology},
+  Year                     = {2007},
+  Pages                    = {179-182},
+  Publisher                = {ACM New York, NY, USA},
+
+  Abstract                 = {Physical leisure activities such as table tennis provide healthy exercise and can offer a means to connect with others socially; however, players have to be in the same physical location to play. Networked computer games support players in geographically distant locations, but their communication channel is often limited to text or audio only. Furthermore, recent input devices that encourage exertion often do not support adequate force-feedback. We have developed a networked table tennis-like game that is played with a real paddle and ball, augmented with a large-scale videoconference. Similar to networked computer games, this concept can support more than two locations, while simultaneously aiming to provide similar benefits known from traditional physical leisure activity such as exercise, enjoyment and bringing people together to socialize.},
+  Keywords                 = {Seismography, WSN},
+  Owner                    = {Sebastian Wille},
+  Timestamp                = {2011.07.28}
+}
+
+@Booklet{mue_07,
+  Title                    = {{E}rror {C}orrection {C}odes},
+  Author                   = {Stefan Mueller},
+  Year                     = {2007},
+
+  Annote                   = {internes Paper, nicht zitieren!},
+  Cds_grade                = {5},
+  Cds_keywords             = {BCH, RS, Reed-Solomon codes, Galois Fields, Syndrome, Key Equation, Chien Search, forward error correction},
+  Cds_read                 = {2008-09},
+  Cds_review               = {high-speed key equation solver circuit for BCH codes},
+  Comment                  = {for internal use only, not citeable},
+  Date-added               = {2008-07-25 14:13:59 +0200},
+  Date-modified            = {2008-07-25 14:16:21 +0200},
+  File                     = {mue_07.pdf:mue_07.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{muhhol_06,
+  Title                    = {{A}ccelerating {RTL} {S}imulation by {S}everal {O}rders of {M}agnitude {U}sing {C}lock {S}uppression},
+  Author                   = {H. {Muhr} and R. {Holler}},
+  Booktitle                = {2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation},
+  Year                     = {2006},
+  Month                    = {July},
+  Pages                    = {123-128},
+
+  Doi                      = {10.1109/ICSAMOS.2006.300818},
+  Keywords                 = {embedded systems;formal verification;hardware description languages;hardware-software codesign;RTL simulation;clock suppression;embedded computer system design;event based simulation engine;register transfer level;functional verification;Acceleration;Clocks;Computational modeling;Discrete event simulation;Embedded computing;Frequency;Real time systems;Embedded system;Engines;Computer simulation},
+  Owner                    = {MJ},
+  Timestamp                = {2019-08-08}
+}
+
+@InProceedings{mukeme_05,
+  Title                    = {{T}he {S}oft {E}rror {P}roblem: {A}n {A}rchitectural {P}erspective},
+  Author                   = {Shubhendu S. Mukherjee and Joel Emer and Steven K. Reinhardt},
+  Booktitle                = {HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture},
+  Year                     = {2005},
+  Pages                    = {243--247},
+  Publisher                = {IEEE Computer Society},
+
+  File                     = {mukeme_05.pdf:mukeme_05.pdf:PDF;mukeme_05_slides.ppt:mukeme_05_slides.ppt:PowerPoint},
+  ISBN                     = {0-7695-2275-0},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mukhun_13,
+  Title                    = {{U}nderstanding and {M}itigating {R}efresh {O}verheads in {H}igh-density {DDR}4 {DRAM} {S}ystems},
+  Author                   = {Mukundan, Janani and Hunter, Hillery and Kim, Kyu-hyoun and Stuecheli, Jeffrey and Mart\'{\i}nez, Jos{\'e} F.},
+  Booktitle                = {Proceedings of the 40th Annual International Symposium on Computer Architecture},
+  Year                     = {2013},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {48--59},
+  Publisher                = {ACM},
+  Series                   = {ISCA '13},
+
+  Acmid                    = {2485927},
+  Doi                      = {10.1145/2485922.2485927},
+  ISBN                     = {978-1-4503-2079-5},
+  Location                 = {Tel-Aviv, Israel},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.13},
+  Url                      = {http://doi.acm.org/10.1145/2485922.2485927}
+}
+
+@Article{mulbag_09,
+  Title                    = {{F}rom {P}arallelism {L}evels to a {M}ulti-{ASIP} {A}rchitecture for {T}urbo {D}ecoding},
+  Author                   = {Muller, O. and Baghdadi, A. and J\'{e}z\'{e}quel, M.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2009},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {92--102},
+  Volume                   = {17},
+
+  Doi                      = {10.1109/TVLSI.2008.2003164},
+  File                     = {mulbag_09.pdf:mulbag_09.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.08.31}
+}
+
+@Article{mulbag_08,
+  Title                    = {{F}rom {A}pplication to {ASIP}-based {FPGA} {P}rototype: a {C}ase {S}tudy on {T}urbo {D}ecoding},
+  Author                   = {Olivier Muller and Amer Baghdadi and Michel J\'{e}z\'{e}quel},
+  Journal                  = {IEEE International Workshop on Rapid System Prototyping},
+  Year                     = {2008},
+
+  Month                    = jun,
+  Pages                    = {128-134},
+
+  Address                  = {Los Alamitos, CA, USA},
+  Cds_grade                = {0},
+  Doi                      = {http://doi.ieeecomputersociety.org/10.1109/RSP.2008.16},
+  File                     = {mulbag_08.pdf:mulbag_08.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Publisher                = {IEEE Computer Society},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mulbag_06,
+  Title                    = {{ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding}},
+  Author                   = {O. Muller and A. Baghdadi and M. J\'{e}z\'{e}quel},
+  Booktitle                = {Proc. 2006 Design, Automation and Test in Europe (DATE '06)},
+  Year                     = {2006},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+
+  File                     = {mulbag_06.pdf:mulbag_06.pdf:PDF;mulbag_06c.pdf:mulbag_06c.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mulbag_06a,
+  Title                    = {{On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference}},
+  Author                   = {Olivier Muller and Amer Baghdadi and Michel J\'{e}z\'{e}quel},
+  Booktitle                = {Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE},
+  Year                     = {2006},
+  Month                    = nov,
+
+  Doi                      = {10.1109/GLOCOM.2006.558},
+  File                     = {mulbag_06a.pdf:mulbag_06a.pdf:PDF},
+  Keywords                 = {Turbo shuffled decoding},
+  Owner                    = {alles},
+  Timestamp                = {2008.02.11}
+}
+
+@InProceedings{mulbag_06b,
+  Title                    = {{E}xploring {P}arallel {P}rocessing {L}evels for {C}onvolutional {T}urbo {D}ecoding},
+  Author                   = {Muller, O. and Baghdadi, A. and J\'{e}z\'{e}quel, M.},
+  Booktitle                = {Proc. 2nd Information and Communication Technologies ICTTA '06},
+  Year                     = {2006},
+  Pages                    = {2353--2358},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/ICTTA.2006.1684774},
+  File                     = {mulbag_06b.pdf:mulbag_06b.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InProceedings{mulsch_09,
+  Title                    = {{A} novel {LDPC} decoder for {DVB}-{S}2 {IP}},
+  Author                   = {Müller, S. and Schreger, M. and Kabutz, M. and Alles, M. and Kienle, F. and Wehn, N.},
+  Booktitle                = {Proc. DATE '09. Design, Automation. Test in Europe Conference. Exhibition},
+  Year                     = {2009},
+  Month                    = apr,
+  Pages                    = {1308--1313},
+
+  File                     = {mulsch_09.pdf:mulsch_09.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InCollection{muelrit_09,
+  Title                    = {{V}ariable {S}ubspace {S}ampling and {M}ulti-level {A}lgorithms},
+  Author                   = {Müller-Gronbach, Thomas and Ritter, Klaus},
+  Booktitle                = {Monte Carlo and Quasi-Monte Carlo Methods 2008},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2009},
+  Editor                   = {L' Ecuyer, Pierre and Owen, Art B.},
+  Pages                    = {131-156},
+
+  Doi                      = {10.1007/978-3-642-04107-5_8},
+  ISBN                     = {978-3-642-04106-8},
+  Language                 = {English},
+  Owner                    = {Brugger},
+  Timestamp                = {2013.11.05}
+}
+
+@Book{muelack_95,
+  Title                    = {{O}ptionen und {F}utures--{G}rundlagen und {S}trategien für das {T}ermingeschäft in der {S}chweiz, {D}eutschland und {Ö}sterreich},
+  Author                   = {Müller-Möhl, Ernst and Ackermann, Carole and Krebs, Jürgen and Künzle, Marcel},
+  Year                     = {1995},
+  Edition                  = {3rd},
+
+  Journal                  = {Auflage, Stuttgart},
+  Owner                    = {CdS},
+  Timestamp                = {2014.05.21}
+}
+
+@Misc{mulintel16,
+  Title                    = {{I}ntel® {X}eon® {P}rocessor {E}5-2600 {V}4 {P}roduct {F}amily {T}echnical {O}verview},
+
+  Author                   = {David Mulnix},
+  HowPublished             = {Online: \url{https://software.intel.com/en-us/articles/intel-xeon-processor-e5-2600-v4-product-family-technical-overview}},
+  Month                    = {Apr.},
+  Note                     = {Last access: 15 Dec. 2017},
+  Year                     = {2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.15},
+  Url                      = {https://software.intel.com/en-us/articles/intel-xeon-processor-e5-2600-v4-product-family-technical-overview}
+}
+
+@PhdThesis{Phdmuench99,
+  Title                    = {{S}ynthesis and {O}ptimization of {A}lgorithmic {H}ardware {D}escriptions},
+  Author                   = {Michael Münch},
+  School                   = {University of Kaiserslautern},
+  Year                     = {1999},
+  Note                     = {ISBN 3-925178-29-5},
+
+  Owner                    = {CdS},
+  Timestamp                = {2010.02.10}
+}
+
+@InProceedings{mweh_98,
+  Title                    = {{Architectural Optimization of a Pipelined Signal Processing Unit: A Case Study}},
+  Author                   = {M. Münch and N. Wehn and F. Gilbert and U. Wasenmüller},
+  Booktitle                = {Proceedings of the 1st International Workshop on Design, Test and Applications},
+  Year                     = {1998},
+
+  Address                  = {Dubrovnik, Croatia},
+  Month                    = jun,
+  Pages                    = {29-33},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{mweh_97,
+  Title                    = {{An Efficient ILP-Based Scheduling Algorithm forControl-Dominated VHDL Descriptions}},
+  Author                   = {M. Münch and N. Wehn and M. Glesner},
+  Journal                  = {ACM Transactions on Design Automation of ElectronicSystems},
+  Year                     = {1997},
+
+  Month                    = oct,
+  Number                   = {4},
+  Pages                    = {344--364},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mweh_96,
+  Title                    = {{An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions}},
+  Author                   = {M. Münch and N. Wehn and M. Glesner},
+  Booktitle                = {Proc. th International Symposium on System Synthesis},
+  Year                     = {1996},
+  Month                    = nov,
+  Pages                    = {45--50},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mweh_95,
+  Title                    = {{Optimum Simultaneous Placement and Binding forBit-Slice Architectures}},
+  Author                   = {M. Münch and N. Wehn and M. Glesner},
+  Booktitle                = {Proc. ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration. Asian and South Pacific Design Automation Conference},
+  Year                     = {1995},
+  Month                    = aug,
+  Pages                    = {735--740},
+  Publisher                = {IEEE Press},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mweh_94,
+  Title                    = {{ Optimizing Control Flow in Behavioral VHDL}},
+  Author                   = {Münch, M. and Wehn, N. and Langmaier, A.},
+  Booktitle                = {Proceedings of the IFIP Workshop on Logic and Architecture Synthesis},
+  Year                     = {1994},
+
+  Address                  = {Grenoble},
+  Month                    = dec,
+  Pages                    = {173--182},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mwur_00,
+  Title                    = {{Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths}},
+  Author                   = {M. Münch and B. Wurth and R. Mehra and J. Sproch and N. Wehn},
+  Booktitle                = {Proc. Design Automation and Test in Europe Conference and Exhibition 2000},
+  Year                     = {2000},
+
+  Address                  = {Paris, France},
+  Month                    = mar,
+  Pages                    = {624--631},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{munayg_11,
+  Title                    = {{ACOTES} {P}roject: {A}dvanced {C}ompiler {T}echnologies for {E}mbedded {S}treaming},
+  Author                   = {Munk, Harm and Ayguadé, Eduard and Bastoul, Cédric and Carpenter, Paul and Chamski, Zbigniew and Cohen, Albert and Cornero, Marco and Dumont, Philippe and Duranton, Marc and Fellahi, Mohammed and Ferrer, Roger and Ladelsky, Razya and Lindwer, Menno and Martorell, Xavier and Miranda, Cupertino and Nuzman, Dorit and Ornstein, Andrea and Pop, Antoniu and Pop, Sebastian and Pouchet, Louis-Noël and Ramírez, Alex and Ródenas, David and Rohou, Erven and Rosen, Ira and Shvadron, Uzi and Trifunović, Konrad and Zaks, Ayal},
+  Journal                  = {International Journal of Parallel Programming},
+  Year                     = {2011},
+  Number                   = {3},
+  Pages                    = {397-450},
+  Volume                   = {39},
+
+  Doi                      = {10.1007/s10766-010-0132-7},
+  ISSN                     = {0885-7458},
+  Keywords                 = {Parallel architectures; Compilers; Streaming applications; Automatic Parallelisation; HiPEAC},
+  Language                 = {English},
+  Owner                    = {Brugger},
+  Publisher                = {Springer US},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://dx.doi.org/10.1007/s10766-010-0132-7}
+}
+
+@InProceedings{murbro_10,
+  Title                    = {{CUDA} {I}mplementation of {B}arrier {O}ption {V}aluation with {J}ump-{D}iffusion {P}rocess and {B}rownian {B}ridge},
+  Author                   = {Dariusz Murakowski and William Brouwer and Vincent Natoli},
+  Booktitle                = {Proceedings of the 2010 IEEE Workshop on High Performance Computational Finance (WHPCF)},
+  Year                     = {2010},
+  Pages                    = {1-4},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.03.25}
+}
+
+@Article{murthe_05,
+  Title                    = {{Analysis of Error Recovery Schemes for Networks on Chips}},
+  Author                   = {Srinivasan Murali and Theocharis Theocharides and N. Vijaykrishnan and Mary Jane Irwin and Luca Benini and De Micheli, Giovanni},
+  Journal                  = {IEEE Design and Test of Computers},
+  Year                     = {2005},
+  Number                   = {5},
+  Pages                    = {434--442},
+  Volume                   = {22},
+
+  File                     = {murthe_05.pdf:murthe_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{mursub_11,
+  Title                    = {{R}educing {M}emory {I}nterference in {M}ulticore {S}ystems via {A}pplication-aware {M}emory {C}hannel {P}artitioning},
+  Author                   = {Muralidhara, Sai Prashanth and Subramanian, Lavanya and Mutlu, Onur and Kandemir, Mahmut and Moscibroda, Thomas},
+  Booktitle                = {Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture},
+  Year                     = {2011},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {374--385},
+  Publisher                = {ACM},
+  Series                   = {MICRO-44},
+
+  Acmid                    = {2155664},
+  Doi                      = {10.1145/2155620.2155664},
+  ISBN                     = {978-1-4503-1053-6},
+  Keywords                 = {data allocation, interference, main memory, memory controllers, memory scheduling, multicore},
+  Location                 = {Porto Alegre, Brazil},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-02},
+  Url                      = {http://doi.acm.org/10.1145/2155620.2155664}
+}
+
+@Article{mur_89,
+  Title                    = {{P}etri nets: {P}roperties, analysis and applications},
+  Author                   = {T. Murata},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {1989},
+
+  Month                    = {Apr},
+  Number                   = {4},
+  Pages                    = {541-580},
+  Volume                   = {77},
+
+  Doi                      = {10.1109/5.24143},
+  ISSN                     = {0018-9219},
+  Keywords                 = {Petri nets;logic programming;stochastic processes;Petri nets;behavioural properties;concurrent system model;high-level nets;logic programming;marked graphs;performance modeling;reachability criteria;stochastic nets;structural properties;subclasses;Books;Equations;History;Information processing;Logic programming;Mathematical model;Petri nets;Power system modeling;Stochastic processes;Stochastic systems},
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-04}
+}
+
+@PhdThesis{Phdmurga06,
+  Title                    = {{High-Level Optimazation of Performance and Power in Very Deep Sub-Micron Interconnects}},
+  Author                   = {T. Murgan},
+  School                   = {Fachbereich Elektrotechnik und Informationstechnik, Technische Universität Darmstadt},
+  Year                     = {2006},
+
+  File                     = {Phdmurga06.pdf:Phdmurga06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.08.01}
+}
+
+@InProceedings{mural-_11,
+  Title                    = {{A} flexible high throughput multi-{ASIP} architecture for {LDPC} and turbo decoding},
+  Author                   = {Murugappa, P. and Al-Khayat, R. and Baghdadi, A. and Jezequel, M.},
+  Booktitle                = {Proc. Design, Automation \& Test in Europe Conf. \& Exhibition (DATE)},
+  Year                     = {2011},
+  Pages                    = {1--6},
+
+  File                     = {mural-_11.pdf:mural-_11.pdf:PDF},
+  Keywords                 = {ASIP LDPC Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{murbaz_12,
+  Title                    = {{FPGA} prototyping and performance evaluation of multi-standard {T}urbo/{LDPC} {E}ncoding and {D}ecoding},
+  Author                   = {Murugappa, P. and Bazin, J. and Baghdadi, A. and Jezequel, M.},
+  Booktitle                = {Rapid System Prototyping (RSP), 2012 23rd IEEE International Symposium on},
+  Year                     = {2012},
+  Month                    = {oct.},
+  Pages                    = {143 -148},
+
+  Doi                      = {10.1109/RSP.2012.6380703},
+  ISSN                     = {2150-5500},
+  Keywords                 = {Decoding;Encoding;Field programmable gate arrays;Graphical user interfaces;Paritycheck codes;Prototypes;Standards;application specific integrated circuits;digitalcommunication;elemental semiconductors;encoding;field programmable gate arrays;graphicaluser interfaces;instruction sets;iterative decoding;microprocessor chips;parity checkcodes;silicon;turbo codes;ASIP-based decoder;DVB-RCS wireless communicationstandards;FPGA prototyping;FPGA-based prototype;GUI;LDPC iterativedecoders;LTE;Si;Turbo;WiFi;WiMAX;application-specific instruction-set processor;channeldecoding;field programmable gate arrays;flexible multistandard implementations;graphicaluser interface;hardware prototyping;hardware simulation matches;multistandard turbo/LDPCEncoding and Decoding;performance evaluation;resource sharing;software model;systemvalidation;}
+}
+
+@InProceedings{mut_17,
+  Title                    = {{T}he {R}ow{H}ammer problem and other issues we may face as memory becomes denser},
+  Author                   = {O. {Mutlu}},
+  Booktitle                = {Design, Automation Test in Europe Conference Exhibition (DATE), 2017},
+  Year                     = {2017},
+  Month                    = {March},
+  Pages                    = {1116-1121},
+
+  Doi                      = {10.23919/DATE.2017.7927156},
+  ISSN                     = {1558-1101},
+  Keywords                 = {DRAM chips;failure analysis;integrated circuit reliability;RowHammer Problem;malicious attack;system security;circuit-level failure mechanism;system security vulnerability;hardware failure mechanism;DRAM disturbance errors;circuit-level cell- to-cell interference;scaled memory technology;Google Project Zero;user-level programs;virtual machine;mobile device;malicious user-level application;memory reliability;memory security;Security;Failure analysis;Reliability;DRAM chips;Error correction codes;Virtual machining},
+  Owner                    = {MJ},
+  Timestamp                = {2019-06-24}
+}
+
+@InProceedings{mutmos_08,
+  Title                    = {{P}arallelism-{A}ware {B}atch-{S}cheduling: {E}nhancing both {P}erformance and {F}airness of
+ {S}hared {DRAM} {S}ystems},
+  Author                   = {Onur Mutlu and Thomas Moscibroda},
+  Booktitle                = {35th International Symposium on Computer Architecture (ISCA)},
+  Year                     = {2008},
+  Month                    = {June},
+  Publisher                = {Association for Computing Machinery, Inc.},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20},
+  Url                      = {http://research.microsoft.com/apps/pubs/default.aspx?id=79626}
+}
+
+@Article{mylcav_11,
+  Title                    = {{A}rchitecture {D}esign and {I}mplementation of the {M}etric {F}irst {L}ist {S}phere {D}etector {A}lgorithm},
+  Author                   = {Myllyla, M. and Cavallaro, J. R. and Juntti, M.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2011},
+  Number                   = {5},
+  Pages                    = {895--899},
+  Volume                   = {19},
+
+  Doi                      = {10.1109/TVLSI.2010.2041800},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@Article{myopar_07,
+  Title                    = {{SIMD} {P}rocessor-{B}ased {T}urbo {D}ecoder {S}upporting {M}ultiple {T}hird-{G}eneration {W}ireless {S}tandards},
+  Author                   = {Myoung-Cheol and In-Cheol Park},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2007},
+  Number                   = {7},
+  Pages                    = {801--810},
+  Volume                   = {15},
+
+  Cb_grade                 = {- ungelesen
+- ASIP
+- Empfehlung von Timo
+- Journal^},
+  Doi                      = {10.1109/TVLSI.2007.899237},
+  File                     = {myopar_07.pdf:myopar_07.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.24}
+}
+
+@InProceedings{myt_16,
+  Title                    = {{P}rogramming {U}ncertain {T}hings},
+  Author                   = {Mytkowicz, T.},
+  Booktitle                = {ACM/IEEE Design Automation Conference (DAC), (Presentation Only)},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-05}
+}
+
+@Article{myuyan_05,
+  Title                    = {{Quasi-Cyclic LDPC Codes for Fast Encoding}},
+  Author                   = {Seho Myung and Kyeongcheol Yang and Jaeyoel Kim},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2005},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {2894--2901},
+  Volume                   = {51},
+
+  File                     = {myuyan_05.pdf:myuyan_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{SPP150011,
+  Title                    = {{Proposol for the Priority Programme 1500 ``Design and Architectures of Dependale Embedded Systems -- A Grand Challenge in the Nano Age''}},
+
+  Author                   = {{N. Wehn}},
+  Year                     = {2010},
+
+  Organization             = {{University of Kaiserslautern}},
+  Type                     = {{DFG Proposal}}
+}
+
+@Misc{Wehn2010,
+  Title                    = {{Proposol for the Priority Programme 1500 ``Design and Architectures of Dependale Embedded Systems -- A Grand Challenge in the Nano Age''}},
+
+  Author                   = {{N. Wehn}},
+  Year                     = {2010},
+
+  Organization             = {{University of Kaiserslautern}},
+  Owner                    = {scholl},
+  Timestamp                = {2015.06.11},
+  Type                     = {{DFG Proposal}}
+}
+
+@Article{tagsie_08,
+  Title                    = {{A}daptive {M}ethods for {L}inear {P}rogramming {D}ecoding},
+  Author                   = {M. H. Taghavi N. and P. H. Siegel},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2008},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {5396-5410},
+  Volume                   = {54},
+
+  Doi                      = {10.1109/TIT.2008.2006384},
+  ISSN                     = {0018-9448},
+  Keywords                 = {adaptive decoding;linear programming;matrix algebra;parity check codes;adaptive LP decoding;adaptive methods;linear programming decoding;parity-check matrix;redundant parity checks;Degradation;Iterative algorithms;Iterative decoding;Iterative methods;Linear programming;Magnetic recording;Maximum likelihood decoding;Message passing;Parity check codes;Performance gain;Cutting planes;LP decoding;linear programming (LP);low-density parity-check (LDPC) codes;maximum-likelihood (ML) decoding;message passing;pseudocodewords}
+}
+
+@InProceedings{naebou_08,
+  Title                    = {{A} unified instruction set programmable architecture for multi-standard advanced forward error correction},
+  Author                   = {Naessens, F. and Bougard, B. and Bressinck, S. and Hollevoet, L. and Raghavan, P. and Van der Perre, L. and Catthoor, F.},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems SiPS 2008},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {31--36},
+
+  Doi                      = {10.1109/SIPS.2008.4671733},
+  File                     = {naebou_08.pdf:naebou_08.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.12}
+}
+
+@InProceedings{naeder_10,
+  Title                    = {{A} 10.37 mm2 675 m{W} reconfigurable {LDPC} and {T}urbo encoder and decoder for 802.11n, 802.16e and 3{GPP}-{LTE}},
+  Author                   = {Naessens, F. and Derudder, V. and Cappelle, H. and Hollevoet, L. and Raghavan, P. and Desmet, M. and AbdelHamid, A. M. and Vos, I. and Folens, L. and O'Loughlin, S. and Singirikonda, S. and Dupont, S. and Weijers, J.-W. and Dejonghe, A. and Van der Perre, L.},
+  Booktitle                = {Proc. IEEE Symp. VLSI Circuits (VLSIC)},
+  Year                     = {2010},
+  Pages                    = {213--214},
+
+  Doi                      = {5560292},
+  File                     = {naeder_10.pdf:naeder_10.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{naerag_11,
+  Title                    = {{Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding}},
+  Author                   = {F. Naessens and P. Raghavan and L. Van der Perre and A. Dejonghe},
+  Booktitle                = {Proc. ESAT- TELEMIC, Telecommunications and Microwaves},
+  Year                     = {2011},
+
+  Address                  = {Grenoble, France},
+  Month                    = dec,
+
+  Cb_grade                 = { - ungelesen,
+ - ASIP },
+  File                     = {naerag_11.pdf:naerag_11.pdf:PDF},
+  Owner                    = {brehm},
+  Timestamp                = {2012.03.30}
+}
+
+@Article{nagses_00,
+  Title                    = {{I}ncreasing data rate over wireless channels},
+  Author                   = {Naguib, A. F. and Seshadri, N. and Calderbank, A. R.},
+  Journal                  = {IEEE Signal Processing Magazine},
+  Year                     = {2000},
+  Number                   = {3},
+  Pages                    = {76--92},
+  Volume                   = {17},
+
+  Abstract                 = {Space-time coding (STC) is a new coding/signal processing framework for wireless communication systems with multiple transmit and multiple receive antennas. This new framework has the potential of dramatically improve the capacity and data rates. In addition, this framework presents the best trade-off between spectral efficiency and power consumption. ST codes (designed so far) come in two different types. ST trellis codes offer the maximum possible diversity gain and a coding gain without any sacrifice in the transmission bandwidth. The decoding of these codes, however, would require the use of a vector form of the Viterbi decoder. Space-time block codes (STBCs) offer a much simpler may of obtaining transmit diversity without any sacrifice in bandwidth and without requiring huge decoding complexity. In fact, the structure of the STBCs is such that it allows for very simple signal processing (linear combining) for encoding/decoding, differential encoding/detection, and interference cancellation. This new signal processing framework offered by ST codes can be used to enhance the data rate and/or capacity in various wireless applications. That is the reason many of these STC ideas have already found their way to some of the current third-generation wireless systems standards},
+  Doi                      = {10.1109/79.841731},
+  File                     = {nagses_00.pdf:nagses_00.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {1053-5888},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@Article{naicho_14,
+  Title                    = {{R}efresh {P}ausing in {DRAM} {M}emory {S}ystems},
+  Author                   = {Nair, Prashant J. and Chou, Chia-Chen and Qureshi, Moinuddin K.},
+  Journal                  = {ACM Trans. Archit. Code Optim.},
+  Year                     = {2014},
+
+  Month                    = feb,
+  Number                   = {1},
+  Pages                    = {10:1--10:26},
+  Volume                   = {11},
+
+  Acmid                    = {2579669},
+  Address                  = {New York, NY, USA},
+  Articleno                = {10},
+  Doi                      = {10.1145/2579669},
+  ISSN                     = {1544-3566},
+  Issue_date               = {February 2014},
+  Keywords                 = {Memory scheduling, memory controller},
+  Numpages                 = {26},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2015.07.13},
+  Url                      = {http://doi.acm.org/10.1145/2579669}
+}
+
+@InProceedings{naikim_13,
+  Title                    = {{A}rch{S}hield: {A}rchitectural {F}ramework for {A}ssisting {DRAM} {S}caling by {T}olerating {H}igh {E}rror {R}ates},
+  Author                   = {Nair, Prashant J. and Kim, Dae-Hyun and Qureshi, Moinuddin K.},
+  Booktitle                = {Proceedings of the 40th Annual International Symposium on Computer Architecture},
+  Year                     = {2013},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {72--83},
+  Publisher                = {ACM},
+  Series                   = {ISCA '13},
+
+  Acmid                    = {2485929},
+  Doi                      = {10.1145/2485922.2485929},
+  ISBN                     = {978-1-4503-2079-5},
+  Keywords                 = {dynamic random access memory, error correction, hard faults},
+  Location                 = {Tel-Aviv, Israel},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2015.12.02},
+  Url                      = {http://doi.acm.org/10.1145/2485922.2485929}
+}
+
+@Article{nairob_15,
+  Title                    = {{F}ault{S}im: {A} {F}ast, {C}onfigurable {M}emory-{R}eliability {S}imulator for {C}onventional and 3{D}-{S}tacked {S}ystems},
+  Author                   = {Nair, Prashant J. and Roberts, David A. and Qureshi, Moinuddin K.},
+  Journal                  = {ACM Trans. Archit. Code Optim.},
+  Year                     = {2015},
+
+  Month                    = dec,
+  Number                   = {4},
+  Pages                    = {44:1--44:24},
+  Volume                   = {12},
+
+  Acmid                    = {2831234},
+  Address                  = {New York, NY, USA},
+  Articleno                = {44},
+  Doi                      = {10.1145/2831234},
+  ISSN                     = {1544-3566},
+  Issue_date               = {January 2016},
+  Keywords                 = {Error correcting codes, monte carlo simulation, reliability, stacked memory, through silicon vias},
+  Numpages                 = {24},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2016-11-24},
+  Url                      = {http://doi.acm.org/10.1145/2831234}
+}
+
+@InProceedings{najwei_15,
+  Title                    = {{A} {H}igh-{L}evel {DRAM} {T}iming, {P}ower and {A}rea {E}xploration {T}ool},
+  Author                   = {Naji, Omar and Weis, Christian and Jung, Matthias and Wehn, Norbert and Hansson, Andreas},
+  Booktitle                = {Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)},
+  Year                     = {2015},
+  Month                    = {July},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.08.11}
+}
+
+@InProceedings{nalu_08,
+  Title                    = {{A} multi-bit error detection scheme for {DRAM} using partial sums with parallel counters},
+  Author                   = {Balaji Narasimham and W.K. Luk},
+  Booktitle                = {IEEE International Reliability Physics Symposium, IRPS 2008},
+  Year                     = {2008},
+  Organization             = {IEEE},
+  Pages                    = {202--205},
+
+  Owner                    = {kraft},
+  Timestamp                = {2017.08.10}
+}
+
+@Article{narshu_08,
+  Title                    = {{Q}uantifying the {R}eduction in {C}ollected {C}harge and {S}oft {E}rrors in the {P}resence of {G}uard {R}ings},
+  Author                   = {Narasimham, B. and Shuler, R. L. and Black, J. D. and Bhuva, B. L. and Schrimpf, R. D. and Witulski, A. F. and Holman, W. T. and Massengill, L. W. },
+  Journal                  = {Device and Materials Reliability, IEEE Transactions on},
+  Year                     = {2008},
+  Number                   = {1},
+  Pages                    = {203--209},
+  Volume                   = {8},
+
+  Doi                      = {10.1109/TDMR.2007.912778},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{narshu_07,
+  Title                    = {{Q}uantifying the {E}ffectiveness of {G}uard {B}ands in {R}educing the {C}ollected {C}harge {L}eading to {S}oft {E}rrors},
+  Author                   = {Narasimham, B. and Shuler, R. L. and Black, J. D. and Bhuva, B. L. and Schrimpf, R. D. and Witulski, A. F. and Holman, W. T. and Massengill, L. W. },
+  Booktitle                = {Proc. proceedings Reliability physics symposium 45th annual. ieee international},
+  Year                     = {2007},
+  Pages                    = {676--677},
+
+  Doi                      = {10.1109/RELPHY.2007.369565},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Electronic{nar_17,
+  Title                    = {{F}ulfilling {Q}uality {R}equirements for {M}emory in {A}utomotive {A}pplications},
+  Author                   = {Narasimhan, Raj},
+  HowPublished             = {http://www.arena-international.com/Journals/2017/04/04/y/l/g/1.-Raj-Narasimhan---Micron.pdf},
+  Month                    = {April},
+  Organization             = {Micron Technology, Inc.},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-03}
+}
+
+@Article{narst_97,
+  Title                    = {{A Novel ARQ Technique using the Turbo Coding Principle}},
+  Author                   = {Narayanan, K. R. and G. Stüber},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {1997},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {49--51},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{narbur_16,
+  Title                    = {{C}ircuit-{L}evel {B}enchmarking of {A}ccess {D}evices for {R}esistive {N}onvolatile {M}emory {A}rrays},
+  Author                   = {P. Narayanan and G. W. Burr and K. Virwani and B. Kurdi},
+  Journal                  = {IEEE Journal on Emerging and Selected Topics in Circuits and Systems},
+  Year                     = {2016},
+
+  Month                    = {Sept},
+  Number                   = {3},
+  Pages                    = {330-338},
+  Volume                   = {6},
+
+  Doi                      = {10.1109/JETCAS.2016.2547744},
+  ISSN                     = {2156-3357},
+  Keywords                 = {resistive RAM;circuit-level benchmarking;resistive nonvolatile memory arrays;large-scale 3D crossbar arrays;high-density storage class memory;non-Von Neumann computation;high-density SCM;nonvolatile memory element;nonlinear access device;power consumption;circuit-level SPICE simulations;copper-containing mixed-ionic-electronic-conduction;copper-containing MIEC materials;generic NVM element;diode-like AD;threshold-switching AD;1AD1R memories;circuit parameters;NVM switching voltage;line resistance;low-current bias condition;TVS threshold current;Nonvolatile memory;Switches;Threshold voltage;SPICE;Resistance;Varistors;Switching circuits;Mixed-ionic-electronic-conduction (MIEC);access device;1S1R;1AD1R;circuit simulation;non-volatile memory;crossbar memory;selector;NPN;varistor;MaSiM;threshold vacuum switch;chalcogenide threshold switch;field-assisted superlinear threshold},
+  Timestamp                = {2018-09-03}
+}
+
+@Misc{nalow06,
+  Title                    = {{Low Density Parity Check Code for Rate 7/8. GSFC - STD - 9100}},
+
+  Author                   = {{NASA}},
+  Month                    = may,
+  Year                     = {2006},
+
+  Key                      = {uwb},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{NASA2006,
+  Title                    = {{Low Density Parity Check Code for Rate 7/8. GSFC - STD - 9100}},
+
+  Author                   = {{NASA}},
+  Month                    = may,
+  Year                     = {2006},
+
+  Key                      = {uwb},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{nasbha_06,
+  Title                    = {{A}nalysis of {S}oft {E}rror {M}itigation {T}echniques for {R}egister {F}iles in {IBM} {C}u-08 90nm {T}echnology},
+  Author                   = {Naseer, Riaz and Bhatti, Rashed Zafar and Draper, Jeff},
+  Booktitle                = {Proc. 49th IEEE Int. Midwest Symp. Circuits and Systems MWSCAS '06},
+  Year                     = {2006},
+  Pages                    = {515--519},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/MWSCAS.2006.382112},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{nas_08,
+  Title                    = {{T}echnology modeling and characterization beyond the 45nm node},
+  Author                   = {Nassif, S. R.},
+  Booktitle                = {Proc. Asia and South Pacific Design Automation Conference ASPDAC 2008},
+  Year                     = {2008},
+  Month                    = mar,
+  Pages                    = {219},
+
+  Doi                      = {10.1109/ASPDAC.2008.4483944},
+  File                     = {nas_08.pdf:nas_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.02.11}
+}
+
+@InProceedings{natjun_20,
+  Title                    = {{E}fficient {G}eneration of {A}pplication {S}pecific {M}emory {C}ontrollers},
+  Author                   = {Natale, Marco V. and Jung, Matthias and Kraft, Kira and Lauer, Frederik and Feldmann, Johannes and Sudarshan, Chirag and Weis, Christian and Krumke, Sven O. and Wehn, Norbert},
+  Booktitle                = {International Symposium on Memory Systems (MEMSYS 2020)},
+  Year                     = {2020},
+  Month                    = {October},
+  Publisher                = {ACM/IEEE},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-09-19}
+}
+
+@Book{NRC2011,
+  Title                    = {{T}he {F}uture of {C}omputing {P}erformance: {G}ame {O}ver or {N}ext {L}evel?},
+  Author                   = {{National Research Council}},
+  Editor                   = {Samuel H. Fuller and Lynette I. Millett},
+  Publisher                = {The National Academies Press},
+  Year                     = {2011},
+
+  Address                  = {Washington, DC, USA},
+
+  Doi                      = {10.17226/12980},
+  ISBN                     = {978-0-309-15951-7}
+}
+
+@MastersThesis{MTnazar10,
+  Title                    = {{QR decomposition algorithms for MIMO systems: impact on computational effort and hardware implementation}},
+  Author                   = {Gabriel Luca Nazar},
+  School                   = {Microelectronic Systems Design Reseach Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2010},
+  Month                    = jan,
+
+  Optnote                  = {Diplomarbeit},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.12.17}
+}
+
+@InProceedings{nazgim_10,
+  Title                    = {{I}mplementation comparisons of the {QR} decomposition for {MIMO} detection},
+  Author                   = {Nazar, Gabriel Luca and Gimmler, Christina and Wehn, Norbert},
+  Booktitle                = {Proceedings of the 23rd symposium on Integrated circuits and system design (SBCCI '10)},
+  Year                     = {2010},
+  Pages                    = {210--214},
+  Publisher                = {ACM},
+
+  Acmid                    = {1854204},
+  Doi                      = {10.1145/1854153.1854204},
+  ISBN                     = {978-1-4503-0152-7},
+  Keywords                 = {MIMO detection, MMSE-SQRD, SQRD},
+  Location                 = {Sao Paulo, Brazil},
+  Numpages                 = {5},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.19}
+}
+
+@InProceedings{nemi_11,
+  Title                    = {{U}nidirectional error detection, localization and correction for {DRAM}s: {A}pplication to on-line {DRAM} repair strategies},
+  Author                   = {M{\u{a}}d{\u{a}}lin Neagu and L. Miclea and J. Figueras},
+  Booktitle                = {IEEE 17th International On-Line Testing Symposium (IOLTS)},
+  Year                     = {2011},
+  Organization             = {IEEE},
+  Pages                    = {264--269},
+
+  Owner                    = {kraft},
+  Timestamp                = {2017.08.10}
+}
+
+@Book{neepra_00,
+  Title                    = {{OFDM} for {W}ireless {M}ultimedia {C}ommunications},
+  Author                   = {van Nee, R. and Prasad, R.},
+  Publisher                = {Artech House},
+  Year                     = {2000},
+
+  Address                  = {MA, USA},
+  Series                   = {Artech House universal personal communications series},
+
+  ISBN                     = {9780890065303},
+  Lccn                     = {99052312},
+  Url                      = {http://books.google.co.uk/books?id=1gBTAAAAMAAJ}
+}
+
+@PhdThesis{Phdneeb08,
+  Title                    = {{I}ssues on {E}fficient {N}etwork-on-{C}hip {D}esign},
+  Author                   = {Christian Neeb},
+  School                   = {Microelectronic System Design Reseach Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2008},
+  Note                     = {ISBN 978-3-939432-84-5},
+
+  Cds_grade                = {0},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2010.02.10}
+}
+
+@InProceedings{thunee_05,
+  Title                    = {{N}etwork-on-{C}hip-{C}entric {A}pproach to {I}nterleaving in {H}igh {T}hroughput {C}hannel {D}ecoders},
+  Author                   = {Christian Neeb and Michael J. Thul and Norbert Wehn},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2005},
+  Year                     = {2005},
+
+  Address                  = {Kobe, Japan},
+  Month                    = may,
+  Pages                    = {1766--1769},
+
+  Abstract                 = {Reliable wireless communication needs efficient
+channel coding schemes like Turbo- and LDPC-Codes. During
+decoding, data is exchanged iteratively between component decoders.
+Between iterations, however, the data blocks are subjected
+to a permutation (or interleaving). As parallelization of the
+decoder architectures is mandatory for high throughput, access
+conflicts can occur. For standard compliant decoders it is impossible
+to design, or pre-process, the permutation patterns such
+that conflicts are avoided. Therefore, we employ networks-onchip
+capable of resolving access conflicts at run-time to support
+arbitrary interleavers without any pre-processing.},
+  Cds_grade                = {4},
+  Cds_keywords             = {NoC, interleaver, conflict resolution, turbo code, LDPC code},
+  Cds_read                 = {2009-03-12},
+  Cds_review               = {Interleaving and conflict resolution are explained
+run-time conflict resolution with packet switched NoC approach: general overview},
+  File                     = {thunee_05.pdf:thunee_05.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{neethu_04,
+  Title                    = {{A}pplication driven {E}valuation of {N}etwork on {C}hip {A}rchitectures for {P}arallel {S}ignal {P}rocessing},
+  Author                   = {C. Neeb and M. J. Thul and N. Wehn},
+  Booktitle                = {Advances in Radio Science},
+  Year                     = {2004},
+
+  Address                  = {Miltenberg, Germany},
+  Pages                    = {181--186},
+  Volume                   = {2},
+
+  File                     = {neethu_04.pdf:neethu_04.pdf:PDF},
+  Optmonth                 = {#oct#},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{neeweh_05,
+  Title                    = {{E}nergieminimierung von {B}asisbandsignalverarbeitungsalgorithmen auf programmierbaren {P}lattformen},
+  Author                   = {Christian Neeb and and Norbert Wehn},
+  Booktitle                = {INFORMATIK 2005 Informatik LIVE! Band 1, Beiträge der 35 Jahrestagung der Gesellschaft für Informatik e.V. (GI)},
+  Year                     = {2005},
+
+  Address                  = {Bonn, Germany},
+  Editor                   = {Armin B. Cremers and Rainer Manthey and Peter Martini and Volker Steinhage},
+  Month                    = sep,
+  Number                   = {1},
+  Organization             = {Gesellschaft für Informatik},
+  Pages                    = {442},
+  Publisher                = {Gesellschaft für Informatik},
+
+  File                     = {neeweh_05.pdf:neeweh_05.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08},
+  Url                      = {http://subs.emis.de/LNI/Proceedings/Proceedings67/article3706.html}
+}
+
+@Article{neeweh_07,
+  Title                    = {{D}esigning {E}fficient {I}rregular {N}etworks for {H}eterogeneous {S}ystems-on-{C}hip},
+  Author                   = {Christian Neeb and and Norbert Wehn},
+  Journal                  = {Journal of Systems Architecture},
+  Year                     = {2008},
+
+  Month                    = mar,
+  Number                   = {3-4},
+  Pages                    = {384--396},
+  Volume                   = {54},
+
+  Abstract                 = {Networks-on-chip will serve as the central integration platform in future complex systems-on-chip (SoC) designs, composed of a large number of heterogeneous processing resources. Most researchers advocate the use of traditional regular networks like meshes, tori or trees as architectural templates which gained a high popularity in general-purpose parallel computing. However, most SoC platforms are special-purpose tailored to the domain-specific requirements of their application. They are usually built from a large diversity of heterogeneous components which communicate in a very specific, mostly irregular way.
+In this work, we propose a methodology for the design of customized irregular networks-on-chip, called INoC. We take advantage of a priori knowledge of the communication characteristic of the application to generate an optimized network topology and routing algorithm. We show that customized irregular networks are clearly superior to traditional regular architectures in terms of performance at comparable implementation costs for irregular workloads. Even more, they inherently offer a high degree of scalability and expansibility which allows to adapt the network to an arbitrary number of nodes with a given communication demand. This can normally not be accomplished by traditional approaches.},
+  ISSN                     = {1383-7621},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{neeweh_06,
+  Title                    = {{D}esigning {E}fficient {I}rregular {N}etworks for {H}eterogeneous {S}ystems-on-{C}hip},
+  Author                   = {Christian Neeb and Norbert Wehn},
+  Booktitle                = {Proc. 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools DSD 2006},
+  Year                     = {2006},
+
+  Address                  = {Cavtat, Croatia},
+  Month                    = aug,
+  Pages                    = {665--672},
+
+  File                     = {neeweh_06.pdf:neeweh_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{nehbru_15,
+  Title                    = {{A}n {E}nergy {N}eutral {W}earable {C}amera with {EPD} {D}isplay},
+  Author                   = {Nehani, Jetmir and Brunelli, Davide and Magno, Michele and Sigrist, Lukas and Benini, Luca},
+  Booktitle                = {Proceedings of the 2015 Workshop on Wearable Systems and Applications},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {1--6},
+  Publisher                = {ACM},
+  Series                   = {WearSys '15},
+
+  Acmid                    = {2753510},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Nehani:2015:ENW:2753509.2753510},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/2753509.2753510},
+  ISBN                     = {978-1-4503-3500-3},
+  Keywords                 = {TCS},
+  Keywords_original        = {electrophoretic displays, energy harvesting, energy neutral, low power camera, power optimization, wearable devices},
+  Location                 = {Florence, Italy},
+  Numpages                 = {6},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/2753509.2753510}
+}
+
+@Misc{neljus_16,
+  Title                    = {{J}ust one autonomous car will use 4,000 {GB} of data/day},
+
+  Author                   = {Nelson, Patrick},
+  HowPublished             = {https://www.networkworld.com/article/3147892/internet/one-autonomous-car-will-use-4000-gb-of-dataday.html},
+  Month                    = {December},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-04}
+}
+
+@Book{nemwol_99,
+  Title                    = {{I}nteger and {C}ombinatorial {O}ptimization},
+  Author                   = {George Nemhauser and Laurence Wolsey},
+  Publisher                = {John Wiley \& Sons, Inc.},
+  Year                     = {1999},
+  Series                   = {Series in discrete mathematics and optimization},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-23}
+}
+
+@Article{nepbah_06,
+  Title                    = {{MRF} {R}einforcer: {A} {P}robabilistic {E}lement for {S}pace {R}edundancy in {N}anoscale {C}ircuits},
+  Author                   = {Nepal, K. and Bahar, R. I. and Muddy, J. and Patterson, W. R. and Zaslavsky, A.},
+  Journal                  = {IEEE Micro},
+  Year                     = {2006},
+
+  Month                    = sep,
+  Number                   = {5},
+  Pages                    = {19--27},
+  Volume                   = {26},
+
+  Doi                      = {10.1109/MM.2006.96},
+  File                     = {nepbah_06.pdf:nepbah_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.21}
+}
+
+@Article{nepbah_07,
+  Title                    = {{D}esigning {N}anoscale {L}ogic {C}ircuits {B}ased on {M}arkov {R}andom {F}ields},
+  Author                   = {Nepal, K. and Bahar, R. I. and Mundy, J. and Patterson, W. R. and Zaslavsky, A.},
+  Journal                  = {Journal of Electronic Testing},
+  Year                     = {2007},
+
+  Month                    = jun,
+  Number                   = {2-3},
+  Pages                    = {255--266},
+  Volume                   = {23},
+
+  Doi                      = {10.1007/s10836-006-0553-9},
+  File                     = {nepbah_07.pdf:nepbah_07.pdf:PDF},
+  Keywords                 = {Reliability}
+}
+
+@Article{netrib_06,
+  Title                    = {{U}sing {B}ulk {B}uilt-in {C}urrent {S}ensors to {D}etect {S}oft {E}rrors},
+  Author                   = {Neto, E. H. and Ribeiro, I. and Vieira, M. and Wirth, G. and Kastensmidt, F. L. },
+  Journal                  = {IEEE Micro},
+  Year                     = {2006},
+
+  Month                    = sep,
+  Number                   = {5},
+  Pages                    = {10--18},
+  Volume                   = {26},
+
+  Doi                      = {10.1109/MM.2006.103},
+  File                     = {netrib_06.pdf:netrib_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.21}
+}
+
+@Book{new_10,
+  Title                    = {{N}etworks: an introduction},
+  Author                   = {Newman, Mark},
+  Publisher                = {Oxford University Press},
+  Year                     = {2010},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.08.09}
+}
+
+@TechReport{Newtec,
+  Title                    = {{HUB6504 and HUB6501 NEWTEC Dialog Hub Modules}},
+  Author                   = {{Newtec}},
+
+  Address                  = {http://www.newtec.eu/backend/files/leaflet/HUB6504%20\&%20HUB6501%20Leaflet%20092014.pdf},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.02.02}
+}
+
+@PhdThesis{Phdng05,
+  Title                    = {{O}ption {P}ricing via the {FFT} and its {A}pplication to {C}alibration},
+  Author                   = {Ng, ManWo},
+  School                   = {Master Thesis, Applied Institute of Mathematics, TU Delft},
+  Year                     = {20054},
+  Note                     = {[Online]. Available: {http://ta.twi.tudelft.nl/mf/users/oosterle/oosterlee/ng.pdf}, last access: 2014-12-31},
+
+  HowPublished             = {Master Thesis, Applied Institute of Mathematics, TU Delft},
+  Owner                    = {Brugger},
+  Timestamp                = {2014.08.21}
+}
+
+@Article{ngomau_15,
+  Title                    = {{E}xtrinsic {I}nformation {T}ransfer {C}harts for {C}haracterizing the {I}terative {D}ecoding {C}onvergence of {F}ully {P}arallel {T}urbo {D}ecoders},
+  Author                   = {H. A. Ngo and R. G. Maunder and L. Hanzo},
+  Journal                  = {IEEE Access},
+  Year                     = {2015},
+  Pages                    = {2100-2110},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/ACCESS.2015.2494861},
+  File                     = {ngomau_15.pdf:ngomau_15.pdf:PDF},
+  ISSN                     = {2169-3536},
+  Keywords                 = {Monte Carlo methods;convergence of numerical methods;error correction codes;iterative decoding;maximum likelihood decoding;turbo codes;EXIT chart technique;FPTD;Log-BCJR turbo decoders;Monte Carlo simulation;component decoder;error correction performance;extrinsic information transfer chart analysis;extrinsic logarithmic likelihood ratio;fully parallel turbo decoder;iterative decoding convergence;logarithmic Bahl-Cocke-Jelinek-Raviv;Decoding;Error correction;IEEE Standards;Iterative decoding;Monte Carlo methods;Parallel processing;Throughput;Turbo codes;EXIT chart;Fully-parallel decoding;turbo code},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.25}
+}
+
+@InProceedings{ngover_00,
+  Title                    = {{Turbo Codes on the Fixed Point DSP TMS320C55x}},
+  Author                   = {T. Ngo and I. Verbauwhede},
+  Booktitle                = {Proc. 2000 Workshop on Signal Processing Systems (SiPS '00)},
+  Year                     = {2000},
+
+  Address                  = {Lafayette, Louisiana, USA},
+  Month                    = sep,
+  Pages                    = {255--264},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTnguye14,
+  Title                    = {{ASIC} {I}mplementation of a {H}eston {O}ption {P}ricer {U}sing the {M}ulti-{L}evel {M}onte {C}arlo {M}ethod},
+  Author                   = {Ngoc Nhan Nguyen},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+  Month                    = feb,
+
+  Cds_grade                = {5},
+  Cds_keywords             = {multilevel Monte Carlo, Heston, architecture, ASIC},
+  File                     = {MTnguye14.pdf:MTnguye14.pdf:PDF},
+  Keywords                 = {finance, AG Wehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@Article{ngupfi_11,
+  Title                    = {{O}n {M}ultiple {D}ecoding {A}ttempts for {R}eed-{S}olomon {C}odes: {A} {R}ate-{D}istortion {A}pproach},
+  Author                   = {P. S. Nguyen and H. D. Pfister and K. R. Narayanan},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2011},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {668-691},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TIT.2010.2095202},
+  ISSN                     = {0018-9448},
+  Keywords                 = {Reed-Solomon codes;error correction codes;rate distortion theory;RD;RDE;RS decoding algorithm;Reed-Solomon codes;erasure patterns;errors-and-erasures decoding;multiple-decoding algorithms;rate distortion approach;rate distortion exponent;soft decision decoding;Algebraic soft-decision (ASD) decoding;Reed–Solomon (RS) codes;errors-and-erasures decoding;list decoding;multiple decoding attempts;rate-distortion (RD) theory;rate-distortion exponent (RDE)}
+}
+
+@InProceedings{nic_10,
+  Title                    = {{D}esign techniques for soft-error mitigation},
+  Author                   = {Nicolaidis, M.},
+  Booktitle                = {Proc. IEEE Int IC Design and Technology (ICICDT) Conf},
+  Year                     = {2010},
+  Pages                    = {208--214},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Basics, ?},
+  Doi                      = {10.1109/ICICDT.2010.5510252},
+  File                     = {nic_10.pdf:nic_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{nic_05,
+  Title                    = {{D}esign for soft error mitigation},
+  Author                   = {Nicolaidis, M. },
+  Journal                  = {IEEE Transactions on Device and Materials Reliability},
+  Year                     = {2005},
+
+  Month                    = sep,
+  Number                   = {3},
+  Pages                    = {405--418},
+  Volume                   = {5},
+
+  Doi                      = {10.1109/TDMR.2005.855790},
+  File                     = {nic_05.pdf:nic_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@InProceedings{nic_99,
+  Title                    = {{T}ime {R}edundancy {B}ased {S}oft-{E}rror {T}olerance to {R}escue {N}anometer {T}echnologies},
+  Author                   = {Nicolaidis, M.},
+  Booktitle                = {VLSI Test Symposium, 1999. Proceedings. 17th IEEE},
+  Year                     = {1999},
+  Month                    = apr,
+  Pages                    = {86--94},
+
+  Doi                      = {10.1109/VTEST.1999.766651},
+  File                     = {nic_99.pdf:nic_99.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@Article{nie_95,
+  Title                    = {{T}he {M}ultiple-{R}ecursive {M}atrix {M}ethod for {P}seudorandom {N}umber {G}eneration},
+  Author                   = {Harald Niederreiter},
+  Journal                  = {Finite Fields and Their Applications},
+  Year                     = {1995},
+  Number                   = {1},
+  Pages                    = {3--30},
+  Volume                   = {1},
+
+  Abstract                 = {We carry out an in-depth analysis of the multiple-recursive matrix method for uniform pseudorandom number generation which was introduced in an earlier paper of the author. This method yields much larger period lengths than the GFSR method with the same order of the recursion and the same precision. Besides periodicity properties, we establish also uniformity properties of s-tuples of successive pseudorandom numbers generated by the multiple-recursive matrix method and we study the performance under the s-dimensional serial test. The uniformity properties and the behavior under the serial test depend on an appropriate figure of merit in the case where the dimension s exceeds the order of the recursion.},
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation},
+  Doi                      = {10.1006/ffta.1995.1002},
+  File                     = {nie_95.pdf:nie_95.pdf:PDF},
+  ISSN                     = {1071-5797},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.26},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S1071579785710027}
+}
+
+@Book{nie_92,
+  Title                    = {{R}andom {N}umber {G}eneration and {Q}uasi-{M}onte {C}arlo {M}ethods},
+  Author                   = {Harald Niederreiter},
+  Publisher                = {Society for Industrial Mathematics},
+  Year                     = {1992},
+  Month                    = jan,
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random numbers, Monte Carlo},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.18}
+}
+
+@Article{nie_78,
+  Title                    = {{Q}uasi-{M}onte {C}arlo {M}ethods and {P}seudo-{R}andom {N}umbers},
+  Author                   = {Harald Niederreiter},
+  Journal                  = {American Mathematical Society},
+  Year                     = {1978},
+  Number                   = {6},
+  Pages                    = {957},
+  Volume                   = {84},
+
+  Cds_grade                = {0},
+  File                     = {nie_78.pdf:nie_78.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.18}
+}
+
+@InProceedings{nigdou_11,
+  Title                    = {{C}ycles, cells and platters: an empirical analysisof hardware failures on a million consumer {PC}s},
+  Author                   = {Nightingale, Edmund B. and Douceur, John R. and Orgovan, Vince},
+  Booktitle                = {Proceedings of the sixth conference on Computer systems},
+  Year                     = {2011},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {343--356},
+  Publisher                = {ACM},
+  Series                   = {EuroSys '11},
+
+  Acmid                    = {1966477},
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Microsoft, processor, error statistics analysis},
+  Doi                      = {http://doi.acm.org/10.1145/1966445.1966477},
+  File                     = {nigdou_11.pdf:nigdou_11.pdf:PDF},
+  ISBN                     = {978-1-4503-0634-8},
+  Keywords                 = {fault tolerance, reliability},
+  Location                 = {Salzburg, Austria},
+  Numpages                 = {14},
+  Url                      = {http://doi.acm.org/10.1145/1966445.1966477}
+}
+
+@InProceedings{nikbur_13,
+  Title                    = {{I}ntel® {V}ersion of {STAC}-{A}2 {B}enchmark: {T}oward {B}etter {P}erformance with {L}ess {E}ffort},
+  Author                   = {Nikolaev, Andrey and Burylov, Ilya and Salahuddin, Sania},
+  Booktitle                = {Proceedings of the 6th Workshop on High Performance Computational Finance (WHCPF)},
+  Year                     = {2013},
+
+  Address                  = {Denver, Colorado, USA},
+  Pages                    = {7:1--7:7},
+  Publisher                = {ACM},
+  Series                   = {WHPCF '13},
+
+  Abstract                 = {Market risk analysis is a computationally intensive problem which requires powerful computing resources. To enable consistent comparisons of vendors' technologies in this area the Securities Technology Analysis Center (STAC*), with inputs from leading trading companies, universities, and high performance computing vendors, has created STAC-A2* specifications which describe realistic market risk analysis workloads.
+
+In this paper we analyze and compare the performance of STAC-A2 workloads on two systems based on Intel® processors: Intel® Xeon® processor E5 family and Intel® Xeon Phi™ coprocessor. We show the importance of algorithmic optimizations and a few mathematical building blocks such as random number generation, mathematical functions and matrix multiplications on overall performance of the benchmark. We demonstrate that changes made in response to this analysis provide an additional ~1.6x performance improvement of the STAC-A2 benchmark on the Intel Xeon processor E5 family and up to ~15x performance improvement on Intel Xeon Phi coprocessor-based systems compared with the previous version of the benchmark. Intel Xeon Phi coprocessor architecture is ~1.10--1.38x faster than 16-core Intel Xeon processor E5 family-based systems, depending on the problem size, while the 32-core Intel Xeon processor E5 is the fastest among all analyzed platforms.},
+  Acmid                    = {2535566},
+  Articleno                = {7},
+  Cds_grade                = {0},
+  Doi                      = {10.1145/2535557.2535566},
+  File                     = {nikbur_13.pdf:nikbur_13.pdf:PDF},
+  ISBN                     = {978-1-4503-2507-3},
+  Keywords                 = {finance},
+  Location                 = {Denver, Colorado},
+  Numpages                 = {7},
+  Owner                    = {CDS},
+  Timestamp                = {2015-04-22},
+  Url                      = {http://doi.acm.org/10.1145/2535557.2535566}
+}
+
+@TechReport{nik_00,
+  Title                    = {{Implementing a MAP Decoder for cdma2000 Turbo Codes on a TMS320C62x DSP Device}},
+  Author                   = {J. Nikolic-Popovic},
+  Institution              = {Texas Instruments Incorporated},
+  Year                     = {2000},
+
+  Address                  = {Houston, Texas, USA},
+  Month                    = may,
+  Note                     = {Application Report SPRA629},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{nikpar_08,
+  Title                    = {{RECFEC}: {A} {R}econfigurable {FEC} {P}rocessor for {V}iterbi, {T}urbo, {R}eed-{S}olomon and {LDPC} {C}oding},
+  Author                   = {Niktash, A. and Parizi, H. T. and Kamalizad, A. H. and Bagherzadeh, N.},
+  Booktitle                = {Proc. IEEE Wireless Communications and Networking Conf. WCNC 2008},
+  Year                     = {2008},
+  Pages                    = {605--610},
+
+  Cb_grade                 = {reconfigurable, but poor throughput},
+  Doi                      = {10.1109/WCNC.2008.112},
+  File                     = {nikpar_08.pdf:nikpar_08.pdf:PDF},
+  Keywords                 = {ASIP Turbo Viterbi},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.08.19}
+}
+
+@InProceedings{nimbla_03,
+  Title                    = {{Inter-Window Shuffle Interleavers for High Throughput Turbo Decoding}},
+  Author                   = {A. Nimbalker and K. T. Blankenship and B. Classon and T. E. Fuja and D. {Costello,~Jr.}},
+  Booktitle                = {Proc. 3nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {355--358},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{nimbla_08,
+  Title                    = {{ARP} and {QPP} {I}nterleavers for {LTE} {T}urbo {C}oding},
+  Author                   = {Nimbalker, A. and Blankenship, Y. and Classon, B. and Blankenship, T. K. },
+  Booktitle                = {Proc. IEEE Wireless Communications and Networking Conference WCNC 2008},
+  Year                     = {2008},
+  Month                    = mar,
+  Pages                    = {1032--1037},
+
+  Doi                      = {10.1109/WCNC.2008.187},
+  File                     = {nimbla_08.pdf:nimbla_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {punekar},
+  Timestamp                = {2009.09.04}
+}
+
+@TechReport{nis_13,
+  Title                    = {{NIST} {C}loud {C}omputing {S}tandards {R}oadmap},
+  Author                   = {{NIST Cloud Computing Standards Roadmap Working Group}},
+  Institution              = {National Institute of Standards and Technology},
+  Year                     = {2013},
+  Month                    = {July},
+  Note                     = {\url{http://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.500-291r2.pdf} , Last accessed: 12 Dec. 2017},
+  Number                   = {Special Publication (NIST SP) - 500-291, Version 2},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.09},
+  Url                      = {http://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.500-291r2.pdf}
+}
+
+@Article{niuche_12,
+  Title                    = {{CRC}-{A}ided {D}ecoding of {P}olar {C}odes},
+  Author                   = {K. Niu and K. Chen},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2012},
+
+  Month                    = {October},
+  Number                   = {10},
+  Pages                    = {1668-1671},
+  Volume                   = {16},
+
+  Doi                      = {10.1109/LCOMM.2012.090312.121501},
+  ISSN                     = {1089-7798},
+  Keywords                 = {computational complexity;cyclic redundancy check codes;decoding;error statistics;turbo codes;3GPP standard;BI-AWGNC;CA-SCL/SCS decoding;CRC-aided decoding;CRC-aided successive cancellation list/stack;binary-input additive white Gaussian noise channel;block error probability;cyclic redundancy check;polar codes;successive cancellation decoder;successive cancellation decoding;time complexity;turbo codes;Complexity theory;Iterative decoding;Maximum likelihood decoding;Measurement;Turbo codes;CRC;Polar codes;list decoding;stack decoding;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{niuche_14,
+  Title                    = {{L}ow-{C}omplexity {S}phere {D}ecoding of {P}olar {C}odes {B}ased on {O}ptimum {P}ath {M}etric},
+  Author                   = {Kai Niu and Kai Chen and Jiaru Lin},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2014},
+
+  Month                    = {February},
+  Number                   = {2},
+  Pages                    = {332-335},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/LCOMM.2014.010214.131826},
+  ISSN                     = {1089-7798},
+  Keywords                 = {AWGN channels;maximum likelihood decoding;additive white Gaussian noise channels;low-complexity sphere decoding;maximum likelihood decoding;optimum path metric;short polar codes;signal-to-noise ratio;sphere decoder;stack SD algorithm;Approximation methods;Complexity theory;Maximum likelihood decoding;Measurement;Signal to noise ratio;Vectors;Polar codes;maximum likelihood rule;sphere decoding;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{niuche_14a,
+  Title                    = {{P}olar codes: {P}rimary concepts and practical decoding algorithms},
+  Author                   = {Kai Niu and Kai Chen and Jiaru Lin and Q. T. Zhang},
+  Journal                  = {IEEE Communications Magazine},
+  Year                     = {2014},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {192-203},
+  Volume                   = {52},
+
+  Doi                      = {10.1109/MCOM.2014.6852102},
+  ISSN                     = {0163-6804},
+  Keywords                 = {channel coding;decoding;error correction codes;parity check codes;turbo codes;CRC codes;LDPC codes;SC algorithm;SC decoding;SC decoding technique;capacity-approaching coding strategy;channel polarization;decoding algorithms;decoding techniques;discrete memoryless channel;error-correcting codes;polar codes;polar encoding;turbo codes;Channel capacity;Channel coding;Decoding;Error probability;Polar codes},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{niucou_13,
+  Title                    = {{A} scalable design approach for stencil computation on reconfigurable clusters},
+  Author                   = {Xinyu Niu and Coutinho, J.G.F. and Luk, W.},
+  Booktitle                = {Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on},
+  Year                     = {2013},
+  Month                    = {Sept},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/FPL.2013.6645551},
+  Keywords                 = {field programmable gate arrays;logic design;reconfigurable architectures;Maxeler MPC-C500 computing system;Virtex-6 SX475T FPGA;large-scale cluster;reconfigurable cluster;scalable communication model;scalable design approach;stencil-based algorithm;Algorithm design and analysis;Computer architecture;Field programmable gate arrays;Hardware;Parallel processing;Peak to average power ratio;System-on-chip},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@InProceedings{noeher_03,
+  Title                    = {{T}urbo synchronization: an {EM} algorithm interpretation},
+  Author                   = {Noels, N. and Herzet, C. and Dejonghe, A. and Lottici, V. and Steendam, H. and Moeneclaey, M. and Luise, M. and Vandendorpe, L.},
+  Booktitle                = {Communications, 2003. ICC '03. IEEE International Conference on},
+  Year                     = {2003},
+  Month                    = may,
+  Pages                    = {2933--2937vol.4},
+  Volume                   = {4},
+
+  Doi                      = {10.1109/ICC.2003.1204575},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{noelot_05,
+  Title                    = {{A} {T}heoretical {F}ramework for {S}oft-{I}nformation-{B}ased {S}ynchronization in {I}terative ({T}urbo) {R}eceivers},
+  Author                   = {Nele Noels and Vincenzo Lottici and Antoine Dejonghe and Heidi Steendam and Marc Moeneclaey and Marco Luise and Luc Vandendorpe},
+  Journal                  = {EURASIP J. Wireless Comm. and Networking},
+  Year                     = {2005},
+  Number                   = {4},
+  Pages                    = {117-129},
+  Volume                   = {2005},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Ee                       = {http://dx.doi.org/10.1155/WCN.2005.117}
+}
+
+@Article{noeste_04,
+  Title                    = {{T}he {T}rue {C}ramer-{R}ao {B}ound for {C}arrier {F}requency {E}stimation {F}rom a {PSK} {S}ignal},
+  Author                   = {Nele Noels and Heidi Steendam and Marc Moeneclaey},
+  Journal                  = {IEEE TRANSACTIONS ON COMMUNICATIONS},
+  Year                     = {2004},
+  Number                   = {5},
+  Pages                    = {834--844},
+  Volume                   = {52},
+
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-07}
+}
+
+@Article{Noels2005,
+  Title                    = {{C}arrier phase and frequency estimation for pilot-symbol assisted transmission: bounds and algorithms},
+  Author                   = {Noels, N. and Steendam, H. and Moeneclaey, M. and Bruneel, H.},
+  Journal                  = {Signal Processing, IEEE Transactions on},
+  Year                     = {2005},
+
+  Month                    = {Dec},
+  Number                   = {12},
+  Pages                    = {4578-4587},
+  Volume                   = {53},
+
+  Doi                      = {10.1109/TSP.2005.859318},
+  ISSN                     = {1053-587X},
+  Keywords                 = {data communication;frequency estimation;iterative methods;phase estimation;signal processing;synchronisation;Cramer-Rao lower bound;carrier phase estimation;data modulation scheme;frequency offset estimation;iterative soft-decision-directed estimation;noisy linearly modulated burst signal;pilot symbol;pilot-symbol assisted transmission;random data symbol;signal-to-noise ratio;Chirp modulation;Decision support systems;Frequency estimation;Frequency synchronization;Parameter estimation;Phase detection;Phase estimation;Phase modulation;Phase noise;Signal to noise ratio;Carrier synchronization;Cramer–Rao bound;frequency estimation;phase estimation},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27}
+}
+
+@Article{nohser_08,
+  Title                    = {{A} {N}ew {A}pproach for {T}ime {S}ynchronization in {W}ireless {S}ensor {N}etworks: {P}airwise {B}roadcast {S}ynchronization},
+  Author                   = {Kyounglae Noh and Serpedin, E. and Qaraqe, K.},
+  Journal                  = {Wireless Communications, IEEE Transactions on},
+  Year                     = {2008},
+
+  Month                    = {September},
+  Number                   = {9},
+  Pages                    = {3318-3322},
+  Volume                   = {7},
+
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {4626304},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1109/TWC.2008.070343},
+  ISSN                     = {1536-1276},
+  Keywords                 = {BLE},
+  Keywords_original        = {protocols;synchronisation;wireless sensor networks;overhearing;pairwise broadcast synchronization;synchronization protocols;time synchronization;timing message exchanges;wireless sensor networks;Broadcasting;Clocks;Communication system security;Maximum likelihood detection;Physical layer;Protocols;Synchronization;Timing;Wireless communication;Wireless sensor networks;Time synchronization;clock synchronization;wireless sensor networks},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30}
+}
+
+@InCollection{nolsyd_10,
+  Title                    = {{R}econfigurable {C}omponents for {A}pplication-{S}pecific {P}rocessor {A}rchitectures},
+  Author                   = {T.G. Noll and T. Sydow and B. Neumann and J. Schleifer and T. Coenen and G. Kappen},
+  Booktitle                = {Dynamically Reconfigurable Systems},
+  Publisher                = {Springer Netherlands},
+  Year                     = {2010},
+  Editor                   = {M. Platzner and J. Teich and N. Wehn},
+  Pages                    = {25-49},
+
+  Affiliation              = {RWTH Aachen University Chair of Electrical Engineering and Computer Systems Schinkelstr. 2 52062 Aachen Germany},
+  ISBN                     = {978-90-481-3485-4},
+  Keyword                  = {Engineering}
+}
+
+@InProceedings{novstu_10,
+  Title                    = {{T}he effect of unreliable {LLR} storage on the performance of {MIMO}-{BICM}},
+  Author                   = {Novak, C. and Studer, C. and Burg, A. and Matz, G.},
+  Booktitle                = {Proc. Conf Signals, Systems and Computers (ASILOMAR) Record of the Forty Fourth Asilomar Conf},
+  Year                     = {2010},
+  Pages                    = {736--740},
+
+  Cb_grade                 = {- gelesen 11/10/20
+- Reliability},
+  Doi                      = {10.1109/ACSSC.2010.5757661},
+  File                     = {novstu_10.pdf:novstu_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.20}
+}
+
+@InProceedings{nownas_08,
+  Title                    = {{C}haracterization and design for variability and reliability},
+  Author                   = {Nowka, K. and Nassif, S. and Agarwal, K.},
+  Booktitle                = {Proc. IEEE Custom Integrated Circuits Conference CICC 2008},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {341--346},
+
+  Doi                      = {10.1109/CICC.2008.4672092},
+  File                     = {nownas_08.pdf:nownas_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.02.11}
+}
+
+@Article{Nuriyev2003,
+  Title                    = {{P}ilot-symbol-assisted coded transmission over the block-noncoherent {AWGN} channel},
+  Author                   = {Nuriyev, Rza and Anastasopoulos, Achilleas},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2003},
+  Number                   = {6},
+  Pages                    = {953--963},
+  Volume                   = {51},
+
+  Owner                    = {ali},
+  Publisher                = {IEEE},
+  Timestamp                = {2015.04.23}
+}
+
+@InProceedings{nur_05,
+  Title                    = {{N}etwork-on-{C}hip: {A} {N}ew {P}aradigm for {S}ystem-on-{C}hip {D}esign},
+  Author                   = {Nurmi, J.},
+  Booktitle                = {System-on-Chip, 2005. Proceedings. 2005 International Symposium on},
+  Year                     = {2005},
+  Month                    = nov,
+  Pages                    = {2-6},
+
+  Abstract                 = {Network-on-chip is a novel category for on-chip communication where the abstraction of layered protocols is utilized to modularize the communication design. This also implies that the computation and communication are separated from each other. In this invited paper, the motivation for such an approach is explained, terminology within network-on-chip area is clarified, some of the proposed networks are analyzed, and the network-on-chip design aspects discussed.},
+  Doi                      = {10.1109/ISSOC.2005.1595630},
+  File                     = {nur_05.pdf:nur_05.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.05}
+}
+
+@InProceedings{nurven_17,
+  Title                    = {{C}an {FPGAs} {B}eat {GPUs} in {A}ccelerating {N}ext-{G}eneration {D}eep {N}eural {N}etworks?},
+  Author                   = {Nurvitadhi, Eriko and Venkatesh, Ganesh and Sim, Jaewoong and Marr, Debbie and Huang, Randy and Ong Gee Hock, Jason and Liew, Yeong Tat and Srivatsan, Krishnan and Moss, Duncan and Subhaschandra, Suchit and Boudoukh, Guy},
+  Booktitle                = {Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {5--14},
+  Publisher                = {ACM},
+  Series                   = {FPGA '17},
+
+  Acmid                    = {3021740},
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {Intel paper: FPGA has always higher GOP/s/Watt },
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1145/3020078.3021740},
+  ISBN                     = {978-1-4503-4354-1},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {FPGA, GPU, accelerator, deep learning, intel stratix 10},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {10},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/3020078.3021740}
+}
+
+@InProceedings{nurwei_14,
+  Title                    = {{G}raph{G}en: {A}n {FPGA} {F}ramework for {V}ertex-{C}entric {G}raph {C}omputation},
+  Author                   = {Nurvitadhi, Eriko and Weisz, Gabriel and Wang, Yu and Hurkat, Skand and Nguyen, Marie and Hoe, James C. and Martinez, Jose F. and Guestrin, Carlos},
+  Booktitle                = {Proceedings of the 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
+  Year                     = {2014},
+  Month                    = {May},
+  Pages                    = {25-28},
+
+  Abstract                 = {Vertex-centric graph computations are widely used in many machine learning and data mining applications that operate on graph data structures. This paper presents GraphGen, a vertex-centric framework that targets FPGA for hardware acceleration of graph computations. GraphGen accepts a vertex-centric graph specification and automatically compiles it onto an application-specific synthesized graph processor and memory system for the target FPGA platform. We report design case studies using GraphGen to implement stereo matching and handwriting recognition graph applications on Terasic DE4 and Xilinx ML605 FPGA boards. Results show up to 14.6x and 2.9x speedups over software on Intel Core i7 CPU for the two applications, respectively.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FCCM.2014.15},
+  File                     = {nurwei_14.pdf:nurwei_14.pdf:PDF},
+  Keywords                 = {graphs},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.28}
+}
+
+@Misc{nviperformance,
+  Title                    = {{P}erformance {P}rimitives},
+
+  Author                   = {NVIDIA},
+  HowPublished             = {https://developer.nvidia.com/npp},
+  Note                     = {last access 2015-01-13},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.24}
+}
+
+@Misc{nvikepler12,
+  Title                    = {{K}epler - {T}he {W}orld's {F}astest, {M}ost {E}fficient {HPC} {A}rchitecture},
+
+  Author                   = {{NVIDIA}},
+  Year                     = {2012},
+
+  Owner                    = {Sadri},
+  Timestamp                = {2014.07.25},
+  Url                      = {http://www.nvidia.com/object/nvidia-kepler.html}
+}
+
+@Misc{nvinvidias09,
+  Title                    = {{NVIDIA}'s {N}ext {G}eneration {CUDA} {C}ompute {A}rchitecture},
+
+  Author                   = {NVIDIA},
+  Year                     = {2009},
+
+  Owner                    = {Sadri},
+  Timestamp                = {2014.07.25},
+  Url                      = {http://www.nvidia.de/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf}
+}
+
+@Electronic{nvi_12,
+  Title                    = {{O}pen{CL} {M}ersenne {T}wister {C}ode {E}xample},
+  Author                   = {{Nvidia Corporation}},
+  HowPublished             = {\url{http://developer.nvidia.com/opencl-sdk-code-samples\#oclMersenneTwister}},
+  Language                 = {en},
+  Month                    = mar,
+  Note                     = {last access 2015-10-13},
+  Url                      = {\url{http://developer.nvidia.com/opencl-sdk-code-samples\#oclMersenneTwister}},
+  Year                     = {2012},
+
+  Cds_keywords             = {random number generator, GPU, OpenCL, Box-Muller},
+  Cds_read                 = {2012-03-22},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@Electronic{nvi_12b,
+  Title                    = {{O}pen{CL} {M}ersenne {T}wister {C}ode {E}xample},
+  Author                   = {{Nvidia Corporation}},
+  HowPublished             = {\url{http://developer.nvidia.com/opencl-sdk-code-samples\#oclMersenneTwister}},
+  Language                 = {en},
+  Month                    = mar,
+  Year                     = {2012},
+
+  Cds_keywords             = {random number generator, GPU, OpenCL, Box-Muller},
+  Cds_read                 = {2012-03-22},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@Electronic{nvidia_computationalfinance,
+  Title                    = {{C}omputational {F}inance {W}ebsite},
+  Author                   = {{NVIDIA Corporation}},
+  Language                 = {en},
+  Month                    = mar,
+  Url                      = {http://www.nvidia.com/object/computational\_finance.html},
+  Year                     = {2012},
+
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.15}
+}
+
+@InProceedings{schasc05,
+  Title                    = {{A}pplication {S}pecific {P}rocessors for {F}lexible {R}eceivers},
+  Author                   = {O. Schliebusch, Gerd Ascheid, A. Wieferink, Rainer Leupers, and Heinrich Meyr},
+  Booktitle                = {Proc. of National Symposium of Radio Science (URSI)},
+  Year                     = {2005},
+
+  Address                  = {Poznan (Poland)},
+  Month                    = {apr},
+
+  Journal                  = {Proc. of National Symposium of Radio Science (URSI)}
+}
+
+@Article{obpie_17,
+  Title                    = {{A} {S}urvey of {P}ower and {E}nergy {P}redictive {M}odels in {HPC} {S}ystems and {A}pplications},
+  Author                   = {Kenneth O'brien and Ilia Pietri and Ravi Reddy and Alexey Lastovetsky and Rizos Sakellariou},
+  Journal                  = {ACM Computing Surveys},
+  Year                     = {2017},
+
+  Month                    = {October},
+  Number                   = {3},
+  Pages                    = {37:1--37:38},
+  Volume                   = {50},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.16}
+}
+
+@Article{ocelg_17,
+  Title                    = {{C}ontinuous software engineering — {A} microservices architecture perspective},
+  Author                   = {O'Connor, Rory V. and Elger, Peter and Clarke, Paul M.},
+  Journal                  = {Journal of Software: Evolution and Process},
+  Year                     = {2017},
+  Note                     = {e1866 JSME-16-0193.R2},
+  Number                   = {11},
+  Pages                    = {e1866--n/a},
+  Volume                   = {29},
+
+  Doi                      = {10.1002/smr.1866},
+  ISSN                     = {2047-7481},
+  Keywords                 = {agile, continuous software engineering, microservices, situational factors, software development process},
+  Owner                    = {MJ},
+  Timestamp                = {2020-02-09},
+  Url                      = {http://dx.doi.org/10.1002/smr.1866}
+}
+
+@InProceedings{6787275,
+  Title                    = {{SHEPARD}: {S}cheduling on {H}eterogeneous {P}latforms {U}sing {A}pplication {R}esource {D}emands},
+  Author                   = {O'Neill, E. and McGlone, J. and Milligan, P. and Kilpatrick, P.},
+  Booktitle                = {Parallel, Distributed and Network-Based Processing (PDP), 2014 22nd Euromicro International Conference on},
+  Year                     = {2014},
+  Month                    = {Feb},
+  Pages                    = {213-217},
+
+  Doi                      = {10.1109/PDP.2014.53},
+  ISSN                     = {1066-6192},
+  Keywords                 = {multiprocessing systems;parallel processing;processor scheduling;program compilers;FPGAs;GPUs;application resource demands;automatic run-time allocation framework;compile time framework;heterogeneous computing devices;heterogeneous computing technology;heterogeneous platforms;in-memory database;managed tasks;multicore CPUs;task parallel application;Dictionaries;Equations;Graphics processing units;Kernel;Mathematical model;Performance evaluation;Resource management;LLVM;OpenCL;heterogeneous computation;managed tasks;run-time allocation},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@Article{OShea1998,
+  Title                    = {{F}eedforward {D}ata-{A}ided {F}requency {E}stimator for {B}urst-{M}ode {D}igital {T}ransmission},
+  Author                   = {O'Shea, Deirdre and Verdin, Dan and Tozer, Tim C.},
+  Journal                  = {Wireless Personal Communications},
+  Year                     = {1998},
+
+  Month                    = sep,
+  Number                   = {2},
+  Pages                    = {131--149},
+  Volume                   = {8},
+
+  Acmid                    = {609361},
+  Address                  = {Hingham, MA, USA},
+  Doi                      = {10.1023/A:1008803209489},
+  ISSN                     = {0929-6212},
+  Issue_date               = {September 1998},
+  Keywords                 = {burst mode systems., feedforward frequency estimation, synchronisation},
+  Numpages                 = {19},
+  Owner                    = {ali},
+  Publisher                = {Kluwer Academic Publishers},
+  Timestamp                = {2015.03.06},
+  Url                      = {http://dx.doi.org/10.1023/A:1008803209489}
+}
+
+@Article{oenmoo_01,
+  Title                    = {{A Low-Density Generator Matrix Interpretation of Parallel Concatenated Single Bit Parity Codes}},
+  Author                   = {T. Oenning and J. Moon},
+  Journal                  = {IEEE Transactions on Magnetics},
+  Year                     = {2001},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {737--741},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{ohson_09,
+  Title                    = {{A}n efficient carrier frequency offset estimation algorithm for {DVB}-{RCS} systems},
+  Author                   = {Jong Gyu Oh and Seung Ho Son and Joon Kim},
+  Booktitle                = {IEEE 13th International Symposium on Consumer Electronics},
+  Year                     = {2009},
+  Pages                    = {342--345},
+
+  Owner                    = {Imran},
+  Timestamp                = {2013.07.30}
+}
+
+@Article{Oh2001,
+  Title                    = {{J}oint decoding and carrier phase recovery algorithm for turbo codes},
+  Author                   = {Wangrok Oh and Kyungwhoon Cheun},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2001},
+
+  Month                    = {Sept},
+  Number                   = {9},
+  Pages                    = {375-377},
+  Volume                   = {5},
+
+  Doi                      = {10.1109/4234.951382},
+  ISSN                     = {1089-7798},
+  Keywords                 = {iterative decoding;synchronisation;turbo codes;MAP decoder;carrier phase recovery;iterative decoding;low hardware complexity;maximum a posteriori probability decoder;turbo codes;AWGN channels;Bit error rate;Demodulation;Hardware;Iterative algorithms;Iterative decoding;Phase estimation;Phase modulation;Signal to noise ratio;Turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.23}
+}
+
+@Article{ohche_00,
+  Title                    = {{Adaptive Channel SNR Estimation Algorithm for Turbo Decoder}},
+  Author                   = {W. Oh and K. Cheun},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2000},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {255--257},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{o_03,
+  Title                    = {{Decoder Architecture for Array-Code-Based LDPC Codes}},
+  Author                   = {Ölcer, S.},
+  Booktitle                = {Proc. 2003 Global Telecommunications Conference (GLOBECOM '03)},
+  Year                     = {2003},
+
+  Address                  = {San Francisco, USA},
+  Month                    = dec,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{olimor_16,
+  Title                    = {{S}oftware {A}rchitectures for {E}mbedded {S}oftware {S}ystems},
+  Author                   = {Oliveira, Pablo and Morgenstern, Andreas and Jung, Matthias and Kuhn, Thomas and Wehn, Norbert},
+  Publisher                = {Distance and Independent Studies Center (DISC) University of Kaiserslautern},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-06-30}
+}
+
+@InCollection{omlhef_15,
+  Title                    = {{E}xploiting {M}ixed-{P}recision {A}rithmetics in a {M}ultilevel {M}onte {C}arlo {A}pproach on {FPGA}s},
+  Author                   = {Steffen Omland and Mario Hefter and Klaus Ritter and Christian Brugger and Christian De Schryver and Norbert Wehn and Anton Kostiuk},
+  Booktitle                = {FPGA Based Accelerators for Financial Applications},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2015},
+  Edition                  = {1st},
+  Editor                   = {De Schryver, Christian},
+  Month                    = jul,
+  Pages                    = {191--220},
+
+  Abstract                 = {Nowadays, high-speed computations are mandatory for financial and insurance institutes to survive in competition and to fulfill the regulatory reporting requirements that have just toughened over the last years. A majority of these computations are carried out on huge computing clusters, which are an ever increasing cost burden for the financial industry. There, state-of-the-art CPU and GPU architectures execute arithmetic operations with predefined precisions only, that may not meet the actual requirements for a specific application. Reconfigurable architectures like Field Programmable Gate Arrays (FPGAs) have a huge potential to accelerate financial simulations while consuming only very low energy by exploiting dedicated precisions in optimal ways. In this work we present a novel methodology to speed up Multilevel Monte Carlo (MLMC) simulations on reconfigurable architectures. The idea is to aggressively lower the precisions for different parts of the algorithm without loosing any accuracy at the end. For this, we have developed a novel heuristic for selecting an appropriate precision at each stage of the simulation that can be executed with low costs at runtime. Further, we introduce a cost model for reconfigurable architectures and minimize the cost of our algorithm without changing the overall error. We consider the showcase of pricing Asian options in the Heston model. For this setup we improve one of the most advanced simulation methods by a factor of 3–9× on the same platform.},
+  Doi                      = {10.1007/978-3-319-15407-7_9},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-08-21}
+}
+
+@Article{omu_69,
+  Title                    = {{On the Viterbi decoding algorithm}},
+  Author                   = {Omura, J. K.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1969},
+
+  Month                    = jan,
+  Pages                    = {177--179},
+  Volume                   = {15},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{onihan_10,
+  Title                    = {{D}esign of {H}igh-{T}hroughput {F}ully {P}arallel {LDPC} {D}ecoders {B}ased on {W}ire {P}artitioning},
+  Author                   = {Onizawa, N. and Hanyu, T. and Gaudet, V.C.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2010},
+  Number                   = {3},
+  Pages                    = {482-489},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/TVLSI.2008.2011360},
+  ISSN                     = {1063-8210},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.04.24}
+}
+
+@InProceedings{onu_07,
+  Title                    = {{S}tall-{T}ime {F}air {M}emory {A}ccess {S}cheduling for {C}hip {M}ultiprocessors},
+  Author                   = {Onur Mutlu, Thomas Moscibroda},
+  Booktitle                = {40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
+  Year                     = {2007},
+  Month                    = {December},
+  Publisher                = {IEEE},
+
+  Abstract                 = {DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory access scheduling techniques try to optimize the overall data throughput obtained from the DRAM and thus do not take into account inter-thread interference.
+Therefore, different threads running together on the same chip can experience extremely different memory system performance: one thread can experience a severe slowdown or starvation while another is unfairly prioritized by the memory scheduler. This paper proposes a new memory access scheduler, called the Stall-Time Fair Memory scheduler (STFM), that provides quality of service to different threads sharing the DRAM memory system. The goal of the proposed scheduler is to “equalize” the DRAM-related slowdown experienced by each thread due to interference from other threads, without hurting overall system performance. As such, STFM takes into account inherent memory characteristics of each thread and does not unfairly penalize threads that use the DRAM system without interfering with other threads. 
+We show that STFM significantly reduces the unfairness in the DRAM system while also improving system throughput (i.e., weighted speedup of threads) on a wide variety of workloads and systems. For example, averaged over 32 different workloads running on an 8-core CMP, the ratio between the highest DRAM-related slowdown and the lowest DRAM-related slowdown reduces from 5.26X to 1.4X, while the average system throughput improves by 7.6%. We qualitatively and quantitatively compare STFM to one new and three previouslyproposed memory access scheduling algorithms, including network fair queueing. Our results show that STFM provides the best fairness, system throughput, and scalability.
+},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-02},
+  Url                      = {https://www.microsoft.com/en-us/research/publication/stall-time-fair-memory-access-scheduling-for-chip-multiprocessors/}
+}
+
+@Article{ony_91,
+  Title                    = {{Truncation Length for Viterbi Decoding}},
+  Author                   = {Onyszchuk, I. M.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1991},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {1023--1026},
+  Volume                   = {39},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{onyche_93,
+  Title                    = {{Quantization Loss in Convolutional Decoding}},
+  Author                   = {Onyszchuk, I. M. and Cheung, K.-M. and O. Collins},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1993},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {261--265},
+  Volume                   = {41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{oomrav_15,
+  Title                    = {{FPGA} implementation of an advanced encoding and decoding architecture of polar codes},
+  Author                   = {M. S. Oommen and S. Ravishankar},
+  Booktitle                = {VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on},
+  Year                     = {2015},
+  Month                    = {Jan},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/VLSI-SATA.2015.7050456},
+  Keywords                 = {block codes;error correction codes;error statistics;field programmable gate arrays;Erdal Arikan;FPGA platform implementation;Xilinx virtex VI;advanced encoding and decoding architecture;belief propagation;bit error rate;hardware architecture efficient;information theory community;linear block error correcting code;list successive cancellation;polar codes;resource utilization;successive cancellation decoder;symmetric binary memory less channels;Complexity theory;Decoding;Manganese;Parity check codes;Table lookup;FPGA;LDPC;LUT;RAM;channel polarization;code tree;polar code;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Book{Oppenheim1979,
+  Title                    = {{D}igital {S}ignal {P}rocessing},
+  Author                   = {A.V. Oppenheim and R.W. Schafer},
+  Publisher                = {Prentice-Hall, Englewood Cliffs},
+  Year                     = {1979},
+
+  Address                  = {NJ},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.02.26}
+}
+
+@Misc{or-fpga14,
+  Title                    = {{FPGA} as {ASIC} {A}lternative: {P}ast and {F}uture},
+
+  Author                   = {Zvi Or-Bach},
+  HowPublished             = {\url{http://www.monolithic3d.com/blog/fpga-as-asic-alternative-past-and-future}},
+  Month                    = apr,
+  Note                     = {last access 2015-02-13},
+  Year                     = {2014},
+
+  Cds_keywords             = {ASIC FPGA cost},
+  File                     = {or-fpga14.pdf:or-fpga14.pdf:PDF},
+  Owner                    = {CDS},
+  Timestamp                = {2015-02-13}
+}
+
+@Article{osb_53,
+  Title                    = {{A}pplied imagination.},
+  Author                   = {Osborn, Alex F},
+  Year                     = {1953},
+
+  Owner                    = {Brugger},
+  Publisher                = {Scribner's},
+  Timestamp                = {2015.06.22}
+}
+
+@PhdThesis{Phdoster01,
+  Title                    = {{Bei Beitrag zur Interzellinterferenzreduktion in zeitgeschlitzten CDMA-Systemen}},
+  Author                   = {J. Oster},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2001},
+  Note                     = {ISBN 3-925178-73-2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{Ostermann2004,
+  Title                    = {{V}ideo coding with {H}.264/{AVC}: {T}ools, {P}erformance, and {C}omplexity},
+  Author                   = {Ostermann, J. and Bormans, J. and List, P. and Marpe, D. and Narroschke, M. and Pereira, F. and Stockhammer, T. and Wedi, T.},
+  Journal                  = {Circuits and Systems Magazine, IEEE},
+  Year                     = {2004},
+
+  Month                    = jan # {--} # mar,
+  Number                   = {1},
+  Pages                    = { 7-28},
+  Volume                   = {4},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {H.264/AVC},
+  Cds_read                 = {2008-05},
+  Date-added               = {2008-10-15 10:41:24 +0200},
+  Date-modified            = {2008-10-15 10:42:14 +0200},
+  Doi                      = {10.1109/MCAS.2004.1286980},
+  File                     = {ostbor_04.pdf:ostbor_04.pdf:PDF},
+  ISSN                     = {1531-636X},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{oupan_12,
+  Title                    = {{E}nergy- and {C}ost-{E}fficiency {A}nalysis of {ARM}-{B}ased {C}lusters},
+  Author                   = {Zhonghong Ou and Bo Pang and Yang Deng and Nurminen, J.K. and Ylä-Jääski, A. and Pan Hui},
+  Booktitle                = {Cluster, Cloud and Grid Computing (CCGrid), 2012 12th IEEE/ACM International Symposium on},
+  Year                     = {2012},
+  Month                    = may,
+  Pages                    = {115--123},
+
+  Abstract                 = {General-purpose computing domain has experienced strategy transfer from scale-up to scale-out in the past decade. In this paper, we take a step further to analyze ARM-processor based cluster against Intel X86 workstation, from both energy-efficiency and cost-efficiency perspectives. Three applications are selected and evaluated to represent diversified applications, including Web server throughput, in-memory database, and video transcoding. Through detailed measurements, we make the observations that the energy-efficiency ratio of the ARM cluster against the Intel workstation varies from 2.6-9.5 in in-memory database, to approximately 1.3 in Web server application, and 1.21 in video transcoding. We also find out that for the Intel processor that adopts dynamic voltage and frequency scaling (DVFS) techniques, the power consumption is not linear with the CPU utilization level. The maximum energy saving achievable from DVFS is 20%. Finally, by utilizing a monthly cost model of data centers, we conclude that ARM cluster based data centers are feasible, and are advantageous in computationally lightweight applications, e.g. in-memory database and network-bounded Web applications. The cost advantage of ARM cluster diminishes progressively for computation-intensive applications, i.e. dynamic Web server application and video transcoding, because the number of ARM processors needed to provide comparable performance increases.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/CCGrid.2012.84},
+  File                     = {oupan_12.pdf:oupan_12.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@InProceedings{Ould-Cheikh-Mouhamedou2006,
+  Title                    = {{A} {M}ethod for {L}owering {T}urbo {C}ode {E}rror {F}lare using {C}orrection {I}mpulses and {R}epeated {D}ecoding},
+  Author                   = {Ould-Cheikh-Mouhamedou, Youssouf and Crozier, Stewart and Gracie, Ken and Guinand, Paul and Kabal, Peter},
+  Booktitle                = {4th International Symposium on Turbo Codes Related Topics; 6th International ITG-Conference on Source and Channel Coding (TURBOCODING), 2006},
+  Year                     = {2006},
+
+  Address                  = {Munich, Germany},
+  Month                    = {April},
+  Pages                    = {1-6},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.04.22}
+}
+
+@InProceedings{oco_16,
+  Title                    = {{W}ill current memories be replaced by new emerging {NV} memories? {W}hen and which ones? {A}nd for which applications?},
+  Author                   = {O’Connor, Ian},
+  Booktitle                = {1st Intl. Workshop on Emerging Memory Solutions, DATE Conference 2016, Dresden, Germany},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-08-17}
+}
+
+@Article{paafle_98,
+  Title                    = {{E}fficient multiplier architectures for {G}alois fields {GF}(24n )},
+  Author                   = {Paar, C. and Fleischmann, P. and Roeise, P.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {1998},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {162-170},
+  Volume                   = {47},
+
+  Abstract                 = {This contribution introduces a new class of multipliers for finite fields GF((2n)4). The architecture is based on a modified version of the Karatsuba-Ofman algorithm (KOA). By determining optimized field polynomials of degree four, the last stage of the KOA and the module reduction can be combined. This saves computation and area in VLSI implementations. The new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with KOA-based architectures with separate module reduction. The new multipliers lead to highly modular architectures and are, thus, well suited for VLSI implementations. Three types of field polynomials are introduced and conditions for their existence are established. For the small fields, where n=2,3,...,8, which are of primary technical interest, optimized field polynomials were determined by an exhaustive search. For each field order, exact space and time complexities are provided},
+  Cds_grade                = {0},
+  Cds_keywords             = {Galois field multiplier, FFM, VLSI},
+  Doi                      = {10.1109/12.663762},
+  File                     = {paafle_98.pdf:paafle_98.pdf:PDF},
+  ISSN                     = {0018-9340},
+  Keywords                 = {Galois fields, computational complexity, digital arithmeticGalois fields, Karatsuba-Ofman algorithm, VLSI architecture, VLSI implementations, bit parallel, complexities, composite fields, exhaustive search, field polynomials, finite fields, modulo reduction, multiplication, multiplier architectures, multipliers},
+  Owner                    = {CdS},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{paalan_95,
+  Title                    = {{A} {C}omparative {VLSI} {S}ynthesis of {F}inite {F}ield {M}ultipliers},
+  Author                   = {Christof Paar and Nikolaus Lange},
+  Booktitle                = {Proceedings of the 3rd International Symposium on Communication Theory \& Applications},
+  Year                     = {1995},
+  Month                    = jul,
+
+  Cds_grade                = {3},
+  Cds_keywords             = {Galois field multiplier, FFM, FPGA},
+  Cds_read                 = {2009-10-27},
+  Cds_review               = {only synthesis results, no architectures explained},
+  File                     = {paalan_95.pdf:paalan_95.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.03.17}
+}
+
+@Conference{paaros_97,
+  Title                    = {{C}omparison of arithmetic architectures for {R}eed-{S}olomon decoders inreconfigurable hardware},
+  Author                   = {Christof Paar and Martin Rosner},
+  Booktitle                = {FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on},
+  Year                     = {1997},
+  Pages                    = {219--225},
+
+  Cds_grade                = {0},
+  Cds_review               = {focus on GF multiplication and inversion on reconfigurable hardware (FPGA)
+compares standard base representation against composite field mult. / inversion},
+  File                     = {paaros_97.pdf:paaros_97.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.03.17}
+}
+
+@Article{paaped_91,
+  Title                    = {{An Area-Efficient Path Memory Structure for VLSI Implementation of High Speed Viterbi Decoders}},
+  Author                   = {E. Paaske and S. Pedersen and J. Sparso},
+  Journal                  = {INTEGRATION, the VLSI Journal},
+  Year                     = {1991},
+
+  Month                    = nov,
+  Number                   = {2},
+  Pages                    = {79--91},
+  Volume                   = {12},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{pa,
+  Author                   = {{PACT XPP Technologies}},
+  HowPublished             = {{{www.pactcorp.com}}},
+
+  Key                      = {PACT},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{PACTXPPT,
+  Author                   = {{PACT XPP Technologies}},
+  HowPublished             = {{{www.pactcorp.com}}},
+
+  Key                      = {PACT},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{pagcha_98,
+  Title                    = {{Improved Architectures for the Add-Compare-Select Operation in Long Constraint Length Viterbi Decoding}},
+  Author                   = {K. Page and Chau, P. M.},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {1998},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {151--155},
+  Volume                   = {33},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{pakeck_10,
+  Title                    = {{A} low cost multi-standard near-optimal soft-output sphere decoder: {A}lgorithm and architecture},
+  Author                   = {Paker, O. and Eckert, S. and Bury, A.},
+  Booktitle                = {Design, Automation Test in Europe Conference Exhibition (DATE), 2010},
+  Year                     = {2010},
+  Pages                    = {1402-1407},
+
+  Doi                      = {10.1109/DATE.2010.5457032},
+  File                     = {pakeck_10.pdf:pakeck_10.pdf:PDF},
+  ISSN                     = {1530-1591},
+  Keywords                 = {MIMO communication;OFDM modulation;decoding;quadrature amplitude modulation;quadrature phase shift keying;table lookup;wireless LAN;BPSK;CMOS technology;Euclidean distances;IEEE 802.11n;MIMO-OFDM reception;QAM;QPSK;WLAN;WiMax;frequency 312 MHz;low cost multistandard near-optimal soft-output sphere decoder;modulation schemes;symbol enumeration;table look-up approach;CMOS technology;Clocks;Computer architecture;Costs;Decoding;Delay;Hardware;Quadrature amplitude modulation;Throughput;Wireless LAN},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.03.27}
+}
+
+@Article{pal_05,
+  Title                    = {{E}nergy {A}ware {C}omputing through {P}robabilistic {S}witching: {A} {S}tudy of {L}imits},
+  Author                   = {Palem, K. V.},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2005},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {1123--1137},
+  Volume                   = {54},
+
+  Doi                      = {10.1109/TC.2005.145},
+  File                     = {pal_05.pdf:pal_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.20}
+}
+
+@InProceedings{pal_03,
+  Title                    = {{E}nergy aware algorithm design via probabilistic computing: from algorithms and models to {M}oore's law and novel (semiconductor) devices},
+  Author                   = {Palem, Krishna V.},
+  Booktitle                = {Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems},
+  Year                     = {2003},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {113--116},
+  Publisher                = {ACM},
+  Series                   = {CASES '03},
+
+  Acmid                    = {951712},
+  Doi                      = {http://doi.acm.org/10.1145/951710.951712},
+  File                     = {pal_03.pdf:pal_03.pdf:PDF},
+  ISBN                     = {1-58113-676-5},
+  Location                 = {San Jose, California, USA},
+  Numpages                 = {4},
+  Url                      = {http://doi.acm.org/10.1145/951710.951712}
+}
+
+@Article{Palmer1974,
+  Title                    = {{C}oarse frequency estimation using the discrete {F}ourier transform ({C}orresp.)},
+  Author                   = {Palmer, L.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1974},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {104-109},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/TIT.1974.1055156},
+  ISSN                     = {0018-9448},
+  Keywords                 = {DFT;Discrete Fourier transforms (DFT's);Frequency estimation;Parameter estimation;Computer simulation;Discrete Fourier transforms;Discrete transforms;Estimation error;Frequency estimation;Frequency measurement;Gaussian noise;Maximum likelihood estimation;Phase estimation;Signal processing},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27}
+}
+
+@InProceedings{panbag_03,
+  Title                    = {{Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver}},
+  Author                   = {Chengzhi Pan and Bagherzadeh, N. and Kamalizad, A.H. and Koohi, A.},
+  Booktitle                = {Design, Automation and Test in Europe Conference and Exhibition, 2003},
+  Year                     = {2003},
+  Pages                    = {468--473},
+
+  Doi                      = {10.1109/DATE.2003.1253653},
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.27}
+}
+
+@InProceedings{pan_01,
+  Title                    = {{SystemC - A Modeling Platform Supporting Multiple Design Abstractions}},
+  Author                   = {P.R. Panda},
+  Booktitle                = {Proceedings of the 14th International Symposium on System Synthesis, 2001 },
+  Year                     = {2001},
+  Pages                    = {75--80},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{pandut_96,
+  Title                    = {{Reducing Address Bus Transitions for Low Power Memory Mapping}},
+  Author                   = {P. R. Panda and N. D. Dutt},
+  Booktitle                = {{Proc. 1996 Design, Automation and Test in Europe (DATE '96)}},
+  Year                     = {1996},
+  Month                    = mar,
+  Pages                    = {63--67},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{panle_06,
+  Title                    = {{I}mproved long-period generators based on linear recurrences modulo 2},
+  Author                   = {Panneton, Fran\c{c}ois and L'Ecuyer, Pierre and Matsumoto, Makoto},
+  Journal                  = {ACM Trans. Math. Softw.},
+  Year                     = {2006},
+
+  Month                    = mar,
+  Number                   = {1},
+  Pages                    = {1--16},
+  Volume                   = {32},
+
+  Acmid                    = {1132974},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation, uniform distribution, WELL},
+  Doi                      = {10.1145/1132973.1132974},
+  File                     = {panle_06.pdf:panle_06.pdf:PDF},
+  ISSN                     = {0098-3500},
+  Issue_date               = {March 2006},
+  Keywords                 = {finance},
+  Numpages                 = {16},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2012.03.26},
+  Url                      = {http://doi.acm.org/10.1145/1132973.1132974}
+}
+
+@InProceedings{pangop_15,
+  Title                    = {{T}owards {P}ractical {P}age {P}lacement for a {G}reen {M}emory {M}anager},
+  Author                   = {A. Panwar and K. Gopinath},
+  Booktitle                = {2015 IEEE 22nd International Conference on High Performance Computing (HiPC)},
+  Year                     = {2015},
+  Month                    = {Dec},
+  Pages                    = {155-164},
+
+  Doi                      = {10.1109/HiPC.2015.42},
+  Keywords                 = {Linux;green computing;paged storage;power aware computing;storage management;Linux VM;Linux memory manager;bank awareness;buddy allocation framework;dynamic voltage-frequency scaling;green memory manager;hardware facilitated partial array self-refresh;memory power optimization;memory-hotplug framework;page migration techniques;physical memory banks;practical page placement;random page allocation;Hardware;Kernel;Linux;Memory management;Optimization;Power demand;Resource management;Buddy Allocator;Memory Power;Memory-Hotplug},
+  Owner                    = {EFZ},
+  Timestamp                = {2016-08-22}
+}
+
+@InProceedings{papbou_09,
+  Title                    = {{P}erformance comparison of {GPU} and {FPGA} architectures for the {SVM} training problem},
+  Author                   = {Papadonikolakis, M. and Bouganis, C. and Constantinides, G.},
+  Booktitle                = {Field-Programmable Technology, 2009. FPT 2009. International Conference on},
+  Year                     = {2009},
+  Pages                    = {388-391},
+
+  Abstract                 = {The Support Vector Machine (SVM) is a popular supervised learning method, providing high accuracy in many classification and regression tasks. However, its training phase is a computationally expensive task. In this work, we focus on the acceleration of this phase and a geometric approach to SVM training based on Gilbert's Algorithm is targeted, due to the high parallelization potential of its heavy computational tasks. The algorithm is mapped on two of the most popular parallel processing devices, a Graphics Processor and an FPGA device. The evaluation analysis points out the best choice under different configurations. The final speed up depends on the problem size, when no chunking techniques are applied to the training set, achieving the largest speed up for small problem sizes.},
+  Cds_grade                = {2},
+  Cds_keywords             = {GPU, FPGA},
+  Cds_read                 = {2011-11-11},
+  Cds_review               = {- no matching algorithms
+- no energy numbers
++ speed numbers},
+  Doi                      = {10.1109/FPT.2009.5377653},
+  File                     = {papbou_09.pdf:papbou_09.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@InProceedings{paprob_96,
+  Title                    = {{Improved Decoding with the SOVA in a Parallel Concatenated (Turbo-code) Scheme}},
+  Author                   = {L. Papke and P. Robertson and E. Villebrun},
+  Booktitle                = {Proc. 1996 International Conference on Communications (ICC '96)},
+  Year                     = {1996},
+  Pages                    = {102--106},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{pappil_02,
+  Title                    = {{P}robability, random variables, and stochastic processes},
+  Author                   = {Papoulis, A. and Pillai, S.U.},
+  Publisher                = {McGraw-Hill},
+  Year                     = {2002},
+  Series                   = {McGraw-Hill electrical and electronic engineering series},
+
+  ISBN                     = {9780073660110},
+  Lccn                     = {01044139},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.05.15},
+  Url                      = {http://books.google.de/books?id=YYwQAQAAIAAJ}
+}
+
+@Article{par_04,
+  Title                    = {{A}n improved pipelined {MSB}-first add-compare select unit structure for {V}iterbi decoders},
+  Author                   = {K. K. Parhi},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2004},
+
+  Month                    = {March},
+  Number                   = {3},
+  Pages                    = {504-511},
+  Volume                   = {51},
+
+  Doi                      = {10.1109/TCSI.2004.823657},
+  File                     = {par_04.pdf:par_04.pdf:PDF},
+  ISSN                     = {1549-8328},
+  Keywords                 = {Viterbi decoding;convolutional codes;logic circuits;pipeline arithmetic;communication systems;convolutional codes;critical path length;error-control performance;high-data-rate applications;high-speed Viterbi decoders;iteration bound;most-significant-bit first bit-level pipelined add-compare select unit structure;pipelined MSB-first add-compare select unit structure;Arithmetic;Convolutional codes;Feedback loop;Hardware;Helium;Iterative decoding;Parallel processing;Pipeline processing;Viterbi algorithm},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.18}
+}
+
+@Article{parkim_09,
+  Title                    = {{D}esign of a low-area, high-throughput {LDPC} decoder using shared memory banks for {DVB}-{S}2},
+  Author                   = {Chang-Soo Park and Seong-Woon Kim and Sun-Young Hwang},
+  Journal                  = {IEEE Transactions on Consumer Electronics},
+  Year                     = {2009},
+
+  Month                    = may,
+  Number                   = {2},
+  Pages                    = {850--854},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCE.2009.5174465},
+  File                     = {parkim_09.pdf:parkim_09.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.08.20}
+}
+
+@Article{parkan_07,
+  Title                    = {{E}fficient {P}uncturing {M}ethod for {R}ate-{C}ompatible {L}ow-{D}ensity {P}arity-{C}heck {C}odes},
+  Author                   = {Hyo Yol Park and Jae Won Kang and Kwang Soon Kim and Keum Chan Whang},
+  Journal                  = {Wireless Communications, IEEE Transactions on},
+  Year                     = {2007},
+  Number                   = {11},
+  Pages                    = {3914-3919},
+  Volume                   = {6},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Unpublished{parcho_10,
+  Title                    = {{A} {P}rogrammable {H}.264 {CABAC} {D}ecoder using a {RISC} {P}rocessor and {T}wo {C}oupled {A}pplication-{S}pecific {VLIW} {P}rocessors},
+  Author                   = {Jason Jong Kyu Park and Soonwoo Choi and Daewoong Kim and Soo-Ik Chae},
+
+  Month                    = {April},
+  Year                     = {2010},
+
+  Abstract                 = {High-definition video applications are getting popular because of the recent advance in display technologies. Their video codecs require huge computation capability and large memory bandwidth. It is highly recommended that the video codecs provide enough flexibility to support various video formats available in the market. In this paper, we describe a programmable H.264 CABAC decoder that employs a general-purpose RISC processor and two tightly-coupled application-specific VLIW processors. Each application-specific processor is responsible for context selection and bin decoding, respectively, and supports condition-controlled instructions each of which represents an if-else construct that is composed of a true execution, a false execution, and a simple condition. We are currently in the process of implementing a parser that can decode H.264 720p 30 fps with the operating frequency of less than 200MHz. In addition, the parser includes SRAM blocks of 20 KB.},
+  Cds_grade                = {5},
+  Cds_keywords             = {H.264, AVC, video, decoder, ASIP, implementation, architecture},
+  Cds_read                 = {2010-04-26},
+  Cds_review               = {Your paper is well-structured and clearly points out what you've done and why. You give a good introduction of your design flow and what CCI instructions are and how they work. I could understand the special commands you added to the control and the bin-decoding processor; the provided implementation details are sufficient, I think. Results are well-elaborated and presented in a clear way.
+
+There are some faults in the paper: The first word in the introduction is IN and should be In and 1080p is 1920x1080 (not 1088). In section 2c you should refer to the tables more precisely in my opinion.
+
+Altogether a very good paper providing enough implementation details and results that perfectly fits into this conference.},
+  File                     = {parcho_10.pdf:parcho_10.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.04.26}
+}
+
+@InProceedings{Park2007,
+  Title                    = {{A}n {E}fficient {D}ata-{A}ided {I}nitial {F}requency {S}ynchronizer for {DVB}-{S}2},
+  Author                   = {Jang Woong Park and Myung Hoon Sunwoo and Pan Soo Kim and Dae Ig Chang},
+  Booktitle                = {Signal Processing Systems, 2007 IEEE Workshop on},
+  Year                     = {2007},
+  Month                    = {Oct},
+  Pages                    = {645-650},
+
+  Doi                      = {10.1109/SIPS.2007.4387625},
+  ISSN                     = {1520-6130},
+  Keywords                 = {Algorithm design and analysis;Demodulation;Digital video broadcasting;Frequency estimation;Frequency synchronization;Hardware;Phase estimation;Satellite broadcasting;Signal processing algorithms;Timing;Auto correlation;Data-aided (DA) algorithm;Demodulator;Digitial Video Broadcasting - Satellite sencond generation (DVB-S2);Initial frequency offset estimator;Modem},
+  Owner                    = {ali},
+  Timestamp                = {2015.03.26}
+}
+
+@InProceedings{parsun_08,
+  Title                    = {{L}ow complexity soft-decision demapper for high order modulation of {DVB}-{S}2 system},
+  Author                   = {Jang Woong Park and Myung Hoon Sunwoo and Pan Soo Kim and Dae-Ig Chang},
+  Booktitle                = {International SoC Design Conference (ISOCC '08)},
+  Year                     = {2008},
+  Month                    = {Nov},
+  Pages                    = {II-37-II-40},
+  Volume                   = {02},
+
+  Keywords                 = {communication complexity;convertors;digital video broadcasting;direct broadcasting by satellite;phase shift keying;DVB-S2 system;FPGA board;M-PSK demodulator;digital video broadcasting via satellite;high-order modulation modes;low complexity soft-decision demapper;parallel to serial converter;symbol rate;AWGN;Bit error rate;Computer interfaces;Digital video broadcasting;Forward error correction;Hardware;Parity check codes;Quadrature phase shift keying;Satellite broadcasting;Transponders;DVB-S2;LDPC;LLR;M-PSK;soft-decision demapper}
+}
+
+@Proceedings{Park2008,
+  Title                    = {{E}fficient coarse frequency synchronizer using serial correlator for {DVB}-{S}2},
+  Year                     = {2008},
+  Month                    = {May},
+
+  Author                   = {Jang Woong Park and Hyoung Jin Yun and Myung Hoon Sunwoo and Pansoo Kim and Dae Ig Chang},
+  Booktitle                = {IEEE International Symposium on Circuits and Systems},
+  Doi                      = {10.1109/ISCAS.2008.4541719},
+  Keywords                 = {adders;computational complexity;digital video broadcasting;field programmable gate arrays;frequency estimation;Luise & Reggiannini algorithm;Xilinx Virtex II FPGA;adders;coarse frequency estimator;coarse frequency synchronizer;data-aided approaches;digital video broadcasting second generation;frequency 1.5625 MHz to -1.5625 MHz;multipliers;robust algorithm;serial correlator;Algorithm design and analysis;Computer architecture;Correlators;Digital video broadcasting;Frequency estimation;Frequency synchronization;Hardware;Multiplexing;Performance analysis;Robustness},
+  Owner                    = {ali},
+  Pages                    = {1520-1523},
+  Timestamp                = {2015.03.06}
+}
+
+@Article{parlim_16,
+  Title                    = {{E}xperiments and root cause analysis for active-precharge hammering fault in {DDR}3 {SDRAM} under 3x nm technology},
+  Author                   = {Kyungbae Park and Chulseung Lim and Donghyuk Yun and Sanghyeon Baeg},
+  Journal                  = {Microelectronics Reliability },
+  Year                     = {2016},
+  Pages                    = {39 - 46},
+  Volume                   = {57},
+
+  Abstract                 = {Abstract This paper investigates the failure mechanism manifested in \{DDR3\} \{SDRAMs\} under 3 × nm technology. \{DRAM\} cells should retain the stored value if they are refreshed within the cell retention time of 64 ms at minimum. However the charge in a \{DRAM\} cell leaked faster, and the values of the stressed cells could not be retained with valid yet stressful hammered accesses to a row. An experiment of accelerated discharging by hammered accesses was duplicated by a \{SPICE\} simulation with a \{TCAD\} device model of a \{DRAM\} cell. Experiments with commercial \{DDR3\} discrete components from three major memory manufacturers were performed to confirm the validity of the \{SPICE\} simulation. The contributions of each in triggering and accelerating the failure mechanisms are investigated depending on the three test parameters—tRP, data pattern, and temperature—based on the experimental results. In the experiments, all commercial \{DDR3\} components failed much earlier than the specified limit of allowed accesses. In the worst condition, the failure in a normal cell of a component occurred at 200 K, which is 15.23% of the permitted cell retention time. },
+  Doi                      = {http://dx.doi.org/10.1016/j.microrel.2015.12.027},
+  ISSN                     = {0026-2714},
+  Keywords                 = {Active-precharge hammering on a row fault},
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-25},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0026271415302742}
+}
+
+@InProceedings{par_15,
+  Title                    = {{T}echnology {S}caling {C}hallenge and {F}uture {P}rospects of {DRAM} and {NAND} {F}lash {M}emory},
+  Author                   = {S. K. Park},
+  Booktitle                = {2015 IEEE International Memory Workshop (IMW)},
+  Year                     = {2015},
+
+  Owner                    = {DMM},
+  Timestamp                = {2017-09-12}
+}
+
+@InProceedings{parkim_00,
+  Title                    = {{Transmission Power Allocation in Turbo Codes}},
+  Author                   = {S.-J. Park and S. W. Kim},
+  Booktitle                = {Proc. 2000-Spring Vehicular Technology Conference (VTC 2000 Spring)},
+  Year                     = {2000},
+
+  Address                  = {Tokyo, Japan},
+  Month                    = may,
+  Pages                    = {2073--2075},
+  Volume                   = {3},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{par_15a,
+  Title                    = {{T}echnology scaling challenge and future prospects of {DRAM} and {NAND} flash memory},
+  Author                   = {Park, Sung-Kye},
+  Year                     = {2015},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-21}
+}
+
+@InProceedings{Park2010,
+  Title                    = {{P}erformance analysis of {T}urbo {P}hi codes with m=3},
+  Author                   = {T. Park and M. Kim and C. Kim and J. Jung},
+  Booktitle                = {12th IEEE International Conference on Communication Technology},
+  Year                     = {2010},
+
+  Address                  = {Ibaraki, Japan},
+  Month                    = {Nov},
+  Pages                    = {1457-1459},
+
+  Doi                      = {10.1109/ICCT.2010.5688979},
+  Keywords                 = {binary codes;channel coding;digital video broadcasting;direct broadcasting by satellite;error statistics;turbo codes;bit error rates;channel coding;double binary turbo codes;next generation DVB-RCS system;permutation patterns;puncturing patterns;return channel via satellite;triple binary turbo codes;turbo φ codes;Convolution;Digital video broadcasting}
+}
+
+@InProceedings{partao_14,
+  Title                    = {{A} 4.68{G}b/s belief propagation polar decoder with bit-splitting register file},
+  Author                   = {Youn Sung Park and Yaoyu Tao and Shuanghong Sun and Zhengya Zhang},
+  Booktitle                = {2014 Symposium on VLSI Circuits Digest of Technical Papers},
+  Year                     = {2014},
+  Month                    = {June},
+  Pages                    = {1-2},
+
+  Doi                      = {10.1109/VLSIC.2014.6858413},
+  File                     = {partao_14.pdf:partao_14.pdf:PDF},
+  ISSN                     = {2158-5601},
+  Keywords                 = {CMOS logic circuits;decoding;flip-flops;CMOS process;belief propagation polar decoder;bit rate 4.68 Gbit/s;bit rate 780 Mbit/s;bit-splitting latch-based register file;double-column 1024-parallel architecture;power 478 mW;size 65 nm;storage capacity 45 Kbit;voltage 1.0 V;voltage 475 mV;word length 1024 bit;AWGN;Abstracts;Decoding;Registers;Routing;Schedules;Semiconductor device measurement},
+  Owner                    = {MH},
+  Timestamp                = {2017-05-22}
+}
+
+@Article{partao_15,
+  Title                    = {{A} {F}ully {P}arallel {N}onbinary {LDPC} {D}ecoder {W}ith {F}ine-{G}rained {D}ynamic {C}lock {G}ating},
+  Author                   = {Youn Sung Park and Yaoyu Tao and Zhengya Zhang},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2015},
+  Number                   = {2},
+  Pages                    = {464--475},
+  Volume                   = {50},
+
+  Doi                      = {10.1109/JSSC.2014.2362854},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.10.20},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6955861}
+}
+
+@InProceedings{patcha_97,
+  Title                    = {{Power Constrained Design of Multiprocessor Interconnection Networks}},
+  Author                   = {C.S. Patel and S.M. Chai and S. Yalamanchili and D.E. Schimmel},
+  Booktitle                = {IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1997 (ICCD '97)},
+  Year                     = {1997},
+  Pages                    = {408--416},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{patben_05,
+  Title                    = {{E}nergy-{E}fficient {V}alue-{B}ased {S}elective {R}efresh for {E}mbedded {DRAM}s},
+  Author                   = {Patel, K. and Benini, L. and Macii, Enrico and Poncino, Massimo},
+  Booktitle                = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2005},
+  Editor                   = {Paliouras, Vassilis and Vounckx, Johan and Verkest, Diederik},
+  Pages                    = {466-476},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {3728},
+
+  Doi                      = {10.1007/11556930_48},
+  ISBN                     = {978-3-540-29013-1},
+  Language                 = {English},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10},
+  Url                      = {http://dx.doi.org/10.1007/11556930_48}
+}
+
+@InProceedings{patkim_17,
+  Title                    = {{T}he {R}each {P}rofiler ({REAPER}): {E}nabling the {M}itigation of {DRAM} {R}etention {F}ailures via {P}rofiling at {A}ggressive {C}onditions},
+  Author                   = {Patel, Minesh and Kim, Jeremie S. and Mutlu, Onur},
+  Booktitle                = {Proceedings of the 44th Annual International Symposium on Computer Architecture},
+  Year                     = {2017},
+
+  Owner                    = {DMM},
+  Timestamp                = {2017-09-12}
+}
+
+@InBook{patpol_12,
+  Title                    = {{A} {C}oding-{T}heoretic {A}pproach to {R}ecovering {N}oisy {RSA} {K}eys},
+  Author                   = {Paterson, Kenneth G.
+and Polychroniadou, Antigoni
+and Sibborn, Dale L.},
+  Pages                    = {386--403},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2012},
+
+  Address                  = {Berlin, Heidelberg},
+
+  Abstract                 = {Inspired by cold boot attacks, Heninger and Shacham (Crypto 2009) initiated the study of the problem of how to recover an RSA private key from a noisy version of that key. They gave an algorithm for the case where some bits of the private key are known with certainty. Their ideas were extended by Henecka, May and Meurer (Crypto 2010) to produce an algorithm that works when all the key bits are subject to error. In this paper, we bring a coding-theoretic viewpoint to bear on the problem of noisy RSA key recovery. This viewpoint allows us to cast the previous work as part of a more general framework. In turn, this enables us to explain why the previous algorithms do not solve the motivating cold boot problem, and to design a new algorithm that does (and more). In addition, we are able to use concepts and tools from coding theory -- channel capacity, list decoding algorithms, and random coding techniques -- to derive bounds on the performance of the previous and our new algorithm.},
+  Booktitle                = {Advances in Cryptology -- ASIACRYPT 2012: 18th International Conference on the Theory and Application of Cryptology and Information Security, Beijing, China, December 2-6, 2012. Proceedings},
+  Doi                      = {10.1007/978-3-642-34961-4_24},
+  ISBN                     = {978-3-642-34961-4},
+  Owner                    = {MJ},
+  Timestamp                = {2017-09-11},
+  Url                      = {https://doi.org/10.1007/978-3-642-34961-4_24}
+}
+
+@Electronic{pat_16,
+  Title                    = {{E}ricsson {M}obility {R}eport {N}ovember 2016},
+
+  Address                  = {https://www.ericsson.com/assets/local/mobility-report/documents/2016/ericsson-mobility-report-november-2016.pdf},
+  Author                   = {Patrik Cerwall, Stephen Carson, Anette Lundvall},
+  Year                     = {2016},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.02.28}
+}
+
+@Article{pat_04,
+  Title                    = {{L}atency {L}ags {B}andwith},
+  Author                   = {Patterson, David A.},
+  Journal                  = {Commun. ACM},
+  Year                     = {2004},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {71--75},
+  Volume                   = {47},
+
+  Acmid                    = {1022596},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/1022594.1022596},
+  ISSN                     = {0001-0782},
+  Issue_date               = {October 2004},
+  Numpages                 = {5},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2018-05-03},
+  Url                      = {http://doi.acm.org/10.1145/1022594.1022596}
+}
+
+@Book{pathen_09,
+  Title                    = {{C}omputer {O}rganization and {D}esign},
+  Author                   = {David A. Patterson and John Hennessy},
+  Editor                   = {4},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2009},
+  Edition                  = {4},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.05.23}
+}
+
+@Book{pathen_04,
+  Title                    = {{C}omputer {O}rganization and {D}esign},
+  Author                   = {David A. Patterson and John Hennessy},
+  Publisher                = {Morgan Kaufmann Publishers Inc.},
+  Year                     = {2004},
+
+  Address                  = {San Francisco, CA, USA},
+  Edition                  = {3rd},
+
+  Date-added               = {2008-07-10 10:16:23 +0200},
+  Date-modified            = {2008-07-10 10:16:37 +0200},
+  ISBN                     = {1558606041},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{paubal_04,
+  Title                    = {{Panel: ``Chips of the Future: Soft, Crunchy or Hard?''}},
+  Author                   = {P. Paulin and J.-M. Balzano and A. Silburt and K. Van Berkel and R. Bramley and N. Wehn},
+  Booktitle                = {Proc. 2004 Design Automation and Test in Europe (DATE '04)},
+  Year                     = {2004},
+
+  Address                  = {Paris, France},
+  Month                    = feb,
+  Pages                    = {844--849},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{paunab_03,
+  Title                    = {{I}ntroduction to {S}pace-{T}ime {W}ireless {C}ommunications},
+  Author                   = {Paulraj, A. and Nabar, R. and Gore, D.},
+  Publisher                = {Cambridge University Press},
+  Year                     = {2003},
+
+  Address                  = {Cambridge, UK},
+
+  ISBN                     = {9780521826150},
+  Lccn                     = {2004296611},
+  Url                      = {http://books.google.co.uk/books?id=YQSsoPDfyngC}
+}
+
+@Article{paugor_04,
+  Title                    = {{A}n {O}verview of {MIMO} {C}ommunications -- a {K}ey to {G}igabit {W}ireless},
+  Author                   = {Paulraj, A. J. and Gore, D. A. and Nabar, R. U. and B\"olcskei, H.},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2004},
+  Number                   = {2},
+  Pages                    = {198--218},
+  Volume                   = {92},
+
+  Abstract                 = {High data rate wireless communications, nearing 1 Gb/s transmission rates, is of interest in emerging wireless local area networks and home audio/visual networks. Designing very high speed wireless links that offer good quality-of-service and range capability in non-line-of-sight (NLOS) environments constitutes a significant research and engineering challenge. Ignoring fading in NLOS environments, we can, in principle, meet the 1 Gb/s data rate requirement with a single-transmit single-receive antenna wireless system if the product of bandwidth (measured in hertz) and spectral efficiency (measured in bits per second per hertz) is equal to 10<sup>9</sup>. A variety of cost, technology and regulatory constraints make such a brute force solution unattractive, if not impossible. The use of multiple antennas at transmitter and receiver, popularly known as multiple-input multiple-output (MIMO) wireless, is an emerging cost-effective technology that offers substantial leverages in making 1 Gb/s wireless links a reality. The paper provides an overview of MIMO wireless technology covering channel models, performance limits, coding, and transceiver design.},
+  Doi                      = {10.1109/JPROC.2003.821915},
+  File                     = {paugor_04.pdf:paugor_04.pdf:PDF},
+  Grade                    = {2},
+  ISSN                     = {0018-9219},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Review                   = {CG:
+Gelesen am 20.11.2008
+zu oberfl�chlich!},
+  Timestamp                = {2008.11.17}
+}
+
+@Misc{pawhybrid11,
+  Title                    = {{H}ybrid {M}emory {C}ube},
+
+  Author                   = {J. T. Pawlowski},
+  HowPublished             = {HotChips 23},
+  Month                    = {August},
+  Year                     = {2011},
+
+  File                     = {pawhybrid11.pdf:pawhybrid11.pdf:PDF},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.11}
+}
+
+@Article{pea_95,
+  Title                    = {{N}otes on regression and inheritance in the case of two parents},
+  Author                   = {Karl Pearson},
+  Journal                  = {Proceedings of the Royal Society of London},
+  Year                     = {1895},
+  Pages                    = {240--242},
+  Volume                   = {58},
+
+  Owner                    = {Ninasnet},
+  Timestamp                = {2014.11.28}
+}
+
+@InProceedings{peehof_99,
+  Title                    = {{LISA}-machine description language for cycle-accurate models of programmable {DSP} architectures},
+  Author                   = {Pees, S. and Hoffmann, A. and Zivojnovic, V. and Meyr, H.},
+  Booktitle                = {Proc. 36th Design Automation Conference},
+  Year                     = {1999},
+  Pages                    = {933--938},
+
+  Abstract                 = {This paper presents the machine description language LISA for the generation of bit- and cycle-accurate models of DSP processors. Based on a behavioral operation description, the architectural details and pipeline operations of modern DSP processors can be covered. Beyond the behavioral model, LISA descriptions include other architecture-related information like the instruction set. The information provided by LISA models enables automatic generation of simulators and assemblers which are essential elements of DSP software development environments. In order to proof the applicability of our approach, a realized model of the Texas Instruments TMS320C6201 DSP is presented and derived LISA code examples are given},
+  Doi                      = {10.1109/DAC.1999.782231},
+  File                     = {peehof_99.pdf:peehof_99.pdf:PDF},
+  Grade                    = {0},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.16}
+}
+
+@MastersThesis{MTpekme14,
+  Title                    = {{A}ccelerating {H}eston {M}odel: {A}n {A}rchitectural {S}tudy on {P}ricer {D}evice},
+  Author                   = {Hüseyin Hakan Pekmezci},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+  Month                    = jul,
+
+  Cds_grade                = {2},
+  Cds_keywords             = {Heston calibration},
+  Cds_read                 = {2014-07-04},
+  File                     = {MTpekme14.pdf:MTpekme14.pdf:PDF},
+  Keywords                 = {AG Wehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.09.09}
+}
+
+@Article{pelave_12,
+  Title                    = {{M}aximum {P}erformance {C}omputing with {D}ataflow {E}ngines},
+  Author                   = {Pell, O. and Averbukh, V.},
+  Journal                  = {Computing in Science Engineering},
+  Year                     = {2012},
+  Number                   = {4},
+  Pages                    = {98-103},
+  Volume                   = {14},
+
+  Doi                      = {10.1109/MCSE.2012.78},
+  File                     = {pelave_12.pdf:pelave_12.pdf:PDF},
+  ISSN                     = {1521-9615},
+  Keywords                 = {finance},
+  Owner                    = {Brugger},
+  Timestamp                = {2013.10.23}
+}
+
+@InProceedings{perhae_05,
+  Title                    = {{ASIC} {I}mplementation of a {MIMO}-{OFDM} {T}ransceiver for 192 {M}bps {WLAN}s},
+  Author                   = {D. Perels and S. Haene and P. Luethi and A. Burg and N. Felber and W. Fichtner and H. Boelcskei},
+  Booktitle                = {Euro. Solid-State Circuits Conference},
+  Year                     = {2005},
+  Pages                    = {215�218},
+
+  File                     = {perhae_05.pdf:perhae_05.pdf:PDF},
+  Grade                    = {4},
+  Journal                  = {Euro. Solid-State Circuits Conference},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Review                   = {CG: 
+Konkurrenz zu UMIC-Project},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{perseg_96,
+  Title                    = {{A Distance Spectrum Interpretation of Turbo-Codes}},
+  Author                   = {L. Perez and J. Seghers and D. {Costello,~Jr.}},
+  Booktitle                = {IEEE Transactions on Information Theory},
+  Year                     = {1996},
+  Month                    = nov,
+  Pages                    = {1698--1709},
+  Volume                   = {42},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{perbur_00,
+  Title                    = {{Voltage Scheduling in the lpARM Microprocessor System}},
+  Author                   = {T. Pering and T. Burd and R. Brodersen},
+  Booktitle                = {Proc. 2000 International Symposium on Low Power Electronics and Design (ISLPED '00)},
+  Year                     = {2000},
+
+  Address                  = {Rapallo, Italy},
+  Month                    = jul,
+  Pages                    = {96--101},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{perbur_98,
+  Title                    = {{The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms}},
+  Author                   = {T. Pering and T. Burd and R. Brodersen},
+  Booktitle                = {Proc. 1998 International Symposium on Low Power Electronics and Design (ISLPED '98)},
+  Year                     = {1998},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = aug,
+  Pages                    = {76--81},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{perdar_12,
+  Title                    = {{C}haracterisation and verification of an {FPGA} signal generator for spectrally efficient wireless {FDM}},
+  Author                   = {Marcus R. Perrett and Izzat Darwazeh},
+  Booktitle                = {Telecommunications (ICT), 2012 19th International Conference on},
+  Year                     = {2012},
+  Month                    = apr,
+  Pages                    = {1--5},
+
+  Abstract                 = {For research and development in computationally intensive bandwidth efficient Frequency Division Multiplexing (FDM) systems, it is generally preferable to implement test systems in hardware. This has the benefit of speed improvement over simulation and enables the generation and evaluation of real signals. This paper describes a system implementation of a versatile signal generator featuring high speed and large bit-depth Digital to Analogue Converters (DACs), RAM storage and an Field Programmable Gate Array (FPGA) to perform multi-carrier real time signal generation. Since the validity of such generated signals requires qualification by characterisation of the generating hardware, this paper describes a measurement methodology and presents results and comparison to vendor specification.},
+  Cds_grade                = {0},
+  Cds_review               = {cites schsch_12},
+  Doi                      = {10.1109/ICTEL.2012.6221226},
+  File                     = {perdar_12.pdf:perdar_12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.08.31}
+}
+
+@InProceedings{pesgru_16,
+  Title                    = {{DRAMA}: {E}xploiting {DRAM} {A}ddressing for {C}ross-{CPU} {A}ttacks},
+  Author                   = {Peter Pessl and Daniel Gruss and Cl{\'e}mentine Maurice and Michael Schwarz and Stefan Mangard},
+  Booktitle                = {25th USENIX Security Symposium (USENIX Security 16)},
+  Year                     = {2016},
+
+  Address                  = {Austin, TX},
+  Month                    = Aug,
+  Pages                    = {565--581},
+  Publisher                = {USENIX Association},
+
+  ISBN                     = {978-1-931971-32-4},
+  Url                      = {https://www.usenix.org/conference/usenixsecurity16/technical-sessions/presentation/pessl}
+}
+
+@InProceedings{pet_94,
+  Title                    = {{Implementierungsaspekte zur Symbol-by-Symbol MAP-Decodierung von Faltungscodes}},
+  Author                   = {J. Petersen},
+  Booktitle                = {ITG-Fachbericht 130, Codierung für Quelle, Kanal und Übertragung},
+  Year                     = {1994},
+
+  Address                  = {Munich, Germany},
+  Month                    = oct,
+  Pages                    = {41--48},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{pet_81,
+  Title                    = {{P}etri {N}et {T}heory and the {M}odeling of {S}ystems},
+  Author                   = {Peterson, James Lyle},
+  Publisher                = {Prentice Hall PTR},
+  Year                     = {1981},
+
+  Address                  = {Upper Saddle River, NJ, USA},
+
+  ISBN                     = {0136619835},
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-27}
+}
+
+@Article{petbro_61,
+  Title                    = {{C}yclic {C}odes for {E}rror {D}etection},
+  Author                   = {Peterson, W.W. and Brown, D.T.},
+  Journal                  = {Proceedings of the IRE},
+  Year                     = {1961},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {228-235},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/JRPROC.1961.287814},
+  File                     = {petbro_61.pdf:petbro_61.pdf:PDF},
+  ISSN                     = {0096-8390},
+  Keywords                 = {Binary codes;Data communication;Decoding;Encoding;Error correction codes;Feedback;Fires;Information theory;Mathematics;Polynomials},
+  Owner                    = {StW},
+  Timestamp                = {2015.12.08}
+}
+
+@Electronic{petwha_16,
+  Title                    = {{HPL} - {A} {P}ortable {I}mplementation of the {H}igh-{P}erformance {L}inpack {B}enchmark for {D}istributed-{M}emory {C}omputers},
+  Author                   = {Petitet, A. and Whaley, R. C. and Dongarra, J. and Cleary, A.},
+  Url                      = {http://www.netlib.org/benchmark/hpl/},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17}
+}
+
+@PhdThesis{pet_62,
+  Title                    = {{K}ommunikation mit {A}utomaten},
+  Author                   = {Carl Adam Petri},
+  School                   = {Universität Hamburg},
+  Year                     = {1962},
+
+  Language                 = {ger},
+  Owner                    = {MJ},
+  Timestamp                = {2016-12-04}
+}
+
+@InProceedings{peyliu_13,
+  Title                    = {{A}n {FPGA} implementation of the fast gradient method for solving the {M}odel {P}redictive {P}ulse {P}attern {C}ontrol problem},
+  Author                   = {H. Peyrl and J. Liu and T. Geyer},
+  Booktitle                = {2013 IEEE International Symposium on Sensorless Control for Electrical Drives and Predictive Control of Electrical Drives and Power Electronics (SLED/PRECEDE)},
+  Year                     = {2013},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [20]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/SLED-PRECEDE.2013.6684480},
+  ISSN                     = {2166-6725},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {computational complexity;field programmable gate arrays;gradient methods;power electronics;predictive control;quadratic programming;sampled data systems;{FPGA} implementation;fast gradient method;model predictive pulse pattern control problem;computational complexity;MP3C;optimisation-based control method;power electronic systems;quadratic program;Switches;Vectors;Stator windings;Field programmable gate arrays;Gradient methods;Trajectory},
+  Owner                    = {CCR}
+}
+
+@InProceedings{pflmou_09,
+  Title                    = {{P}erformance {E}valuation of {N}on-{B}inary {LDPC} {C}odes on {W}ireless {C}hannels},
+  Author                   = {Stephan Pfletschinger and Alain Mourad and Eduardo Lopez and David Declercq and Giacomo Bacci},
+  Booktitle                = {Proc. ICT-MobileSummit 2009},
+  Year                     = {2009},
+  Month                    = jun,
+
+  File                     = {pflmou_09.pdf:pflmou_09.pdf:PDF},
+  Owner                    = {lehnigk},
+  Timestamp                = {2009.09.22}
+}
+
+@InProceedings{pflnav_13,
+  Title                    = {{E}nhanced {T}urbo {D}ecoding for {E}rror {F}loor {R}eduction},
+  Author                   = {S. Pfletschinger and M. Navarro},
+  Booktitle                = {Systems, Communication and Coding (SCC), Proceedings of 2013 9th International ITG Conference on},
+  Year                     = {2013},
+  Month                    = {Jan},
+  Pages                    = {1-6},
+
+  Keywords                 = {Computer integrated manufacturing;Cyclic redundancy check codes;Decoding;Iterative decoding;Standards;Turbo codes;Viterbi algorithm},
+  Owner                    = {StW},
+  Timestamp                = {2016.11.15}
+}
+
+@Unpublished{phapar_10,
+  Title                    = {{P}ro{MIN}o{C}: {A}n {E}fficient {N}etwork-on-{C}hip {D}esign for {F}lexible {D}ata {P}ermutation},
+  Author                   = {Phi-Hung Pham and Jongsun Park and Chulwoo Kim},
+  Note                     = {for IEICE Electronics Express},
+
+  Month                    = {May},
+  Year                     = {2010},
+
+  Abstract                 = {This paper presents a novel Network-on-Chip design to
+efficiently support data-interleaving with arbitrary permutation rule. The
+proposed NoC offers a run-time conflict resolution for interleaved data
+under arbitrary permutation rule by using circuit-switching approach
+combined with a dynamic path-probing scheme. Experimental results in a
+0.18μm STD-cell CMOS process show that the proposed NoC can offer an
+aggregate bandwidth of up to 522.4Gb/s, while occupying a compact area of
+0.473mm2 (52 kGates). A comparison with other interleaving networks
+shows the efficiency of the proposed design.},
+  Cds_grade                = {5},
+  Cds_keywords             = {NoC, Interleaver, VLSI},
+  Cds_read                 = {2010-05-17},
+  Cds_review               = {In my opinion this is a very good paper, easy to understand and showing a great performance gain of your network design approach compared to state-of-the-art networks. I appreciate that you explain your switch structure in that detail and provide the state machine and pseudo code, so everybody is able to understand how it works. Language and length of your paper are very good as well. Excellent!},
+  File                     = {phapar_10.pdf:phapar_10.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.05.17}
+}
+
+@Article{phapar_10a,
+  Title                    = {{P}ro{MIN}o{C}: {A}n efficient {N}etwork-on-{C}hip design for flexible data permutation},
+  Author                   = {Phi-Hung Pham and Jongsun Park and Chulwoo Kim},
+  Journal                  = {IEICE Electronics Express},
+  Year                     = {2010},
+  Number                   = {12},
+  Pages                    = {861-866},
+  Volume                   = {7},
+
+  Abstract                 = {This paper presents a novel Network-on-Chip design to efficiently support data-interleaving with arbitrary permutation rule. The proposed NoC offers a run-time conflict resolution for interleaved data under arbitrary permutation rule by using a circuit-switching approach combined with a dynamic path-probing scheme. Experimental results in a 0.18µm STD-cell CMOS process show that the proposed NoC can offer an aggregate bandwidth of up to 522.4Gb/s, while occupying a compact area of 0.473mm2 (52kGates). A comparison with other interleaving networks shows the efficiency of the proposed design.},
+  Cds_grade                = {0},
+  Cds_keywords             = {NoC},
+  File                     = {phapar_10a.pdf:phapar_10a.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2011.02.07}
+}
+
+@Article{pie_98,
+  Title                    = {{Implementation and Performance of a Turbo/MAP Decoder}},
+  Author                   = {Pietrobon, S. S.},
+  Journal                  = {International Journal on Satellite Communications},
+  Year                     = {1998},
+
+  Month                    = jan # {--} # feb,
+  Pages                    = {22--46},
+  Volume                   = {16},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{pie_96,
+  Title                    = {{Efficient Implementation of Continuous MAP Decoders and a Synchronisation Technique for Turbo Decoders}},
+  Author                   = {S. S. Pietrobon},
+  Booktitle                = {{Proc. 1996 International Symposium on Information Theory and its Applications (ISITA '96)}},
+  Year                     = {1996},
+
+  Address                  = {Victoria, British Columbia, Canada},
+  Month                    = sep,
+  Pages                    = {586--589},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{piebar_94,
+  Title                    = {{A Simplification of the Modified Bahl Decoding Algorithm for Systematic Convolutional Codes}},
+  Author                   = {S. S. Pietrobon and A. S. Barbulescu},
+  Booktitle                = {Proc. International Symposium on Information Theory and its Applications},
+  Year                     = {1994},
+
+  Address                  = {Sydney, Australia},
+  Month                    = nov,
+  Pages                    = {1073--1077},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{pinliu_03,
+  Title                    = {{Interleave-Division Multiple-Access (IDMA) Communications}},
+  Author                   = {L. Ping and L. Liu and K.Y. Wu and W.K. Leung},
+  Booktitle                = {Proc. 3nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {173--180},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{pincas_17,
+  Title                    = {{E}nergy {E}fficiency: {A} {N}ew {C}oncern for {A}pplication {S}oftware {D}evelopers},
+  Author                   = {Gustavo Pinto and Fernando Castor},
+  Journal                  = {Communications of the ACM},
+  Year                     = {2017},
+
+  Month                    = {Dec.},
+  Number                   = {12},
+  Pages                    = {68--75},
+  Volume                   = {60},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.04}
+}
+
+@InProceedings{pirlin_04,
+  Title                    = {{F}ault tolerant algorithms for network-on-chip interconnect},
+  Author                   = {Pirretti, M. and Link, G. M. and Brooks, R. R. and Vijaykrishnan, N. and Kandemir, M. and Irwin, M. J. },
+  Booktitle                = {Proc. IEEE Computer society Annual Symposium on VLSI},
+  Year                     = {2004},
+  Month                    = feb,
+  Pages                    = {46--51},
+
+  File                     = {pirlin_04.pdf:pirlin_04.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Book{pir_98,
+  Title                    = {{Architectures for Digital Signal Processing}},
+  Author                   = {P. Pirsch},
+  Publisher                = {John Wiley \& Sons, Inc.},
+  Year                     = {1998},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{Platzner2010,
+  Title                    = {{D}ynamically {R}econfigurable {S}ystems: {A}rchitectures, {D}esign {M}ethods and {A}pplications},
+  Author                   = {M. Platzner and N. Wehn},
+  Publisher                = {Springer},
+  Year                     = {2010},
+
+  Optnote                  = {ISBN 978-90-481-3485-4},
+  Owner                    = {Ali},
+  Timestamp                = {2015.02.02}
+}
+
+@InCollection{pnebec_14,
+  Title                    = {{E}ffective {R}econfigurable {D}esign: {T}he {FASTER} {A}pproach},
+  Author                   = {Pnevmatikatos, D.N. and Becker, T. and Brokalakis, A. and Gaydadjiev, G.N. and Luk, W. and Papadimitriou, K. and Papaefstathiou, I. and Pau, D. and Pell, Oliver and Pilato, C. and Santambrogio, M.D. and Sciuto, D. and Stroobandt, D.},
+  Booktitle                = {Reconfigurable Computing: Architectures, Tools, and Applications},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2014},
+  Editor                   = {Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso, JoãoM.P. and Bertels, Koen},
+  Pages                    = {318-323},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {8405},
+
+  Doi                      = {10.1007/978-3-319-05960-0_35},
+  ISBN                     = {978-3-319-05959-4},
+  Language                 = {English},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30},
+  Url                      = {http://dx.doi.org/10.1007/978-3-319-05960-0_35}
+}
+
+@InProceedings{pngpen_04,
+  Title                    = {{Performance Studies of a Multi-band OFDM System Using a Simplified LDPC Code}},
+  Author                   = {Khiam-Boon Png and Xiaoming Peng and Francois Chin},
+  Booktitle                = {IEEE Ultra-Wideband Systematic and Technologies 2004},
+  Year                     = {2004},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{pweh_93,
+  Title                    = {{ Automatic Synthesis for Mechatronic Applications }},
+  Author                   = { P. Pöchmüller and N. Wehn and M. Glesner},
+  Booktitle                = { Application-Driven Synthesis},
+  Year                     = {1993},
+  Pages                    = {167--189},
+  Publisher                = { Kluwer Academic Publishers },
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{pod_12,
+  Title                    = {{I}mage {C}onvolution with {CUDA}},
+  Author                   = {Victor Podlozhnyuk},
+  Institution              = {NVIDIA},
+  Year                     = {2012},
+  Month                    = {jul},
+  Note                     = {last access 2015-01-13},
+
+  Abstract                 = {Convolution filtering is a technique that can be used for a wide array of image processing tasks, some of which may include smoothing and edge detection. In this document we show how a separable convolution filter can be implemented in NVIDIA CUDA and provide some guidelines for performance optimizations.},
+  Owner                    = {varela},
+  Timestamp                = {2015.01.13},
+  Url                      = {http://docs.nvidia.com/cuda/samples/3_Imaging/convolutionSeparable/doc/convolutionSeparable.pdf}
+}
+
+@Electronic{pod_07,
+  Title                    = {{P}arallel {M}ersenne {T}wister},
+  Author                   = {Victor Podlozhnyuk},
+  HowPublished             = {\url{http://developer.download.nvidia.com/compute/cuda/2_2/sdk/website/projects/MersenneTwister/doc/MersenneTwister.pdf}},
+  Language                 = {en},
+  Month                    = jun,
+  Note                     = {White Paper, last access 2015-01-13},
+  Organization             = {Nvidia},
+  Url                      = {http://developer.download.nvidia.com/compute/cuda/2_2/sdk/website/projects/MersenneTwister/doc/MersenneTwister.pdf},
+  Year                     = {2007},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {Nvidia, Mersenne Twister, random numbers, GPU},
+  File                     = {pod_07.pdf:pod_07.pdf:PDF},
+  Journal                  = {NVIDIA white paper},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@Electronic{Podlozhnyuk2007,
+  Title                    = {{P}arallel {M}ersenne {T}wister},
+  Author                   = {Victor Podlozhnyuk},
+  HowPublished             = {\url{http://developer.download.nvidia.com/compute/cuda/2_2/sdk/website/projects/MersenneTwister/doc/MersenneTwister.pdf}},
+  Language                 = {en},
+  Month                    = jun,
+  Note                     = {White Paper},
+  Organization             = {Nvidia},
+  Url                      = {http://developer.download.nvidia.com/compute/cuda/2_2/sdk/website/projects/MersenneTwister/doc/MersenneTwister.pdf},
+  Year                     = {2007},
+
+  Cds_grade                = {0},
+  File                     = {pod_07.pdf:pod_07.pdf:PDF},
+  Journal                  = {NVIDIA white paper},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@InProceedings{poehel_91,
+  Title                    = {{ HADES High-Level Architecture Development and Exploration System}},
+  Author                   = {P.~Poechmueller and M.~Held and N.~Wehn and M.~Glesner},
+  Booktitle                = { Proceedings of the First Great Lake Symposium on VLSI},
+  Year                     = {1991},
+  Pages                    = {342--343},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{polsze_05,
+  Title                    = {{T}elos: enabling ultra-low power wireless research},
+  Author                   = {Polastre, J. and Szewczyk, R. and Culler, D.},
+  Year                     = {2005},
+  Month                    = {apr.},
+  Pages                    = { 364 - 369},
+
+  Abstract                 = {We present Telos, an ultra low power wireless sensor module ("mote") for research and experimentation. Telos is the latest in a line of motes developed by UC Berkeley to enable wireless sensor network (WSN) research. It is a new mote design built from scratch based on experiences with previous mote generations. Telos' new design consists of three major goals to enable experimentation: minimal power consumption, easy to use, and increased software and hardware robustness. We discuss how hardware components are selected and integrated in order to achieve these goals. Using a Texas Instruments MSP430 microcontroller, Chipcon IEEE 802.15.4-compliant radio, and USB, Telos' power profile is almost one-tenth the consumption of previous mote platforms while providing greater performance and throughput. It eliminates programming and support boards, while enabling experimentation with WSNs in both lab, testbed, and deployment settings.},
+  Doi                      = {10.1109/IPSN.2005.1440950},
+  File                     = {polsze_05.pdf:polsze_05.pdf:PDF},
+  ISSN                     = { },
+  Journal                  = {Information Processing in Sensor Networks, 2005. IPSN 2005. Fourth International Symposium on},
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.20}
+}
+
+@Article{ponvuc_02,
+  Title                    = {{S}oft decision decoding of {R}eed-{S}olomon codes},
+  Author                   = {V. Ponnampalam and B. Vucetic},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2002},
+
+  Month                    = {Nov},
+  Number                   = {11},
+  Pages                    = {1758-1768},
+  Volume                   = {50},
+
+  Doi                      = {10.1109/TCOMM.2002.805279},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Reed-Solomon codes;computational complexity;maximum likelihood decoding;AWGN channel;RS codes;Reed-Solomon codes;Vardy-Be'ery MLD algorithm;algebraic structure;binary images;decoding complexity;generalized minimum distance decoding;maximum likelihood decoding;minimum Hamming distance;near-MLD performance;simulation results;soft decision decoding;suboptimum algorithm;suboptimun decoding algorithm;CD recording;Communication systems;Computational complexity;Error correction;Helium;Information theory;Interpolation;Maximum likelihood decoding;Partitioning algorithms;Reed-Solomon codes}
+}
+
+@InProceedings{pormit_15,
+  Title                    = {{DESTINY}: {A} tool for modeling emerging 3{D} {NVM} and e{DRAM} caches},
+  Author                   = {M. Poremba and S. Mittal and D. Li and J. S. Vetter and Y. Xie},
+  Booktitle                = {2015 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2015},
+  Month                    = {March},
+  Pages                    = {1543-1546},
+
+  Doi                      = {10.7873/DATE.2015.0733},
+  ISSN                     = {1530-1591},
+  Keywords                 = {cache storage;DRAM chips;memory architecture;phase change memories;resistive RAM;SRAM chips;3D NVM modeling;fabrication method;design space exploration;PCM;phase change RAM;ReRAM;resistive RAM;STT-RAM;spin transfer torque RAM;eDRAM cache;embedded DRAM;SRAM;3D cache design modeling;microarchitecture level tool;DESTINY;Three-dimensional displays;Random access memory;Solid modeling;Integrated circuit modeling;Nonvolatile memory;Prototypes;Stacking;Cache;SRAM;eDRAM;STT-RAM;ReRAM;PCM;non-volatile memory (NVM or NVRAM);modeling tool;validation},
+  Timestamp                = {2018-08-29}
+}
+
+@InProceedings{porxie_12,
+  Title                    = {{NVM}ain: {A}n {A}rchitectural-{L}evel {M}ain {M}emory {S}imulator for {E}merging {N}on-volatile {M}emories},
+  Author                   = {M. {Poremba} and Y. {Xie}},
+  Booktitle                = {2012 IEEE Computer Society Annual Symposium on VLSI},
+  Year                     = {2012},
+  Month                    = {Aug},
+  Pages                    = {392-397},
+
+  Doi                      = {10.1109/ISVLSI.2012.82},
+  ISSN                     = {2159-3469},
+  Keywords                 = {circuit reliability;DRAM chips;memory architecture;NVMain;architectural-level main memory simulator;nonvolatile memories;DRAM-based main memory design;computer systems;NVM technologies;computer architecture;architectural-level simulator;main memory design;design space explorations;Nonvolatile memory;Random access memory;Delay;Integrated circuit modeling;Computational modeling;Organizations;emerging memory technology;memory architecture},
+  Owner                    = {MJ},
+  Timestamp                = {2020-03-12}
+}
+
+@Article{porzha_15,
+  Title                    = {{NVM}ain 2.0: {A} {U}ser-{F}riendly {M}emory {S}imulator to {M}odel ({N}on-){V}olatile {M}emory {S}ystems},
+  Author                   = {M. {Poremba} and T. {Zhang} and Y. {Xie}},
+  Journal                  = {IEEE Computer Architecture Letters},
+  Year                     = {2015},
+
+  Month                    = {July},
+  Number                   = {2},
+  Pages                    = {140-143},
+  Volume                   = {14},
+
+  Doi                      = {10.1109/LCA.2015.2402435},
+  ISSN                     = {2473-2575},
+  Keywords                 = {cache storage;DRAM chips;memory architecture;phase change memories;user interfaces;NVMain 2.0;user-friendly memory simulator;nonvolatile memory system;flexible memory simulator;commodity DRAM;memory technology;die-stacked DRAM cache;STT-RAM;PCRAM;ReRAM;multilevel cells;DRAM memory systems;flexible user interface;Nonvolatile memory;Memory management;Computational modeling;Phase change random access memory;Computer architecture;Memory architecture, random access memory, nonvolatile memory, phase change memory, SDRAM},
+  Owner                    = {MJ},
+  Timestamp                = {2020-03-12}
+}
+
+@InProceedings{porpla_05,
+  Title                    = {{S}ystem{C} implementation of a {N}o{C}},
+  Author                   = {Portero, A. and Pla, R. and Carrabina, J.},
+  Booktitle                = {Industrial Technology, 2005. ICIT 2005. IEEE International Conference on},
+  Year                     = {2005},
+  Month                    = dec,
+  Pages                    = {1132 -1135},
+
+  Abstract                 = {In this paper we describe the implementation in SystemC of a scalable and parametrical network on chip (NoC). The NoC, with a mesh topology and wormhole routing, is formed of resources and routers connected by channels. Each router is connected to four neighbours' routers through input and output channels. The channels of the routers have a data bus and two control signals to let a communication based on handshake. A wrapper establishes the communication between the resource and its environment converting the messages into a format appropriated for the NoC. The information is packed to be able to circulate through the NoC and it is unpacked when it arrives to the destination},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ICIT.2005.1600805},
+  File                     = {porpla_05.pdf:porpla_05.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2011.02.07}
+}
+
+@Article{poudec_08,
+  Title                    = {{E}fficient decoding of turbo codes with nonbinary belief propagation},
+  Author                   = {Poulliat, Charly and Declercq, David and Lestable, Thierry},
+  Journal                  = {EURASIP Journal on Wireless Communications and Networking},
+  Year                     = {2008},
+  Number                   = {1},
+  Pages                    = {473613},
+  Volume                   = {2008},
+
+  Owner                    = {kraft},
+  Publisher                = {Springer},
+  Timestamp                = {2018.05.31}
+}
+
+@Article{poufos_08,
+  Title                    = {{D}esign of regular (2,d/sub c/)-{LDPC} codes over {GF}(q) using their binary images},
+  Author                   = {Poulliat, C. and Fossorier, M. and Declercq, D.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2008},
+  Number                   = {10},
+  Pages                    = {1626--1635},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TCOMM.2008.060527},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.21}
+}
+
+@InProceedings{poufos_06,
+  Title                    = {{Using binary images of non binary LDPC codes to improve overall performance}},
+  Author                   = {C. Poulliat and M. Fossorier and D. Declercq},
+  Booktitle                = {Proc. 4nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2006},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{poulan_01,
+  Title                    = {{Energy Priority Scheduling for Variable Voltage Processors}},
+  Author                   = {J. Pouwelse and K. Langendoen and H. Sips},
+  Booktitle                = {Proc. 2001 International Symposium on Low Power Electronics and Design (ISLPED '01)},
+  Year                     = {2001},
+
+  Address                  = {Huntington Beach, California, USA},
+  Month                    = aug,
+  Pages                    = {28--33},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{poulan_01a,
+  Title                    = {{Dynamic Voltage Scaling on a Low Power Microprocessor}},
+  Author                   = {J. Pouwelse and K. Langendoen and H. Sips},
+  Booktitle                = {7th ACM International Conference on Mobile Computing and Networking (Mobicom '01)},
+  Year                     = {2001},
+
+  Address                  = {Rome, Italy},
+  Month                    = jul,
+  Pages                    = {251--259},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{prasil_17,
+  Title                    = {{A} {L}ive {D}emo for {S}howing the {B}enefits of {A}pplying the {R}emote {GPU} {V}irtualization {T}echnique to {C}loud {C}omputing},
+  Author                   = {Javier Prades and Federico Silla},
+  Booktitle                = {2017 17th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGRID)},
+  Year                     = {2017},
+  Month                    = {May},
+  Pages                    = {735-738},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.22}
+}
+
+@InProceedings{pregem_05,
+  Title                    = {{A} {P}arameterizable {L}ow-{P}ower {H}igh-{T}hroughput {T}urbo-{D}ecoder},
+  Author                   = {G. Prescher and T. Gemmeke and T. Noll},
+  Booktitle                = {Proc. 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2005)},
+  Year                     = {2005},
+
+  Address                  = {Philadelphia, Pennsylvania, USA},
+  Month                    = mar,
+  Pages                    = {V-25--28},
+
+  File                     = {pregem_05.pdf:pregem_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{preparameterizable04,
+  Title                    = {{A Parameterizable Low-Power High-Throughput Turbo-Decoder}},
+
+  Author                   = {G. Prescher and T. Gemmeke and T. Noll},
+  HowPublished             = {Personal Communication},
+  Year                     = {2004},
+
+  Optnote                  = {Failed CICC 2004 Submission on Design Time Conflcit Resolution},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Prescher2004,
+  Title                    = {{A Parameterizable Low-Power High-Throughput Turbo-Decoder}},
+
+  Author                   = {G. Prescher and T. Gemmeke and T. Noll},
+  HowPublished             = {Personal Communication},
+  Year                     = {2004},
+
+  Optnote                  = {Failed CICC 2004 Submission on Design Time Conflcit Resolution},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{wil_07,
+  Title                    = {{N}umerical {R}ecipes - {T}he {A}rt of {S}cientific {C}omputing},
+  Author                   = {William H. Press and Saul A. Teukolsky and William T. Vetterling and Brian P. Flannery},
+  Publisher                = {Cambridge University Press},
+  Year                     = {2007},
+  Edition                  = {3rd},
+  Note                     = {ISBN: 978-0521880688},
+
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.04}
+}
+
+@InProceedings{prezha_19,
+  Title                    = {{A}pis: {A}rchitecture for {F}ederated {P}ower {M}anagement},
+  Author                   = {A. {Prey} and J. {Zhai} and C. {Kelley} and J. {Hallstrom}},
+  Booktitle                = {2019 IEEE International Conference on Smart Computing (SMARTCOMP)},
+  Year                     = {2019},
+  Month                    = {June},
+  Pages                    = {156-161},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {low},
+  Ccr_key_original         = {8784017},
+  Ccr_keywords             = {not worth citing, the work is ok but kinda useless},
+  Ccr_topic                = {n.a.},
+  Doi                      = {10.1109/SMARTCOMP.2019.00046},
+  Keywords                 = {TCS},
+  Keywords_original        = {Capacitors;Task analysis;Software;Regulators;Voltage control;Pins;Discharges (electric);IoT;Embedded Systems;Energy Harvesting;Power Management;Battery free Computing;Architecture},
+  Owner                    = {CCR}
+}
+
+@Book{pro_95,
+  Title                    = {{Digital Communications}},
+  Author                   = {J. G. Proakis},
+  Publisher                = {McGraw-Hill, Inc.},
+  Year                     = {1995},
+  Edition                  = {3rd},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{puebei_99,
+  Title                    = {{Adaptive bubble router: a design to improve performance in torus networks}},
+  Author                   = {V. Puente and R. Beivide and J.A. Gregorio and J.M. Prellezo and J. Duato and C. Izu},
+  Booktitle                = {1999 International Conference on Parallel Processing},
+  Year                     = {1999},
+  Month                    = sep,
+  Pages                    = {58-67},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{puegre_01,
+  Title                    = {{A New Routing Mechanism for Networks with Irregular Topology}},
+  Author                   = {V. Puente and J. A. Gregorio and R. Beivide and F. Vallejo and A. Iba{\~n}ez},
+  Booktitle                = {Supercomputing (SC2001)},
+  Year                     = {2001},
+
+  Address                  = {Dallas, Texas, USA},
+  Month                    = nov,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{punkie_10,
+  Title                    = {{C}alculating the minimum distance of linear block codes via {I}nteger {P}rogramming},
+  Author                   = {Punekar, M. and Kienle, F. and Wehn, N. and Tanatmis, A. and Ruzika, S. and Hamacher, H. W. },
+  Booktitle                = {Proc. 6th Int Turbo Codes and Iterative Information Processing (ISTC) Symp},
+  Year                     = {2010},
+  Pages                    = {329--333},
+
+  Doi                      = {10.1109/ISTC.2010.5613894},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.07.06}
+}
+
+@InProceedings{pyngla_94,
+  Title                    = {{N}ear optimum decoding of product codes},
+  Author                   = {Pyndiah, R. and Glavieux, A. and Picart, A. and Jacq, S.},
+  Booktitle                = {Proc. IEEE Global Telecommunications Conf. GLOBECOM '94. Communications: The Global Bridge},
+  Year                     = {1994},
+  Pages                    = {339--343},
+
+  Doi                      = {10.1109/GLOCOM.1994.513494},
+  File                     = {pyngla_94.pdf:pyngla_94.pdf:PDF},
+  Keywords                 = {Turbo, InfTheory},
+  Owner                    = {Scholl},
+  Review                   = {first paper on block turbo decoding},
+  Timestamp                = {2011.04.27}
+}
+
+@InProceedings{5453930,
+  Title                    = {{CORDIC} implementation with parameterizable {ASIC}/{S}o{C} flow},
+  Author                   = {Zhenyu Qi and Cabe, A.C. and Jones, R.T. and Stan, M.R.},
+  Booktitle                = {IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the},
+  Year                     = {2010},
+  Month                    = {march},
+  Pages                    = {13 -16},
+
+  Abstract                 = {A CORDIC processor with three computation modes is designed. The design targets low power applications. A novel fine grain clock gating scheme is employed to reduce power. The design is mapped to two technology nodes, i.e., 350 nm and 65 nm, using a script-based, parameterizable ASIC/SoC flow that can be easily adapted for different designs and technologies for fast concept-to-silicon mapping. Power numbers at both technology nodes are reported for the CORDIC design. The contribution of the paper includes both the actual design and the design flow.},
+  Doi                      = {10.1109/SECON.2010.5453930},
+  Keywords                 = {CORDIC processor;application specific integrated circuits;concept-to-silicon mapping;coordinate rotation digital computer;parameterizable ASIC/SoC flow;size 350 nm;size 65 nm;system-on-chip;application specific integrated circuits;digital arithmetic;logic design;system-on-chip;}
+}
+
+@InProceedings{qiahua_11,
+  Title                    = {{101.7-Tb/s (370x294-Gb/s) PDM-128QAM-OFDM transmission over 3x55-km SSMF using pilot-based phase noise mitigation}},
+  Author                   = {Dayou Qian and Ming-Fang Huang and Ip, E. and Yue-Kai Huang and Yin Shao and Junqiang Hu and Ting Wang},
+  Booktitle                = {Optical Fiber Communication Conference and Exposition (OFC/NFOEC), 2011 and the National Fiber Optic Engineers Conference},
+  Year                     = {2011},
+  Pages                    = {1-3},
+
+  ISSN                     = {pending},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.04.24}
+}
+
+@Article{qiali_11,
+  Title                    = {{A}n {A}rchitecture for {F}ault-{T}olerant {C}omputation with {S}tochastic {L}ogic},
+  Author                   = {Weikang Qian and Xin Li and Riedel, M.D. and Bazargan, K. and Lilja, D.J.},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2011},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {93--105},
+  Volume                   = {60},
+
+  Doi                      = {10.1109/TC.2010.202},
+  File                     = {qiali_11.pdf:qiali_11.pdf:PDF},
+  Keywords                 = {Reliability}
+}
+
+@InProceedings{quavac_06,
+  Title                    = {{I}nterconnection framework for high-throughput, flexible {LDPC} decoders},
+  Author                   = {Quaglio, F. and Vacca, F. and Castellano, C. and Tarable, A. and Masera, G.},
+  Booktitle                = {Proc. Design, Automation and Test in Europe DATE '06},
+  Year                     = {2006},
+  Month                    = mar,
+  Pages                    = {6pp.},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/DATE.2006.243815},
+  File                     = {quavac_06.pdf:quavac_06.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.08.05}
+}
+
+@InProceedings{quavac_05,
+  Title                    = {{Low Complexity, Flexible LDPC Decoders}},
+  Author                   = {F. Quaglio and Fabrizio Vacca and Guido Masera},
+  Booktitle                = {Proc. 2005 IST Mobile and Wireless Communications Summit},
+  Year                     = {2005},
+
+  Address                  = {Dresden, Germany},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{quizhu_02,
+  Title                    = {{Third-Generation and Beyond (3.5G) Wireless Networks and Its Applications}},
+  Author                   = {R. C. Qui and W. Zhu and Y.-Q. Zhang},
+  Booktitle                = {Proc. 2002 IEEE International Symposium on Circuits and Systems (ISCAS '02)},
+  Year                     = {2002},
+
+  Address                  = {Phoenix, Arizona, USA},
+  Month                    = may,
+  Pages                    = {41--44},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{Quinn1994,
+  Title                    = {{E}stimating frequency by interpolation using {F}ourier coefficients},
+  Author                   = {Quinn, B.G.},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {1994},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {1264-1268},
+  Volume                   = {42},
+
+  Doi                      = {10.1109/78.295186},
+  ISSN                     = {1053-587X},
+  Keywords                 = {Fourier analysis;interpolation;parameter estimation;signal processing;time series;Cramer-Rao lower bound;Fourier coefficients;asymptotic variance;frequency parameter;interpolation;maximizer;periodogram;root mean square error;sinusoidal component;time series;Frequency estimation;Hardware;Interpolation;Least squares approximation;Materials science and technology;Mean square error methods;Noise level;Phase noise;Root mean square;Signal processing},
+  Owner                    = {ali},
+  Timestamp                = {2015.03.04}
+}
+
+@Article{Quinn1997,
+  Title                    = {{E}stimation of frequency, amplitude, and phase from the {DFT} of a time series},
+  Author                   = {Quinn, Barry G},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {1997},
+  Number                   = {3},
+  Pages                    = {814--817},
+  Volume                   = {45},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.03.04}
+}
+
+@Article{qurkim_15,
+  Title                    = {{AVATAR}: {A} {V}ariable-{R}etention-{T}ime ({VRT}) {A}ware {R}efresh for {DRAM} {S}ystems},
+  Author                   = {Qureshi, Moinuddin K and Kim, Dae-Hyun and Khan, Samira and Nair, Prashant J and Mutlu, Onur},
+  Journal                  = {Memory},
+  Year                     = {2015},
+  Number                   = {4Gb},
+  Pages                    = {20},
+  Volume                   = {2},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@InProceedings{rab_05,
+  Title                    = {{D}esign at the end of the silicon roadmap [{K}eynote {A}ddress {III}]},
+  Author                   = {Rabaey, J.M.},
+  Booktitle                = {Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific},
+  Year                     = {2005},
+  Month                    = jan,
+  Pages                    = {K1--K2},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ASPDAC.2005.1466108},
+  File                     = {rab_05.pdf:rab_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@InProceedings{rabcam_02,
+  Title                    = {{Panel: ``What's the Next EDA Driver?''}},
+  Author                   = {J. Rabaey and R. Camposano and D. Samani and L. Lerner and R. Hetherington},
+  Booktitle                = {Proc. 2002 Design Automation Conference (DAC '02)},
+  Year                     = {2002},
+
+  Address                  = {New Orleans, Louisiana, USA},
+  Month                    = jun,
+  Pages                    = {652},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{rabgue_95,
+  Title                    = {{Design guidance in the Power Dimension}},
+  Author                   = {J. Rabaey and L. Guerra and R. Mehra},
+  Booktitle                = {Proc. 1995 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '95)},
+  Year                     = {1995},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Electronic{rab_10,
+  Title                    = {{T}he "{S}warm" at the {E}dge of the {C}loud},
+  Author                   = {Jan M. Rabaey},
+  HowPublished             = {\url{http://www.cs.waseda.ac.jp/gcoe/jpn/publication/symposium/img/S28-panel2.pdf}},
+  Language                 = {en},
+  Note                     = {last access 2014-06-27},
+  Url                      = {\url{http://www.cs.waseda.ac.jp/gcoe/jpn/publication/symposium/img/S28-panel2.pdf}},
+  Year                     = {2010},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {Cloud computing},
+  File                     = {rab_10.pdf:rab_10.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.27}
+}
+
+@Book{rab_09,
+  Title                    = {{L}ow {P}ower {D}esign {E}ssentials},
+  Author                   = {Jan M. Rabaey},
+  Publisher                = {Springer},
+  Year                     = {2009},
+  Edition                  = {1ed}
+}
+
+@Book{rabchanik_04,
+  Title                    = {{D}igital integrated circuits- {A} design perspective},
+  Author                   = {Jan M. Rabaey and Anantha Chandrakasan and Borivoje Nikolic},
+  Publisher                = {Prentice Hall},
+  Year                     = {2004},
+  Edition                  = {2ed}
+}
+
+@InBook{rabped_96,
+  Title                    = {{Low Power Design Methodologies}},
+  Author                   = {J. M. Rabaey and M. Pedram},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {1996},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{rad_81,
+  Title                    = {{Memory Management in a Viterbi Decoder}},
+  Author                   = {Rader, C. M.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1981},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {1399--1401},
+  Volume                   = {29},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{radyua_92,
+  Title                    = {{N}ovel approaches to the design of {VLSI} {RNS} multipliers},
+  Author                   = {D. Radhakrishnan and Y. Yuan},
+  Journal                  = {IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing},
+  Year                     = {1992},
+  Number                   = {1},
+  Pages                    = {52--57},
+  Volume                   = {39},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {Galois, FFM, Finite Field Multiplier,},
+  File                     = {radyua_92.pdf:radyua_92.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.10.27}
+}
+
+@InProceedings{ragdey_01,
+  Title                    = {{Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies}},
+  Author                   = {A. Raghunathan and S. Dey},
+  Booktitle                = {{Proc. 14th International Conference on VLSI Design (VLSI '01)}},
+  Year                     = {2001},
+
+  Address                  = {Bangalore, India},
+  Month                    = jan,
+  Note                     = {Tutorial},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{ragliu_99,
+  Title                    = {{VLSI Implementation Considerations for Turbo Decoding Using a Low Latency Log-MAP}},
+  Author                   = {A. Raghupathy and K. J Ray Liu},
+  Booktitle                = {Proc. 1999 International Conference on Consumer Electronics (ICCE '99)},
+  Year                     = {1999},
+  Month                    = jun,
+  Pages                    = {182--183},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{rahjay_15,
+  Title                    = {{Q}uality-aware {D}ata {A}llocation in {A}pproximate {DRAM}},
+  Author                   = {Raha, Arnab and Jayakumar, Hrishikesh and Sutar, Soubhagya and Raghunathan, Vijay},
+  Booktitle                = {Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems},
+  Year                     = {2015},
+
+  Address                  = {Piscataway, NJ, USA},
+  Pages                    = {89--98},
+  Publisher                = {IEEE Press},
+  Series                   = {CASES '15},
+
+  Acmid                    = {2830702},
+  ISBN                     = {978-1-4673-8320-2},
+  Keywords                 = {DRAM power management, approximate computing, intrinsic application resilience, low power design},
+  Location                 = {Amsterdam, The Netherlands},
+  Numpages                 = {10},
+  Owner                    = {MJ},
+  Timestamp                = {2015.10.26},
+  Url                      = {http://dl.acm.org/citation.cfm?id=2830689.2830702}
+}
+
+@Article{rahsut_17,
+  Title                    = {{Q}uality {C}onfigurable {A}pproximate {DRAM}},
+  Author                   = {Arnab Raha and S. Sutar and H. Jayakumar and V. Raghunathan},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2017},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {1172-1187},
+  Volume                   = {66},
+
+  Doi                      = {10.1109/TC.2016.2640296},
+  ISSN                     = {0018-9340},
+  Keywords                 = {DRAM chips;fault tolerant computing;power aware computing;power consumption;resource allocation;storage management;Altera Stratix IV GX FPGA;Terasic TR4-230 development board;approximate computing;data allocation;error-resilient applications;inherent error tolerance;power consumption;power performance;quality configurable approximate DRAM system;substantial energy savings;Capacitors;Energy consumption;Integrated circuits;Power demand;Random access memory;Resilience;Resource management;DRAM;Low power design;approximate computing;approximate memory;approximate storage},
+  Owner                    = {MJ},
+  Timestamp                = {2017-09-11}
+}
+
+@InProceedings{rahhic_14,
+  Title                    = {{R}efreshing thoughts on {DRAM}: {P}ower saving vs. data integrity},
+  Author                   = {Rahmati, Amir and Hicks, Matthew and Holcomb, Daniel and Fu, Kevin},
+  Booktitle                = {Workshop on Approximate Computing Across the System Stack (WACAS)},
+  Year                     = {2014},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.12.02}
+}
+
+@InProceedings{rahhic_15,
+  Title                    = {{P}robable cause: {T}he deanonymizing effects of approximate {DRAM}},
+  Author                   = {Amir Rahmati and M. Hicks and D. E. Holcomb and K. Fu},
+  Booktitle                = {2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA)},
+  Year                     = {2015},
+  Month                    = {June},
+  Pages                    = {604-615},
+
+  Doi                      = {10.1145/2749469.2750419},
+  ISSN                     = {1063-6897},
+  Keywords                 = {DRAM chips;security of data;DRAM chip;analog properties;approximate DRAM;approximate computing;approximate memory platform;approximate output;commodity system;computation accuracy;digital components;distance metric;end-to-end deanonymizing effects;error pattern;guard bands;image manipulation program;mathematical model;memory cell decay times;opportunistic relaxation;power consumption;probable cause threat model;system identifying fingerprint;two-orders-of-magnitude difference;Approximation algorithms;Computational modeling;Fingerprint recognition;Hardware;Random access memory;Tin;Writing},
+  Owner                    = {MJ},
+  Timestamp                = {2017-09-11}
+}
+
+@InProceedings{rajshe_05,
+  Title                    = {{Design of an Architecture and Instruction-Set of a Reconfigurable ASIP for Software-Defined Radio}},
+  Author                   = {K.S. Raju and C. Shekhar and R.C. Joshi},
+  Booktitle                = {XXIIIth General Assembly of International Union of Radio Science (URSI)},
+  Year                     = {2005},
+
+  File                     = {rajshe_05.pdf:rajshe_05.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.27}
+}
+
+@Article{ram_07,
+  Title                    = {{S}oftware-{D}efined {R}adio {P}rospects for {M}ultistandard {M}obile {P}hones},
+  Author                   = {Ramacher, U.},
+  Journal                  = {Computer},
+  Year                     = {2007},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {62--69},
+  Volume                   = {40},
+
+  Doi                      = {10.1109/MC.2007.362},
+  File                     = {ram_07.pdf:ram_07.pdf:PDF},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{ram_06,
+  Title                    = {{The Future of Mobile Computing}},
+  Author                   = {U. Ramacher},
+  Booktitle                = {Proc. 6th International Symposium on Multiprocessor Systems-on-Chips (MPSoC'06)},
+  Year                     = {2006},
+
+  Address                  = {Estes Park, Colorado, USA},
+  Month                    = aug,
+  Pages                    = {281-294},
+
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.01}
+}
+
+@InProceedings{ramraa_11,
+  Title                    = {{A}rchitecture and implementation of a {S}oftware-{D}efined {R}adio baseband processor},
+  Author                   = {Ulrich Ramacher and Wolfgang Raab and J. A. Ulrich Hachmann and Dominik Langen and J{\"o}rg Berthold and R. Kramer and A. Schackow and Cyprian Grassmann and Mirko Sauermann and P. Szreder and F. Capar and G. Obradovic and W. Xu and Nico Br{\"u}ls and Kang Lee and Eugene Weber and Ray Kuhn and John Harrington},
+  Booktitle                = {ISCAS},
+  Year                     = {2011},
+  Pages                    = {2193-2196},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Ee                       = {http://dx.doi.org/10.1109/ISCAS.2011.5938035},
+  File                     = {ramraa_11.pdf:ramraa_11.pdf:PDF}
+}
+
+@InProceedings{ramwit_09,
+  Title                    = {{E}fficient and portable {SDR} waveform development: {T}he {N}ucleus concept},
+  Author                   = {Ramakrishnan, V. and Witte, E.M. and Kempf, T. and Kammler, D. and Ascheid, G. and Leupers, R. and Meyr, H. and Adrat, M. and Antweiler, M.},
+  Booktitle                = {Military Communications Conference, 2009. MILCOM 2009. IEEE},
+  Year                     = {2009},
+  Month                    = {oct.},
+  Pages                    = {1 -7},
+
+  Doi                      = {10.1109/MILCOM.2009.5379897},
+  File                     = {ramwit_09.pdf:ramwit_09.pdf:PDF},
+  Keywords                 = {cognitive radio;energy demand;interface properties;nucleus concept;portable SDR waveform development;software defined radios;software flexibility;wireless communication;wireless signal processing;cognitive radio;signal processing;software radio;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.12.04}
+}
+
+@Article{ram_06a,
+  Title                    = {{I}ntel({R}) {M}ulti-{C}ore {P}rocessors {M}aking the {M}ove to {Q}uad-{C}ore and {B}eyond},
+  Author                   = {Ramanathan, R.M.},
+  Journal                  = {Intel Corporation},
+  Year                     = {2006},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-06-05}
+}
+
+@Electronic{ram_09,
+  Title                    = {{C}hallenges and {S}olutions for {F}uture {M}ain {M}emory},
+  Author                   = {Rambus},
+  Month                    = {May},
+  Url                      = {\url{https://www.rambus.com/challenges-and-solutions-for-future-main-memory/}},
+  Year                     = {2009},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-08-10}
+}
+
+@InProceedings{ramflo_10,
+  Title                    = {{A}n {FPGA}-based architecture for linear and morphological image filtering},
+  Author                   = {Ramirez, J.M. and Flores, E.M. and Martínez-Carballido, J. and Enriquez, R. and Alarcón-Aquino, V. and Baez-Lopez, D.},
+  Booktitle                = {Electronics, Communications and Computer (CONIELECOMP), 2010 20th International Conference on},
+  Year                     = {2010},
+  Month                    = {Feb},
+  Pages                    = {90-95},
+
+  Abstract                 = {Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of real time algorithms suited to video image processing applications. The unique architecture of the FPGA has allowed the technology to be used in many applications encompassing all aspects of video image processing. Among those algorithms, linear filtering based on a 2D convolution, and non-linear 2D morphological filters, represent a basic set of image operations for a number of applications. In this work, an implementation of linear and morphological image filtering using a FPGA NexysII, Xilinx, Spartan 3E, with educational purposes, is presented. The system is connected to a USB port of a personal computer, which in that way form a powerful and low-cost design station. The FPGA-based system is accessed through a Matlab graphical user interface, which handles the communication setup. A comparison between results obtained from MATLAB simulations and the described FPGA-based implementation is presented.},
+  Cds_grade                = {2},
+  Cds_keywords             = {morphological filter, FPGA},
+  Cds_read                 = {2014-07-15},
+  Cds_review               = {no architectural details
+no energy numbers
+no GPU comparison},
+  Doi                      = {10.1109/CONIELECOMP.2010.5440788},
+  File                     = {ramflo_10.pdf:ramflo_10.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.07.15}
+}
+
+@MastersThesis{MTrane13,
+  Title                    = {{F}ast {M}orphological {I}mage {P}rocessing on {GPU} using {CUDA}},
+  Author                   = {Mugdha A. Rane},
+  School                   = {Department of Computer Engineering and Information Technology College of Engineering, Pune},
+  Year                     = {2013},
+
+  Owner                    = {Sadri},
+  Timestamp                = {2014.07.28}
+}
+
+@Article{ransor_11,
+  Title                    = {{M}ementos: {S}ystem {S}upport for {L}ong-running {C}omputation on {RFID}-scale {D}evices},
+  Author                   = {Ransford, Benjamin and Sorber, Jacob and Fu, Kevin},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {2011},
+
+  Month                    = mar,
+  Number                   = {1},
+  Pages                    = {159--170},
+  Volume                   = {39},
+
+  Acmid                    = {1950386},
+  Address                  = {New York, NY, USA},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Ransford:2011:MSS:1961295.1950386},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/1961295.1950386},
+  ISSN                     = {0163-5964},
+  Issue_date               = {March 2011},
+  Keywords                 = {TCS},
+  Keywords_original        = {computational rfid, energy-aware checkpointing, mementos, rfid-scale devices},
+  Numpages                 = {12},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/1961295.1950386}
+}
+
+@Article{raowri_98,
+  Title                    = {{A}pplication of {I}nterior-{P}oint {M}ethods to {M}odel {P}redictive {C}ontrol},
+  Author                   = {Rao, C. V. and Wright, S. J. and Rawlings, J. B.},
+  Journal                  = {Journal of Optimization Theory and Applications},
+  Year                     = {1998},
+
+  Month                    = {Dec},
+  Number                   = {3},
+  Pages                    = {723--757},
+  Volume                   = {99},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [50]},
+  Ccr_topic                = {NetControl Paper},
+  Day                      = {01},
+  Doi                      = {10.1023/A:1021711402723},
+  ISSN                     = {1573-2878},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR},
+  Url                      = {https://doi.org/10.1023/A:1021711402723}
+}
+
+@Article{raogar_71,
+  Title                    = {{C}yclic and multiresidue codes for arithmetic operations},
+  Author                   = {Rao, T. and Garcia, O.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1971},
+  Number                   = {1},
+  Pages                    = {85--91},
+  Volume                   = {17},
+
+  Doi                      = {10.1109/TIT.1971.1054579},
+  File                     = {raogar_71.pdf:raogar_71.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2011.08.04}
+}
+
+@Article{rao_68,
+  Title                    = {{E}rror-{C}hecking {L}ogic for {A}rithmetic-{T}ype {O}perations of a {P}rocessor},
+  Author                   = {Rao, T. R. N.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {1968},
+  Number                   = {9},
+  Pages                    = {845--849},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/TC.1968.229144},
+  File                     = {rao_68.pdf:rao_68.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.01.21}
+}
+
+@InProceedings{raodin_99,
+  Title                    = {{Saving Memory in Turbo-Decoders Using the Max-Log-MAP Algorithm}},
+  Author                   = {F. Raouafi and A. Dingninou and C. Berrou},
+  Booktitle                = {Proc. IEE Colloquium on Turbo Codes in Digital Broadcasting -- Could It Double Capacity?},
+  Year                     = {1999},
+  Month                    = nov,
+  Pages                    = {14/1--14/4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{raodou_00,
+  Title                    = {{Efficient Turbo Decoder Design and its Implementation on a Low-Cost, 16-Bit Fixed-Point DSP}},
+  Author                   = {F. Raouafi and C. Douillard and C. Berrou},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {339--342},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{rapgur_00,
+  Title                    = {{Investigation into Decoding Algorithm for Turbo Codes}},
+  Author                   = {D. Raphaeli and A. Gurevitz},
+  Journal                  = {Electronics Letters},
+  Year                     = {2000},
+
+  Month                    = apr,
+  Number                   = {9},
+  Pages                    = {809--810},
+  Volume                   = {36},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{rap_02,
+  Title                    = {{W}ireless communications: principles and practice},
+  Author                   = {Rappaort, Theodore S},
+  Publisher                = {Prentice-Hall},
+  Year                     = {2002}
+}
+
+@TechReport{ras_11,
+  Title                    = {{D}etermining {T}otal {C}ost of {O}wnership for {D}ata {C}enter and {N}etwork {R}oom {I}nfrastructure},
+  Author                   = {Neil Rasmussen},
+  Institution              = {Schneider Electric},
+  Year                     = {2011},
+  Note                     = {Rev. 4},
+  Number                   = {6},
+  Type                     = {White paper},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.11.22}
+}
+
+@Article{ratkav_08,
+  Title                    = {{A} {H}igh-{T}hroughput {M}aximum a {P}osteriori {P}robability {D}etector},
+  Author                   = {Ratnayake, R. and Kavcic, A. and Gu-Yeon Wei},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2008},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {1846--1858},
+  Volume                   = {43},
+
+  Doi                      = {10.1109/JSSC.2008.925404},
+  File                     = {ratkav_08.pdf:ratkav_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.08.14}
+}
+
+@InProceedings{rausmi_06,
+  Title                    = {{R}econfigurable {T}urbo/{V}iterbi {C}hannel {D}ecoder in the {C}oarse-{G}rained {M}ontium {A}rchitecture},
+  Author                   = {G.K. {Rauwerda} and G.J.M. {Smit} and C.R.W. {van Benthem} and P.M. {Heysters}},
+  Booktitle                = {Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'06)},
+  Year                     = {2006},
+
+  Address                  = {USA},
+  Month                    = {June},
+  Pages                    = {110--116},
+  Publisher                = {CSREA Press},
+
+  Abstract                 = {Mobile wireless communication systems become multi-mode systems. These future mobile systems employ multiple wireless communication standards, which are different by means of algorithms that are used to implement the baseband processing and the channel decoding. Efficient implementation of multiple wireless standards in mobile terminals requires energy-efficient and flexible hardware. We propose to implement both the baseband processing and channel decoding in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains many processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. We already showed the feasibility to implement the baseband processing of OFDM and WCDMA based communication systems in the MONTIUM. In this paper we implemented two kinds of channel decoders in the same MONTIUM architecture: Viterbi and Turbo decoding.},
+  File                     = {rausmi_06.pdf:rausmi_06.pdf:PDF}
+}
+
+@Article{raygro_14,
+  Title                    = {{A} {S}calable {S}uccessive-{C}ancellation {D}ecoder for {P}olar {C}odes},
+  Author                   = {A. J. Raymond and W. J. Gross},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2014},
+
+  Month                    = {Oct},
+  Number                   = {20},
+  Pages                    = {5339-5347},
+  Volume                   = {62},
+
+  Doi                      = {10.1109/TSP.2014.2347262},
+  ISSN                     = {1053-587X},
+  Keywords                 = {channel capacity;decoding;error correction codes;optimisation;Polar codes;SRAM;channel capacity;error-correcting codes;full-throughput decoding;novel semi-parallel encoder-based partial-sum computation module;optimization techniques;scalable successive-cancellation decoder algorithm;variable quantization scheme;very-low-complexity implementations;Clocks;Computer architecture;Decoding;Indexes;Quantization (signal);Random access memory;Vectors;Error-correcting codes;hardware implementation;polar codes;successive-cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{raygro_13,
+  Title                    = {{S}calable successive-cancellation hardware decoder for polar codes},
+  Author                   = {A. J. Raymond and W. J. Gross},
+  Booktitle                = {Global Conference on Signal and Information Processing (GlobalSIP), 2013 IEEE},
+  Year                     = {2013},
+  Month                    = {Dec},
+  Pages                    = {1282-1285},
+
+  Doi                      = {10.1109/GlobalSIP.2013.6737143},
+  Keywords                 = {channel capacity;decoding;error correction codes;field programmable gate arrays;linear codes;quantisation (signal);Altera Stratix IV FPGA;Arikan;SRAM;channel capacity;error-correcting codes;error-correction performance;finite lengths;polar codes;polar decoders;scalable hardware decoder;successive-cancellation algorithm;Clocks;Decoding;Encoding;Field programmable gate arrays;Hardware;Quantization (signal);Random access memory;Error-correcting codes;hardware implementation;polar codes;successive-cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{redpan_12,
+  Title                    = {{R}obust and resilient designs from the bottom-up: {T}echnology, {CAD}, circuit, and system issues},
+  Author                   = {Reddi, V.J. and Pan, D.Z. and Nassif, S.R. and Bowman, K.A.},
+  Booktitle                = {Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific},
+  Year                     = {2012},
+  Month                    = {30 2012-feb. 2},
+  Pages                    = {7 -16},
+
+  Cb_grade                 = {- ungelesen
+- Reliability},
+  Doi                      = {10.1109/ASPDAC.2012.6165064},
+  File                     = {redpan_12.pdf:redpan_12.pdf:PDF},
+  ISSN                     = {2153-6961},
+  Keywords                 = {CAD level;circuit level;circuit parameter variability;device parameter variability;high-performance energy-efficient system design;manufacturing process;reliability;resilient design;robust design;semiconductor industry;system level;system operation;system-level metrics;technology level;circuit CAD;circuit reliability;}
+}
+
+@InProceedings{redwal_17,
+  Title                    = {{E}mpirical {CPU} power modelling and estimation in the gem5 simulator},
+  Author                   = {B. K. Reddy and M. J. Walker and D. Balsamo and S. Diestelhorst and B. M. Al-Hashimi and G. V. Merrett},
+  Booktitle                = {2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
+  Year                     = {2017},
+  Month                    = {Sept},
+  Pages                    = {1-8},
+
+  Doi                      = {10.1109/PATMOS.2017.8106988},
+  Keywords                 = {cache storage;microprocessor chips;multiprocessing systems;power aware computing;DVFS level;PMC;design space exploration;dynamic voltage and frequency scaling level;empirical CPU power modelling;full-system architectural simulator;gem5 simulated activity statistics;hardware PMC;integrated model;performance monitoring counters;power management approaches;power simulators;simulated quadcore ARM Cortex-A15;Data models;Hardware;Microarchitecture;Power demand;Power measurement;Timing;Tools},
+  Owner                    = {MJ},
+  Timestamp                = {2018-06-19}
+}
+
+@InProceedings{redcle_10,
+  Title                    = {{P}ower consumption analysis and energy efficient optimization for turbo decoder implementation},
+  Author                   = {Reddy, P. and Clermidy, F. and Al Khayat, R. and Baghdadi, A. and Jezequel, M.},
+  Booktitle                = {Proc. Int System Chip (SoC) Symp},
+  Year                     = {2010},
+  Pages                    = {12--17},
+
+  Cb_grade                 = {ASIP - Brest},
+  Doi                      = {10.1109/ISSOC.2010.5625565},
+  File                     = {redcle_10.pdf:redcle_10.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.03.23}
+}
+
+@InProceedings{redcle_11,
+  Title                    = {{A} low complexity stopping criterion for reducing power consumption in turbo decoders},
+  Author                   = {Reddy, P. and Clermidy, F. and Baghdadi, A. and Jezequel, M.},
+  Booktitle                = {Proc. Design, Automation \& Test in Europe Conf. \& Exhibition (DATE)},
+  Year                     = {2011},
+  Pages                    = {1--6},
+
+  File                     = {redcle_11.pdf:redcle_11.pdf:PDF},
+  Keywords                 = {ASIP Brest},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.12}
+}
+
+@Article{reeshi_91,
+  Title                    = {{VLSI} design of inverse-free {B}erlekamp-{M}assey algorithm},
+  Author                   = {Irving S. Reed and Shih, M. T. and Truong, T. K.},
+  Journal                  = {Computers and Digital Techniques, IEE Proceedings E},
+  Year                     = {1991},
+
+  Month                    = sep,
+  Number                   = {5},
+  Pages                    = { 295-298},
+  Volume                   = {138},
+
+  Abstract                 = {The Berlekamp-Massey iterative algorithm for decoding BCH codes is modified to eliminate the calculation of inverses. This new algorithm is useful in the practical application of multiple-error-correcting BCH or RS codes. A VLSI architecture is developed for this algorithm.},
+  Cds_grade                = {0},
+  File                     = {reeshi_91.pdf:reeshi_91.pdf:PDF},
+  ISSN                     = {0143-7062},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2009.05.14}
+}
+
+@Article{reesol_60,
+  Title                    = {{P}olynomial {C}odes {O}ver {C}ertain {F}inite {F}ields},
+  Author                   = {I. S. Reed and G. Solomon},
+  Journal                  = {Journal of the Society for Industrial and Applied Mathematics},
+  Year                     = {1960},
+  Number                   = {2},
+  Pages                    = {300-304},
+  Volume                   = {8},
+
+  Doi                      = {10.1137/0108018},
+  Publisher                = {SIAM},
+  Url                      = {http://link.aip.org/link/?SMM/8/300/1}
+}
+
+@InProceedings{reease_97,
+  Title                    = {{A Novel Variance Estimator for Turbo-Code Decoding}},
+  Author                   = {M. C. Reed and J. Asenstorfer},
+  Booktitle                = {Proc. International Conference on Telecommunications},
+  Year                     = {1997},
+
+  Address                  = {Melbourne, Australia},
+  Month                    = apr,
+  Pages                    = {173--178},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{reepie_96,
+  Title                    = {{Turbo-Code Termination Schemes and a Novel Alternative for Short Frames}},
+  Author                   = {M. C. Reed and S. S. Pietrobon},
+  Booktitle                = {Proc. 1996 International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC '96)},
+  Year                     = {1996},
+
+  Address                  = {Taipei, Taiwan},
+  Month                    = oct,
+  Pages                    = {354--358},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{reewal_12,
+  Title                    = {{L}arge-{S}cale {C}redit {R}isk {L}oss {S}imulation},
+  Author                   = {Simon J. Rees and Joseph Walkenhorst},
+  Booktitle                = {GPU Computing Gems},
+  Publisher                = {Morgan Kaufmann},
+  Year                     = {2012},
+  Chapter                  = {24},
+  Edition                  = {Jade},
+  Editor                   = {Wen-Mei W. Hwu},
+  Pages                    = {323-335},
+  Volume                   = {2},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.31}
+}
+
+@InProceedings{refroy_11,
+  Title                    = {{A} new approach for {FEC} decoding based on the {BP} algorithm in {LTE} and {W}i{MAX} systems},
+  Author                   = {Refaey, A. and Roy, S. and Fortier, P.},
+  Booktitle                = {Information Theory (CWIT), 2011 12th Canadian Workshop on},
+  Year                     = {2011},
+  Month                    = {May},
+  Pages                    = {9-14},
+
+  Doi                      = {10.1109/CWIT.2011.5872112},
+  Keywords                 = {Long Term Evolution;WiMax;convolutional codes;forward error correction;iterative decoding;parity check codes;turbo codes;BP algorithm;EDGE;FEC decoding;GSM evolution;IS-54;LDPC;LTE;Long Term Evolution;WiMAX system;belief propagation;forward error correcting codes;low-complexity iterative decoding;low-density parity-check;parity-check matrix representation;tail-biting convolutional codes;turbo codes;universal decoder;wireless communication system;worldwide interoperability for microwave access;Convolutional codes;Decoding;Generators;Iterative decoding;Turbo codes;WiMAX},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@InProceedings{refroy_09,
+  Title                    = {{O}n the application of {BP} decoding to convolutional and turbo codes},
+  Author                   = {Refaey, Ahmed and Roy, Sebastien and Fortier, Paul},
+  Booktitle                = {Signals, Systems and Computers, 2009 Conference Record of the Forty-Third Asilomar Conference on},
+  Year                     = {2009},
+  Organization             = {IEEE},
+  Pages                    = {996--1001},
+
+  Owner                    = {kraft},
+  Timestamp                = {2018.05.31}
+}
+
+@Article{reisan_08,
+  Title                    = {{F}ault-{T}olerant {D}esign of the {IBM} {P}ower6 {M}icroprocessor},
+  Author                   = {Reick, K. and Sanda, P. N. and Swaney, S. and Kellington, J. W. and Mack, M. J. and Floyd, M. S. and Henderson, D.},
+  Journal                  = {IEEE Micro},
+  Year                     = {2008},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {30--38},
+  Volume                   = {28},
+
+  Doi                      = {10.1109/MM.2008.22},
+  File                     = {reisan_08.pdf:reisan_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.22}
+}
+
+@InProceedings{reigra_03,
+  Title                    = {{L}ow {C}omplexity {L}ist {D}etection for {H}igh-{R}ate {MIMO} {C}hannels},
+  Author                   = {Aaron B. Reid and Alex J. Grant and Adriel P. Kind},
+  Booktitle                = {in Proc. 4th Australian Commun. Theory Workshop},
+  Year                     = {2003},
+  Pages                    = {66--69},
+
+  File                     = {reigra_03.pdf:reigra_03.pdf:PDF},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.08.06}
+}
+
+@Electronic{rei_12,
+  Title                    = {{An Overview of Programming for Intel Xeon processors and Intel Xeon Phi coprocessors}},
+  Author                   = {James Reinders},
+  Note                     = {last access: 31 Aug 2017},
+  Organization             = {Intel},
+  Url                      = {http://download.intel.com/newsroom/kits/xeon/phi/pdfs/overview-programming-intel-xeon-intel-xeon-phi-coprocessors.pdf},
+  Year                     = {2012},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.12.03}
+}
+
+@Book{Reinders2015,
+  Title                    = {{H}igh {P}erformance {P}arallelism {P}earls: {M}ulticore and {M}any-core {P}rogramming {A}pproaches},
+  Author                   = {James Reinders and Jim Jeffers},
+  Publisher                = {Morgan Kaufmann Publishers Inc.},
+  Year                     = {2015},
+
+  Address                  = {San Francisco, CA, USA},
+  Volume                   = {2}
+}
+
+@Conference{reikuc_13,
+  Title                    = {{D}omain {C}ontrolled {A}rchitecture - {A} {N}ew {A}pproach for {L}arge {S}cale {S}oftware {I}ntegrated {A}utomotive {S}ystems},
+  Author                   = {Dominik Reinhardt and Markus Kucera},
+  Booktitle                = {Proceedings of the 3rd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS,},
+  Year                     = {2013},
+  Organization             = {INSTICC},
+  Pages                    = {221-226},
+  Publisher                = {SciTePress},
+
+  Doi                      = {10.5220/0004340702210226},
+  ISBN                     = {978-989-8565-43-3},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-25}
+}
+
+@InProceedings{reikuc_13a,
+  Title                    = {{D}omain {C}ontrolled {A}rchitecture - {A} {N}ew {A}pproach for {L}arge {S}cale {S}oftware {I}ntegrated {A}utomotive {S}ystems},
+  Author                   = {Reinhardt, Dominik and Kucera, Markus},
+  Booktitle                = {Proceedings of the PECCS2013 - International Conference on Pervasive and Embedded Computing and Communication Systems},
+  Year                     = {2013},
+
+  Location                 = {Barcelona, Spain},
+  Owner                    = {MJ},
+  Timestamp                = {2020-02-09}
+}
+
+@InProceedings{reisou_11,
+  Title                    = {{A} 65{N}m {VLSI} {I}mplementation for the {LTE} {T}urbo {D}ecoder},
+  Author                   = {Reis, Vinicius Torres dos and Souza, Ilan Schnitman},
+  Booktitle                = {Proceedings of the 24th Symposium on Integrated Circuits and Systems Design},
+  Year                     = {2011},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {155--160},
+  Publisher                = {ACM},
+  Series                   = {SBCCI '11},
+
+  Acmid                    = {2020912},
+  Doi                      = {10.1145/2020876.2020912},
+  ISBN                     = {978-1-4503-0828-1},
+  Keywords                 = {digital communications, turbo codes, vlsi},
+  Location                 = {Jo\&\#227;o Pessoa, Brazil},
+  Numpages                 = {6},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22},
+  Url                      = {http://doi.acm.org/10.1145/2020876.2020912}
+}
+
+@Article{renzhe_12,
+  Title                    = {{H}ardware {E}mulation of {W}ideband {C}orrelated {M}ultiple-{I}nput {M}ultiple-{O}utput {F}ading {C}hannels},
+  Author                   = {Ren, Fei and Zheng, Yahong},
+  Journal                  = {Journal of Signal Processing Systems},
+  Year                     = {2012},
+  Note                     = {10.1007/s11265-011-0605-y},
+  Pages                    = {273--284},
+  Volume                   = {66},
+
+  Abstract                 = {A low-complexity hardware emulator is proposed for wideband, correlated, multiple-input multiple-output (MIMO) fading channels. The proposed emulator generates multiple discrete-time channel impulse responses (CIR) at the symbol rate and incorporates three types of correlation functions of the subchannels via Kronecker product: the spatial correlation between transmit or receive elements, temporal correlation due to Doppler shifts, and inter-tap correlation due to multipaths. The Kronecker product is implemented by a novel mixed parallel-serial (mixed P-S) matrix multiplication method to reduce memory storage and to meet the real-time requirement in high data-rate, large MIMO size, or long CIR systems. We present two practical MIMO channel examples implemented on an Altera Stratix III EP3SL150F FPGA DSP development kit: a 2-by-2 MIMO WiMAX channel with a symbol rate of 1.25 million symbols/second and a 2-by-6 MIMO underwater acoustic channel with 100-tap CIR. Both examples meet real-time requirement using only 12–14% of hardware resources of the FPGA.},
+  Affiliation              = {Department of Electrical & Computer Engineering, Missouri University of Science and Technology, Rolla, MO 65409, USA},
+  File                     = {renzhe_12.pdf:renzhe_12.pdf:PDF},
+  ISSN                     = {1939-8018},
+  Issue                    = {3},
+  Keyword                  = {Technik},
+  Keywords                 = {MIMO},
+  Owner                    = {CdS},
+  Publisher                = {Springer New York},
+  Timestamp                = {2012.06.20},
+  Url                      = {http://dx.doi.org/10.1007/s11265-011-0605-y}
+}
+
+@TechReport{rcr_13,
+  Title                    = {{F}inancial {R}egulatory {R}eform: {F}inancial {C}risis {L}osses and {P}otential {I}mpacts of the {D}odd-{F}rank {A}ct},
+  Author                   = {{Report to Congressional Requesters}},
+  Institution              = {United States Government Accountability Office},
+  Year                     = {2013},
+  Month                    = {Jan},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.04},
+  Url                      = {http://www.gao.gov/assets/660/651322.pdf}
+}
+
+@Article{reyhas_04,
+  Title                    = {{L}ow {C}omplexity {B}it {P}arallel {A}rchitectures for {P}olynomial {B}asis {M}ultiplication over {GF}(2m)},
+  Author                   = {Reyhani-Masoleh, A. and Hasan, M.A.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {2004},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = { 945-959},
+  Volume                   = {53},
+
+  Abstract                 = {Representing the field elements with respect to the polynomial (or standard) basis, we consider bit parallel architectures for multiplication over the finite field GF(2m). In this effect, first we derive a new formulation for polynomial basis multiplication in terms of the reduction matrix Q. The main advantage of this new formulation is that it can be used with any field defining irreducible polynomial. Using this formulation, we then develop a generalized architecture for the multiplier and analyze the time and gate complexities of the proposed multiplier as a function of degree m and the reduction matrix Q. To the best of our knowledge, this is the first time that these complexities are given in terms of Q. Unlike most other articles on bit parallel finite field multipliers, here we also consider the number of signals to be routed in hardware implementation and we show that, compared to the well-known Mastrovito's multiplier, the proposed architecture has fewer routed signals. The proposed generalized architecture is further optimized for three special types of polynomials, namely, equally spaced polynomials, trinomials, and pentanomials. We have obtained explicit formulas and complexities of the multipliers for these three special irreducible polynomials. This makes it very easy for a designer to implement the proposed multipliers using hardware description languages like VHDL and Verilog with minimum knowledge of finite field arithmetic.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Galois Field Multiplier},
+  Date-added               = {2008-10-06 14:28:15 +0200},
+  Date-modified            = {2008-10-06 14:35:23 +0200},
+  Doi                      = {10.1109/TC.2004.47},
+  File                     = {reyhas_04.pdf:reyhas_04.pdf:PDF},
+  ISSN                     = {0018-9340},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{rheber_19,
+  Title                    = {{S}tructural {D}ata {C}ompression for {E}mbedded {L}ong {P}rediction {H}orizon {M}odel {P}redictive {C}ontrol on {R}esource-{C}onstrained {FPGA} {P}latforms},
+  Author                   = {C. C. {Rheinländer} and F. {Berkel} and M. {Douglas} and M. {Schäfer} and N. {Wehn} and S. {Liu}},
+  Booktitle                = {2019 1st International Conference on Electrical, Control and Instrumentation Engineering (ICECIE)},
+  Year                     = {2019},
+  Pages                    = {1-7},
+
+  Ccr_grade                = {b*s*},
+  Ccr_keywords             = {own paper},
+  Ccr_topic                = {NetControl},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR}
+}
+
+@InProceedings{rheweh_19,
+  Title                    = {{A}daptive {T}ransient {C}omputing for {P}ower-{N}eutral {E}mbedded {D}evices},
+  Author                   = {C. C. {Rheinländer} and N. {Wehn}},
+  Booktitle                = {2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
+  Year                     = {2019},
+  Pages                    = {63-68},
+
+  Ccr_grade                = {awesome},
+  Ccr_keywords             = {own paper},
+  Ccr_topic                = {ATC},
+  Keywords                 = {TCS},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-26}
+}
+
+@InProceedings{rheweh_16,
+  Title                    = {{P}recise synchronization time stamp generation for {B}luetooth low energy},
+  Author                   = {C. C. {Rheinländer} and N. {Wehn}},
+  Booktitle                = {2016 IEEE SENSORS},
+  Year                     = {2016},
+  Pages                    = {1-3},
+
+  Ccr_grade                = {awesome},
+  Ccr_keywords             = {own paper},
+  Ccr_topic                = {BLE_Sync},
+  Keywords                 = {BLE},
+  Owner                    = {CCR}
+}
+
+@Article{ribpou_13,
+  Title                    = {{A}pproximation behoves calibration},
+  Author                   = {André Ribeiro and Rolf Poulsen},
+  Journal                  = {Quantitative Finance Letters},
+  Year                     = {2013},
+
+  Month                    = mar,
+  Pages                    = {36-40},
+  Volume                   = {1},
+
+  Abstract                 = {Our aim with this paper is three-fold: first, to give a short overview of the recent literature on expansion methods for option pricing. This includes an Edgeworth-type formula whose terms are explicit for the Heston (1993) model. We initially thought this was a new result, but then we discov- ered Sartorelli (2010). The second aim is to test whether the expansion is accurate enough to be used for calibration to real-life data. Several papers, see Guillaume and Schoutens (2010) and references therein,† document that even at the best of times, calibration of the Heston model is a delicate matter. But with the turmoil in the financial markets since 2007, we are likely to be at the other end of that Dick- ens novel starter. And maybe the expansion literature just reports benign cases? The title of the paper gives the con- clusion. Expansion-based calibration offers approximately a factor 5 speed-up, is stable, and gives results that are accu- rate enough to be of practical use. The third aim is to put a good dataset of option prices in the public domain; daily observations of implied volatility surfaces for the S&P500- index over the period 2005–2009 synchronized with the index itself and with estimated complete term structures of interest rates and dividend yields.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Feller condition},
+  Doi                      = {10.1080/21649502.2013.803781},
+  File                     = {ribpou_13.pdf:ribpou_13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.11}
+}
+
+@Book{ric_06,
+  Title                    = {{M}athematical statistics and data analysis},
+  Author                   = {Rice, John},
+  Publisher                = {Cengage Learning},
+  Year                     = {2006},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.08.09}
+}
+
+@Book{ricurb_08,
+  Title                    = {{M}odern {C}oding {T}heory},
+  Author                   = {Tom Richardson and Ruediger Urbanke},
+  Publisher                = {Cambridge University Press},
+  Year                     = {2008},
+
+  Optnote                  = {ISBN 978-0521852296},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.01.20}
+}
+
+@Article{ricurb_03,
+  Title                    = {{The Renaissance of Gallager's Low-Density Pariy-Check Codes}},
+  Author                   = {T. Richardson and R. Urbanke},
+  Journal                  = {IEEE Communications Magazine},
+  Year                     = {2003},
+
+  Month                    = aug,
+  Pages                    = {126--131},
+  Volume                   = {41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{ricurb_01,
+  Title                    = {{The Capacity of Low-Density Parity-Check Codes Under Message-Passing Decoding}},
+  Author                   = {Richardson, T.J. and Urbanke, R.L.},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {599--618},
+  Volume                   = {47},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{ricsho_01,
+  Title                    = {{Design of Capacity-Approaching irregular Low-Density Parity-Check Codes}},
+  Author                   = {Richardson, T. J. and Shokrollahi, M. A. and Urbanke, R. L.},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {619--637},
+  Volume                   = {47},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{ricurb_01a,
+  Title                    = {{Efficient Encoding of Low-Density Parity-Check Codes}},
+  Author                   = {Richardson, T. J. and Urbanke, R. L.},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {638--656},
+  Volume                   = {47},
+
+  File                     = {ricurb_01a.pdf:ricurb_01a.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{ricgey_17,
+  Title                    = {{R}esource-{E}fficient {G}radient {M}ethods for {M}odel {P}redictive {P}ulse {P}attern {C}ontrol on an {FPGA}},
+  Author                   = {S. Richter and T. Geyer and M. Morari},
+  Journal                  = {IEEE Transactions on Control Systems Technology},
+  Year                     = {2017},
+
+  Month                    = {May},
+  Number                   = {3},
+  Pages                    = {828-841},
+  Volume                   = {25},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [28]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/TCST.2016.2577000},
+  ISSN                     = {1063-6536},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {digital arithmetic;digital signal processing chips;field programmable gate arrays;gradient methods;optimisation;power semiconductor devices;resource allocation;resource-efficient gradient methods;model predictive pulse pattern control;{FPGA};optimization-based model predictive pulse pattern controller;hardware resource usage;field-programmable gate array;problem reformulation;coldstarted classic gradient method;fixed-point arithmetic;switching transitions;digital signal processor-type multipliers;DSP;resource reduction;Switches;Field programmable gate arrays;Stators;Gradient methods;Predictive models;Clocks;Digital signal processing;Embedded optimization;field-programmable gate array ({FPGA});gradient methods;model predictive control;optimized pulse patterns (OPPs)},
+  Owner                    = {CCR}
+}
+
+@InProceedings{ricjon_09,
+  Title                    = {{R}eal-time input-constrained {MPC} using fast gradient methods},
+  Author                   = {S. Richter and C. N. Jones and M. Morari},
+  Booktitle                = {Proceedings of the 48h IEEE Conference on Decision and Control (CDC) held jointly with 2009 28th Chinese Control Conference},
+  Year                     = {2009},
+  Month                    = {Dec},
+  Pages                    = {7387-7393},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [60]; the first that introduced fast gradient methods to {MPC}},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/CDC.2009.5400619},
+  ISSN                     = {0191-2216},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {computational complexity;gradient methods;linear quadratic control;predictive control;real-time systems;real time input constrained {MPC};gradient methods;linear quadratic model predictive control;computational complexity analysis;online optimization methods;prespecified accuracy;warm-and cold-starting techniques;algorithmic simplicity;numerical simplicity;Gradient methods;Upper bound;Costs;Predictive models;Predictive control;Constraint optimization;Optimization methods;Computational modeling;Sampling methods;Stability},
+  Owner                    = {CCR}
+}
+
+@Article{ricfet_02,
+  Title                    = {{Parallel Interleaving on Parallel DSP Architectures}},
+  Author                   = {T. Richter and G. Fettweis},
+  Journal                  = {Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on},
+  Year                     = {2002},
+
+  Month                    = oct,
+  Pages                    = {195-200},
+
+  Address                  = {San Diego, USA},
+  File                     = {ricfet_02.pdf:ricfet_02.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{Rife1973,
+  Title                    = {{D}igital {T}one {P}arameter {E}stimation in the {P}resence of {G}aussian {N}oise},
+  Author                   = {Rife, D.C.},
+  Publisher                = {Polytechnic Institute of Brooklyn},
+  Year                     = {1973},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.03.03},
+  Url                      = {http://books.google.de/books?id=Bl5XngEACAAJ}
+}
+
+@Article{rifboo_74,
+  Title                    = {{S}ingle tone parameter estimation from discrete-time observations},
+  Author                   = {Rife, D. and Boorstyn, R.R.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1974},
+
+  Month                    = {Sep},
+  Number                   = {5},
+  Pages                    = {591-598},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/TIT.1974.1055282},
+  ISSN                     = {0018-9448},
+  Keywords                 = {Parameter estimation;maximum-likelihood (ML) estimation;Algorithm design and analysis;Analytical models;Discrete Fourier transforms;Maximum likelihood estimation;Parameter estimation;Radar applications;Radar measurements;Sampling methods;System testing;Telephony},
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-07}
+}
+
+@Article{Rife1974,
+  Title                    = {{S}ingle {T}one {P}arameter {E}stimation from {D}iscrete-time {O}bservations},
+  Author                   = {Rife, D. and Boorstyn, R.R.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1974},
+
+  Month                    = {Sep},
+  Number                   = {5},
+  Pages                    = {591-598},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/TIT.1974.1055282},
+  ISSN                     = {0018-9448},
+  Keywords                 = {Parameter estimation;maximum-likelihood (ML) estimation;Algorithm design and analysis;Analytical models;Discrete Fourier transforms;Maximum likelihood estimation;Parameter estimation;Radar applications;Radar measurements;Sampling methods;System testing;Telephony},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.25}
+}
+
+@PhdThesis{Phdrista10,
+  Title                    = {{E}ntwurfsraumexploration heterogener {M}ulti-{P}rozessor-{S}ysteme},
+  Author                   = {Bastian Ristau},
+  School                   = {TU Dresden},
+  Year                     = {2010},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {MPSoC, Mapping},
+  File                     = {Phdrista10.pdf:Phdrista10.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.08.11}
+}
+
+@InProceedings{rislim_09,
+  Title                    = {{D}imensioning heterogeneous {MPS}o{C}s via parallelism analysis},
+  Author                   = {Bastian Ristau and Torsten Limberg and Oliver Arnold and Gerhard Fettweis},
+  Booktitle                = {Proc. DATE '09. Design, Automation \& Test in Europe Conf. \& Exhibition},
+  Year                     = {2009},
+  Pages                    = {554--557},
+
+  Abstract                 = {Abstract—In embedded computing we face a continuously
+growing algorithm complexity combined with a constantly rising
+number of applications running on a single system. Multi-core
+systems are becoming popular to cope with these requirements.
+Growing computational complexity is handled by increasing the
+number of cores and core types within one system – leading to
+heterogeneous many-core MPSoCs in the near future. One key
+challenge in designing such systems is to determine the number of
+cores required to meet performance, power and area constraints.
+In this paper we present a methodology that helps dimensioning
+these systems via a novel parallelism analysis methodology within
+seconds. The presented methodology has an average performance
+estimation error of less than 4% compared to transaction level
+simulation.},
+  Cds_grade                = {4},
+  Cds_keywords             = {MPSoC, Design, Mapping, Tool,},
+  Cds_read                 = {2010-06-02},
+  Cds_review               = {static analysis method of how many cores should be used in an MPSoC
+based on graphs, gives estimation of speedup related to number of cores, also of different core types},
+  File                     = {rislim_09.pdf:rislim_09.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.06.01}
+}
+
+@Article{rivgup_11,
+  Title                    = {{E}rror {T}olerance in {S}erver {C}lass {P}rocessors},
+  Author                   = {Rivers, J. A. and Gupta, M. S. and Jeonghee Shin and Kudva, P. N. and Bose, P.},
+  Journal                  = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
+  Year                     = {2011},
+  Number                   = {7},
+  Pages                    = {945--959},
+  Volume                   = {30},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Gupta
+- Empfehlung Norbert, Server, IBM},
+  Doi                      = {10.1109/TCAD.2011.2158100},
+  File                     = {rivgup_11.pdf:rivgup_11.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{rixdal_00,
+  Title                    = {{M}emory {A}ccess {S}cheduling},
+  Author                   = {Rixner, Scott and Dally, William J. and Kapasi, Ujval J. and Mattson, Peter and Owens, John D.},
+  Booktitle                = {Proceedings of the 27th Annual International Symposium on Computer Architecture},
+  Year                     = {2000},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {128--138},
+  Publisher                = {ACM},
+  Series                   = {ISCA '00},
+
+  Acmid                    = {339668},
+  Doi                      = {10.1145/339647.339668},
+  ISBN                     = {1-58113-232-8},
+  Location                 = {Vancouver, British Columbia, Canada},
+  Numpages                 = {11},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20},
+  Url                      = {http://doi.acm.org/10.1145/339647.339668}
+}
+
+@InProceedings{rob_97,
+  Title                    = {{An Overview of Bandwidth Efficient Turbo Coding Schemes}},
+  Author                   = {P. Robertson},
+  Booktitle                = {Proc. 1st International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {1997},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {103--110},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{rob_94,
+  Title                    = {{Illuminating the Structure of Code and Decoder of Parallel Concatenated Recursive Systematic (Turbo) Codes}},
+  Author                   = {P. Robertson},
+  Booktitle                = {Proc. 1994 Global Telecommunications Conference (GLOBECOM '94)},
+  Year                     = {1994},
+
+  Address                  = {San Francisco, California, USA},
+  Month                    = dec,
+  Pages                    = {1298--1303},
+
+  File                     = {rob_94.pdf:rob_94.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{robhoe_97,
+  Title                    = {{Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding}},
+  Author                   = {P. Robertson and P. Hoeher and E. Villebrun},
+  Journal                  = {European Transactions on Telecommunications (ETT)},
+  Year                     = {1997},
+
+  Month                    = mar # {--} # apr,
+  Number                   = {2},
+  Pages                    = {119--125},
+  Volume                   = {8},
+
+  File                     = {robhoe_97.pdf:robhoe_97.pdf:PDF},
+  Optnote                  = {Almost the same as ICC '95 paper},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Robertson1995,
+  Title                    = {{A} comparison of optimal and sub-optimal {MAP} decoding algorithms operating in the log domain},
+  Author                   = {Robertson, P. and Villebrun, E. and Hoeher, P.},
+  Booktitle                = {Communications, 1995. ICC '95 Seattle, 'Gateway to Globalization', 1995 IEEE International Conference on},
+  Year                     = {1995},
+  Month                    = {Jun},
+  Pages                    = {1009-1013 vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/ICC.1995.524253},
+  Keywords                 = {Markov processes;Viterbi decoding;computational complexity;convolutional codes;maximum likelihood decoding;maximum likelihood estimation;quantisation (signal);Markov process;SOVA;Turbo decoding;computational complexity reduction;log domain;log-MAP algorithm;low SNR;max function;max-log-MAP;optimal MAP decoding algorithms;quantization effects;recursive systematic convolutional component codes;simulations;soft-output Viterbi algorithm;suboptimal MAP decoding algorithms;Communications technology;Computational complexity;Convolution;Convolutional codes;Decoding;Markov processes;Quantization;State estimation;Turbo codes;Viterbi algorithm},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.14}
+}
+
+@InProceedings{robvil_95,
+  Title                    = {{A Comparison of Optimal and Sub-Optimal MAP decoding Algorithms Operating in the Log-Domain}},
+  Author                   = {P. Robertson and E. Villebrun and P. Hoeher},
+  Booktitle                = {Proc. 1995 International Conference on Communications (ICC '95)},
+  Year                     = {1995},
+
+  Address                  = {Seattle, Washington, USA},
+  Month                    = jun,
+  Pages                    = {1009--1013},
+
+  File                     = {robvil_95.pdf:robvil_95.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{robw_98,
+  Title                    = {{Bandwidth-Efficient Turbo Trellis-Coded Modulation Using Punctured Component Codes}},
+  Author                   = {P. Robertson and T. Wörz},
+  Journal                  = {IEEE Journal On Selected Areas In Communications},
+  Year                     = {1998},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {206-218},
+  Volume                   = {16},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{roc_88,
+  Title                    = {{A}n {SEU}-hardened {CMOS} data latch design},
+  Author                   = {Rockett, L. R. Jr.},
+  Journal                  = {IEEE Transactions on Nuclear Science},
+  Year                     = {1988},
+
+  Month                    = dec,
+  Number                   = {6},
+  Pages                    = {1682--1687},
+  Volume                   = {35},
+
+  Doi                      = {10.1109/23.25522},
+  File                     = {roc_88.pdf:roc_88.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Article{roc_96,
+  Title                    = {{I}ndexing memory banks to maximize page mode hit percentage and minimize memory latency},
+  Author                   = {Rockicki, Tomas},
+  Journal                  = {Hewlett-Packard Laboratories Technical Report, HPL-96-95},
+  Year                     = {1996},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11}
+}
+
+@Article{rodhem_11,
+  Title                    = {{T}he {S}tructural {S}imulation {T}oolkit},
+  Author                   = {Rodrigues, A. F. and Hemmert, K. S. and Barrett, B. W. and Kersey, C. and Oldfield, R. and Weston, M. and Risen, R. and Cook, J. and Rosenfeld, P. and CooperBalls, E. and Jacob, B.},
+  Journal                  = {SIGMETRICS Perform. Eval. Rev.},
+  Year                     = {2011},
+
+  Month                    = mar,
+  Number                   = {4},
+  Pages                    = {37--42},
+  Volume                   = {38},
+
+  Acmid                    = {1964225},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/1964218.1964225},
+  ISSN                     = {0163-5999},
+  Issue_date               = {March 2011},
+  Keywords                 = {SST, architecture, performance analysis, simulation},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2017-06-13},
+  Url                      = {http://doi.acm.org/10.1145/1964218.1964225}
+}
+
+@InProceedings{rodbal_15,
+  Title                    = {{A}pproaches to {T}ransient {C}omputing for {E}nergy {H}arvesting {S}ystems: {A} {Q}uantitative {E}valuation},
+  Author                   = {Rodriguez Arreola, Alberto and Balsamo, Domenico and Das, Anup K. and Weddell, Alex S. and Brunelli, Davide and Al-Hashimi, Bashir M. and Merrett, Geoff V.},
+  Booktitle                = {Proceedings of the 3rd International Workshop on Energy Harvesting \&\#38; Energy Neutral Sensing Systems},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {3--8},
+  Publisher                = {ACM},
+  Series                   = {ENSsys '15},
+
+  Acmid                    = {2820652},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {RodriguezArreola:2015:ATC:2820645.2820652},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/2820645.2820652},
+  ISBN                     = {978-1-4503-3837-0},
+  Keywords                 = {TCS},
+  Keywords_original        = {IoT, checkpoint, energy harvesting, hibernus, mementos, photo voltaic cells, quickrecall, transient computing, wind turbines},
+  Location                 = {Seoul, South Korea},
+  Numpages                 = {6},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/2820645.2820652}
+}
+
+@Article{rodbal_18,
+  Title                    = {{RESTOP}: {R}etaining {E}xternal {P}eripheral {S}tate in {I}ntermittently-{P}owered {S}ensor {S}ystems},
+  Author                   = {Rodriguez Arreola, Alberto and Balsamo, Domenico and Merrett, Geoff V. and Weddell, Alex S.},
+  Journal                  = {Sensors},
+  Year                     = {2018},
+  Number                   = {1},
+  Volume                   = {18},
+
+  Article-number           = {172},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {s18010172},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.3390/s18010172},
+  ISSN                     = {1424-8220},
+  Keywords                 = {TCS},
+  Owner                    = {CCR},
+  Url                      = {http://www.mdpi.com/1424-8220/18/1/172}
+}
+
+@InProceedings{rodbal_17,
+  Title                    = {{I}ntermittently-powered energy harvesting step counter for fitness tracking},
+  Author                   = {A. Rodriguez and D. Balsamo and Z. Luo and S. P. Beeby and G. V. Merrett and A. S. Weddel},
+  Booktitle                = {2017 IEEE Sensors Applications Symposium (SAS)},
+  Year                     = {2017},
+  Month                    = {March},
+  Pages                    = {1-6},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7894114},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/SAS.2017.7894114},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;energy storage element removal;event detection sensor;ferroelectret insole;fitness tracking;footsteps energy harvesting;integrated wearable applications;intermittently-powered energy harvesting step counter;Accelerometers;Capacitance;Capacitors;Energy harvesting;Legged locomotion;Nonvolatile memory;Radiation detectors;Energy Harvesting;Event Sensor;Ferroelectret Insole;Intermittent Source;Step Counter},
+  Owner                    = {CCR}
+}
+
+@Misc{gfkglobal14,
+  Title                    = {{G}lobal smartphone sales exceed 1.2b units in 2014},
+
+  Author                   = {Rogers, Wes},
+  HowPublished             = {GfK NOP Limited, 25 Canada Square, Canary Wharf, London E14 5LQ. \url{http://www.gfk.com/news-and-events/press-room/press-releases/pages/global-smartphone-sales-exceed-1-2b-units-in-2014.aspx}},
+  Month                    = feb,
+  Note                     = {last access 2015-06-01},
+  Year                     = {2014},
+
+  Language                 = {en},
+  Organization             = {GfK NOP Limited},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01},
+  Url                      = {http://www.gfk.com/news-and-events/press-room/press-releases/pages/global-smartphone-sales-exceed-1-2b-units-in-2014.aspx}
+}
+
+@Article{rom_55,
+  Title                    = {{V}ereinfachte numerische integration},
+  Author                   = {Romberg, Werner},
+  Journal                  = {Det Kongelige Norske Videnskabers Selskab Forhandlinger},
+  Year                     = {1955},
+  Number                   = {7},
+  Pages                    = {30--36},
+  Volume                   = {28},
+
+  File                     = {rom_55.pdf:rom_55.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.10}
+}
+
+@Article{roscoo_11,
+  Title                    = {{DRAMS}im2: {A} {C}ycle {A}ccurate {M}emory {S}ystem {S}imulator},
+  Author                   = {Rosenfeld, Paul and Cooper-Balis, Elliot and Jacob, Bruce},
+  Journal                  = {Computer Architecture Letters},
+  Year                     = {2011},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {16-19},
+  Volume                   = {10},
+
+  Doi                      = {10.1109/L-CA.2011.4},
+  ISSN                     = {1556-6056},
+  Keywords                 = {DRAM chips;memory architecture;memory cards;DDR2/3 memory system model;DRAMSim2 simulation;DRAMSim2 timing;Verilog model;cycle accurate memory system simulator;trace-based simulation;visualization tool;Computational modeling;Driver circuits;Hardware design languages;Load modeling;Object oriented modeling;Random access memory;Timing;DRAM;Primary memory;Simulation},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.17}
+}
+
+@Article{Rosing2007,
+  Title                    = {{Power and Reliability Management of SoCs}},
+  Author                   = {Rosing, T.S. and Mihic, K. and De Micheli, G.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2007},
+
+  Month                    = {April},
+  Number                   = {4},
+  Pages                    = {391-403},
+  Volume                   = {15},
+
+  Doi                      = {10.1109/TVLSI.2007.895245},
+  ISSN                     = {1063-8210},
+  Keywords                 = {embedded systems;industrial property;integrated circuit reliability;integrated circuit testing;system-on-chip;embedded systems;intellectual property;power management;reliability management;system-on-chip;transistor scaling;Constraint optimization;Embedded system;Energy consumption;Energy management;Error analysis;Power system interconnection;Power system management;Power system reliability;Temperature sensors;Voltage;Optimal control;power consumption;reliability management}
+}
+
+@Article{Rosnes2005,
+  Title                    = {{I}mproved algorithms for the determination of turbo-code weight distributions},
+  Author                   = {Rosnes, E. and Ytrehus, Y.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2005},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {20--26},
+  Volume                   = {53},
+
+  Doi                      = {10.1109/TCOMM.2004.840632},
+  Owner                    = {punekar},
+  Timestamp                = {2009.09.04}
+}
+
+@Article{RosPul_17,
+  Title                    = {{E}nergy-{E}fficient {N}ear-{T}hreshold {P}arallel {C}omputing: {T}he {PULP}v2 {C}luster},
+  Author                   = {D. {Rossi} and A. {Pullini} and I. {Loi} and M. {Gautschi} and F. K. {Gürkaynak} and A. {Teman} and J. {Constantin} and A. {Burg} and I. {Miro-Panades} and E. {Beignè} and F. {Clermidy} and P. {Flatresse} and L. {Benini}},
+  Journal                  = {IEEE Micro},
+  Year                     = {2017},
+
+  Month                    = {Sep.},
+  Number                   = {5},
+  Pages                    = {20-31},
+  Volume                   = {37},
+
+  Doi                      = {10.1109/MM.2017.3711645},
+  ISSN                     = {0272-1732},
+  Keywords                 = {Internet of Things;low-power electronics;parallel processing;system-on-chip;near-threshold parallel computing;PULPv2 Cluster;ultra-low-power parallel computing platform;system-on-chip embodiment;SoC;near-sensor processing tasks;first-generation Parallel Ultra-Low-Power architecture;Internet of Things applications;word length 32.0 bit;Random access memory;Energy efficiency;Memory management;System-on-chip;Low power electronics;Reduced instruction set computing;Power system management;energy efficiency;parallel processing;power management;body biasing;UTBB FD-SOI}
+}
+
+@Misc{rospython14,
+  Title                    = {{P}ython {R}eference {M}anual},
+
+  Author                   = {van Rossum, Guido and Kuchling, A. M. and L. Drake Jr., Fred},
+  HowPublished             = {\url{https://www.python.org}},
+  Month                    = {October},
+  Year                     = {2014, Last Access: 23.02.2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.23}
+}
+
+@Article{rotbel_14,
+  Title                    = {{E}fficient {P}arallel {T}urbo-{D}ecoding for {H}igh-{T}hroughput {W}ireless {S}ystems},
+  Author                   = {C. Roth and S. Belfanti and C. Benkeser and Qiuting Huang},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2014},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {1824-1835},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCSI.2013.2290831},
+  File                     = {rotbel_14.pdf:rotbel_14.pdf:PDF},
+  ISSN                     = {1549-8328},
+  Keywords                 = {MIMO communication;VLSI;maximum likelihood decoding;turbo codes;MAP component decoders;SISO;VLSI implementation;code rates;error rate performance;high throughput wireless systems;maximum a-posteriori;parallel turbo decoding;sliding-window soft-input soft-output;window length;wireless communication systems;Computer architecture;Decoding;Standards;Systematics;Throughput;Very large scale integration;Wireless communication;3GPP-LTE-Advanced;soft-input soft-output (SISO) maximum a-posteriori (MAP) decoding;turbo codes and parallel decoding;very-large scale integration (VLSI);wireless communications},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{rotben_12,
+  Title                    = {{D}ata mapping for unreliable memories},
+  Author                   = {Roth, C. and Benkeser, C. and Studer, C. and Karakonstantis, G. and Burg, A.},
+  Booktitle                = {Communication, Control, and Computing (Allerton), 2012 50th Annual Allerton Conference on},
+  Year                     = {2012},
+  Pages                    = {679-685},
+
+  Doi                      = {10.1109/Allerton.2012.6483283},
+  File                     = {rotben_12.pdf:rotben_12.pdf:PDF},
+  Keywords                 = {data structures;digital integrated circuits;reliability;semiconductor technology;signal processing;DSP systems;coded communication systems;data mapping;digital integrated circuits;digital signal processing;error-rate performance;optimized data representations;reliability issues;semiconductor process technologies;system reliability;unreliable memories;Circuit faults;Communication systems;Digital signal processing;Integrated circuit modeling;Robustness;Signal to noise ratio},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@InProceedings{rovgen_09,
+  Title                    = {{A} flexible state-metric recursion unit for a multi-standard {BCJR} decoder},
+  Author                   = {Rovini, M. and Gentile, G. and Fanucci, L.},
+  Booktitle                = {Proc. 3rd Int Signals, Circuits and Systems (SCS) Conf},
+  Year                     = {2009},
+  Pages                    = {1--6},
+
+  Cb_grade                 = {001 
+ASIP, multi-standard, ACS 
+Relevance: high 
+
+2010-10-05
+Flexible ACS Unit with 4 double butterflies like in FlexiTreP
+- Uses Normalization instead of Modulo
+
+Open issues:
+- How is normalization done (selection of Metric)
+- How/Why are inputs truncated/extended
+
+s.a.:
+"Towards Multi Std. Channel Decoding, eingereicht für DATE '11
+"A Multi-Standard Flexible Turbo-LDPC Decoder via ASIC Design" (Turbo Code Symposium)},
+  Doi                      = {10.1109/ICSCS.2009.5412319},
+  File                     = {rovgen_09.pdf:rovgen_09.pdf:PDF},
+  Keywords                 = {ASIP Turbo},
+  Owner                    = {Brehm},
+  Timestamp                = {2010.05.12}
+}
+
+@Article{rovgen_07a,
+  Title                    = {{M}ulti-size circular shifting networks for decoders of structured {LDPC} codes},
+  Author                   = {Rovini, M. and Gentile, G. and Fanucci, L.},
+  Journal                  = {Electronics Letters},
+  Year                     = {2007},
+
+  Month                    = aug,
+  Number                   = {17},
+  Pages                    = {938--940},
+  Volume                   = {43},
+
+  Doi                      = {10.1049/el:20071157},
+  File                     = {rovgen_07a.pdf:rovgen_07a.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.17}
+}
+
+@InProceedings{rovgen_07,
+  Title                    = {{A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes}},
+  Author                   = {Massimo Rovini and Giuseppe Gentile and Francesco Rossi and Luca Fanucci},
+  Booktitle                = {Proc. 2007 Global Telecommunications Conference (GLOBECOM '07)},
+  Year                     = {2007},
+
+  Address                  = {Washington, USA},
+  Month                    = nov,
+
+  File                     = {rovgen_07.pdf:rovgen_07.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{rovins_05,
+  Title                    = {{VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes}},
+  Author                   = {M. Rovini and N. Insalata and F.Rossi and L. Fanucci},
+  Booktitle                = {Proc. 8th Euromicro Conference on Digital System Design (DSD)},
+  Year                     = {2005},
+  Month                    = aug,
+  Pages                    = {202-209},
+
+  File                     = {rovins_05.pdf:rovins_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{rovins_05a,
+  Title                    = {{LDPC Decoding in Fixed-Point Precision: a Systematic Quantisation Study}},
+  Author                   = {Massimo Rovini and Nicola Insalata and Francesco Rossi and Luca Fanucci},
+  Booktitle                = {Proc. 2005 SoftCOM},
+  Year                     = {2005},
+
+  Address                  = {Split, Croatia},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{rovros_06,
+  Title                    = {{Layered Decoding of Non-Layered LDPC Codes}},
+  Author                   = {M. Rovini and F.o Rossi and P.e Ciao and N. Insalata and L. Fanucci},
+  Booktitle                = {Proc. 9th EUROMICRO Conference on Digital System Design (DSD'06)},
+  Year                     = {2006},
+
+  Address                  = {Dubrovnik, Croatia},
+  Month                    = sep,
+  Pages                    = {537--544},
+
+  File                     = {rovros_06.pdf:rovros_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{row_10,
+  Title                    = {{S}ilicon-{E}fficient {DSP}s and {D}igital {A}rchitecture for {LTE} {B}aseband},
+  Author                   = {C. Rowen},
+  Booktitle                = {10th International Forum on Embedded MPSoC and Multicore},
+  Year                     = {2010},
+
+  Address                  = {Gifu, Japan},
+  Month                    = aug,
+
+  Owner                    = {brehm},
+  Timestamp                = {2011.04.20}
+}
+
+@InProceedings{row_09,
+  Title                    = {{E}nergy-{E}fficient {LTE} {B}aseband with {E}xtensible {D}ataplane {P}rocessor {U}nits},
+  Author                   = {C. Rowen},
+  Booktitle                = {9th International Forum on Embedded MPSoC and Multicore},
+  Year                     = {2009},
+
+  Address                  = {Savanna, USA},
+  Month                    = aug,
+
+  Owner                    = {kienle},
+  Timestamp                = {2010.01.15}
+}
+
+@Book{row_04,
+  Title                    = {{Engineering the Complex SOC. Fast, Flexible Design with Configurable Processors.}},
+  Author                   = {C. Rowen},
+  Publisher                = {Prentice Hall PTR},
+  Year                     = {2004},
+
+  Address                  = {Upper Saddle River, New Jersey, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Rowen2004a,
+  Title                    = {{Engineering Complex SoCs}},
+
+  Author                   = {C. Rowen and N. Wehn and M. Baron and S. Leibson},
+  HowPublished             = {International Symposium on System-on-Chips, Tutorial},
+  Month                    = oct,
+  Year                     = {2004},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Misc{rowengineering04,
+  Title                    = {{Engineering Complex SoCs}},
+
+  Author                   = {C. Rowen and N. Wehn and M. Baron and S. Leibson},
+  HowPublished             = {International Symposium on System-on-Chips, Tutorial},
+  Month                    = oct,
+  Year                     = {2004},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@InProceedings{rowsan_97,
+  Title                    = {{I}nterface-based design},
+  Author                   = {Ja. A. Rowson and A. Sangiovanni-Vincentelli},
+  Booktitle                = {Proceedings of the Design automation Conference},
+  Year                     = {1997},
+  Pages                    = {178-183},
+
+  Abstract                 = {A new system design methodology is proposed that separates communication
+from behavior. To demonstrate the methodology we
+applied it to a simple ATM design. Since verification is clearly a
+major stumbling block for large system design, we focussed on the
+verification aspects of our methodology.
+In particular, a simulator was developed that is based on the communication
+paradigm typical of our methodology. The simulator
+gives substantial performance improvements without sacrificing
+user access to detail.
+Finally, the potential for this methodology to improve verification,
+modeling and synthesis is explored.},
+  Cds_grade                = {3},
+  Cds_keywords             = {methodology, modelling, design, communication},
+  Cds_read                 = {2009-03-17},
+  Cds_review               = {modelling approach: separating communication from behavior
+formlerly: design methodologies based on 1) formalization, 2) abstraction, 3) decomposition},
+  File                     = {rowsan_97.pdf:rowsan_97.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.03.16}
+}
+
+@Article{roz_01,
+  Title                    = {{Systems-on-chip: what are the limits?}},
+  Author                   = {E. Roza},
+  Journal                  = {IEE Electronics \& Communication Engineering Journal},
+  Year                     = {2001},
+
+  Month                    = dec,
+  Number                   = {6},
+  Pages                    = {249--255},
+  Volume                   = {13},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{rucsay_11,
+  Title                    = {{P}ricing {A}merican options in the {H}eston model: a close look on incorporating correlation},
+  Author                   = {P. Ruckdeschel and T. Sayer and A. Szimayer},
+  Booktitle                = {Berichte des Fraunhofer ITWM},
+  Publisher                = {Fraunhofer ITWM},
+  Year                     = {2011},
+  Volume                   = {204},
+
+  Cds_grade                = {0},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.07},
+  Url                      = {http://www.itwm.fraunhofer.de/fileadmin/ITWM-Media/Zentral/Pdf/Berichte_ITWM/2011/bericht_204.pdf}
+}
+
+@Booklet{ruf_05,
+  Title                    = {{S}ystem{C}},
+  Author                   = {Jürgen Ruf},
+  Year                     = {2005},
+
+  Cds_grade                = {0},
+  File                     = {ruf_05.pdf:ruf_05.pdf:PDF},
+  LastChecked              = {2005-11-03},
+  Owner                    = {CdS},
+  Timestamp                = {2009.04.06}
+}
+
+@Electronic{Rukhin2010,
+  Title                    = {{A} {S}tatistical {T}est {S}uite for {R}andom and {P}seudorandom {N}umber {G}enerators for {C}ryptographic {A}pplications},
+  Author                   = {Andrew Rukhin and Juan Soto and James Nechvatal and Miles Smid and Elaine Barker and Stefan Leigh and Mark Levenson and Mark Vangel and David Banks and Alan Heckert and James Dray and San Vo},
+  HowPublished             = {\url{http://csrc.nist.gov/publications/nistpubs/800-22-rev1a/SP800-22rev1a.pdf}},
+  Language                 = {en},
+  Month                    = apr,
+  Note                     = {Special Publication 800-22, Revision 1a},
+  Organization             = {National Institute of Standards and Technology, U.S. Department of Commerce},
+  Url                      = {http://csrc.nist.gov/publications/nistpubs/800-22-rev1a/SP800-22rev1a.pdf},
+  Year                     = {2010},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random numbers, test},
+  File                     = {ruksot_10.pdf:ruksot_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@Electronic{ruksot_10,
+  Title                    = {{A} {S}tatistical {T}est {S}uite for {R}andom and {P}seudorandom {N}umber {G}enerators for {C}ryptographic {A}pplications},
+  Author                   = {Andrew Rukhin and Juan Soto and James Nechvatal and Miles Smid and Elaine Barker and Stefan Leigh and Mark Levenson and Mark Vangel and David Banks and Alan Heckert and James Dray and San Vo},
+  HowPublished             = {\url{http://csrc.nist.gov/publications/nistpubs/800-22-rev1a/SP800-22rev1a.pdf}},
+  Language                 = {en},
+  Month                    = apr,
+  Note                     = {Special Publication 800-22, Revision 1a, last access 2014-07-02},
+  Organization             = {National Institute of Standards and Technology, U.S. Department of Commerce},
+  Url                      = {http://csrc.nist.gov/publications/nistpubs/800-22-rev1a/SP800-22rev1a.pdf},
+  Year                     = {2010},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random numbers, test},
+  File                     = {ruksot_10.pdf:ruksot_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@Misc{rus_99,
+  Title                    = {{P}artitioning in {A}vionics {A}rchitectures: {R}equirements, {M}echanisms, and {A}ssurance},
+
+  Author                   = {John Rushby},
+  Year                     = {1999},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-03}
+}
+
+@InProceedings{rusret_03,
+  Title                    = {{F}rom high-level {P}etri nets to {S}ystem{C}},
+  Author                   = {C. {Rust} and A. {Rettberg} and K. {Gossens}},
+  Booktitle                = {SMC'03 Conference Proceedings. 2003 IEEE International Conference on Systems, Man and Cybernetics. Conference Theme - System Security and Assurance (Cat. No.03CH37483)},
+  Year                     = {2003},
+  Month                    = {Oct},
+  Pages                    = {1032-1038 vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/ICSMC.2003.1244548},
+  ISSN                     = {1062-922X},
+  Keywords                 = {Petri nets;distributed programming;C language;embedded systems;program compilers;high level Petri nets;standard SystemC language;Petri net based design;distributed embedded real-time systems;Petri net components;partitions;single transition execution;conflicting transitions;transition delay realization;code generation;Petri nets;Real time systems;Embedded system;Hardware design languages;Vehicles;Performance analysis;Delay;Design methodology;Process design;Microcontrollers},
+  Owner                    = {MJ},
+  Timestamp                = {2019-06-04}
+}
+
+@InProceedings{rusose_11,
+  Title                    = {{I}mplementation of a {L}ow {P}ower {L}ow {C}omplexity {ASIP} for various {S}phere {D}ecoding {A}lgorithms},
+  Author                   = {Rust, Jochen and Osewold, Christof and Paul, Steffen},
+  Booktitle                = {Wireless Conference 2011 - Sustainable Wireless Technologies (European Wireless), 11th European},
+  Year                     = {2011},
+  Pages                    = {1-6},
+
+  Keywords                 = {Complexity theory;Decoding;Hardware;MIMO;Pipelines;Power demand;Signal processing algorithms},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.07.03}
+}
+
+@InProceedings{ryamcl_00,
+  Title                    = {{Turbo, LDPC, and RLL Codes in Magnetic Recording}},
+  Author                   = {W. E. Ryan and S. W. McLaughlin and K. Anim-Appiah and M. Yang},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {327--330},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTrybal13,
+  Title                    = {{D}esign and {I}mplementation of a {M}ultilevel {M}onte {C}arlo {H}eston {P}ricer on the {X}ilinx {Z}ynq-7000 {A}ll {P}rogrammable {S}o{C}},
+  Author                   = {Vladimir Rybalkin},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2013},
+  Month                    = mar,
+
+  Cds_grade                = {5},
+  Cds_keywords             = {multilevel MC, hardware architecture, Heston, FPGA},
+  Keywords                 = {finance, AG Wehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@InProceedings{ryokim_03,
+  Title                    = {{E}fficient soft demapping method for high order modulation schemes},
+  Author                   = {Sunheui Ryoo and Sooyoung Kim and Sung Pal Lee},
+  Booktitle                = {CDMA International Conference (CIC), Seoul, Korea},
+  Year                     = {2003},
+
+  Abstract                 = {In this paper we introduce an efficient soft demapping method for high order modulation schemes combined with iterative decoder. To reduce the demapping complexity, we employ a simple demapping method using a decision threshold instead of using an exhaustive Euclidean distance estimation method. The proposed demapping process needs a reduced number of computing operations and our simulation results show that the proposed demapping method produce the performance approximating to the exhaustive estimation method at a bit error rate (BER) range from 10-5 to 10-6 .},
+  Owner                    = {Imran},
+  Timestamp                = {2014.11.05}
+}
+
+@InProceedings{ryorod_08,
+  Title                    = {{O}ptimization {P}rinciples and {A}pplication {P}erformance {E}valuation of a {M}ultithreaded {GPU} {U}sing {CUDA}},
+  Author                   = {Ryoo, Shane and Rodrigues, Christopher I. and Baghsorkhi, Sara S. and Stone, Sam S. and Kirk, David B. and Hwu, Wen-mei W.},
+  Booktitle                = {Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming},
+  Year                     = {2008},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {73--82},
+  Publisher                = {ACM},
+  Series                   = {PPoPP '08},
+
+  Acmid                    = {1345220},
+  Doi                      = {10.1145/1345206.1345220},
+  ISBN                     = {978-1-59593-795-7},
+  Keywords                 = {GPU computing, parallel computing},
+  Location                 = {Salt Lake City, UT, USA},
+  Numpages                 = {10},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.26},
+  Url                      = {http://doi.acm.org/10.1145/1345206.1345220}
+}
+
+@InProceedings{S.Godtmann2006,
+  Title                    = {{C}oarse and {T}urbo {S}ynchronization: {A} {C}ase-{S}tudy for {DVB}-{RCS}},
+  Author                   = {S. Godtmann, N. Hadaschik, W. Steinert, A. Pollok, Gerd Ascheid, and Heinrich Meyr},
+  Booktitle                = {NEWCOM-ACoRN Workshop},
+  Year                     = {2006},
+
+  Address                  = {Vienna, Austria},
+  Month                    = {sep},
+
+  Journal                  = {NEWCOM-ACoRN Workshop},
+  Owner                    = {scholl},
+  Timestamp                = {2015.06.11}
+}
+
+@Article{s.ini_06,
+  Title                    = {{E}rror control coding in low-power wireless sensor networks: {W}hen is {ECC} energy-efficient?},
+  Author                   = {S. L. Howard, C. Schlegel, and K. Iniewski},
+  Journal                  = {EURASIP Journal on Wireless Communications and Networking},
+  Year                     = {2006},
+  Pages                    = {1..14},
+
+  File                     = {s.ini_06.pdf:s.ini_06.pdf:PDF},
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.22}
+}
+
+@InProceedings{sacirw_98,
+  Title                    = {{The Logarithmic Number System for Strength Reduction in Adaptive Filtering}},
+  Author                   = {J. Sacha and M. Irwin},
+  Booktitle                = {Proc. 1998 International Symposium on Low Power Electronics and Design (ISLPED '98)},
+  Year                     = {1998},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = aug,
+  Pages                    = {256--261},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{Phdsadri14,
+  Title                    = {{T}emperature {V}ariation {A}ware {E}nergy {O}ptimization in {H}eterogeneous {MPS}o{C}s},
+  Author                   = {Mohammadsadegh Sadri},
+  School                   = {alma},
+  Year                     = {2014},
+  Month                    = {Maggio},
+
+  Keywords                 = {Multi-scale Thermal Analysis, RT and Gate Level, Temperature Variation, Hardware Acceleration, Heterogeneous Architecture},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-16},
+  Url                      = {http://amsdottorato.unibo.it/6406/}
+}
+
+@InProceedings{sadjun_14,
+  Title                    = {{E}nergy {O}ptimization in 3{D} {MPS}o{C}s with {W}ide-{I}/{O} {DRAM} {U}sing {T}emperature {V}ariation {A}ware {B}ank-{W}ise {R}efresh},
+  Author                   = {Sadri, MohammadSadegh and Jung, Matthias and Weis, Christian and Wehn, Norbert and Benini, Luca},
+  Booktitle                = {Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014},
+  Year                     = {2014},
+  Month                    = {March},
+  Pages                    = {1-4},
+
+  Doi                      = {10.7873/DATE2014.294},
+  File                     = {sadjun_14.pdf:sadjun_14.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {MJ},
+  Timestamp                = {2017-07-05}
+}
+
+@InCollection{sadsch_15,
+  Title                    = {{H}igh-{B}andwidth {L}ow-{L}atency {I}nterfacing with {FPGA} {A}ccelerators {U}sing {PCI} {E}xpress},
+  Author                   = {Mohammadsadegh Sadri and Christian De Schryver and Norbert Wehn},
+  Booktitle                = {FPGA Based Accelerators for Financial Applications},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2015},
+  Edition                  = {1st},
+  Editor                   = {De Schryver, Christian},
+  Month                    = jul,
+  Pages                    = {117--141},
+
+  Abstract                 = {The need for high performance computing dictates constraints on the acceptable bandwidth of data transfer between processing units and the memory. Consequently it is crucial to build high performance, scalable, and energy efficient architectures capable of completing data transfer requests at satisfactory rates. Thanks to increased transfer rates obtained by exploiting high-speed serial data transfer links instead of traditional parallel ones, PCI Express provides a promising solution to the problem of connectivity for todays complex heterogeneous architectures. In this chapter, we first cover the principals of interfacing using PCI Express. To illustrate a practical situation, we select the Xilinx Zynq device and develop an example architecture which allows the x86 CPU cores of the host system, the ARM cores of the Zynq device, and the hardware accelerators directly realized on the FPGA fabric of the Zynq to share the available DRAM memory for efficient data sharing. We provide estimates on possible data transfer bandwidths in our architecture.},
+  Doi                      = {10.1007/978-3-319-15407-7_6},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-08-21}
+}
+
+@TechReport{sae16,
+  Title                    = {{T}axonomy and {D}efinitions for {T}erms {R}elated to {D}riving {A}utomation {S}ystems for {O}n-{R}oad {M}otor {V}ehicles},
+  Author                   = {{SAE International}},
+  Year                     = {2014},
+  Month                    = jan,
+
+  Url                      = {https://www.sae.org/standards/content/j3016\_201609}
+}
+
+@Article{saeric_01,
+  Title                    = {{Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation}},
+  Author                   = {C. Sae-Young and T. Richardson and Urbanke, R. L.},
+  Journal                  = {Information Theory, IEEE Transactions on},
+  Year                     = {2001},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {657--670},
+  Volume                   = {47},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{sagwan_05,
+  Title                    = {{A}n experimental study of soft errors in microprocessors},
+  Author                   = {Saggese, G. P. and Wang, N. J. and Kalbarczyk, Z. T. and Patel, S. J. and Iyer, R. K.},
+  Journal                  = {Micro, IEEE},
+  Year                     = {2005},
+  Number                   = {6},
+  Pages                    = {30--39},
+  Volume                   = {25},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- processor, DLX, pipeline analysis},
+  Doi                      = {10.1109/MM.2005.104},
+  File                     = {sagwan_05.pdf:sagwan_05.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.03.03}
+}
+
+@InProceedings{sahsat_16,
+  Title                    = {{MS}im{DRAM}: {F}ormal {M}odel {D}riven {D}evelopment of a {DRAM} {S}imulator},
+  Author                   = {D. {Sahoo} and M. {Satpathy}},
+  Booktitle                = {2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)},
+  Year                     = {2016},
+  Month                    = {Jan},
+  Pages                    = {597-598},
+
+  Doi                      = {10.1109/VLSID.2016.88},
+  ISSN                     = {2380-6923},
+  Keywords                 = {DRAM chips;finite state machines;MSimDRAM;formal model driven development;DRAM simulator;DRAM controller requirements;DRAM-C requirements;architectural design;interacting state machines;rigorous verification;truncated simulator;agent-interaction;Random access memory;Timing;Control systems;Databases;Model checking;Radiation detectors;Jacobian matrices;Memory Controller;Hardware simulation;Formal Modeling},
+  Owner                    = {MJ},
+  Timestamp                = {2019-06-04}
+}
+
+@InProceedings{sahsav_08,
+  Title                    = {{S}cheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability},
+  Author                   = {Sahraii, N. and Savaria, Y. and Thibeault, C. and Gagnon, F.},
+  Booktitle                = {Proc. Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference NEWCAS-TAISA 2008},
+  Year                     = {2008},
+  Month                    = jun,
+  Pages                    = {73--76},
+
+  Doi                      = {10.1109/NEWCAS.2008.4606324},
+  File                     = {sahsav_08.pdf:sahsav_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.09.11}
+}
+
+@InCollection{saimat_08,
+  Title                    = {{SIMD}-{O}riented {F}ast {M}ersenne {T}wister: a 128-bit {P}seudorandom {N}umber {G}enerator},
+  Author                   = {Saito, Mutsuo and Matsumoto, Makoto},
+  Booktitle                = {Monte Carlo and Quasi-Monte Carlo Methods 2006},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2008},
+  Editor                   = {Keller, Alexander and Heinrich, Stefan and Niederreiter, Harald},
+  Pages                    = {607--622},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {SFMT},
+  Doi                      = {10.1007/978-3-540-74496-2_36},
+  ISBN                     = {978-3-540-74495-5},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.07},
+  Url                      = {http://dx.doi.org/10.1007/978-3-540-74496-2_36}
+}
+
+@InCollection{saimat_09,
+  Title                    = {{A} {PRNG} {S}pecialized in {D}ouble {P}recision {F}loating {P}oint {N}umbers {U}sing an {A}ffine {T}ransition},
+  Author                   = {Saito, Mutsuo and Matsumoto, Makoto},
+  Booktitle                = {Monte Carlo and Quasi-Monte Carlo Methods 2008},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2009},
+  Editor                   = {L' Ecuyer, Pierre and Owen, Art B.},
+  Pages                    = {589--602},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {SFMT, dSFMT},
+  Doi                      = {10.1007/978-3-642-04107-5_38},
+  File                     = {saimat_09.pdf:saimat_09.pdf:PDF},
+  ISBN                     = {978-3-642-04106-8},
+  Keywords                 = {random numbers},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.07},
+  Url                      = {http://dx.doi.org/10.1007/978-3-642-04107-5_38}
+}
+
+@Article{saimat_13,
+  Title                    = {{V}ariants of {M}ersenne {T}wister {S}uitable for {G}raphic {P}rocessors},
+  Author                   = {Saito, Mutsuo and Matsumoto, Makoto},
+  Journal                  = {ACM Trans. Math. Softw.},
+  Year                     = {2013},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {12:1--12:20},
+  Volume                   = {39},
+
+  Acmid                    = {2427029},
+  Address                  = {New York, NY, USA},
+  Articleno                = {12},
+  Cds_grade                = {0},
+  Cds_keywords             = {Mersenne Twister GPU},
+  Doi                      = {10.1145/2427023.2427029},
+  File                     = {saimat_13.pdf:saimat_13.pdf:PDF},
+  ISSN                     = {0098-3500},
+  Issue_date               = {February 2013},
+  Keywords                 = {random numbers},
+  Numpages                 = {20},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2014.04.03},
+  Url                      = {http://doi.acm.org/10.1145/2427023.2427029}
+}
+
+@Article{salant_09,
+  Title                    = {{3G Long Term Evolution Baseband Processing with Application-Specific Processors}},
+  Author                   = {Perttu Salmela and Juho Antikainen and Teemu Pitkänen and Olli Silvén and Jarmo Takala},
+  Journal                  = {International Journal of Digital Multimedia Broadcasting},
+  Year                     = {2009},
+  Pages                    = {1--14},
+  Volume                   = {2009},
+
+  Doi                      = {10.1155/2009/503130},
+  Masid                    = {27491465},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.01.16}
+}
+
+@InProceedings{salbur_08,
+  Title                    = {{C}omplex-valued {QR} decomposition implementation for {MIMO} receivers},
+  Author                   = {Salmela, P. and Burian, A. and Sorokin, H. and Takala, J.},
+  Booktitle                = {Proc. IEEE Int. Conf. Acoustics, Speech and Signal Processing ICASSP 2008},
+  Year                     = {2008},
+  Pages                    = {1433--1436},
+
+  File                     = {salbur_08.pdf:salbur_08.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.12}
+}
+
+@InProceedings{salgu_08,
+  Title                    = {{E}fficient parallel memory organization for turbo decoders},
+  Author                   = {Perttu Salmela and Ruirui Gu and Shuvra S. Bhattacharyya and Jarmo Takala},
+  Booktitle                = {Proc. European Signal Processing Conference (EUSIPCO)},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {831--835},
+
+  File                     = {salgu_08.pdf:salgu_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May}
+}
+
+@InProceedings{salsor_08,
+  Title                    = {{L}ow-complexity polynomials modulo integer with linearly incremented variable},
+  Author                   = {Salmela, P. and Sorokin, H. and Takala, J.},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems SiPS 2008},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {251--256},
+
+  Doi                      = {10.1109/SIPS.2008.4671771},
+  File                     = {salsor_08.pdf:salsor_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.15}
+}
+
+@InProceedings{salmor_11,
+  Title                    = {{P}arallel random numbers: {A}s easy as 1, 2, 3},
+  Author                   = {Salmon, J.K. and Moraes, M.A. and Dror, R.O. and Shaw, D.E.},
+  Booktitle                = {High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for},
+  Year                     = {2011},
+  Pages                    = {1--12},
+
+  Abstract                 = {Most pseudorandom number generators (PRNGs) scale poorly to massively parallel high-performance computation because they are designed as sequentially dependent state transformations. We demonstrate that independent, keyed transformations of counters produce a large alternative class of PRNGs with excellent statistical properties (long period, no discernable structure or correlation). These counter-based PRNGs are ideally suited to modern multi- core CPUs, GPUs, clusters, and special-purpose hardware because they vectorize and parallelize well, and require little or no memory for state. We introduce several counter-based PRNGs: some based on cryptographic standards (AES, Threefish) and some completely new (Philox). All our PRNGs pass rigorous statistical tests (including TestUOl's BigCrush) and produce at least 264 unique parallel streams of random numbers, each with period 2128 or more. In addition to essentially unlimited parallel scalability, our PRNGs offer excellent single-chip performance: Philox is faster than the CURAND library on a single NVIDIA GPU.},
+  Cds_grade                = {0},
+  Cds_keywords             = {RNG, PRNG, cryptography},
+  File                     = {salmor_11.pdf:salmor_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.16}
+}
+
+@InProceedings{samdie_11,
+  Title                    = {{E}ner{J}: {A}pproximate {D}ata {T}ypes for {S}afe and {G}eneral {L}ow-power {C}omputation},
+  Author                   = {Sampson, Adrian and Dietl, Werner and Fortuna, Emily and Gnanapragasam, Danushen and Ceze, Luis and Grossman, Dan},
+  Booktitle                = {Proceedings of the 32Nd ACM SIGPLAN Conference on Programming Language Design and Implementation},
+  Year                     = {2011},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {164--174},
+  Publisher                = {ACM},
+  Series                   = {PLDI '11},
+
+  Acmid                    = {1993518},
+  Doi                      = {10.1145/1993498.1993518},
+  ISBN                     = {978-1-4503-0663-8},
+  Keywords                 = {accuracy-aware computing, critical data, energy, power-aware computing, soft errors},
+  Location                 = {San Jose, California, USA},
+  Numpages                 = {11},
+  Owner                    = {MJ},
+  Timestamp                = {2015.10.28},
+  Url                      = {http://doi.acm.org/10.1145/1993498.1993518}
+}
+
+@Misc{samm471b2874eh109,
+  Title                    = {{M}471{B}2874{EH}1-{CF}8 {DDR}3 1{GB} 533{MH}z},
+
+  Author                   = {Samsung},
+  Year                     = {2009},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.10.29}
+}
+
+@Article{sangan_18a,
+  Title                    = {{T}he {EH} {M}odel: {A}nalytical {E}xploration of {E}nergy-{H}arvesting {A}rchitectures},
+  Author                   = {J. {San Miguel} and K. {Ganesan} and M. {Badr} and N. E. {Jerger}},
+  Journal                  = {IEEE Computer Architecture Letters},
+  Year                     = {2018},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {76-79},
+  Volume                   = {17},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8119973},
+  Ccr_keywords             = {NVP, not applicable to PN systems},
+  Ccr_relevance            = {low},
+  Ccr_topic                = {n.a.},
+  Doi                      = {10.1109/LCA.2017.2777834},
+  ISSN                     = {1556-6056},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;power aware computing;random-access storage;intermittent computing;frequent power outages;conventional systems;perpetual loop;forward progress;intermittent execution model;nonvolatile memory;EH model;analytical exploration;energy-harvesting architectures;energy-harvesting devices;Nonvolatile memory;Mathematical model;Computational modeling;Analytical models;Computer architecture;Power system reliability;Energy-harvesting;intermittent computing;analytical model},
+  Owner                    = {CCR}
+}
+
+@InProceedings{sangan_18,
+  Title                    = {{T}he {EH} {M}odel: {E}arly {D}esign {S}pace {E}xploration of {I}ntermittent {P}rocessor {A}rchitectures},
+  Author                   = {J. {San Miguel} and K. {Ganesan} and M. {Badr} and C. {Xia} and R. {Li} and H. {Hsiao} and N. {Enright Jerger}},
+  Booktitle                = {2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
+  Year                     = {2018},
+  Month                    = {Oct},
+  Pages                    = {600-612},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8574572},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/MICRO.2018.00055},
+  Keywords                 = {TCS},
+  Keywords_original        = {embedded systems;energy conservation;energy harvesting;logic design;low-power electronics;microprocessor chips;optimisation;space exploration;power outages;energy-harvesting model;energy-harvesting devices;intermittent processor architectures;intermittent processors;energy cost;intermittent system;intermittent computing;Nonvolatile memory;Computer architecture;Mathematical model;Space exploration;Power system reliability;Computational modeling;Task analysis;Energy harvesting;Intermittent computing;Analytical modelling},
+  Owner                    = {CCR}
+}
+
+@Article{sankoz_13,
+  Title                    = {{ZS}im: fast and accurate microarchitectural simulation of thousand-core systems},
+  Author                   = {Sanchez, Daniel and Kozyrakis, Christos},
+  Journal                  = {ACM SIGARCH Computer Architecture News},
+  Year                     = {2013},
+
+  Month                    = {07},
+  Pages                    = {475},
+  Volume                   = {41},
+
+  Doi                      = {10.1145/2508148.2485963}
+}
+
+@Book{sankan_10,
+  Title                    = {{CUDA by Example: An Introduction to General-Purpose GPU Programming}},
+  Author                   = {Jason Sanders and Edward Kandrot},
+  Publisher                = {{Addison-Wesley}},
+  Year                     = {2010},
+  Month                    = {Jul},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.12.03}
+}
+
+@InProceedings{sansch_13,
+  Title                    = {{Think Locally, Act Globally: Highly Balanced Graph Partitioning}},
+  Author                   = {Sanders, Peter and Schulz, Christian},
+  Booktitle                = {Proceedings of the 12th International Symposium on Experimental Algorithms (SEA'13)},
+  Year                     = {2013},
+  Pages                    = {164--175},
+  Publisher                = {Springer},
+  Series                   = {LNCS},
+  Volume                   = {7933},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-13}
+}
+
+@Article{san_02,
+  Title                    = {{D}efining platform-based design},
+  Author                   = {Sangiovanni-Vincentelli, Alberto},
+  Journal                  = {EEDesign of EETimes},
+  Year                     = {2002},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.27}
+}
+
+@Article{sanmar_01,
+  Title                    = {{P}latform-{B}ased {D}esign and {S}oftware {D}esign {M}ethodology for {E}mbedded {S}ystems},
+  Author                   = {Sangiovanni-Vincentelli, Alberto and Martin, Grant},
+  Journal                  = {IEEE Des. Test},
+  Year                     = {2001},
+
+  Month                    = nov,
+  Number                   = {6},
+  Pages                    = {23--33},
+  Volume                   = {18},
+
+  Acmid                    = {623108},
+  Address                  = {Los Alamitos, CA, USA},
+  Doi                      = {10.1109/54.970421},
+  ISSN                     = {0740-7475},
+  Issue_date               = {November 2001},
+  Numpages                 = {11},
+  Owner                    = {Brugger},
+  Publisher                = {IEEE Computer Society Press},
+  Timestamp                = {2015.04.27},
+  Url                      = {http://dx.doi.org/10.1109/54.970421}
+}
+
+@Article{Sani2013,
+  Title                    = {{A} {F}irst {S}tep {T}oward {O}n-{C}hip {M}emory {M}apping for {P}arallel {T}urbo and {LDPC} {D}ecoders: {A} {P}olynomial {T}ime {M}apping {A}lgorithm},
+  Author                   = {Sani, A. and Coussy, P. and Chavet, C.},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2013},
+  Number                   = {16},
+  Pages                    = {4127--4140},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TSP.2013.2264057},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.03.20},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6517513}
+}
+
+@InProceedings{Santos2014a,
+  Title                    = {{U}sing {TSV}s for {T}hermal {M}itigation in 3{D} {C}ircuits: {W}ish and {T}ruth},
+  Author                   = {Santos, C. and Souare, P. M. and Crecy, F. de and Coudrain, P.and Colonna, J.-P. and Vivet, P. and Borbely, A. and et al.},
+  Booktitle                = {IEEE 3DIC, Cork, Ireland},
+  Year                     = {2014},
+
+  Owner                    = {weis},
+  Timestamp                = {2015.04.14}
+}
+
+@InProceedings{sanviv_13,
+  Title                    = {{S}ystem-level thermal modeling for 3{D} circuits: {C}haracterization with a 65nm memory-on-logic circuit},
+  Author                   = {Santos, C. and Vivet, P. and Dutoit, D. and Garrault, P. and Peltier, N. and Reis, R.},
+  Booktitle                = {3D Systems Integration Conference (3DIC), 2013 IEEE International},
+  Year                     = {2013},
+  Month                    = {Oct},
+
+  Doi                      = {10.1109/3DIC.2013.6702379},
+  Keywords                 = {integrated circuit modelling;integrated memory circuits;logic circuits;thermal analysis;three-dimensional integrated circuits;transient response;3D integrated circuits;TSV;formal reduction;integrated thermal sensors;material homogenization;memory-on-logic circuit;power dissipation hot spots;size 65 nm;steady-state analysis;system level thermal modeling;thermal analysis;thermal transient response;through silicon via;transient analysis;vertically integrated circuits;Heating;Integrated circuit modeling;Materials;Temperature measurement;Temperature sensors;Three-dimensional displays;3DIC;CTM;characterization;material homogenization;temperature;thermal modeling},
+  Owner                    = {MJ},
+  Timestamp                = {2015.04.13}
+}
+
+@InProceedings{Santos2014,
+  Title                    = {{T}hermal modeling methodology for efficient system-level thermal analysis},
+  Author                   = {Santos, C. and Vivet, P. and Matter, G. and Peltier, N. and Kaiser, S. and Reis, R.},
+  Booktitle                = {Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the},
+  Year                     = {2014},
+  Month                    = {Sept},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/CICC.2014.6946045},
+  Keywords                 = {cooling;electric connectors;logic circuits;thermal analysis;three-dimensional integrated circuits;μ-bumps;3D integration technology parameters;TSV arrays;die thickness;dynamic compact thermal model;efficient system-level thermal analysis;fine grain structures;heat dissipation;material homogenization;memory-on-logic 3D circuit;multilength scale systems;package modeling;silicon temperature;size 65 nm;socket;steady-state analysis;thermal impact;thermal modeling methodology;transient thermal analysis;vertical stacking;Analytical models;Heating;Integrated circuit modeling;Solid modeling;Thermal analysis;Three-dimensional displays;Through-silicon vias},
+  Owner                    = {weis},
+  Timestamp                = {2015.04.14}
+}
+
+@InProceedings{sanbri_00,
+  Title                    = {{I}terative channel estimation and decoding with product codes in multicarrier systems},
+  Author                   = {Sanzi, F. and ten Brink, S.},
+  Booktitle                = {Vehicular Technology Conference, 2000. IEEE VTS-Fall VTC 2000. 52nd},
+  Year                     = {2000},
+  Month                    = sep,
+  Pages                    = {1338--1344vol.3},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/VETECF.2000.886316},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{saober_02,
+  Title                    = {{Fast SUBMAP Decoders for Duo-Binary Turbo-Codes}},
+  Author                   = {Saouter, Y. and Berrou, C.},
+  Booktitle                = {Circuits and Systems for Communications, 2002. Proceedings. ICCSC '02. 1st IEEE International Conference on},
+  Year                     = {2002},
+  Month                    = jun,
+  Pages                    = {150--153},
+
+  Doi                      = {10.1109/OCCSC.2002.1029067},
+  File                     = {saober_02.pdf:saober_02.pdf:PDF},
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.28}
+}
+
+@Article{sap_11,
+  Title                    = {{O}vercoming {V}ariations in {N}anometer-{S}cale {T}echnologies},
+  Author                   = {Sapatnekar, S. S.},
+  Journal                  = {Emerging and Selected Topics in Circuits and Systems, IEEE Journal on},
+  Year                     = {2011},
+  Number                   = {1},
+  Pages                    = {5--18},
+  Volume                   = {1},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- 
+- Technology, Empfehlung Norbert},
+  Doi                      = {10.1109/JETCAS.2011.2138250},
+  File                     = {sap_11.pdf:sap_11.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Electronic{sarmac_12,
+  Title                    = {{L}ight{W}eight {IP} (lw{IP}) {A}pplication {E}xamples},
+  Author                   = {Anirudha Sarangi and Stephen MacMahon},
+  HowPublished             = {\url{http://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf}},
+  Language                 = {en},
+  Month                    = oct,
+  Note                     = {last access 2014-05-22},
+  Organization             = {Xilinx Inc.},
+  Url                      = {http://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf},
+  Year                     = {2012},
+
+  File                     = {sarmac_12.pdf:sarmac_12.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.05.22}
+}
+
+@InProceedings{sargia_14,
+  Title                    = {{I}ncreasing the speed of polar list decoders},
+  Author                   = {G. Sarkis and P. Giard and A. Vardy and C. Thibeault and W. J. Gross},
+  Booktitle                = {Signal Processing Systems (SiPS), 2014 IEEE Workshop on},
+  Year                     = {2014},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/SiPS.2014.6986089},
+  Keywords                 = {AWGN channels;adaptive decoding;data structures;error correction;parity check codes;software engineering;Chase-like decoding process;LDPC decoder;adaptive decoding algorithm;additive white Gaussian noise channel;cancellation list decoding;data structures;error-correction performance advantage;polar list decoders;simplified successive cancellation list decoder;software decoding solution;standard successive-cancellation polar decoders;Maximum likelihood decoding;Parity check codes;Reliability;Simulation;Software;Throughput},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Article{sargia_14a,
+  Title                    = {{F}ast {P}olar {D}ecoders: {A}lgorithm and {I}mplementation},
+  Author                   = {G. Sarkis and P. Giard and A. Vardy and C. Thibeault and W. J. Gross},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2014},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {946-957},
+  Volume                   = {32},
+
+  Abstract                 = {Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.},
+  Doi                      = {10.1109/JSAC.2014.140514},
+  File                     = {sargia_14a.pdf:sargia_14a.pdf:PDF},
+  ISSN                     = {0733-8716},
+  Keywords                 = {block codes;decoding;error correction codes;field programmable gate arrays;linear codes;FPGA implementation;fast polar decoders;flexible polar decoder;gigabit-per-second polar decoder;polar codes;polar decoding hardware throughput;successive-cancellation decoders;symmetric memoryless channel capacity;Complexity theory;Maximum likelihood decoding;Parity check codes;Reliability;Systematics;Throughput;polar codes;storage systems;successive-cancellation decoding},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-29}
+}
+
+@InProceedings{sargro_13,
+  Title                    = {{P}olar codes for data storage applications},
+  Author                   = {G. Sarkis and W. J. Gross},
+  Booktitle                = {Computing, Networking and Communications (ICNC), 2013 International Conference on},
+  Year                     = {2013},
+  Month                    = {Jan},
+  Pages                    = {840-844},
+
+  Doi                      = {10.1109/ICCNC.2013.6504198},
+  Keywords                 = {channel capacity;channel coding;decoding;error correction codes;data storage application;error-correcting code;low complexity decoding algorithm;low complexity encoding algorithm;memoryless channel capacity;polar code;Clocks;Generators;Maximum likelihood decoding;Memory;Reliability;Throughput},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{sarhem_13,
+  Title                    = {{S}tochastic {D}ecoding of {LDPC} {C}odes over {GF}(q)},
+  Author                   = {Sarkis, G. and Hemati, S. and Mannor, S. and Gross, W.J.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2013},
+  Number                   = {3},
+  Pages                    = {939--950},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCOMM.2013.012913.110340},
+  Owner                    = {PS},
+  Timestamp                = {2014.10.07},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6451069}
+}
+
+@InProceedings{sarrab_03,
+  Title                    = {{Massively Parallel Wireless Reconfigurable Processor Architecture and Programming}},
+  Author                   = {K. Sarrigeorgidis and J. Rabaey},
+  Booktitle                = {{ Proc. Parallel and Distributed Processing Symposium, 2003}},
+  Year                     = {2003},
+
+  Address                  = {Nice, France},
+  Month                    = apr,
+  Pages                    = {8--15},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{sarmue_10,
+  Title                    = {{A}ccelerating dynamic time warping subsequence search with {GPU}s and {FPGA}s},
+  Author                   = {Sart, Doruk and Mueen, Abdullah and Najjar, Walid and Keogh, Eamonn and Niennattrakul, Vit},
+  Booktitle                = {Data Mining (ICDM), 2010 IEEE 10th International Conference on},
+  Year                     = {2010},
+  Organization             = {IEEE},
+  Pages                    = {1001--1006},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01}
+}
+
+@Article{sarkum_13,
+  Title                    = {{B}ranch and {D}ata {H}erding: {R}educing {C}ontrol and {M}emory {D}ivergence for {E}rror-{T}olerant {GPU} {A}pplications},
+  Author                   = {John Sartori and Rakesh Kumar},
+  Journal                  = {IEEE Transactions on Multimedia},
+  Year                     = {2013},
+
+  Month                    = {Feb.},
+  Number                   = {2},
+  Pages                    = {279-290},
+  Volume                   = {15},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.27}
+}
+
+@InProceedings{sarsri_16,
+  Title                    = {{C}ross-{L}ayer {A}pproximations for {N}euromorphic
+{C}omputing: {F}rom {D}evices to {C}ircuits and {S}ystems},
+  Author                   = {Sarwar, S. and Srinivasan, G. and Venkataramani, S. and Sengupta, A. and
+Raghunathan, A. and Roy, K.},
+  Booktitle                = {ACM/IEEE Design Automation Conference (DAC)},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-05}
+}
+
+@Article{sarsha_01,
+  Title                    = {{H}igh-speed architectures for {R}eed-{S}olomon decoders},
+  Author                   = {Sarwate, D. V. and Shanbhag, N. R.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2001},
+
+  Month                    = oct,
+  Number                   = {5},
+  Pages                    = {641-655},
+  Volume                   = {9},
+
+  Abstract                 = {New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented in this paper. The speed bottleneck in the Berlekamp-Massey algorithm is in the iterative computation of discrepancies followed by the updating of the error-locator polynomial. This bottleneck is eliminated via a series of algorithmic transformations that result in a fully systolic architecture in which a single array of processors computes both the error-locator and the error-evaluator polynomials. In contrast to conventional Berlekamp-Massey architectures in which the critical path passes through two multipliers and 1+[log2,(t+1)] adders, the critical path in the proposed architecture passes through only one multiplier and one adder, which is comparable to the critical path in architectures based on the extended Euclidean algorithm. More interestingly, the proposed architecture requires approximately 25% fewer multipliers and a simpler control structure than the architectures based on the popular extended Euclidean algorithm. For block-interleaved Reed-Solomon codes, embedding the interleaver memory into the decoder results in a further reduction of the critical path delay to just one XOR gate and one multiplexer, leading to speed-ups of as much as an order of magnitude over conventional architectures},
+  Cds_grade                = {0},
+  Cds_keywords             = {Reed-Solomon, VLSI},
+  Date-added               = {2008-07-17 11:40:07 +0200},
+  Date-modified            = {2008-07-17 11:40:57 +0200},
+  Doi                      = {10.1109/92.953498},
+  File                     = {sarsha_01.pdf:sarsha_01.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InProceedings{satal_11,
+  Title                    = {{E}nhanced {F}orced {S}ymbol {M}ethod for improving the error rate performance of turbo codes},
+  Author                   = {Z. Sattar and A. M. Al-Sanie and Y. Ould-Cheikh-Mouhamedou},
+  Booktitle                = {Electronics, Communications and Photonics Conference (SIECPC), 2011 Saudi International},
+  Year                     = {2011},
+  Month                    = {April},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/SIECPC.2011.5876993},
+  Keywords                 = {error correction codes;iterative decoding;turbo codes;EFSM;average complexity;enhanced forced symbol method;error correction coding;error rate performance;frame fail decoding;peak reduction;turbo code;Complexity theory;Decoding;Error analysis;Floors;Iterative decoding;Signal to noise ratio;Turbo codes;Turbo codes;enhanced forced symbol method;error floor;iterative decoding;repeated decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.11.15}
+}
+
+@Book{sau_06,
+  Title                    = {{V}orlesungsscript "{E}inführung in die {I}nformations- und {C}odierungstheorie"},
+  Author                   = {Wolfgang Sauer-Greff},
+  Publisher                = {Wolfgang Sauer-Greff},
+  Year                     = {2006},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {Channel Coding},
+  Cds_read                 = {2008-02},
+  Date-added               = {2008-02-04 10:58:09 +0100},
+  Date-modified            = {2008-08-08 11:58:06 +0200},
+  File                     = {sau_06.pdf:sau_06.pdf:PDF},
+  Keywords                 = {Channel Code, BCH, Berlekamp-Massey},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10},
+  Url                      = {http://nt.eit.uni-kl.de/lehre/einfuehrung-in-die-informations-und-codierungstheorie/downloads.html}
+}
+
+@Booklet{sausch_06,
+  Title                    = {{P}rinzipien der {BCH}-{K}analcodierung - {E}ine {E}inführung},
+  Author                   = {Wolfgang Sauer-Greff and Torsten Schorr and Frank Kienle},
+  Month                    = nov,
+  Year                     = {2006},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {BCH Code},
+  Cds_read                 = {2008-08},
+  Date-added               = {2008-08-08 11:51:25 +0200},
+  Date-modified            = {2008-08-08 11:55:22 +0200},
+  File                     = {sausch_06.pdf:sausch_06.pdf:PDF},
+  Keywords                 = {BCH, Syndrome, RS},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Book{saucor_12,
+  Title                    = {{F}inancial {M}arkets and {I}nstitutions},
+  Author                   = {Anthony Saunders and Marcia Millon Cornett},
+  Publisher                = {McGraw-Hill/Irwin},
+  Year                     = {2012},
+
+  Address                  = {New York, USA},
+  Edition                  = {5th},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.05}
+}
+
+@InProceedings{sav_08a,
+  Title                    = {{M}in-{M}ax decoding for non binary {LDPC} codes},
+  Author                   = {Savin, V.},
+  Booktitle                = {Proc. IEEE Int. Symp. Information Theory ISIT 2008},
+  Year                     = {2008},
+  Pages                    = {960--964},
+
+  Doi                      = {.2008.4595129},
+  Owner                    = {Lehnigk},
+  Timestamp                = {2010.08.18}
+}
+
+@InProceedings{scamon_01,
+  Title                    = {{C}onvergence properties of iterative decoders working at bit and symbol level},
+  Author                   = {Scanavino, B. and Montorsi, G. and Benedetto, S.},
+  Booktitle                = {Global Telecommunications Conference, 2001. GLOBECOM '01. IEEE},
+  Year                     = {2001},
+  Month                    = nov,
+  Pages                    = {1037--1041vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/GLOCOM.2001.965577},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{scasin_08,
+  Title                    = {{R}econfigurable {A}rchitecture for {LDPC} and {T}urbo {D}ecoding: {A} {N}o{C} {C}ase {S}tudy},
+  Author                   = {Scarpellino, Michelangelo and Singh, Ashwani and Boutillon, Emmanuel and Masera, Guido},
+  Booktitle                = {Proc. IEEE 10th International Symposium on Spread Spectrum Techniques and Applications ISSSTA '08},
+  Year                     = {2008},
+  Month                    = aug,
+  Pages                    = {671--676},
+
+  Doi                      = {10.1109/ISSSTA.2008.131},
+  File                     = {scasin_08.pdf:scasin_08.pdf:PDF},
+  Keywords                 = {Turbo, LDPC},
+  Owner                    = {May},
+  Timestamp                = {2009.06.15}
+}
+
+@Article{sca_09,
+  Title                    = {{A}rchitectures for distributed and hierarchical {M}odel {P}redictive {C}ontrol - {A} review},
+  Author                   = {Riccardo Scattolini},
+  Journal                  = {Journal of Process Control},
+  Year                     = {2009},
+  Number                   = {5},
+  Pages                    = {723 - 731},
+  Volume                   = {19},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {https://doi.org/10.1016/j.jprocont.2009.02.003},
+  ISSN                     = {0959-1524},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {Distributed control, Hierarchical control, Model Predictive Control, Process control},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0959152409000353}
+}
+
+@Article{SchA¶ber2009,
+  Title                    = {{AIS} – {A}utonomous {I}ntegrated {S}ystems},
+  Author                   = {V. Schöber and O. Bringmann and A. Herkersdorf and W. Stechele and N. Wehn and M. May and D. Ziener and A. Bouajila and D. Baldin and J. Zeppenfeld and B. Sander and J. Teich and M. Sebastian and D. Treytnar and R. Ernst},
+  Journal                  = {newsletter edacentrum 04 2009},
+  Year                     = {2009},
+
+  Month                    = dec,
+  Pages                    = {5--13},
+
+  File                     = {schbri_09.pdf:schbri_09.pdf:PDF},
+  Keywords                 = {Reliability, AGWehn},
+  Owner                    = {May},
+  Timestamp                = {2010.01.04},
+  Url                      = {http://www.edacentrum.de/ais/files/publications/2009-12-18_AIS_-_Autonomous_Integrated_Systems.pdf}
+}
+
+@Article{SchA¶ber2008,
+  Title                    = {{AIS} – {A}utonome integrierte {S}ysteme},
+  Author                   = {V. Schöber and A. Herkersdorf and W. Stechele and J. Zeppenfeld and A. Bouajila and R. Ernst and M. Sebastian and O. Bringmann and B. Sander and J. Teich and D. Ziener and N. Wehn and M. May and F. Rammig and K. Stahl},
+  Journal                  = {newsletter edacentrum 02 2008},
+  Year                     = {2008},
+
+  Month                    = jul,
+  Pages                    = {23--25},
+
+  File                     = {schher_08.pdf:schher_08.pdf:PDF},
+  Keywords                 = {Reliability, AGWehn},
+  Owner                    = {May},
+  Timestamp                = {2010.01.04}
+}
+
+@InProceedings{schbon_85,
+  Title                    = {{SELLAV: A New Symbolic Design Method and its System Implementation}},
+  Author                   = {G.~Schaefer and W.~Bonath and N.~Wehn and M.~Glesner},
+  Booktitle                = {Proc.\ VLSI85, North Holland},
+  Year                     = {1985},
+
+  Address                  = {Tokyo},
+  Pages                    = {293--302},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTscher01,
+  Title                    = {{Software Implementation of Turbo-Decoders on VLIW Signal Processor ST120 (Implementierung eines Turbo-Decoders auf VLIW-Architekturen am Beispiel des ST120)}},
+  Author                   = {H. Scherner},
+  School                   = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2001},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{schkas_12,
+  Title                    = {{H}ow to {G}uarantee {A}pplication {F}unctionality in a {MOST}150 {N}etwork - {A}n {E}mbedded {S}ystems {A}pproach},
+  Author                   = {F. Schick and W. El Kassem and N. Wehn},
+  Booktitle                = {MOST Forum 2012 Conference},
+  Year                     = {2012},
+
+  Address                  = {Stuttgart / Esslingen, Germany},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@InProceedings{schhua_16,
+  Title                    = {{E}rror {R}esilience and {E}nergy {E}fficiency: {A}n {LDPC} {D}ecoder {D}esign {S}tudy},
+  Author                   = {Philipp {Schl{\"a}fer} and Chu-Hsiang Huang and Clayton Schoeny and Christian Weis and Yao Li and Norbert Wehn and Lara Dolecek},
+  Booktitle                = {Proceedings of the 2016 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
+  Year                     = {2016},
+
+  Address                  = {Dresden, Germany},
+  Month                    = march,
+
+  Owner                    = {schläfer},
+  Timestamp                = {2015.11.26}
+}
+
+@InProceedings{schryb_15,
+  Title                    = {{A} new {A}rchitecture for {H}igh {T}hroughput, {L}ow {L}atency {NB}-{LDPC} {C}heck {N}ode {P}rocessing},
+  Author                   = {Schl{\"a}fer, Philipp and Rybalkin, Vladimir and Wehn, Norbert and Alles, Matthias and Lehnigk-Emden, Timo and Boutillon, Emmanuel},
+  Booktitle                = {International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)},
+  Year                     = {2015}
+}
+
+@InProceedings{schsch_15,
+  Title                    = {{A} {N}ew {LDPC} {D}ecoder {H}ardware {I}mplementation with {I}mproved {E}rror {R}ates},
+  Author                   = {Philipp {Schl{\"a}fer} and Stefan Scholl and Eduardo Leonardi and Norbert Wehn},
+  Booktitle                = {2015 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT)},
+  Year                     = {2015},
+
+  Address                  = {The Dead Sea, Jordan},
+  Month                    = nov,
+
+  Abstract                 = {LDPC codes are commonly decoded by conventional belief propagation
+algorithms like the min-sum algorithm. However especially for small block
+lengths belief propagation performs poorly in comparison to maximum
+likelihood decoding. In this paper we propose a new decoding algorithm,
+that is inspired by augmented belief propagation from literature and
+present hardware architectures and implementations for 28 nm ASIC
+technology. The new decoder has a much higher complexity, but provides a
+gain of up to 1.2 dB signal-to-noise ratio over conventional belief
+propagation decoding.},
+  Days                     = {3},
+  Owner                    = {schläfer},
+  Timestamp                = {2015.10.04}
+}
+
+@Article{schall_12,
+  Title                    = {{D}esign {S}pace of {F}lexible {M}ulti-{G}igabit {LDPC} {D}ecoders},
+  Author                   = {Philipp Schl\"{a}fer and Matthias Alles and Christian Weis and Norbert Wehn},
+  Journal                  = {Hindawi VLSI Design Journal},
+  Year                     = {2012},
+  Volume                   = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@Unpublished{schsch_15_unpublished,
+  Title                    = {{A} {N}ew {LDPC} {D}ecoder {H}ardware {I}mplementation with {I}mproved {E}rror {R}ates},
+  Author                   = {Philipp Schl\"{a}fer and Stefan Scholl and Eduardo Leonardi and Norbert Wehn},
+  Note                     = {{A}ccepted for Publication, IEEE AEECT 2015},
+  Year                     = {2015},
+
+  Owner                    = {scholl},
+  Timestamp                = {2015.08.13}
+}
+
+@InProceedings{schweh_15a,
+  Title                    = {{S}yndrome based check node processing of high order {NB}-{LDPC} decoders},
+  Author                   = {Schl\"{a}fer, Philipp and Wehn, Norbert and Alles, Matthias and Lehnigk-Emden, Timo and Boutillon, Emmanuel},
+  Booktitle                = {Telecommunications (ICT), 2015 22nd International Conference on},
+  Year                     = {2015},
+  Pages                    = {156--162},
+
+  Doi                      = {10.1109/ICT.2015.7124675},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.10.14},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7124675}
+}
+
+@InProceedings{schall_13,
+  Title                    = {{A New Dimension of Parallelism in Ultra High Throughput LDPC Decoding}},
+  Author                   = {Philipp Schl\"{a}fer and Norbert Wehn and Timo Lehnigk-Emden and Matthias Alles},
+  Booktitle                = {IEEE Workshop on Signal Processing Systems (SIPS)},
+  Year                     = {2013},
+
+  Address                  = {Taipei, Taiwan},
+  Month                    = okt,
+
+  File                     = {schall_13.pdf:schall_13.pdf:PDF},
+  Owner                    = {schlaefer},
+  Timestamp                = {2017-02-15}
+}
+
+@PhdThesis{Phdschlae13,
+  Title                    = {{D}issertation in preparation},
+  Author                   = {Philipp Schläfer},
+  School                   = {Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2013},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2014.07.24}
+}
+
+@MastersThesis{MTschlae10,
+  Title                    = {{I}mplementation of a {S}ynthesizable {IP} {C}ore for {M}ulti-{G}bit {LDPC} {D}ecoding},
+  Author                   = {Philipp Schläfer},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2011},
+  Type                     = {Diploma Thesis},
+
+  Owner                    = {Schläfer},
+  Timestamp                = {2014.07.23}
+}
+
+@Book{sch_97,
+  Title                    = {{Trellis Coding}},
+  Author                   = {C. Schlegel},
+  Publisher                = {IEEE Press},
+  Year                     = {1997},
+
+  Address                  = {Piscataway, New Jersey, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{schper_04,
+  Title                    = {{Trellis and Turbo Coding}},
+  Author                   = {C.B. Schlegel and L.C. Perez},
+  Publisher                = {IEEE Press},
+  Year                     = {2004},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{schper_99,
+  Title                    = {{On Error Bounds and Turbo-Codes}},
+  Author                   = {C. Schlegel and L. Peréz},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {1999},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {205--207},
+  Volume                   = {3},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{sch_08,
+  Title                    = {6{F}2 buried wordline {DRAM} cell for 40nm and beyond},
+  Author                   = {T. Schloesser},
+  Journal                  = {IEEE International Electron Devices Meeting, San Francisco, CA},
+  Year                     = {2008},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-27}
+}
+
+@TechReport{sch_10a,
+  Title                    = {{O}ption {P}ricing {F}ormulae using {F}ourier {T}ransform: {T}heory and {A}pplication},
+  Author                   = {Schmelzle, Martin},
+  Year                     = {2010},
+
+  Abstract                 = {Fourier transform techniques are playing an increasingly important role in Mathematical Finance. For arbitrary stochastic price processes for which the characteristic functions are tractable either analytically or numerically, prices for a wide range of derivatives contracts are readily available by means of Fourier inversion methods. In this paper we first review the convenient mathematical properties of Fourier transforms and characteristic functions, survey the most popular pricing algorithms and finally compare numerical quadratures for the evaluation of density functions and option prices. At the end, we discuss practical implementation details and possible refinements with respect to computational efficiency.},
+  Cds_keywords             = {calibration, numerical analysis, FFT},
+  Cds_read                 = {2014-08-15},
+  File                     = {sch_10a.pdf:sch_10a.pdf:PDF},
+  Journal                  = {Unpublished Manuscript},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.08.15}
+}
+
+@Electronic{sch_11,
+  Title                    = {{D}eutsche {B}ank {S}haves {T}rade {L}atency {D}own to 1.25 {M}icroseconds},
+  Author                   = {Ivy Schmerken},
+  HowPublished             = {\url{http://www.advancedtrading.com/infrastructure/229300997}},
+  Language                 = {en},
+  Month                    = mar,
+  Note                     = {last access 2015-02-09},
+  Organization             = {www.advancedtrading.com},
+  Url                      = {http://www.advancedtrading.com/infrastructure/229300997},
+  Year                     = {2011},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {FPGA, real-time trading},
+  File                     = {sch_11.odt:sch_11.odt:OpenDocument text},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-02-05}
+}
+
+@Electronic{Schmerken2011,
+  Title                    = {{D}eutsche {B}ank {S}haves {T}rade {L}atency {D}own to 1.25 {M}icroseconds},
+  Author                   = {Ivy Schmerken},
+  Language                 = {en},
+  Month                    = mar,
+  Organization             = {www.advancedtrading.com},
+  Url                      = {http://www.advancedtrading.com/infrastructure/229300997},
+  Year                     = {2011},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {FPGA, real-time trading},
+  File                     = {sch_11.odt:sch_11.odt:OpenDocument text},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.26}
+}
+
+@InProceedings{schber_09,
+  Title                    = {{E}rror {C}orrection in {S}ingle-{H}op {W}ireless {S}ensor {N}etworks -- {A} {C}ase {S}tudy},
+  Author                   = {Daniel Schmidt and Matthias Berning and Norbert Wehn},
+  Booktitle                = {Proc. DATE '09. Design, Automation. Test in Europe Conference. Exhibition},
+  Year                     = {2009},
+  Pages                    = {1296--1301},
+
+  Owner                    = {schmidt},
+  Timestamp                = {2009.07.16}
+}
+
+@Article{Schmidt2006,
+  Title                    = {{F}rom algorithm to implementation: a case study on blind carrier synchronization},
+  Author                   = {Schmidt, D. and Brack, T. and Wasenm\"uller, U. and Wehn, N.},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2006},
+  Pages                    = {313--318},
+  Volume                   = {4},
+
+  Doi                      = {10.5194/ars-4-313-2006},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27},
+  Url                      = {http://www.adv-radio-sci.net/4/313/2006/}
+}
+
+@InProceedings{schbra_06,
+  Title                    = {{F}rom {A}lgorithm to {I}mplementation: a {C}ase {S}tudy on {B}lind {C}arrier {S}ynchronization},
+  Author                   = {D. Schmidt and T. Brack and U. Wasenmüller and N. Wehn},
+  Booktitle                = {Advances in Radio Science},
+  Year                     = {2006},
+
+  Address                  = {Miltenberg, Germany},
+  Month                    = mar,
+  Pages                    = {313--318},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{schkr_06,
+  Title                    = {{E}nergy {M}odelling in {S}ensor {N}etworks},
+  Author                   = {D. Schmidt and M. Krämer and T. Kuhn and N. Wehn and R. Gotzhein},
+  Booktitle                = {Advances in Radio Science},
+  Year                     = {2007},
+
+  Address                  = {Kleinheubach, Germany},
+  Month                    = oct,
+  Pages                    = {347--351},
+  Volume                   = {5},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{schweh_06,
+  Title                    = {{C}ustomizable {E}mbedded {P}rocessors},
+  Author                   = {D. Schmidt and N. Wehn},
+  Chapter                  = {Hardware/Software Tradeoffs for Advanced 3G Channel Decoding},
+  Editor                   = {P. Ienne and R. Leupers},
+  Pages                    = {361--379},
+  Publisher                = {Morgan Kaufmann Publishers},
+  Year                     = {2006},
+
+  Owner                    = {vogt},
+  Timestamp                = {2006.08.22}
+}
+
+@Conference{schweh_09,
+  Title                    = {{A} {R}eview of {C}ommon {B}elief on {P}ower {M}anagement and {P}ower {C}onsumption},
+  Author                   = {Daniel Schmidt and Norbert Wehn},
+  Booktitle                = {White Paper},
+  Year                     = {2009},
+
+  Address                  = {Kaiserslautern, Germany},
+  Month                    = apr,
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{schweh_09a,
+  Title                    = {{DRAM} {P}ower {M}anagement and {E}nergy {C}onsumption: a {C}ritical {A}ssessment},
+  Author                   = {Daniel Schmidt and Norbert Wehn},
+  Booktitle                = {Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design},
+  Year                     = {2009},
+
+  Address                  = {Natal, Brazil.},
+  Month                    = sep,
+
+  File                     = {schweh_09a.pdf:schweh_09a.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@Article{schfet_00,
+  Title                    = {{On Memory Redundancy in the BCJR Algorithm for Nonrecursive Shift Register Processes}},
+  Author                   = {M. Schmidt and Fettweis, G. P.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2000},
+
+  Month                    = jul,
+  Number                   = {4},
+  Pages                    = {1580--1584},
+  Volume                   = {46},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{schwhe_02,
+  Title                    = {{PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology}},
+  Author                   = {H. Schmit and D. Whelihan and A. Tsai and M. Moe and B. Levine and R.R. Taylor},
+  Booktitle                = {{Proc. 2002 Custom Integrated Circuits Conference (CICC '02)}},
+  Year                     = {2002},
+
+  Address                  = {Orlando, Florida, USA},
+  Month                    = may,
+  Pages                    = {63--66},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{schal-_02,
+  Title                    = {{Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems}},
+  Author                   = {M. T. Schmitz and B. Al-Hashimi and P. Eles},
+  Booktitle                = {Proc. 2002 Design, Automation and Test in Europe (DATE '02)},
+  Year                     = {2002},
+
+  Address                  = {Paris, France},
+  Month                    = mar,
+  Pages                    = {514--521},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{schhei_13,
+  Title                    = {{I}mproving the {F}ault {R}esilience of an {H}.264 {D}ecoder {U}sing {S}tatic {A}nalysis {M}ethods},
+  Author                   = {Schmoll, Florian and Heinig, Andreas and Marwedel, Peter and Engel, Michael},
+  Journal                  = {ACM Trans. Embed. Comput. Syst.},
+  Year                     = {2013},
+
+  Month                    = dec,
+  Number                   = {1s},
+  Pages                    = {31:1--31:27},
+  Volume                   = {13},
+
+  Acmid                    = {2536753},
+  Address                  = {New York, NY, USA},
+  Articleno                = {31},
+  Doi                      = {10.1145/2536747.2536753},
+  ISSN                     = {1539-9087},
+  Issue_date               = {November 2013},
+  Keywords                 = {Flexible error handling, annotations, application knowledge, delayed error handling, embedded systems, error classification, static analysis, transient faults, type qualifier},
+  Numpages                 = {27},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2015.07.08},
+  Url                      = {http://doi.acm.org/10.1145/2536747.2536753}
+}
+
+@Book{sch_99,
+  Title                    = {{Untersuchungen zur Implementierung von Sliding-Window Verfahren für Maximum-A-Posteriori Symbolschätzer zur Turbodecodierung}},
+  Author                   = {D. Schmoltzi},
+  Publisher                = {Project thesis, Institute of Microelectronic Systems, Department of Electrical Engineering, University of Kaiserslautern},
+  Year                     = {1999},
+  Month                    = nov,
+  Note                     = {In German},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{schtra_13,
+  Title                    = {{C}onditional {S}afety {C}ertification of {O}pen {A}daptive {S}ystems},
+  Author                   = {Schneider, Daniel and Trapp, Mario},
+  Journal                  = {ACM Trans. Auton. Adapt. Syst.},
+  Year                     = {2013},
+
+  Month                    = jul,
+  Number                   = {2},
+  Pages                    = {8:1--8:20},
+  Volume                   = {8},
+
+  Acmid                    = {2491467},
+  Address                  = {New York, NY, USA},
+  Articleno                = {8},
+  Doi                      = {10.1145/2491465.2491467},
+  ISSN                     = {1556-4665},
+  Issue_date               = {July 2013},
+  Keywords                 = {Adaptive systems, conditional certification, open systems, safety},
+  Numpages                 = {20},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2019-01-02},
+  Url                      = {http://doi.acm.org/10.1145/2491465.2491467}
+}
+
+@Article{scheuc_94,
+  Title                    = {{L}attice basis reduction: {I}mproved practical algorithms and solving subset sum problems},
+  Author                   = {C. P. Schnorr and M. Euchner},
+  Journal                  = {Mathematical Programming},
+  Year                     = {1994},
+
+  Month                    = {August},
+  Pages                    = {181-199},
+  Volume                   = {66},
+
+  Doi                      = {10.1007/BF01581144},
+  File                     = {scheuc_94.pdf:scheuc_94.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.03.30},
+  Url                      = {http://www.springerlink.com/content/p3511w638h45616u}
+}
+
+@Article{schbri_09,
+  Title                    = {{AIS} – {A}utonomous {I}ntegrated {S}ystems},
+  Author                   = {V. Schöber and O. Bringmann and A. Herkersdorf and W. Stechele and N. Wehn and M. May and D. Ziener and A. Bouajila and D. Baldin and J. Zeppenfeld and B. Sander and J. Teich and M. Sebastian and D. Treytnar and R. Ernst},
+  Journal                  = {newsletter edacentrum 04 2009},
+  Year                     = {2009},
+
+  Month                    = dec,
+  Pages                    = {5--13},
+
+  File                     = {schbri_09.pdf:schbri_09.pdf:PDF},
+  Keywords                 = {Reliability, AGWehn},
+  Owner                    = {May},
+  Timestamp                = {2010.01.04},
+  Url                      = {http://www.edacentrum.de/ais/files/publications/2009-12-18_AIS_-_Autonomous_Integrated_Systems.pdf}
+}
+
+@Article{schher_08,
+  Title                    = {{AIS} – {A}utonome integrierte {S}ysteme},
+  Author                   = {V. Schöber and A. Herkersdorf and W. Stechele and J. Zeppenfeld and A. Bouajila and R. Ernst and M. Sebastian and O. Bringmann and B. Sander and J. Teich and D. Ziener and N. Wehn and M. May and F. Rammig and K. Stahl},
+  Journal                  = {newsletter edacentrum 02 2008},
+  Year                     = {2008},
+
+  Month                    = jul,
+  Pages                    = {23--25},
+
+  File                     = {schher_08.pdf:schher_08.pdf:PDF},
+  Keywords                 = {Reliability, AGWehn},
+  Owner                    = {May},
+  Timestamp                = {2010.01.04}
+}
+
+@PhdThesis{Phdscholl,
+  Title                    = {{D}issertation in preparation},
+  Author                   = {Scholl, Stefan},
+  School                   = {Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.12.16}
+}
+
+@MastersThesis{MTschol10,
+  Title                    = {{E}ntwurf und {D}ecodierung nicht-binärer {L}ow-{D}ensity-{P}arity-{C}heck-{C}odes},
+  Author                   = {Stefan Scholl},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2010},
+  Month                    = mar,
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.26}
+}
+
+@InProceedings{schhai_16,
+  Title                    = {{A}n {E}fficient {S}oft {D}ecision {R}eed-{S}olomon {D}ecoder for {M}oderate {T}hroughput},
+  Author                   = {Stefan Scholl and Syed Haider and Norbert Wehn},
+  Booktitle                = {IEEE 18th Mediterranean Electrotechnical Conference (MELECON 2016)},
+  Year                     = {2016},
+
+  Address                  = {Limassol, Cyprus},
+  Month                    = april,
+
+  Owner                    = {scholl},
+  Timestamp                = {2016.05.17}
+}
+
+@Electronic{schhel_11,
+  Title                    = {{D}atabase of {C}hannel {C}odes and {ML} {S}imulation {R}esults},
+
+  Address                  = {www.uni-kl.de/channel-codes},
+  Author                   = {Scholl, S. and Helmling, M.},
+  Year                     = {2015},
+
+  Owner                    = {scholl},
+  Timestamp                = {2015.07.30}
+}
+
+@InProceedings{schkie_13,
+  Title                    = {{I}nteger {P}rogramming as a {T}ool for {C}ode {A}nalysis},
+  Author                   = {Scholl, S. and Kienle, F. and Helmling, M and Ruzika, S.},
+  Booktitle                = {9th International ITG Conference on Systems, Communications and Coding},
+  Year                     = {2013},
+  Month                    = {Jan},
+
+  Owner                    = {Kienle},
+  Timestamp                = {2012.11.02}
+}
+
+@InProceedings{schkie_12,
+  Title                    = {{ML} vs. {MP} {D}ecoding of {B}inary and {N}on-{B}inary {LDPC} {C}odes},
+  Author                   = {Scholl, S. and Kienle, F. and Helmling, M and Ruzika, S.},
+  Booktitle                = {Proc. 7th International Symposium on Turbo Codes and Iterative Information Processing},
+  Year                     = {2012},
+  Month                    = aug
+}
+
+@InProceedings{schsch_16,
+  Title                    = {{S}aturated {M}in-{S}um {D}ecoding: {A}n “{A}fterburner” for {LDPC} {D}ecoder {H}ardware},
+  Author                   = {Stefan Scholl and Philipp {Schl{\"a}fer} and Norbert Wehn},
+  Booktitle                = {Proceedings of the 2016 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
+  Year                     = {2016},
+
+  Address                  = {Dresden, Germany},
+  Month                    = march,
+
+  Owner                    = {schläfer},
+  Timestamp                = {2015.11.26}
+}
+
+@InBook{schsch_14,
+  Title                    = {{A}dvanced {H}ardware {D}esign for {E}rror {C}orrection {C}odes},
+  Author                   = {Stefan Scholl AND Philipp Schläfer AND Norbert Wehn AND Timo Lehnigk-Emden AND Matthias Alles},
+  Chapter                  = {Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding},
+  Editor                   = {Cyrille Chavet AND Philippe Coussy},
+  Publisher                = {Springer},
+  Year                     = {2014},
+
+  Owner                    = {Schläfer},
+  Timestamp                = {2014.07.23}
+}
+
+@InProceedings{schstu_13,
+  Title                    = {{H}ardware {I}mplementations of {G}aussian {E}limination over {GF}(2) for {C}hannel {D}ecoding {A}lgorithms},
+  Author                   = {Scholl, S. and Stumm, C. and Wehn, N.},
+  Booktitle                = {Proc. IEEE AFRICON 2013},
+  Year                     = {2013},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2013.03.04}
+}
+
+@Conference{schweh_15,
+  Title                    = {{E}fficient {A}rchitectures for {P}arity {C}heck {M}atrix {G}eneration},
+  Author                   = {Stefan Scholl and Norbert Wehn},
+  Booktitle                = {23rd Telecommunications Forum, TELFOR 2015},
+  Year                     = {2015},
+
+  Address                  = {Belgrade, Serbia},
+  Month                    = {November},
+
+  Owner                    = {scholl},
+  Timestamp                = {2015.08.13}
+}
+
+@InProceedings{schweh_14,
+  Title                    = {{H}ardware {I}mplementation of a {R}eed-{S}olomon {S}oft {D}ecoder based on {I}nformation {S}et {D}ecoding},
+  Author                   = {Scholl, S. and Wehn, N.},
+  Booktitle                = {Proc. Design, Automation and Test in Europe DATE '14},
+  Year                     = {2014},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2014.03.07}
+}
+
+@InProceedings{schweh_14a,
+  Title                    = {{A}dvanced hardware architecture for soft decoding {Reed}-{Solomon} codes},
+  Author                   = {Scholl, S. and Wehn, N.},
+  Booktitle                = {Turbo Codes and Iterative Information Processing (ISTC), 2014 8th International Symposium on},
+  Year                     = {2014},
+  Pages                    = {22--26},
+
+  Doi                      = {10.1109/ISTC.2014.6955078},
+  Owner                    = {scholl},
+  Timestamp                = {2015.08.13}
+}
+
+@InProceedings{schwei_16,
+  Title                    = {{A}dvanced iterative channel coding schemes: {W}hen {S}hannon meets {M}oore},
+  Author                   = {Stefan Scholl and Stefan Weithoffer and Norbert Wehn},
+  Booktitle                = {2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)},
+  Year                     = {2016},
+  Month                    = {Sept},
+  Pages                    = {406-411},
+
+  Doi                      = {10.1109/ISTC.2016.7593146},
+  File                     = {schwei_16.pdf:schwei_16.pdf:PDF},
+  Keywords                 = {channel coding;iterative decoding;semiconductor technology;communication system;decoding algorithms;hardware implementation;information theory;iterative channel coding scheme;parallel hardware architecture;semiconductor technology;spectral efficiency;Computer architecture;Decoding;Energy efficiency;Hardware;Iterative decoding;Throughput},
+  Owner                    = {MH},
+  Timestamp                = {2017-01-29}
+}
+
+@PhdThesis{Phdschor06,
+  Title                    = {{I}terative {C}odierungs- und {E}ntzerrungsverfahren für die optische {N}achrichtenübertragung},
+  Author                   = {Schorr},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2006},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.08.03}
+}
+
+@Article{schsim_04,
+  Title                    = {{A} perfect calibration! {N}ow what?},
+  Author                   = {Schoutens, Wim and Simons, Erwin and Tistaert, Jurgen},
+  Journal                  = {Wilmott Magazine},
+  Year                     = {2004},
+  Pages                    = {66-78},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.08.21}
+}
+
+@Article{schg.b_06,
+  Title                    = {{B}it-interleaved coded irregular modulation},
+  Author                   = {F. Schreckenbach and G. Bauch},
+  Journal                  = {European Transactions on Telecommunications},
+  Year                     = {2006},
+  Pages                    = {269-282},
+  Volume                   = {17},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.02}
+}
+
+@InProceedings{schgor_03,
+  Title                    = {{O}ptimized symbol mappings for bit-interleaved coded modulation with iterative decoding},
+  Author                   = {Schreckenbach, F. and Gortz, N. and Hagenauer, J. and Bauch, G.},
+  Booktitle                = {Global Telecommunications Conference, 2003. GLOBECOM '03. IEEE},
+  Year                     = {2003},
+  Month                    = dec,
+  Pages                    = {3316--3320},
+  Volume                   = {6},
+
+  Doi                      = {10.1109/GLOCOM.2003.1258849},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.02}
+}
+
+@Book{sch_86,
+  Title                    = {{T}heory of linear and integer programming},
+  Author                   = {Schrijver, A.},
+  Publisher                = {John Wiley \& Sons},
+  Year                     = {1986},
+
+  File                     = {:Schrijver - Theory of Linear and Integer Programming.djvu:Djvu},
+  Owner                    = {helmling},
+  Timestamp                = {2012.02.24}
+}
+
+@InProceedings{schpin_09,
+  Title                    = {{DRAM} {E}rrors in the {W}ild: {A} {L}arge-{S}cale {F}ield {S}tudy},
+  Author                   = {Bianca Schroeder and Eduardo Pinheiro and Wolf-Dietrich Weber},
+  Booktitle                = {SIGMETRICS},
+  Year                     = {2009},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-03}
+}
+
+@MastersThesis{MTschr03,
+  Title                    = {{Aufbau eines parallelen MAP-Decoders (X- / D-Architektur)}},
+  Author                   = {B. Schrörs},
+  School                   = {Microelectronic System Design Reseach Group, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2003},
+  Month                    = nov,
+  Note                     = {In German},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{Phdschry14,
+  Title                    = {{D}esign {M}ethodologies for {H}ardware {A}ccelerated {H}eterogeneous {C}omputing {S}ystems},
+  Author                   = {Christian de Schryver},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+
+  Cds_grade                = {5},
+  File                     = {Phdschry14.pdf:Phdschry14.pdf:PDF},
+  Keywords                 = {CHPC, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-02-05}
+}
+
+@Article{sch_13,
+  Title                    = {{R}esearch {P}roject for {E}nergy-{E}fficient {R}isk {M}anagement {A}cceleration {S}tarted},
+  Author                   = {Christian de Schryver},
+  Journal                  = {HiPEAC info},
+  Year                     = {2013},
+
+  Month                    = may,
+  Pages                    = {19},
+  Volume                   = {23},
+
+  Cds_grade                = {5},
+  Cds_read                 = {2013-06-06},
+  File                     = {sch_13.pdf:sch_13.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.06.06}
+}
+
+@Misc{schhigh12,
+  Title                    = {{H}igh-{P}erformance {H}ardware {A}cceleration for {A}sset {S}imulations},
+
+  Author                   = {Christian de Schryver},
+  HowPublished             = {Invited Talk / Guest Lecture at IPE Seminar, Karlsruhe Institute of Technology, Germany},
+  Month                    = mar,
+  Year                     = {2012},
+
+  File                     = {schhigh12.pptx:schhigh12.pptx:PPTX},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.30}
+}
+
+@Misc{schmulti12,
+  Title                    = {{M}ulti-{L}evel {M}onte {C}arlo {S}imulations},
+
+  Author                   = {Christian de Schryver},
+  HowPublished             = {Invited Talk / Guest Lecture at the Custom Computing Group of Wayne Luk, Imperial College, London},
+  Month                    = apr,
+  Year                     = {2012},
+
+  Abstract                 = {The financial and insurance business needs to run a lot of
+simulations for pricing and risk assessment tasks throughout the
+day, since for many products no closed-form pricing formulas exist.
+Although for special types other algorithms may converge much
+faster, Monte Carlo methods are very robust and applicable to a
+wide range of problems. For the showcase "European option pricing
+with the Heston model", this talk will present hardware efficient
+solutions for random number generation and path simulations on
+FPGAs, together with detailed speedup and energy numbers.
+Furthermore I will highlight how an application-level benchmark
+suite allows us to compare accelerator solutions in a fair way.},
+  File                     = {schmulti12.pdf:schmulti12.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.30}
+}
+
+@Misc{schhigh11,
+  Title                    = {{H}igh-{P}erformance {H}ardware {A}cceleration for {A}sset {S}imulations},
+
+  Author                   = {Christian de Schryver},
+  HowPublished             = {Invited Talk at the HiPEAC Design and Simulation Cluster Meeting in Barcelona, Spain},
+  Month                    = nov,
+  Year                     = {2011},
+
+  Cds_grade                = {5},
+  File                     = {schhigh11.pptx:schhigh11.pptx:PPTX},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.03.06}
+}
+
+@Misc{Schryver2011,
+  Title                    = {{H}igh-{P}erformance {H}ardware {A}cceleration for {A}sset {S}imulations},
+
+  Author                   = {Christian de Schryver},
+  HowPublished             = {Invited Talk at the HiPEAC Design and Simulation Cluster Meeting in Barcelona, Spain},
+  Month                    = nov,
+  Year                     = {2011},
+
+  Cds_grade                = {5},
+  File                     = {schhigh11.pptx:schhigh11.pptx:PPTX},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.03.06}
+}
+
+@MastersThesis{MTschry08,
+  Title                    = {{I}mplementation of a {F}lexible {S}yndrome {C}omputation and {E}rror {S}earch for {D}ecoding {A}lgebraic {C}odes},
+  Author                   = {Christian de Schryver},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2008},
+  Month                    = mar,
+
+  Cds_grade                = {5},
+  Cds_keywords             = {Channel Code, BCH, RS, Syndrome, Chien Search, Galois Fields},
+  Cds_read                 = {2008-03},
+  Date-added               = {2008-07-03 11:46:57 +0200},
+  Date-modified            = {2008-09-19 12:20:07 +0200},
+  File                     = {MTschry08.pdf:MTschry08.pdf:PDF},
+  Keywords                 = {AGWehn, BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@MastersThesis{MTschry08a,
+  Title                    = {{I}mplementation of a {F}lexible {H}igh-{T}hroughput {BCH} {D}ecoder},
+  Author                   = {Christian de Schryver},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2008},
+  Month                    = sep,
+
+  Cds_grade                = {5},
+  Cds_keywords             = {BCH, BCH codes, Channel Code, Syndrome, Chien Search, Key Equation, Euclidean Algorithm, Berlekamp-Massey, decoding, VHDL, FPGA},
+  Cds_read                 = {2008-09},
+  Date-added               = {2008-09-19 12:19:34 +0200},
+  Date-modified            = {2008-09-19 12:21:29 +0200},
+  File                     = {MTschry08a.pdf:MTschry08a.pdf:PDF},
+  Keywords                 = {AGWehn, BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@InCollection{schjun_11,
+  Title                    = {{E}nergy {E}fficient {A}cceleration and {E}valuation of {F}inancial {C}omputations towards {R}eal-{T}ime {P}ricing},
+  Author                   = {Christian de Schryver and Matthias Jung and Norbert Wehn and Henning Marxen and Anton Kostiuk and Ralf Korn},
+  Booktitle                = {Knowledge-Based and Intelligent Information and Engineering Systems},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2011},
+  Editor                   = {Andreas König and Andreas Dengel and Knut Hinkelmann and Koichi Kise and Robert J. Howlett and Lakhmi C. Jain},
+  Month                    = sep,
+  Note                     = {Proceedings of 15th International Conference on Knowledge-Based and Intelligent Information \& Engineering Systems (KES)},
+  Pages                    = {177--186},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {6884},
+
+  Abstract                 = {Modern financial markets are as vivid as never before. Asset prices - and therefore the prices of all related financial products - change within several milliseconds nowadays. However, not only due to the financial crisis in 2008, calculating fair and meaningful prices for these products is much more important than in the past. In order to obtain reliable prices, sophisticated simulation models have to be used. Pricing in these models in general has a very high computational complexity and can in many cases only be approximately done by using numerical methods. On the other hand, we all know that energy costs will become more and more significant in the future. The gap between the increasing computational complexity and the consumed energy can only be bridged by using more tailored computation engines, like dedicated hardware accelerators or application specific instruction set processors (ASIPs). In this paper we present a comprehensive methodology for the efficient design of optimal hardware accelerators and the evaluation thereof. We give two case studies: a new hardware random number generator for arbitrary distributions and a dedicated hardware accelerator for calculating European barrier option prices.},
+  Cds_grade                = {5},
+  Cds_keywords             = {finance, benchmarking, option pricing, Heston},
+  Doi                      = {10.1007/978-3-642-23866-6_19},
+  File                     = {schjun_11.pdf:schjun_11.pdf:PDF},
+  ISBN                     = {978-3-642-23865-9},
+  Keywords                 = {finance, AGWehn},
+  Location                 = {Heidelberg},
+  Owner                    = {CdS},
+  Timestamp                = {2011.09.22},
+  Url                      = {http://dx.doi.org/10.1007/978-3-642-23866-6_19}
+}
+
+@Unpublished{schjun_11_unpublished,
+  Title                    = {{E}nergy {E}fficient {A}cceleration and {E}valuation of {F}inancial {C}omputations {T}owards {R}eal-{T}ime {P}ricing},
+  Author                   = {Christian de Schryver and Matthias Jung and Norbert Wehn and Henning Marxen and Anton Kostiuk and Ralf Korn},
+  Note                     = {Accepted for Publication in Proceedings of 15th International Conference on Knowledge-Based and Intelligent Information \& Engineering Systems (KES)},
+
+  Month                    = sep,
+  Year                     = {2011},
+
+  Booktitle                = {Proceedings of 5th International Conference on Knowledge-Based and Intelligent Information \& Engineering Systems (KES)},
+  Cds_grade                = {5},
+  Cds_keywords             = {finance, benchmarking, option pricing, Heston},
+  File                     = {schjun_11_unpublished.pdf:schjun_11_unpublished.pdf:PDF},
+  Keywords                 = {finance, AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2011.06.22},
+  Url                      = {http://www.uni-kl.de/benchmarking}
+}
+
+@InProceedings{schmar_11,
+  Title                    = {{H}ardware {A}ccelerators for {F}inancial {M}athematics - {M}ethodology, {R}esults and {B}enchmarking},
+  Author                   = {Christian de Schryver and Henning Marxen and Daniel Schmidt},
+  Booktitle                = {Proceedings of the 1st Young Researcher Symposium (YRS) 2011},
+  Year                     = {2011},
+  Month                    = feb,
+  Note                     = {ISSN 1613-0073, urn:nbn:de:0074-750-0},
+  Organization             = {Center for Mathematical and Computational Modelling (CM)\textsuperscript{2}},
+  Pages                    = {55--60},
+  Publisher                = {(CM)\textsuperscript{2} Nachwuchsring},
+
+  Abstract                 = {Modern financial mathematics consume more and more computational power and energy. Finding efficient algorithms and implementations to accelerate calculations is therefore a very active area of research. We show why interdisciplinary cooperation such as (CM)\textsuperscript{2} are key in order to build optimal designs.
+
+For option pricing based on the state-of-the-art Heston model, no implementation on dedicated hardware is known, yet. We are currently designing a highly parallel architecture for field programmable gate arrays based on the multi-level Monte Carlo method. It is optimized for high throughput and low energy consumption, compared to GPGPUs. In order to be able to evaluate different algorithms and their implementations, we present a benchmark set for this application. We will show a very promising outlook on future work, including dedicated ASIPs, fixed-point research and real-time applications.},
+  Cds_grade                = {5},
+  Cds_keywords             = {benchmark, methodology},
+  Cds_read                 = {2011-02-15},
+  File                     = {schmar_11.pdf:schmar_11.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.02.15},
+  Url                      = {CEUR-WS.org/Vol-750/yrs08.pdf}
+}
+
+@InCollection{schmar_13,
+  Title                    = {{H}igh-{P}erformance {H}ardware {A}cceleration of {A}sset {S}imulations},
+  Author                   = {Christian de Schryver and Henning Marxen and Stefan Weithoffer and Norbert Wehn},
+  Booktitle                = {High-Performance Computing Using FPGAs},
+  Publisher                = {Springer New York},
+  Year                     = {2013},
+  Editor                   = {Wim Vanderbauwhede and Khaled Benkrid},
+  Pages                    = {3--32},
+
+  Abstract                 = {State-of-the-art financial computations based on realistic market models like the Heston model require a high computational effort, since no closed-form solutions are available in general. Due to the fact that the underlying asset behavior predictions are mainly based on number crunching operations, FPGAs are promising target devices for this task. In this chapter, we give an overview about current problems and solutions in the finance and insurance domain and show how state-of-the-art market models and solution methods have increased the necessary computational power over time. For the reason of universality and robustness, we focus on Monte Carlo methods that require a huge amount of normally distributed random numbers. We summarize the state-of-the-art and present efficient hardware architectures to obtain these numbers, together with comprehensive quality investigations. Build on these high-quality random number generators, we present an efficient FPGA architecture for option pricing in the Heston model, tailored to FPGAs. For the problem pricing European barrier options in the Heston model we show that a Xilinx Virtex-5 device can save up to 97% of energy, providing the same simulation throughput as a Nvidia Tesla 2050 GPU.},
+  Cds_grade                = {5},
+  Cds_read                 = {2013-06-06},
+  Doi                      = {10.1007/978-1-4614-1791-0_1},
+  File                     = {schmar_13.pdf:schmar_13.pdf:PDF},
+  ISBN                     = {978-1-4614-1790-3},
+  Keywords                 = {AGWehn, finance},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Timestamp                = {2013.06.06},
+  Url                      = {http://dx.doi.org/10.1007/978-1-4614-1791-0_1}
+}
+
+@InProceedings{schsch_13,
+  Title                    = {{L}oopy - {A}n {O}pen-{S}ource {TCP}/{IP} {R}apid {P}rototyping and {V}alidation {F}ramework},
+  Author                   = {Christian de Schryver and Schläfer, Philipp and Wehn, Norbert and Fischer, Thomas and Poetzsch-Heffter, Arnd},
+  Booktitle                = {Proceedings of the 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
+  Year                     = {2013},
+  Month                    = dec,
+  Pages                    = {1--6},
+
+  Abstract                 = {Setting up host-to-board connections for hardware validation or hybrid simulation purposes is a time-consuming and error-prone process. In this paper we present a novel approach to automatically generate host-to-board connections, called the Loopy framework. The generated drivers enable blocking and non-blocking access to the hardware from high-level languages like C++ through an intuitive, object-based model of the hardware implementation. The framework itself is written in Java, and offers cross-platform support. It is open-source, well-documented, and can be enhanced with new supported languages, boards, tools, and features easily. Loopy combines several approaches presented in the past to an all-embracing helper toolkit for hardware designers, verification engineers, or people who want to use hardware accelerators in a software context. We have evaluated Loopy with real-life examples and present a case study with a complex MIMO system hardware-in-the-Ioop setup.},
+  Cds_grade                = {5},
+  Cds_keywords             = {Loopy, Rapid Prototyping, Hardware-in-the-loop, HitL},
+  Doi                      = {10.1109/ReConFig.2013.6732305},
+  File                     = {schsch_13.pdf:schsch_13.pdf:PDF},
+  Keywords                 = {AG}
+}
+
+@InProceedings{schsch_10,
+  Title                    = {{A} {N}ew {H}ardware {E}fficient {I}nversion {B}ased {R}andom {N}umber {G}enerator for {N}on-{U}niform {D}istributions},
+  Author                   = {Christian de Schryver and Daniel Schmidt and Norbert Wehn and Elke Korn and Henning Marxen and Ralf Korn},
+  Booktitle                = {Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
+  Year                     = {2010},
+  Month                    = dec,
+  Pages                    = {190--195},
+
+  Abstract                 = {For numerous computationally complex applications, like financial modelling and Monte Carlo simulations, the fast generation of high quality non-uniform random numbers (RNs) is essential. The implementation of such generators in FPGA-based accelerators has therefore become a very active research field. In this paper we present a novel approach to create RNs for different distributions based on an efficient transformation of floating-point inputs. For the Gaussian distribution we can reduce the number of slices needed by up to 48\% compared to the state-of-the-art while achieving a higher output precision in the tail region. Our architecture produces samples up to $8.37\sigma$ and achieves 381MHz. We also present a comprehensive testing methodology based on stochastic analysis and verification in practical applications.},
+  Cds_grade                = {5},
+  Cds_read                 = {2010-08},
+  Doi                      = {10.1109/ReConFig.2010.20},
+  File                     = {schsch_10.pdf:schsch_10.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.01.06}
+}
+
+@Unpublished{schsch_10unpublished,
+  Title                    = {{A} {N}ew {H}ardware {E}fficient {I}nversion {B}ased {R}andom {N}umber {G}enerator for {N}on-{U}niform {D}istributions},
+  Author                   = {Christian de Schryver and Daniel Schmidt and Norbert Wehn and Elke Korn and Henning Marxen and Ralf Korn},
+  Note                     = {To appear in proceedings of ReConFig '10, Cancun, Mexico},
+
+  Month                    = dec,
+  Year                     = {2010},
+
+  Abstract                 = {For numerous computationally complex applications, like financial modelling and Monte Carlo simulations, the fast generation of high quality non-uniform random numbers (RNs) is essential. The implementation of such generators in FPGA-based accelerators has therefore become a very active research field. In this paper we present a novel approach to create RNs for different distributions based on an efficient transformation of floating-point inputs. For the Gaussian distribution we can reduce the number of slices needed by up to 48\% compared to the state-of-the-art while achieving a higher output precision in the tail region. Our architecture produces samples up to $8.37\sigma$ and achieves 381MHz. We also present a comprehensive testing methodology based on stochastic analysis and verification in practical applications.},
+  Cds_grade                = {5},
+  Cds_read                 = {2010-08},
+  File                     = {schsch_10unpublished.pdf:schsch_10unpublished.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.23}
+}
+
+@Unpublished{schsch_11unpublished,
+  Title                    = {{A} {H}ardware {E}fficient {R}andom {N}umber {G}enerator for {N}on-{U}niform {D}istributions with {A}rbitrary {P}recision},
+  Author                   = {Christian de Schryver and Daniel Schmidt and Norbert Wehn and Elke Korn and Henning Marxen and Anton Kostiuk and Ralf Korn},
+  Note                     = {Accepted for publication in the International Journal of Reconfigurable Computing (IJRC)},
+  Year                     = {2012},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {random numbers},
+  File                     = {schsch_11unpublished.pdf:schsch_11unpublished.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.08.30}
+}
+
+@Article{schsch_12,
+  Title                    = {{A} {H}ardware {E}fficient {R}andom {N}umber {G}enerator for {N}onuniform {D}istributions with {A}rbitrary {P}recision},
+  Author                   = {Christian de Schryver and Daniel Schmidt and Norbert Wehn and Elke Korn and Henning Marxen and Anton Kostiuk and Ralf Korn},
+  Journal                  = {International Journal of Reconfigurable Computing (IJRC)},
+  Year                     = {2012},
+
+  Month                    = mar,
+  Note                     = {Article ID 675130, 11 pages},
+  Volume                   = {2012},
+
+  Abstract                 = {Nonuniform random numbers are key for many technical applications, and designing efficient hardware implementations of non-uniform random number generators is a very active research field. However, most state-of-the-art architectures are either tailored to specific distributions or use up a lot of hardware resources. At ReConFig 2010, we have presented a new design that saves up to 48% of area compared to state-of-the-art inversion-based implementation, usable for arbitrary distributions and precision. In this paper, we introduce a more flexible version together with a refined segmentation scheme that allows to further reduce the approximation error significantly. We provide a free software tool allowing users to implement their own distributions easily, and we have tested our random number generator thoroughly by statistic analysis and two application tests.},
+  Cds_grade                = {5},
+  Cds_keywords             = {random number generator, FPGA, hardware, ICDF, floating point},
+  Cds_read                 = {2010-03-08},
+  Doi                      = {10.1155/2012/675130},
+  File                     = {schsch_12.pdf:schsch_12.pdf:PDF},
+  Keywords                 = {finance, AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.08}
+}
+
+@InProceedings{schshc_11,
+  Title                    = {{A}n {E}nergy {E}fficient {FPGA} {A}ccelerator for {M}onte {C}arlo {O}ption {P}ricing with the {H}eston {M}odel},
+  Author                   = {Christian de Schryver and Ivan Shcherbakov and Frank Kienle and Norbert Wehn and Henning Marxen and Anton Kostiuk and Ralf Korn},
+  Booktitle                = {Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
+  Year                     = {2011},
+
+  Address                  = {Cancún, Mexico},
+  Month                    = dec,
+  Pages                    = {468--474},
+
+  Abstract                 = {Today, pricing of derivates (particularly options) in financial institutions is a challenge. Besides the increasing complexity of the products, obtaining fair prices requires more realistic (and therefore complex) models of the underlying asset behavior. Not only due to the increasing costs, energy efficient and accurate pricing of these models becomes more and more important. In this paper we present - to the best of our knowledge - the first FPGA based accelerator for option pricing with the state-of-the-art Heston model. It is based on advanced Monte Carlo simulations. Compared to an 8-core Intel Xeon Server running at 3.07GHz, our hybrid FPGA-CPU-system saves 89 #x025; of the energy and provides around twice the speed. The same system reduces the energy consumption per simulation to around 40 #x025; of a fully-loaded Nvidia Tesla C2050 GPU. For a three-Virtex-5 chip only accelerator, we expect to achieve the same simulation speed as a Nvidia Tesla C2050 GPU, by consuming less than 3 #x025; of the energy at the same time.},
+  Cds_grade                = {5},
+  Cds_keywords             = {FPGA, hardware, accelerator, energy saving},
+  Cds_read                 = {2011-12-02},
+  Doi                      = {10.1109/ReConFig.2011.11},
+  File                     = {schshc_11.pdf:schshc_11.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-04-22}
+}
+
+@Unpublished{schshc_11_unpublished,
+  Title                    = {{A}n {E}nergy {E}fficient {FPGA} {A}ccelerator for {M}onte {C}arlo {O}ption {P}ricing with the {H}eston {M}odels},
+  Author                   = {Christian de Schryver and Ivan Shcherbakov and Frank Kienle and Norbert Wehn and Henning Marxen and Anton Kostiuk and Ralf Korn},
+  Note                     = {Accepted for Publicaton in Proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
+  Year                     = {2011},
+
+  Cds_grade                = {5},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.08.30}
+}
+
+@InProceedings{schtor_13,
+  Title                    = {{A} {M}ulti-{L}evel {M}onte {C}arlo {FPGA} {A}ccelerator for {O}ption {P}ricing in the {H}eston {M}odel},
+  Author                   = {Christian de Schryver and Pedro Torruella and Norbert Wehn},
+  Booktitle                = {Proceedings of the IEEE Conference on Design, Automation and Test in Europe (DATE)},
+  Year                     = {2013},
+  Month                    = mar,
+  Pages                    = {248--253},
+
+  Abstract                 = {The increasing demand for fast and accurate prod- uct pricing and risk computation together with high energy costs currently make finance and insurance institutes to rethink their IT infrastructure. Heterogeneous systems including specialized accelerator devices are a promising alternative to current CPU and GPU-clusters towards hardware accelerated computing. It has already been shown in previous work that complex state-of- the-art computations that have to be performed very frequently can be sped up by FPGA accelerators in a highly efficient way in this domain. A very common task is the pricing of credit derivatives, in particular options, under realistic market models. Monte Carlo methods are typically employed for complex or path dependent products. It has been shown that the multi-level Monte Carlo can provide a much better convergence behavior than standard single-level methods. In this work we present the first hardware architecture for pricing European barrier options in the Heston model based on the advanced multi-level Monte Carlo method. The presented architecture uses industry-standard AXI4-Stream flow control, is constructed in a modular way and can be extended to more products easily. We show that it computes around 100 millions of steps in a second with a total power consumption of 3.58 W on a Xilinx Virtex-6 FPGA.},
+  Cds_grade                = {5},
+  Cds_keywords             = {Heston, multi-level, Monte Carlo, hardware accelerator},
+  File                     = {schtor_13.pdf:schtor_13.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.03.20}
+}
+
+@Article{schweh_12,
+  Title                    = {{E}nergy {E}fficient {A}cceleration of {A}sset {S}imulations {U}sing {FPGA}s},
+  Author                   = {Christian de Schryver and Norbert Wehn},
+  Journal                  = {HiPEAC info},
+  Year                     = {2012},
+
+  Month                    = jan,
+  Pages                    = {10--11},
+  Volume                   = {29},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {FPGA, summary, Heston, random number generator},
+  Cds_read                 = {2012-02-01},
+  File                     = {schweh_12.pdf:schweh_12.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.03},
+  Url                      = {http://www.hipeac.net/system/files/hipeacinfo29bm.pdf}
+}
+
+@Misc{schgpu11,
+  Title                    = {{GPU} vs. {CPU} vs. {FPGA} - {C}ase {S}tudies and {N}umbers},
+
+  Author                   = {Christian de Schryver and Norbert Wehn},
+  HowPublished             = {Invited Talk at the Fraunhofer Innovationscafé, Kaiserslautern, Germany},
+  Month                    = apr,
+  Year                     = {2011},
+
+  File                     = {schgpu11.pptx:schgpu11.pptx:PPTX},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.10.30}
+}
+
+@Article{schwei_12,
+  Title                    = {{D}esign space exploration of high throughput finite field multipliers for channel coding on {X}ilinx {FPGA}s},
+  Author                   = {Christian de Schryver and Stefan Weithoffer and Uwe Wasenmüller and Norbert Wehn},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2012},
+
+  Month                    = sep,
+  Pages                    = {175--181},
+  Volume                   = {10},
+
+  Abstract                 = {Channel coding is a standard technique in all wireless communication systems. In addition to the typically employed methods like convolutional coding, turbo coding or low density parity check (LDPC) coding, algebraic codes are used in many cases. For example, outer BCH coding is applied in the DVB-S2 standard for satellite TV broadcasting. A key operation for BCH and the related Reed-Solomon codes are multiplications in finite fields (Galois Fields), where extension fields of prime fields are used. A lot of architectures for multiplications in finite fields have been published over the last decades. This paper examines four different multiplier architectures in detail that offer the potential for very high throughputs. We investigate the implementation performance of these multipliers on FPGA technology in the context of channel coding. We study the efficiency of the multipliers with respect to area, frequency and throughput, as well as configurability and scalability. The implementation data of the fully verified circuits are provided for a Xilinx Virtex-4 device after place and route.},
+  Cds_grade                = {5},
+  Cds_keywords             = {Galois field multipliers, finite field multipliers, FFM, BCH code},
+  Cds_read                 = {2012-09-18},
+  Doi                      = {10.5194/ars-10-175-2012},
+  File                     = {schwei_12.pdf:schwei_12.pdf:PDF},
+  Keywords                 = {BCH, AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2012.09.19},
+  Url                      = {http://www.adv-radio-sci.net/10/175/2012/}
+}
+
+@Misc{schitg15,
+  Title                    = {{T}owards {R}un-{T}ime {F}lexible {A}ccelerators in {H}igh {P}erformance {C}omputing},
+
+  Author                   = {Christian De Schryver},
+  HowPublished             = {Invited Talk at the 2nd Workshop of the Fachgruppe Architektur hochintegrierter Schaltungen of the ITG / VDE, TU Darmstadt, Germany},
+  Month                    = jun,
+  Year                     = {2015},
+
+  Owner                    = {CDS},
+  Timestamp                = {2015-07-09}
+}
+
+@Misc{schtowards15,
+  Title                    = {{T}owards {R}un-{T}ime {F}lexible {R}isk {M}anagement {S}ystems on {H}ybrid {P}latforms},
+
+  Author                   = {Christian De Schryver},
+  HowPublished             = {Invited Talk at the 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip (ReCoSoC 2015), Bremen, Germany},
+  Month                    = jun,
+  Year                     = {2015},
+
+  File                     = {schtowards15.pptx:schtowards15.pptx:PPTX},
+  Keywords                 = {AG_Wehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-06-30}
+}
+
+@InCollection{schnog_15,
+  Title                    = {{T}owards {A}utomated {B}enchmarking and {E}valuation of {H}eterogeneous {S}ystems in {F}inance},
+  Author                   = {Christian De Schryver and Carolina Pereira Nogueira},
+  Booktitle                = {FPGA Based Accelerators for Financial Applications},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2015},
+  Edition                  = {1st},
+  Editor                   = {De Schryver, Christian},
+  Month                    = jul,
+  Pages                    = {75--95},
+
+  Abstract                 = {Benchmarking and fair evaluation of computing systems is a challenge for High Performance Computing (HPC) in general, and for financial systems in particular. The reason is that there is no optimal solution for a specific problem in most cases, but the most appropriate models, algorithms, and their implementations depend on the desired accuracy of the result or the input parameters, for instance. In addition, flexibility and development effort of those systems are important metrics for purchasers from the finance domain and thus need to be well-quantified. In this section we introduce a precise terminology for separating the problem, the employed model, and a solution that consists of a selected algorithm and its implementation. We show how the design space (the space of all possible solutions to a problem) can be systematically structured and explored. In order to evaluate and characterize systems independent of their underlying execution platforms, we illustrate the concept of application-level benchmarks and summarize the state-of-the-art for financial applications. In particular for heterogeneous and Field Programmable Gate Array (FPGA)-accelerated systems, we present a framework structure for automatically executing and evaluating such benchmarks. We describe the framework structure in detail and show how this generic concept can be integrated with existing computing systems. A generic implementation of this framework is freely available for download.},
+  Doi                      = {10.1007/978-3-319-15407-7_4},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-08-21}
+}
+
+@Article{schweh_88,
+  Title                    = {{ALGIC - a Silicon Compiler for Digital Signal Processing}},
+  Author                   = {J.~Schuck and N. Wehn and M. Glesner},
+  Journal                  = {Computer-Aided Engineering Journal},
+  Year                     = {1988},
+
+  Month                    = oct,
+  Pages                    = {191--199},
+  Volume                   = {10/88},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{schweh_87,
+  Title                    = {{Das Silicon-Compiler System ALGIC: Konzeption, Implementierung und Einsatz in der digitalen Signalverarbeitung}},
+  Author                   = {J. Schuck and N. Wehn and M. Glesner},
+  Journal                  = {Design Automation, 1987. 24th Conference on},
+  Year                     = {1987},
+
+  Month                    = sep,
+  Note                     = {Titel Deutsch,-> Englisch??},
+  Pages                    = {370--375},
+  Volume                   = {1/87},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{schweh_87a,
+  Title                    = {{The ALGIC Silicon Compiler System: Implementation, Design, Experience, Results}},
+  Author                   = {J.~Schuck and N.~Wehn and M.~Glesner and G.~Kamp},
+  Booktitle                = {Proc. 24th Conference on Design Automation},
+  Year                     = {1987},
+
+  Address                  = {Miami},
+  Pages                    = {370--375},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{schshe_87,
+  Title                    = {{P}rocessor control flow monitoring using signatured instruction streams},
+  Author                   = {Schuette, Michael A. and Shen, John Paul},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {1987},
+  Number                   = {3},
+  Pages                    = {264--277},
+  Volume                   = {36},
+
+  Address                  = {Washington, DC, USA},
+  ISSN                     = {0018-9340},
+  Publisher                = {IEEE Computer Society}
+}
+
+@Article{schcat_01,
+  Title                    = {{Memory Optimization of MAP Turbo Decoder Algorithms}},
+  Author                   = {C. Schurgers and F. Catthoor and M. Engels},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2001},
+
+  Month                    = apr,
+  Number                   = {2},
+  Pages                    = {305--312},
+  Volume                   = {9},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{schcat_00,
+  Title                    = {{Optimized MAP Turbo Decoder}},
+  Author                   = {C. Schurgers and F. Catthoor and M. Engels},
+  Booktitle                = {Proc. 2000 Workshop on Signal Processing Systems (SiPS `00)},
+  Year                     = {2000},
+
+  Address                  = {Lafayette, Louisiana, USA},
+  Month                    = sep,
+  Pages                    = {245--254},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{scheng_99,
+  Title                    = {{Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module}},
+  Author                   = {C. Schurgers and M. Engels and F. Catthoor},
+  Booktitle                = {Proc. 1999 International Symposium on Low Power Electronics and Design (ISLPED '99)},
+  Year                     = {1999},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = aug,
+  Pages                    = {76--81},
+
+  File                     = {scheng_99.pdf:scheng_99.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{Schutz1992,
+  Title                    = {{A} {VLSI}-chip for a hardware-accelerator for the simplex-method},
+  Author                   = {Schutz, B. and Klindworth, A.},
+  Booktitle                = {ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International},
+  Year                     = {1992},
+  Month                    = {Sep},
+  Pages                    = {553-556},
+
+  File                     = {schkli_92.pdf:schkli_92.pdf:PDF},
+  Keywords                 = {LPDecoding},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.08}
+}
+
+@Book{sch_04,
+  Title                    = {{A}gile {P}roject {M}anagement with {S}crum},
+  Author                   = {Schwaber, K.},
+  Publisher                = {Pearson Education},
+  Year                     = {2004},
+  Series                   = {Developer Best Practices},
+
+  ISBN                     = {9780735637900},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.26},
+  Url                      = {https://books.google.de/books?id=6pZCAwAAQBAJ}
+}
+
+@Article{sch_10,
+  Title                    = {{G}raphene transistors},
+  Author                   = {Frank Schwierz},
+  Journal                  = {Nature Nanotechnology},
+  Year                     = {2010},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {487 - 496},
+  Volume                   = {5},
+
+  Doi                      = {10.1038/nnano.2010.89},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.02.24},
+  Url                      = {http://www.nature.com/nnano/journal/v5/n7/index.html}
+}
+
+@Article{scotav_86,
+  Title                    = {{A} {F}ast {VLSI} {M}ultiplier for {GF}(2m)},
+  Author                   = {Scott, P. and Tavares, S. and Peppard, L.},
+  Journal                  = {Selected Areas in Communications, IEEE Journal on},
+  Year                     = {1986},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = { 62-66},
+  Volume                   = {4},
+
+  Abstract                 = {Multiplication in the finite fieldGF(2^{m}) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication inGF(2^{m}), which isO(m)in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given. The design is highly regular, modular, and well-suited for VLSI implementation. The resulting multiplier will have application in algorithms based on arithmetic in large finite fields of characteristic 2, and which require high throughput.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Galois field multiplier, FFM, VLSI},
+  Cds_review               = {low-level paper, easy to understand
+algorithmic description -> easy implementation in VHDL
+old approach},
+  File                     = {scotav_86.pdf:scotav_86.pdf:PDF},
+  ISSN                     = {0733-8716},
+  Keywords                 = {null Galois fields, Multiplication, VLSI, Very large-scale integration (VLSI)},
+  Owner                    = {CdS},
+  Timestamp                = {2009.03.17}
+}
+
+@Misc{sea_15,
+  Title                    = {{H}ow physical addresses map to rows and banks in {DRAM}},
+
+  Author                   = {Mark Seaborn},
+  HowPublished             = {\url{http://lackingrhoticity.blogspot.de/2015/05/how-physical-addresses-map-to-rows-and-banks.html}},
+  Month                    = {May},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-20}
+}
+
+@Misc{seadul_15,
+  Title                    = {{E}xploiting the {DRAM} rowhammer bug to gain kernel privileges},
+
+  Author                   = {Seaborn, Mark and Dullien, Thomas},
+  HowPublished             = {\url{http://googleprojectzero.blogspot.de/2015/03/exploiting-dram-rowhammer-bug-to-gain.html}},
+  Month                    = {March},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-03-23}
+}
+
+@Electronic{see_14,
+  Title                    = {{S}onder-{CPU}s für {C}loud-{D}ienstleister: {I}ntel kombiniert {X}eons mit {FPGA}s für {S}pezial-{B}efehle},
+  Author                   = {Jürgen Seeger},
+  HowPublished             = {\url{http://www.heise.de/ix/meldung/Sonder-CPUs-fuer-Cloud-Dienstleister-Intel-kombiniert-Xeons-mit-FPGAs-fuer-Spezial-Befehle-2235150.html}},
+  Language                 = {de},
+  Month                    = jun,
+  Note                     = {last access 2014-07-02},
+  Organization             = {Heise Verlag},
+  Url                      = {http://www.heise.de/ix/meldung/Sonder-CPUs-fuer-Cloud-Dienstleister-Intel-kombiniert-Xeons-mit-FPGAs-fuer-Spezial-Befehle-2235150.html},
+  Year                     = {2014},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {Intel, Xeon, CPU, FPGA, news, Altera},
+  File                     = {see_14.pdf:see_14.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.22}
+}
+
+@InProceedings{segmar_16,
+  Title                    = {{E}xploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud},
+  Author                   = {Oren Segal and Martin Margala},
+  Booktitle                = {2016 International Conference on High Performance Computing Simulation (HPCS)},
+  Year                     = {2016},
+  Month                    = {July},
+  Pages                    = {132-139},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.22}
+}
+
+@InProceedings{segver_06,
+  Title                    = {{A} {DVB}-{S}2 compliant {LDPC} decoder integrating the {H}orizontal {S}huffle {S}cheduling},
+  Author                   = {Segard, A. and Verdier, F. and Declercq, D. and Urard, P.},
+  Booktitle                = {Proc. International Symposium on Intelligent Signal Processing and Communications ISPACS '06},
+  Year                     = {2006},
+  Month                    = dec,
+  Pages                    = {1013--1016},
+
+  Doi                      = {10.1109/ISPACS.2006.364808},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{sei_08,
+  Title                    = {{S}oft {E}rror {R}ates of {H}ardened {S}equentials utilizing {L}ocal {R}edundancy},
+  Author                   = {Seifert, N. },
+  Booktitle                = {Proc. 14th IEEE Int. On-Line Testing Symp. IOLTS '08},
+  Year                     = {2008},
+  Pages                    = {49--50},
+
+  Doi                      = {10.1109/IOLTS.2008.61},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{seiamb_10,
+  Title                    = {{O}n the radiation-induced soft error performance of hardened sequential elements in advanced bulk {CMOS} technologies},
+  Author                   = {Seifert, N. and Ambrose, V. and Gill, B. and Shi, Q. and Allmon, R. and Recchia, C. and Mukherjee, S. and Nassif, N. and Krause, J. and Pickholtz, J. and Balasubramanian, A. },
+  Booktitle                = {Proc. IEEE Int. Reliability Physics Symp. (IRPS)},
+  Year                     = {2010},
+  Pages                    = {188--197},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/IRPS.2010.5488831},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{seigil_07,
+  Title                    = {{O}n the {S}calability of {R}edundancy based {SER} {M}itigation {S}chemes},
+  Author                   = {Seifert, N. and Gill, B. and Zia, V. and Ming Zhang and Ambrose, V. },
+  Booktitle                = {Proc. IEEE Int. Conf. Integrated Circuit Design and Technology ICICDT '07},
+  Year                     = {2007},
+  Pages                    = {1--9},
+
+  Doi                      = {10.1109/ICICDT.2007.4299573},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{seizhu_02,
+  Title                    = {{I}mpact of scaling on soft-error rates in commercial microprocessors},
+  Author                   = {Seifert, N. and Xiaowei Zhu and Massengill, L. W. },
+  Journal                  = {Nuclear Science, IEEE Transactions on},
+  Year                     = {2002},
+  Number                   = {6},
+  Pages                    = {3100--3106},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/TNS.2002.805402},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Misc{sensysnetworks,
+  Title                    = {http://www.sensysnetworks.com/},
+
+  Author                   = {Sensys Networks, Inc.},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://www.sensysnetworks.com/}
+}
+
+@InProceedings{seomud_07,
+  Title                    = {{Design and Analyis of LDPC Decoders for Software Define Radio}},
+  Author                   = {Sangwon Seo and Trevor Mudge and Yuming Zhu and Chaitali Chakrabarti},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing (SIPS'07)},
+  Year                     = {2007},
+
+  Address                  = {Shanghai, China},
+  Month                    = oct,
+  Pages                    = {210-215},
+
+  File                     = {seomud_07.pdf:seomud_07.pdf:PDF},
+  Owner                    = {alles},
+  Timestamp                = {2008.03.06}
+}
+
+@Article{seoche_11,
+  Title                    = {{CAS}-{FEST} 2010: {M}itigating {V}ariability in {N}ear-{T}hreshold {C}omputing},
+  Author                   = {Mingoo Seok and Chen, G. and Hanson, S. and Wieckowski, M. and Blaauw, D. and Sylvester, D.},
+  Journal                  = {Emerging and Selected Topics in Circuits and Systems, IEEE Journal on},
+  Year                     = {2011},
+  Number                   = {1},
+  Pages                    = {42--49},
+  Volume                   = {1},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Technology, Empfehlung Norbert},
+  Doi                      = {10.1109/JETCAS.2011.2135550},
+  File                     = {seoche_11.pdf:seoche_11.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.15}
+}
+
+@InProceedings{sesmul_15,
+  Title                    = {{G}ather-scatter {DRAM}: {I}n-{DRAM} {A}ddress {T}ranslation to {I}mprove the {S}patial {L}ocality of {N}on-unit {S}trided {A}ccesses},
+  Author                   = {Seshadri, Vivek and Mullins, Thomas and Boroumand, Amirali and Mutlu, Onur and Gibbons, Phillip B. and Kozuch, Michael A. and Mowry, Todd C.},
+  Booktitle                = {Proceedings of the 48th International Symposium on Microarchitecture},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {267--280},
+  Publisher                = {ACM},
+  Series                   = {MICRO-48},
+
+  Acmid                    = {2830820},
+  Doi                      = {10.1145/2830772.2830820},
+  ISBN                     = {978-1-4503-4034-2},
+  Keywords                 = {DRAM, SIMD, caches, energy, in-memory databases, memory bandwidth, performance, strided accesses},
+  Location                 = {Waikiki, Hawaii},
+  Numpages                 = {14},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11},
+  Url                      = {http://doi.acm.org/10.1145/2830772.2830820}
+}
+
+@Misc{sesdesign02,
+  Title                    = {{Design methodologies meet network applications}},
+
+  Author                   = {DAC'02 Sessions},
+  Month                    = jun,
+  Year                     = {2002},
+
+  Address                  = {New Orleans, LA, USA},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Sessions2002,
+  Title                    = {{Design methodologies meet network applications}},
+
+  Author                   = {DAC'02 Sessions},
+  Month                    = jun,
+  Year                     = {2002},
+
+  Address                  = {New Orleans, LA, USA},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Sessions2002a,
+  Title                    = {{System on chip design}},
+
+  Author                   = {DAC'02 Sessions},
+  Month                    = jun,
+  Year                     = {2002},
+
+  Address                  = {New Orleans, LA, USA},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{sessystem02,
+  Title                    = {{System on chip design}},
+
+  Author                   = {DAC'02 Sessions},
+  Month                    = jun,
+  Year                     = {2002},
+
+  Address                  = {New Orleans, LA, USA},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{sey_17,
+  Title                    = {{M}itigating {B}itline {C}rosstalk {N}oise in {DRAM} {M}emories},
+  Author                   = {Seyedzadeh, Seyed Mohammad},
+  Year                     = {2017},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-21}
+}
+
+@InProceedings{sgrshe_01,
+  Title                    = {{A}ddressing the {S}ystem-on-a-{C}hip {I}nterconnect {W}oes {T}hrough {C}ommunication-{B}ased {D}esign},
+  Author                   = {M. Sgroi and M. Sheets and A. Mihal and K. Keutzer and S. Malik and J. Rabaey and A. Sangiovanni-Vincentelli},
+  Booktitle                = {Proceedings of the 38th Design Automation Conference, 2001},
+  Year                     = {2001},
+  Pages                    = {667--672},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{shalin_09,
+  Title                    = {{LDPC} decoder design for {IEEE} 802.15 standard},
+  Author                   = {Jin Sha and Jun Lin and Li Li and Gao Minglun and Zhongfeng Wang},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2009},
+  Year                     = {2009},
+  Month                    = may,
+  Pages                    = {2441--2444},
+
+  Doi                      = {10.1109/ISCAS.2009.5118294},
+  File                     = {shalin_09.pdf:shalin_09.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.08.06}
+}
+
+@Article{Sha2009,
+  Title                    = {{LDPC} decoder design for high rate wireless personal area networks},
+  Author                   = {Jin Sha and Jun Lin and Zhongfeng Wang and Li Li and Minglun Gao},
+  Journal                  = IEEE_J_CE,
+  Year                     = {2009},
+  Number                   = {2},
+  Pages                    = {455--460},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCE.2009.5174407},
+  File                     = {Sha2009.pdf:Sha2009.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.01.26}
+}
+
+@Article{shawan_09,
+  Title                    = {{M}ulti-{G}b/s {LDPC} {C}ode {D}esign and {I}mplementation},
+  Author                   = {Jin Sha and Zhongfeng Wang and Minglun Gao and Li Li},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2009},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {262--268},
+  Volume                   = {17},
+
+  Doi                      = {10.1109/TVLSI.2008.2002487},
+  File                     = {shawan_09.pdf:shawan_09.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.08}
+}
+
+@Article{shages_03,
+  Title                    = {{G}uest editorial: {MIMO} systems and applications. 1},
+  Author                   = {Shafi, M. and Gesbert, D. and shan Shiu, Da and Smith, P. J. and Tranter, W. H.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2003},
+  Number                   = {3},
+  Pages                    = {277--280},
+  Volume                   = {21},
+
+  Doi                      = {10.1109/JSAC.2003.809538},
+  File                     = {shages_03.pdf:shages_03.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {0733-8716},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@Article{shages_03a,
+  Title                    = {{G}uest editorial {MIMO} systems and applications. {II}},
+  Author                   = {Shafi, M. and Gesbert, D. and shan Shiu, Da and Smith, P. J. and Tranter, W. H.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2003},
+  Number                   = {5},
+  Pages                    = {681--683},
+  Volume                   = {21},
+
+  Doi                      = {10.1109/JSAC.2003.809537},
+  File                     = {shages_03a.pdf:shages_03a.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {0733-8716},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@Article{shayak_18,
+  Title                    = {{R}eal-{P}ower {C}omputing},
+  Author                   = {R. {Shafik} and A. {Yakovlev} and S. {Das}},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2018},
+
+  Month                    = {Oct},
+  Number                   = {10},
+  Pages                    = {1445-1461},
+  Volume                   = {67},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8330023},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/TC.2018.2822697},
+  ISSN                     = {0018-9340},
+  Keywords                 = {TCS},
+  Keywords_original        = {Task analysis;Real-time systems;Embedded systems;Taxonomy;Power demand;Uncertainty;Embedded systems;Energy-driven computing;Energy harvesting;Energy-modulated computing;Energy transparency;Low-power design;Power-compute co-design;Power-neutral computing;Power-proportional computing;Run-time systems;Survivability;Transient computing;Worst-case power consumption},
+  Owner                    = {CCR}
+}
+
+@InProceedings{shagar_14a,
+  Title                    = {{T}he {EDA} challenges in the dark silicon era},
+  Author                   = {Shafique, M. and Garg, S. and Henkel, J. and Marculescu, D.},
+  Booktitle                = {Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE},
+  Year                     = {2014},
+  Pages                    = {1--6},
+
+  Doi                      = {10.1145/2593069.2593229},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.08.26},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6881512}
+}
+
+@InProceedings{shagar_14,
+  Title                    = {{D}ark silicon as a challenge for hardware/software co-design},
+  Author                   = {Shafique, M. and Garg, S. and Mitra, T. and Parameswaran, S. and Henkel, J.},
+  Booktitle                = {Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2014 International Conference on},
+  Year                     = {2014},
+  Pages                    = {1--10},
+
+  Doi                      = {10.1145/2656075.2661645},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.08.26},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6971829}
+}
+
+@InProceedings{shagna_15,
+  Title                    = {{V}ariability-aware dark silicon management in on-chip many-core systems},
+  Author                   = {Shafique, M. and Gnad, D. and Garg, S. and Henkel, J.},
+  Booktitle                = {Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2015},
+  Year                     = {2015},
+  Pages                    = {387--392},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.08.26},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7092419}
+}
+
+@InProceedings{shahaf_16,
+  Title                    = {{C}ross-{L}ayer {A}pproximate {C}omputing: {F}rom {L}ogic to {A}rchitectures},
+  Author                   = {Shafique, M. and Hafiz, R. and Rehman, S. and El-Harouni, W. and Henkel, J.},
+  Booktitle                = {ACM/IEEE Design Automation Conference (DAC)},
+  Year                     = {2016},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-05}
+}
+
+@Book{sha_14,
+  Title                    = {{C}ontinuous {E}ngineering for {D}ummies},
+  Author                   = {Shamieh, Cathleen},
+  Publisher                = {John Wiley \& Sons, Inc.},
+  Year                     = {2014},
+
+  ISBN                     = {3319112821, 9783319112824},
+  Owner                    = {MJ},
+  Timestamp                = {2020-02-09}
+}
+
+@Article{sha_87,
+  Title                    = {{T}he {E}fficiency of the {S}implex {M}ethod: {A} {S}urvey},
+  Author                   = {Shamir, Ron},
+  Journal                  = {Management Science},
+  Year                     = {1987},
+  Number                   = {3},
+  Pages                    = {301-334},
+  Volume                   = {33},
+
+  Doi                      = {10.1287/mnsc.33.3.301},
+  Eprint                   = {http://pubsonline.informs.org/doi/pdf/10.1287/mnsc.33.3.301},
+  Owner                    = {scholl},
+  Timestamp                = {2016.08.02},
+  Url                      = {http://pubsonline.informs.org/doi/abs/10.1287/mnsc.33.3.301}
+}
+
+@InProceedings{sha_02,
+  Title                    = {{R}eliable and {E}nergy-{E}fficient {D}igital {S}ignal {P}rocessing},
+  Author                   = {Shanbhag, N. },
+  Booktitle                = {Proc. 39th Design Automation Conference},
+  Year                     = {2002},
+  Month                    = jun,
+  Pages                    = {830--835},
+
+  Doi                      = {10.1109/DAC.2002.1012737},
+  File                     = {sha_02.pdf:sha_02.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.22}
+}
+
+@Article{sha_04,
+  Title                    = {{Reliable and Efficient System-on-Chip Design}},
+  Author                   = {Shanbhag, Naresh R.},
+  Journal                  = {Computer},
+  Year                     = {2004},
+  Number                   = {3},
+  Pages                    = {42-50},
+  Volume                   = {37},
+
+  Cb_grade                 = {- nicht gelesen
+- Reliability
+- Shanbhag
+- allg?
+-},
+  File                     = {sha_04.pdf:sha_04.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Publisher                = {IEEE Computer Society},
+  Timestamp                = {2011.10.18}
+}
+
+@InProceedings{shaabd_10,
+  Title                    = {{S}tochastic {C}omputation},
+  Author                   = {Shanbhag, N. R. and Abdallah, R. A. and Kumar, R. and Jones, D. L.},
+  Booktitle                = {Proc. 47th ACM/IEEE Design Automation Conf. (DAC)},
+  Year                     = {2010},
+  Pages                    = {859--864},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- Shanbhag
+- Basics, ANT, Soft N Modular Redundancy},
+  File                     = {shaabd_10.pdf:shaabd_10.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{shamit_08,
+  Title                    = {{T}he {S}earch for {A}lternative {C}omputational {P}aradigms},
+  Author                   = {Shanbhag, N. R. and Mitra, S. and de Veciana, G. and Orshansky, M. and Marculescu, R. and Roychowdhury, J. and Jones, D. and Rabaey, J. M.},
+  Journal                  = {IEEE Design \& Test of Computers},
+  Year                     = {2008},
+
+  Month                    = jul # {--} # aug,
+  Number                   = {4},
+  Pages                    = {334--343},
+  Volume                   = {25},
+
+  Doi                      = {10.1109/MDT.2008.113},
+  File                     = {shamit_08.pdf:shamit_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.07.14}
+}
+
+@Article{shalys_10,
+  Title                    = {{C}ontrol {F}ocused {S}oft {E}rror {D}etection for {E}mbedded {A}pplications},
+  Author                   = {Shankar, K. and Lysecky, R.},
+  Journal                  = {Embedded Systems Letters, IEEE},
+  Year                     = {2010},
+  Number                   = {4},
+  Pages                    = {127--130},
+  Volume                   = {2},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- control logic, pipeline, processor},
+  Doi                      = {10.1109/LES.2010.2091940},
+  File                     = {shalys_10.pdf:shalys_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{sha_53,
+  Title                    = {{G}eneral treatment of the problem of coding},
+  Author                   = {C. Shannon},
+  Journal                  = {Transactions of the IRE Professional Group on Information Theory},
+  Year                     = {1953},
+
+  Month                    = {Feb},
+  Number                   = {1},
+  Pages                    = {102-104},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/TIT.1953.1188559},
+  ISSN                     = {2168-2690},
+  Keywords                 = {Acoustic noise;Decoding;Ear;Entropy;Humans;Phase distortion;Stochastic processes;TV;Telephony;Transmitters},
+  Owner                    = {StW},
+  Timestamp                = {2017.02.16}
+}
+
+@Article{sha_59,
+  Title                    = {{P}robability of {E}rror for {O}ptimal {C}odes in a {G}aussian {C}hannel},
+  Author                   = {Shannon, C. E.},
+  Journal                  = {Bell System Technical Journal},
+  Year                     = {1959},
+  Pages                    = {611--656},
+  Volume                   = {38},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.02.04}
+}
+
+@Article{sha_48,
+  Title                    = {{A} {M}athematical {T}heory of {C}ommunication},
+  Author                   = {Shannon, Claude E.},
+  Journal                  = {Bell System Technical Journal},
+  Year                     = {1948},
+
+  Month                    = jul # {--} # oct,
+  Pages                    = {379--423 and 623--656},
+  Volume                   = {27},
+
+  Cds_grade                = {0},
+  File                     = {sha_48.pdf:sha_48.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Url                      = {http://cm.bell-labs.com/cm/ms/what/shannonday/paper.html}
+}
+
+@Article{shatru_85,
+  Title                    = {{A} {VLSI} {D}esign of a {P}ipeline {R}eed-{S}olomon {D}ecoder},
+  Author                   = {Howard M. Shao and Truong, T.K. and Deutsch, L.J. and Yuen, J.H. and Irving S. Reed},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {1985},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {393-403},
+  Volume                   = {C-34},
+
+  Abstract                 = {A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a (15,9) RS code.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TC.1985.1676579},
+  File                     = {shatru_85.pdf:shatru_85.pdf:PDF},
+  ISSN                     = {0018-9340},
+  Keywords                 = {nullPipeline, Reed-Solomon decoder, VLSI, systolic array},
+  Owner                    = {CdS},
+  Timestamp                = {2009.06.22}
+}
+
+@InProceedings{shadav_05,
+  Title                    = {{T}he {B}it-reversal {SDRAM} {A}ddress {M}apping},
+  Author                   = {Shao, Jun and Davis, Brian T.},
+  Booktitle                = {Proceedings of the 2005 Workshop on Software and Compilers for Embedded Systems},
+  Year                     = {2005},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {62--71},
+  Publisher                = {ACM},
+  Series                   = {SCOPES '05},
+
+  Acmid                    = {1140396},
+  Doi                      = {10.1145/1140389.1140396},
+  ISBN                     = {1-59593-207-0},
+  Keywords                 = {SDRAM, address mapping, memory controller},
+  Location                 = {Dallas, Texas, USA},
+  Numpages                 = {10},
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-11},
+  Url                      = {http://doi.acm.org/10.1145/1140389.1140396}
+}
+
+@InProceedings{shafos_98,
+  Title                    = {{Two Simple Stopping Criteria for Turbo Decoding}},
+  Author                   = {R. Y. Shao and M. C. P. Fossorier and S. Lin},
+  Booktitle                = {Proc. 1998 IEEE International Symposium on Information Theory (ISIT)},
+  Year                     = {1998},
+
+  Address                  = {Cambridge, Massachusetts, USA},
+  Month                    = aug,
+  Pages                    = {279},
+
+  File                     = {shafos_98.pdf:shafos_98.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{shalin_99,
+  Title                    = {{Two Simple Stopping Criteria for Turbo Decoding}},
+  Author                   = {Shao, R. Y. and S. Lin and Fossorier, M. C. P.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1999},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {1117--1120},
+  Volume                   = {47},
+
+  Cb_grade                 = {- ASIP
+- Iteration Control
+- sign-change ratio},
+  File                     = {shalin_99.pdf:shalin_99.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{sharea_14,
+  Title                    = {{A}laddin: {A} pre-{RTL}, power-performance accelerator simulator enabling large design space exploration of customized architectures},
+  Author                   = {Shao, Yakun Sophia and Reagen, Brandon and Wei, Gu-Yeon and Brooks, David},
+  Booktitle                = {Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on},
+  Year                     = {2014},
+  Organization             = {IEEE},
+  Pages                    = {97--108},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.24}
+}
+
+@Misc{shanvidia18,
+  Title                    = {{NVIDIA} {DRIVE} {X}avier, {W}orld's {M}ost {P}owerful {S}o{C}, {B}rings {D}ramatic {N}ew {AI} {C}apabilities},
+
+  Author                   = {Shapiro, Danny},
+  Month                    = {January},
+  Year                     = {2018},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-03},
+  Url                      = {https://blogs.nvidia.com/blog/2018/01/07/drive-xavier-processor/}
+}
+
+@Article{shawil_65,
+  Title                    = {{A}n {A}nalysis-of-{V}ariance {T}est for {N}ormality ({C}omplete {S}amples)},
+  Author                   = {Shapiro, S. S. and Wilk, M. B.},
+  Journal                  = {Biometrika},
+  Year                     = {1965},
+
+  Month                    = {December},
+  Pages                    = {591-611},
+  Volume                   = {52},
+
+  Owner                    = {marxen},
+  Timestamp                = {2011.04.23}
+}
+
+@Article{shaman_08,
+  Title                    = {{F}ully {P}arallel {S}tochastic {LDPC} {D}ecoders},
+  Author                   = {Sharifi Tehrani, S. and Mannor, S. and Gross, W. J. },
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2008},
+  Number                   = {11},
+  Pages                    = {5692--5703},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TSP.2008.929671},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.03.29}
+}
+
+@Article{shasol_11,
+  Title                    = {{E}fficient {I}terative {T}echniques for {S}oft {D}ecision {D}ecoding of {R}eed-{S}olomon {C}odes},
+  Author                   = {Shayegh, F. and Soleymani, M. R.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2011},
+  Number                   = {2},
+  Pages                    = {428--436},
+  Volume                   = {59},
+
+  Doi                      = {10.1109/TCOMM.2011.121410.090612},
+  File                     = {shasol_11.pdf:shasol_11.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{shasol_11a,
+  Title                    = {{E}fficient soft decoding of reed-solomon codes based on sphere decoding},
+  Author                   = {Shayegh, F. and Soleymani, M. R.},
+  Journal                  = {IET Communications},
+  Year                     = {2011},
+  Number                   = {2},
+  Pages                    = {141--153},
+  Volume                   = {5},
+
+  Doi                      = {10.1049/iet-com.2010.0078},
+  File                     = {shasol_11a.pdf:shasol_11a.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{shasol_10,
+  Title                    = {{I}terative soft decoding of {R}eed-{S}olomon codes using information correction},
+  Author                   = {Shayegh, F. and Soleymani, M. R.},
+  Booktitle                = {Proc. 5th Int Telecommunications (IST) Symp},
+  Year                     = {2010},
+  Pages                    = {345--350},
+
+  Doi                      = {10.1109/ISTEL.2010.5734050},
+  File                     = {shasol_10.pdf:shasol_10.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{shasol_09,
+  Title                    = {{A} {L}ow {C}omplexity {I}terative {T}echnique for {S}oft {D}ecision {D}ecoding of {R}eed-{S}olomon {C}odes},
+  Author                   = {Shayegh, F. and Soleymani, M. R. },
+  Booktitle                = {Proc. IEEE Int. Conf. Communications ICC '09},
+  Year                     = {2009},
+  Pages                    = {1--6},
+
+  Doi                      = {10.1109/ICC.2009.5198625},
+  File                     = {shasol_09.pdf:shasol_09.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {machen die Matrix vorher dünn und schieben zykisch},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{shasol_08,
+  Title                    = {{S}oft {D}ecision {D}ecoding of {R}eed-{S}olomon {C}odes {U}sing {S}phere {D}ecoding},
+  Author                   = {Shayegh, F. and Soleymani, M. R. },
+  Booktitle                = {Proc. IEEE Int. Conf. Communications ICC '08},
+  Year                     = {2008},
+  Pages                    = {4489--4495},
+
+  Doi                      = {10.1109/ICC.2008.842},
+  File                     = {shasol_08.pdf:shasol_08.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {Sphere Decoding für Block Codes (möglicherweise erstes Paper)},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{schweh_12a,
+  Title                    = {{A} {P}arallel {A}daptive {R}ange {C}oding {C}ompressor: {A}lgorithm, {FPGA} {P}rototype, {E}valuation},
+  Author                   = {Shcherbakov, I. and Wehn, N.},
+  Booktitle                = {Data Compression Conference (DCC), 2012},
+  Year                     = {2012},
+  Month                    = {april},
+  Pages                    = {119 -128},
+
+  Doi                      = {10.1109/DCC.2012.20},
+  ISSN                     = {1068-0314},
+  Keywords                 = {7-zip compressor;FPGA prototype;Virtex5 FPGA;automotive systems;distributed FPGA logic;field programmable gate array;fixed-table Huffman encoder;hardware LZSS coder;loss less compression algorithms;parallel adaptive range coding compressor;real-time communication log compression;Huffman codes;adaptive codes;data compression;field programmable gate arrays;}
+}
+
+@Conference{shcweh_12,
+  Title                    = {{A} {P}arallel {A}daptive {R}ange {C}oding {C}ompressor: {A}lgorithm, {FPGA} {P}rototype, {E}valuation},
+  Author                   = {I. Shcherbakov and N. Wehn},
+  Booktitle                = {Data Compression Conference},
+  Year                     = {2012},
+
+  Address                  = {Snowbird, UT, USA},
+  Month                    = {April},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@InProceedings{shcwei_12,
+  Title                    = {{A} {H}igh-{P}erformance {FPGA}-{B}ased {I}mplementation of the {LZSS} {C}ompression {A}lgorithm},
+  Author                   = {Shcherbakov, I. and Weis, C. and Wehn, N.},
+  Booktitle                = {Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), 2012 IEEE 26th International},
+  Year                     = {2012},
+  Month                    = {may},
+  Pages                    = {449 -453},
+
+  Doi                      = {10.1109/IPDPSW.2012.58},
+  Keywords                 = {FPGA resource utilization;LZSS compression algorithm;Virtex-5 FPGA chip;ZLib library;compression ratio;cycle-accurate estimation tool;data representation;deflate specification;embedded networking applications;field programmable gate array;fixed Huffman table;high-performance FPGA-based implementation;high-performance logging systems;independent addressable dual-port block RAM;logged stream compression;logger performance maximization;redundant data;data compression;data structures;field programmable gate arrays;random-access storage;}
+}
+
+@InProceedings{shcwei_11,
+  Title                    = {{B}ringing {C}++ {P}roductivity to {VHDL} {W}orld: from {L}anguage {D}efinition to a {C}ase {S}tudy},
+  Author                   = {Ivan Shcherbakov and Christian Weis and Norbert Wehn},
+  Booktitle                = {Specification Design Languages, 2011. IC 2011. Forum on},
+  Year                     = {2011},
+  Month                    = sep,
+  Pages                    = {76 --82},
+
+  Cds_grade                = {0},
+  ISSN                     = {1636-9874},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2011.10.04}
+}
+
+@Unpublished{shcwei_11_unpublished,
+  Title                    = {{B}ringing {C}++ {P}roductivity to {VHDL} {W}orld: {F}rom {L}anguage {D}efinition to a {C}ase {S}tudy},
+  Author                   = {Ivan Shcherbakov and Christian Weis and Norbert Wehn},
+  Note                     = {Accepted for publication in Proceedings of Forum on Specification and Design Languages (FDL) 2011},
+
+  Month                    = sep,
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.07.21}
+}
+
+@InProceedings{shepar_07,
+  Title                    = {{D}esign {M}ethodology for {P}ipelined {H}eterogeneous {M}ultiprocessor {S}ystem},
+  Author                   = {Seng Lin Shee and Parameswaran, S. },
+  Booktitle                = {Proc. 44th ACM/IEEE Design Automation Conf. DAC '07},
+  Year                     = {2007},
+  Pages                    = {811--816},
+
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.08}
+}
+
+@InProceedings{shexia_08,
+  Title                    = {{V}ersatile and {E}fficient {T}echniques for {S}peeding-{U}p {C}ircuit {L}evel {S}imulated {F}ault-{I}njection {C}ampaigns},
+  Author                   = {Weiguang Sheng and Liyi Xiao and Zhigang Mao},
+  Booktitle                = {Proc. 14th IEEE Pacific Rim Int. Symp. Dependable Computing PRDC '08},
+  Year                     = {2008},
+  Pages                    = {17--23},
+
+  Doi                      = {10.1109/PRDC.2008.9},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{shiwu_18,
+  Title                    = {{T}ime {S}tamp {B}ased {S}cheduling for {E}nergy {H}arvesting {S}ystems with {H}ybrid {N}onvolatile {H}ardware {S}upport},
+  Author                   = {X. {Shi} and T. {Wu} and K. {Qiu} and H. {Yang} and Y. {Liu}},
+  Booktitle                = {2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
+  Year                     = {2018},
+  Month                    = {July},
+  Pages                    = {339-344},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {Kinda confusing what they want to achieve},
+  Ccr_key_original         = {8429390},
+  Ccr_keywords             = {n.a.},
+  Ccr_relevance            = {low},
+  Ccr_topic                = {n.a.},
+  Doi                      = {10.1109/ISVLSI.2018.00069},
+  ISSN                     = {2159-3477},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;scheduling;intermittent power supply;task execution time;previous scheduling algorithms;hybrid nonvolatile hardware platform;time stamp based scheduling algorithm;state-of-the-art algorithms;energy harvesting systems;hybrid nonvolatile hardware support;nonvolatile processors;strong vitality;endurable features;Task analysis;Optimal scheduling;Hardware;Switches;Nonvolatile memory;Energy harvesting;energy harvesting;scheduling;nonvolatile hardware},
+  Owner                    = {CCR}
+}
+
+@InProceedings{shiche_14,
+  Title                    = {{O}n {O}ptimized {U}niform {Q}uantization for {SC} {D}ecoder of {P}olar {C}odes},
+  Author                   = {Z. Shi and K. Chen and K. Niu},
+  Booktitle                = {Vehicular Technology Conference (VTC Fall), 2014 IEEE 80th},
+  Year                     = {2014},
+  Month                    = {Sept},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/VTCFall.2014.6966081},
+  Keywords                 = {Gaussian processes;channel coding;decoding;error statistics;optimisation;quantisation (signal);channel cutoff rate optimization;frame error rate estimation;hardware implementation;modified Gaussian approximation method;polar codes;quantization scheme;regular recursive structure;successive-cancellation decoding;Decoding;Encoding;Probability density function;Quantization (signal);Reliability;Upper bound;Vectors},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{shiniu_14,
+  Title                    = {{O}n uniform quantization for successive cancellation decoder of polar codes},
+  Author                   = {Z. Shi and K. Niu},
+  Booktitle                = {Personal, Indoor, and Mobile Radio Communication (PIMRC), 2014 IEEE 25th Annual International Symposium on},
+  Year                     = {2014},
+  Month                    = {Sept},
+  Pages                    = {545-549},
+
+  Doi                      = {10.1109/PIMRC.2014.7136225},
+  Keywords                 = {Gaussian processes;approximation theory;channel coding;decoding;error statistics;estimation theory;mean square error methods;FER estimation;MSE;SC;cutoff rate maximizing criterion;equivalent channel capacity;floating point performance;frame error rate estimation;mean-squared error;modified GA method;modified Gaussian approximation;polar code;regular-recursive structure;successive cancellation decoder;uniform quantization scheme;word length 6 bit;Approximation algorithms;Channel capacity;Decoding;Encoding;Hardware;Quantization (signal);Simulation;Gauss Approximation;Polar Codes;Quantization;SC Decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{shisud_99,
+  Title                    = {{Complexity Reduction of Turbo Decoding}},
+  Author                   = {A. Shibutani and H. Suda and F. Adachi},
+  Booktitle                = {{Proc. 1999-Fall Vehicular Technology Conference (VTC '99 Fall)}},
+  Year                     = {1999},
+
+  Address                  = {Amsterdam, The Netherlands},
+  Month                    = sep,
+  Pages                    = {1570--1574},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{shisud_99a,
+  Title                    = {{Reducing Average Number of Turbo Decoding Iterations}},
+  Author                   = {A. Shibutani and H. Suda and F. Adachi},
+  Journal                  = {Electronic Letters},
+  Year                     = {1999},
+
+  Month                    = apr,
+  Number                   = {9},
+  Pages                    = {701--702},
+  Volume                   = {35},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{shitsa_12,
+  Title                    = {{O}n the {I}napproximability of {M}aximum {I}ntersection {P}roblems},
+  Author                   = {Shieh, M.Z. and Tsai, S.C. and Yang, M-C.},
+  Journal                  = {Information Processing Letters},
+  Year                     = {2012},
+  Number                   = {19},
+  Pages                    = {723--727},
+  Volume                   = {112},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-25}
+}
+
+@InProceedings{shishe_98,
+  Title                    = {{Efficient management of in-place path metric update and its implementation for Viterbi decoders}},
+  Author                   = {M. D. Shieh and M. H. Sheu and C. H. Wu and W. S. Ju},
+  Booktitle                = {{Proc. 1998 International Symposium on Circuits and Systems (ISCAS '98)}},
+  Year                     = {1998},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = jun,
+  Pages                    = {449--452},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{shizha_08,
+  Title                    = {{A}n 8.29 mm 52 m{W} {M}ulti-{M}ode {LDPC} {D}ecoder {D}esign for {M}obile {W}i{MAX} {S}ystem in 0.13 \& {CMOS} {P}rocess},
+  Author                   = {Xin-Yu Shih and Cheng-Zhou Zhan and Cheng-Hung Lin and An-Yeu Wu},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2008},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {672--683},
+  Volume                   = {43},
+
+  Doi                      = {10.1109/JSSC.2008.916606},
+  File                     = {shizha_08.pdf:shizha_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.01.27}
+}
+
+@Electronic{shi_14,
+  Title                    = {({N}obel) {P}rize {L}ecture: {S}peculative {A}sset {P}rices},
+  Author                   = {Robert J. Shiller},
+  HowPublished             = {\url{http://www.nobelprize.org/nobel_prizes/economic-sciences/laureates/2013/shiller-lecture.html}},
+  Note                     = {Last access: 05 Oct 2017},
+  Organization             = {Nobel Media AB},
+  Url                      = {{http://www.nobelprize.org/nobel_prizes/economic-sciences/laureates/2013/shiller-lecture.html}},
+  Year                     = {2014},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.05}
+}
+
+@Article{shi_13,
+  Title                    = {{C}apitalism and {F}inancial {I}nnovation},
+  Author                   = {Robert J. Shiller},
+  Journal                  = {Financial Analysts Journal},
+  Year                     = {2013},
+
+  Month                    = {Jan/Feb},
+  Number                   = {1},
+  Pages                    = {21--25},
+  Volume                   = {69},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.05},
+  Url                      = {http://www.cfapubs.org/doi/abs/10.2469/faj.v69.n1.4}
+}
+
+@InProceedings{shimyu_05,
+  Title                    = {{A Novel Metric Representation for Low-complexity Log-MAP Decoder}},
+  Author                   = {Byonghyo Shim and Myung, H.G.},
+  Booktitle                = {Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on},
+  Year                     = {2005},
+  Month                    = may,
+  Pages                    = {5830--5833Vol.6},
+
+  Doi                      = {10.1109/ISCAS.2005.1465964},
+  Owner                    = {vogt},
+  Timestamp                = {2007.02.01}
+}
+
+@Article{shisha_06,
+  Title                    = {{Energy-Efficient Soft Error-Tolerant Digital Signal Processing}},
+  Author                   = {Byonghyo Shim and Shanbhag, Naresh R.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2006},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {336--348},
+  Volume                   = {14},
+
+  File                     = {shisha_06.pdf:shisha_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{shisri_04,
+  Title                    = {{Reliable low-power digital signal processing via reduced precision redundancy}},
+  Author                   = {B. Shim and Sridhara, S. R. and Shanbhag, N. R.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2004},
+
+  Month                    = may,
+  Pages                    = {497-510},
+  Volume                   = {12},
+
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{shiheo_07,
+  Title                    = {{A Stopping Criterion for Low-Density Parity-Check Codes}},
+  Author                   = {Donghyuk Shin and Kyoungwoo Heo and Sangbong Oh and Jeongseok Ha},
+  Booktitle                = {Proc. 56th Vehicular Technology Conference (VTC Spring '07)},
+  Year                     = {2007},
+
+  Address                  = {Dublin, Ireland},
+  Month                    = apr,
+
+  File                     = {shiheo_07.pdf:shiheo_07.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{shikim_01,
+  Title                    = {{A Profile-Based Energy-Efficient Intra-Task Voltage Scheduling Algorithm for Hard Real-Time Applications}},
+  Author                   = {D. Shin and J. Kim},
+  Booktitle                = {Proc. 2001 International Symposium on Low Power Electronics and Design (ISLPED '01)},
+  Year                     = {2001},
+
+  Address                  = {Huntington Beach, California, USA},
+  Month                    = aug,
+  Pages                    = {271--274},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{shikim_01a,
+  Title                    = {{Intra Task Voltage SCheduling for Low-Energy Hard Real-Time Applications}},
+  Author                   = {D. Shin and J. Kim and S. Lee},
+  Journal                  = {IEEE Design \& Test of Computers},
+  Year                     = {2001},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {20--30},
+  Volume                   = {18},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{shikim_00,
+  Title                    = {{Turbo Decoding in a Rayleigh Fading Channel with Estimated Channel State Information}},
+  Author                   = {H. Shin and S. Kim and J. H. Lee},
+  Booktitle                = {Proc. 2000-Fall Vehicular Technology Conference (VTC '00 Fall)},
+  Year                     = {2000},
+
+  Address                  = {Boston, Massachusetts, USA},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{shipar_03,
+  Title                    = {{P}rocessor-based turbo interleaver for multiple third-generation wireless standards},
+  Author                   = {Myoung-Cheol Shin and In-Cheol Park},
+  Journal                  = {IEEE COMMUNICATIONS LETTERS},
+  Year                     = {2003},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {210--212},
+  Volume                   = {7},
+
+  Doi                      = {10.1109/LCOMM.2003.812176},
+  File                     = {shipar_03.pdf:shipar_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.09}
+}
+
+@Article{shicho_16,
+  Title                    = {{DRAM}-{L}atency {O}ptimization {I}nspired by {R}elationship between {R}ow-{A}ccess {T}ime and {R}efresh {T}iming},
+  Author                   = {W. Shin and J. Choi and J. Jang and J. Suh and Y. Moon and Y. Kwon and L. S. Kim},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2016},
+
+  Month                    = {Oct},
+  Number                   = {10},
+  Pages                    = {3027-3040},
+  Volume                   = {65},
+
+  Doi                      = {10.1109/TC.2015.2512863},
+  ISSN                     = {0018-9340},
+  Keywords                 = {DRAM chips;circuit simulation;electric charge;timing;DRAM cell capacitors;DRAM latency optimization;DRAM row-access latency;DRAM structure;DRAM vendors;NUAT-1;NUAT-2;circuit-level simulations;computing systems;electric charge variation;nonuniform access time;refresh timing;row-access time;system-level simulations;Capacitors;DRAM;Decoding;Memory management;Random access memory;Transistors;DRAM;DRAM-latency;memory controller;non-uniform access time (NUAT);refresh},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-17}
+}
+
+@InProceedings{shiyan_14,
+  Title                    = {{NUAT}: {A} non-uniform access time memory controller},
+  Author                   = {Shin, Wongyu and Yang, Jeongmin and Choi, Jungwhan and Kim, Lee-Sup},
+  Booktitle                = {2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)},
+  Year                     = {2014},
+  Organization             = {IEEE},
+  Pages                    = {464--475},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-17}
+}
+
+@InProceedings{shimoh_11,
+  Title                    = {{A} reduced routing network architecture for partial parallel {LDPC} decoders},
+  Author                   = {Houshmand Shiran-Mehr and Tinoosh Mohsenin and Bevan Baas},
+  Booktitle                = {Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on},
+  Year                     = {2011},
+  Pages                    = {2192--2196},
+
+  Doi                      = {10.1109/ACSSC.2011.6190420},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.03.25},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6190420}
+}
+
+@InProceedings{shikis_02,
+  Title                    = {{M}odeling the effect of technology trends on the soft error rate of combinational logic},
+  Author                   = {Shivakumar, P. and Kistler, M. and Keckler, S.W. and Burger, D. and Alvisi, L.},
+  Booktitle                = {Dependable Systems and Networks, 2002. Proceedings. International Conference on},
+  Year                     = {2002},
+  Month                    = jun,
+  Pages                    = {389--398},
+
+  Doi                      = {10.1109/DSN.2002.1028924},
+  File                     = {shikis_02.pdf:shikis_02.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@InProceedings{shrcha_11,
+  Title                    = {{A} 6.6p{J}/bit/iter radix-16 modified log-{MAP} decoder using two-stage {ACS} architecture},
+  Author                   = {Kai-Ting Shr and Yu-Cheng Chang and Chu-Yi Lin and Yuan-Hao Huang},
+  Booktitle                = {Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian},
+  Year                     = {2011},
+  Month                    = {Nov},
+  Pages                    = {313-316},
+
+  Doi                      = {10.1109/ASSCC.2011.6123575},
+  Keywords                 = {CMOS integrated circuits;channel coding;maximum likelihood decoding;turbo codes;1P9M CMOS technology;3GPP-LTE;MAP processors;WiMAX;bit rate 502 Mbit/s;channel coding technique;next-generation communication systems;power 3.32 mW;power consumption;radix-16 modified log-MAP decoder algorithm;size 90 nm;turbo code;turbo decoder;two-stage ACS architecture;Algorithm design and analysis;Bit error rate;Calculators;Decoding;Measurement;Table lookup},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@Article{shrpai_14,
+  Title                    = {{H}igh-{T}hroughput {T}urbo {D}ecoder {W}ith {P}arallel {A}rchitecture for {LTE} {W}ireless {C}ommunication {S}tandards},
+  Author                   = {R. Shrestha and R. P. Paily},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2014},
+
+  Month                    = {Sept},
+  Number                   = {9},
+  Pages                    = {2699-2710},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCSI.2014.2332266},
+  File                     = {shrpai_14.pdf:shrpai_14.pdf:PDF},
+  ISSN                     = {1549-8328},
+  Keywords                 = {3G mobile communication;CMOS integrated circuits;Long Term Evolution;VLSI;integrated circuit design;maximum likelihood decoding;telecommunication standards;turbo codes;3GPP-LTE standard;90 nm CMOS technology;ACSU;LBCJR algorithm;LTE wireless communication standards;LTE-Advanced standard;VLSI design aspect;add-compare-select-unit;backward state metric computation;critical path delay reduction;high-speed maximum a posteriori probability decoders;high-throughput turbo decoder;iteration energy-efficiency;logarithmic-Bahl-Cocke-Jelinek-Raviv algorithm;parallel MAP decoders;parallel architecture;peak data-rates;state metric normalization technique;ungrouped backward recursion technique;Computer architecture;Decoding;Delays;Standards;Throughput;Wireless communication;3GPP-LTE/LTE-advanced;Bahl–Cocke–Jelinek–Raviv (BCJR) algorithm;maximum a posteriori (MAP) decoder;parallel turbo decoding and VLSI design;turbo codes;wireless communications},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{shukhu_17,
+  Title                    = {{S}oftware and {H}ardware {C}ode {G}eneration for {P}redictive {C}ontrol {U}sing {S}plitting {M}ethods},
+  Author                   = {Harsh A. Shukla and Bulat Khusainov and Eric C. Kerrigan and Colin N. Jones},
+  Journal                  = {IFAC-PapersOnLine},
+  Year                     = {2017},
+  Note                     = {20th IFAC World Congress},
+  Number                   = {1},
+  Pages                    = {14386 - 14391},
+  Volume                   = {50},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {HETEROGENEOUS PLATFORMS; cite number in presentation [37]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {https://doi.org/10.1016/j.ifacol.2017.08.2025},
+  ISSN                     = {2405-8963},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {Model predictive, optimization-based control, Hardware-software co-design, Embedded computer architectures, Hardware-in-the-loop simulation, Splitting methods},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S2405896317326642}
+}
+
+@InProceedings{shusie_90,
+  Title                    = {{VLSI} architectures for metric normalization in the {V}iterbi algorithm},
+  Author                   = {Shung, C. B. and Siegel, P. H. and Ungerboeck, G. and Thapar, H. K.},
+  Booktitle                = {Proc. IEEE Int Communications ICC '90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conf. Record. Conf},
+  Year                     = {1990},
+  Pages                    = {1723--1728},
+
+  Doi                      = {10.1109/ICC.1990.117356},
+  File                     = {shusie_90.pdf:shusie_90.pdf:PDF},
+  Keywords                 = {Turbo, Convolutional},
+  Owner                    = {Gimmler},
+  Review                   = {Modulo Arithmetik für den MAP},
+  Timestamp                = {2011.02.14}
+}
+
+@InProceedings{sieshu_91,
+  Title                    = {{Exact Bounds for Viterbi Detector Path Metric Differences}},
+  Author                   = {Siegel, P.H. and Shung, C.B. and Howell, T.D. and Thapar, H.K.},
+  Booktitle                = {Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on},
+  Year                     = {1991},
+  Month                    = apr,
+  Pages                    = {1093--1096vol.2},
+
+  Doi                      = {10.1109/ICASSP.1991.150552},
+  Owner                    = {vogt},
+  Timestamp                = {2007.02.06}
+}
+
+@InProceedings{sileva_08,
+  Title                    = {{B}uilding a reliable internet core using soft error prone electronics},
+  Author                   = {Silburt, A. L. and Evans, A. and Burghelea, A. and Shi-Jie Wen and Ward, D. and Norrish, R. and Hogle, D. },
+  Booktitle                = {Proc. IEEE Int. Conf. Integrated Circuit Design and Technology and Tutorial ICICDT 2008},
+  Year                     = {2008},
+  Pages                    = {227--232},
+
+  Doi                      = {10.1109/ICICDT.2008.4567283},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{sinlee_00,
+  Title                    = {{MorphoSys: an integrated reconfigurable system for data-parallel and computationintensive applications}},
+  Author                   = {H. Singh and M.H. Lee and G. Lu and F.J. Kurdahi and N. Bagherzadeh and E.M.C. Filho},
+  Booktitle                = {IEEE Transactions on Computers (2000)},
+  Year                     = {2000},
+  Pages                    = {465--481},
+
+  Optvolume                = {49},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{sinsuj_13,
+  Title                    = {{VLSI} {I}mplementation of {P}arallel {CRC} {U}sing {P}ipelining, {U}nfolding and {R}etiming},
+  Author                   = {Singh, Sangeeta and Sujana, S and Babu, I and Latha, K},
+  Journal                  = {IOSR Journal of VLSI and Signal Processing},
+  Year                     = {2013},
+  Number                   = {5},
+  Pages                    = {66--72},
+  Volume                   = {2},
+
+  File                     = {sinsuj_13.pdf:sinsuj_13.pdf:PDF},
+  Owner                    = {StW},
+  Timestamp                = {2014.11.17}
+}
+
+@InProceedings{sinhal_08,
+  Title                    = {{F}inancial {M}onte {C}arlo {S}imulation on {A}rchitecturally {D}iverse {S}ystems},
+  Author                   = {Naveen Singla and Michael Hall and Berkley Shands and Roger D. Chamberlain},
+  Booktitle                = {Proceedings of the Workshop on High Performance Computational Finance (WHPCF) 2008},
+  Year                     = {2008},
+  Month                    = {Nov},
+  Pages                    = {1-7},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.30}
+}
+
+@InProceedings{sinsin_19,
+  Title                    = {{F}lexi{C}heck: {A}n {A}daptive {C}heckpointing {A}rchitecture for {E}nergy {H}arvesting {D}evices},
+  Author                   = {P. {Singla} and S. S. {Singh} and S. R. {Sarangi}},
+  Booktitle                = {2019 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2019},
+  Month                    = {March},
+  Pages                    = {546-551},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8715130},
+  Ccr_keywords             = {CP, optimal CP positioning},
+  Ccr_relevance            = {medium},
+  Ccr_topic                = {ATC, PCP},
+  Doi                      = {10.23919/DATE.2019.8715130},
+  ISSN                     = {1558-1101},
+  Keywords                 = {TCS},
+  Keywords_original        = {checkpointing;energy harvesting;greedy algorithms;linear programming;power engineering computing;adaptive checkpointing architecture;energy harvesting devices;solar energy;vibration energy;energy consumption;energy production;processor;constant energy source;checkpointing algorithm;ambient energy;Checkpointing;Silicon;Hardware;Energy harvesting;Mathematical model;Computer architecture;Vibrations},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27}
+}
+
+@InProceedings{sincha_01,
+  Title                    = {{Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces}},
+  Author                   = {A. Sinha and A. P. Chandrakasan},
+  Booktitle                = {Proc. 2001 International Conference on VLSI Design},
+  Year                     = {2001},
+
+  Address                  = {Bangalore, India},
+  Month                    = jan,
+  Pages                    = {221--226},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{sir_16,
+  Title                    = {{F}in{T}ech {I}nnovation: {F}rom {R}obo-{A}dvisors to {G}oal {B}ased {I}nvesting and {G}amification},
+  Author                   = {Paolo Sironi},
+  Publisher                = {Wiley},
+  Year                     = {2016},
+
+  Address                  = {Chichester, West Sussex, UK},
+  Series                   = {The Wiley finance series},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.29}
+}
+
+@InProceedings{sitfit_06,
+  Title                    = {{A} {N}ovel {S}oft-{O}utput {L}ayered {O}rthogonal {L}attice {D}etector for {M}ultiple {A}ntenna {C}ommunications},
+  Author                   = {Siti, M. and Fitz, M.P.},
+  Booktitle                = {Communications, 2006. ICC '06. IEEE International Conference on},
+  Year                     = {2006},
+  Pages                    = {1686-1691},
+  Volume                   = {4},
+
+  Doi                      = {10.1109/ICC.2006.254962},
+  File                     = {sitfit_06.pdf:sitfit_06.pdf:PDF},
+  ISSN                     = {8164-9547},
+  Keywords                 = {Decoding;Detectors;Integrated circuit noise;Lattices;MIMO;OFDM;Signal to noise ratio;Testing;Transmitting antennas;Very large scale integration},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.03}
+}
+
+@InProceedings{siwfit_02,
+  Title                    = {{I}mproved high-rate space-time codes via orthogonality and set partitioning},
+  Author                   = {Siwamogsatham, S. and Fitz, M. P.},
+  Booktitle                = {Proc. WCNC2002 Wireless Communications and Networking Conference 2002 IEEE},
+  Year                     = {2002},
+  Pages                    = {264--270 vol.1},
+  Volume                   = {1},
+
+  Abstract                 = {In this paper, we propose a new technique for constructing improved high-rate space-time codes. The proposed code construction is based on a concatenation of an orthogonal spacetime block code and an outer M-TCM encoder. However, unlike the existing STB-MTCM schemes which are rate-lossy, the proposed construction yields higher-rate space-time codes by expanding the cardinality of the orthogonal space-time block code before concatenating with an outer M-TCM encoder. An advantage of the proposed construction is that the standard techniques for designing a good TCM code, such as the classic set partitioning concept, can be adopted to realize the STB-MTCM designs with large coding gains. We present several design examples of improved full-rate space-time codes for a system with 2 transmit antennas. Simulation results show that the new space-time codes considerably outperform the existing ST-TCM designs. For example, the new 4-state 2-bits/symbol QPSK space-time code performs even better than the original 32-state design, while performance of the new 32-state QPSK code is only 1.5 dB away from the outage probability limit. Moreover, decoding complexity of the proposed M-TCM construction is made reasonably low by exploiting signal orthogonality.},
+  Doi                      = {10.1109/WCNC.2002.993504},
+  File                     = {siwfit_02.pdf:siwfit_02.pdf:PDF},
+  Grade                    = {0},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@InProceedings{siwfit_02a,
+  Title                    = {{I}mproved high-rate space-time codes via concatenation of expanded orthogonal block code and {M}-{TCM}},
+  Author                   = {Siwamogsatham, S. and Fitz, M. P.},
+  Booktitle                = {Proc. IEEE International Conference on Communications ICC 2002},
+  Year                     = {2002},
+  Pages                    = {636--640},
+  Volume                   = {1},
+
+  Abstract                 = {In this paper, we propose a new technique for designing an improved high-rate space-time code. The proposed code construction is based on a typical concatenation of a space-time block code and an outer TCM/MTCM encoder. However, unlike the existing STB-MTCM schemes which are rate-lossy, the proposed technique produces higher-rate space-time codes by expanding the cardinality of the available orthogonal space-time signal points before concatenating with an outer M-TCM encoder. The set partitioning concept is then employed to realize large coding gains. Here, we present design examples for the 2-transmitter and 3-transmitter cases. The new space-time codes considerably outperform the existing designs. Furthermore, signal orthogonality is exploited to keep decoding complexity of the proposed construction relatively low},
+  Doi                      = {10.1109/ICC.2002.996930},
+  File                     = {siwfit_02a.pdf:siwfit_02a.pdf:PDF},
+  Grade                    = {0},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@Article{skl_97,
+  Title                    = {{A Primer on Turbo Code Concepts}},
+  Author                   = {B. Sklar},
+  Journal                  = {IEEE Communications Magazine},
+  Year                     = {1997},
+
+  Month                    = dec,
+  Pages                    = {94--102},
+  Volume                   = {35},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{sla_10,
+  Title                    = {{S}oft errors --- {P}ast history and recent discoveries},
+  Author                   = {Slayman, Charles},
+  Booktitle                = {Proc. IEEE Int. Integrated Reliability Workshop Final Report (IRW)},
+  Year                     = {2010},
+  Pages                    = {25--30},
+
+  Doi                      = {10.1109/IIRW.2010.5706479},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{slomad_14,
+  Title                    = {{C}omplex {N}etwork {A}nalysis {U}sing {P}arallel {A}pproximate {M}otif {C}ounting},
+  Author                   = {Slota, G.M. and Madduri, K.},
+  Booktitle                = {Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium},
+  Year                     = {2014},
+  Month                    = {May},
+  Pages                    = {405-414},
+
+  Abstract                 = {Subgraph counting forms the basis of many complex network analysis metrics, including motif and anti-motif finding, relative graph let frequency distance, and graph let degree distribution agreements. Determining exact subgraph counts is computationally very expensive. In recent work, we present FASCIA, a shared-memory parallel algorithm and implementation for approximate subgraph counting. FASCIA uses a dynamic programming-based approach and is significantly faster than exhaustive enumeration, while generating high-quality approximations of subgraph counts. However, the memory usage of the dynamic programming step prohibits us from applying FASCIA to very large graphs. In this paper, we introduce a distributed-memory parallelization of FASCIA by partitioning the graph and the dynamic programming table. We discuss a new collective communication scheme to make the dynamic programming step memory-efficient. These optimizations enable scaling to much larger networks than before. We also present a simple parallelization strategy for distributed subgraph counting on smaller networks. The new additions let us use subgraph counts as graph signatures for a large network collection, and we analyze this collection using various subgraph count-based graph analytics.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/IPDPS.2014.50},
+  ISSN                     = {1530-2075},
+  Keywords                 = {graphs},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.28}
+}
+
+@InProceedings{smisch_05,
+  Title                    = {{O}verview of the 4{S} {P}roject},
+  Author                   = {Smit, G. and Schuler, E. and Becker, J. and Quevremont, J. and Brugger, W.},
+  Booktitle                = {System-on-Chip, 2005. Proceedings. 2005 International Symposium on},
+  Year                     = {2005},
+  Month                    = {Nov},
+  Pages                    = {70-73},
+
+  Doi                      = {10.1109/ISSOC.2005.1595647},
+  Keywords                 = {digital audio broadcasting;field programmable gate arrays;system-on-chip;video coding;4S Project;EU-FP6;ambient devices;dynamic reconfiguration;heterogeneous wireless networks;product development;reconfigurable ambient systems;reconfigurable systems;smart chips;smart surroundings;Communication standards;Computer architecture;Energy efficiency;MPEG 4 Standard;Personal digital assistants;Product development;Reconfigurable architectures;Standards development;Tiles;Wireless networks;Coarse-grain reconfigurable;DRM;MPEG-4;SoC;ambient systems;low power},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@InProceedings{smismi_02,
+  Title                    = {{Influences of RAKE Receiver/Turbo Decoder parameters on energy consumption and quality Energy }},
+  Author                   = {L. T. Smit and G. J. M. Smit and P. J. M. Havinga and J. L. Hurink and H. Broersma},
+  Booktitle                = {Proc. International Conference on Third Generation Wireless and Beyond, May 2002)},
+  Year                     = {2002},
+
+  Address                  = {San Francisco, CA, USA},
+  Month                    = may,
+  Pages                    = {227--235},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{smigon_12,
+  Title                    = {{GPU} {A}cceleration of the {M}atrix-{F}ree {I}nterior {P}oint {M}ethod},
+  Author                   = {Smith, Edmund and Gondzio, Jacek and Hall, Julian},
+  Booktitle                = {Parallel Processing and Applied Mathematics},
+  Year                     = {2012},
+
+  Address                  = {Berlin, Heidelberg},
+  Editor                   = {Wyrzykowski, Roman and Dongarra, Jack and Karczewski, Konrad and Wa{\'{s}}niewski, Jerzy},
+  Pages                    = {681--689},
+  Publisher                = {Springer Berlin Heidelberg},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{GPU} PLATFORM; cite number in presentation [26]},
+  Ccr_topic                = {NetControl Paper},
+  ISBN                     = {978-3-642-31464-3},
+  Keywords                 = {MPC_FPGA},
+  Owner                    = {CCR}
+}
+
+@Book{smi_97,
+  Title                    = {{Application-Specific Integrated Circuits}},
+  Author                   = {M. J. S. Smith},
+  Publisher                = {Addison-Wesley},
+  Year                     = {1997},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{smoweh_96,
+  Title                    = {{Einsatz von Hardwarebeschreibungssprachen beim Entwurf komplexer Multimedia-Bausteine}},
+  Author                   = {M. Smola and N. Wehn},
+  Booktitle                = {2. GI/ITG/GME-Workshop Hardwarebeschreibungssprachen und Modellierungsparadigmen (eingeladener Vortrag)},
+  Year                     = {1996},
+  Month                    = feb,
+  Pages                    = {72--80},
+  Publisher                = {Verlag Shaker},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{sny_91,
+  Title                    = {{R}educed lists of error patterns for maximum likelihood soft decoding},
+  Author                   = {J. Snyders},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1991},
+
+  Month                    = {Jul},
+  Number                   = {4},
+  Pages                    = {1194-1200},
+  Volume                   = {37},
+
+  Doi                      = {10.1109/18.86973},
+  ISSN                     = {0018-9448},
+  Keywords                 = {coding errors;decoding;error patterns;maximum likelihood soft decoding;predetermined lists;survivors;Block codes;Computational complexity;Hamming weight;Information theory;Lattices;Maximum likelihood decoding;Maximum likelihood detection;Parallel processing;Sections;Sorting}
+}
+
+@Book{soipes_11,
+  Title                    = {{M}athematical {M}orphology and {I}ts {A}pplications to {I}mage and {S}ignal {P}rocessing: 10th {I}nternational {S}ymposium, {ISMM} 2011, {V}erbania-{I}ntra, {I}taly, {J}uly 6-8, 2011, {P}roceedings},
+  Author                   = {Soille, P. and Pesaresi, M. and Ouzounis, G.},
+  Publisher                = {Springer},
+  Year                     = {2011},
+  Series                   = {LNCS sublibrary. SL 6, Image processing, computer vision, pattern recognition, and graphics},
+
+  ISBN                     = {9783642215681},
+  Lccn                     = {2011928710},
+  Owner                    = {Sadri},
+  Timestamp                = {2014.07.14},
+  Url                      = {http://books.google.de/books?id=\_YLGvJVjDzsC}
+}
+
+@InProceedings{sombau_02,
+  Title                    = {{A}nalysis and modeling of multiple-input multiple-output ({MIMO}) radio channel based on outdoor measurements conducted at 2.5 {GH}z for fixed {BWA} applications},
+  Author                   = {Soma, P. and Baum, D. S. and Erceg, V. and Krishnamoorthy, R. and Paulraj, A. J.},
+  Booktitle                = {Proc. IEEE International Conference on Communications ICC 2002},
+  Year                     = {2002},
+  Pages                    = {272--276},
+  Volume                   = {1},
+
+  Abstract                 = {This paper summarizes our 2&times;2 multiple-input multiple-output (MIMO) fixed wireless outdoor propagation measurements at 2.48 GHz conducted in the suburban residential areas of San Jose, California. We report on various channel characteristics such as path loss, Ricean K-factor, cross-polarization-discrimination (XPD) and channel capacity. We present simple models for these characteristics, focusing on excess loss dependency and, derived from that, the variation with distance. Also, we introduce an idea for a generalized MIMO channel model based on these modeled channel characteristics and the correlation properties between them. Path loss results show that blockage due to buildings or foliage causes an excess loss of 35.45 dB compared to free space propagation at a distance of 1 km. The narrowband K-factor distribution matches previously reported results. The XPD of the total received signal varies from -10 to 15 dB at various locations. The K-factor and XPD were found to be very much dependent on excess loss due to blockage conditions at various distances},
+  Doi                      = {10.1109/ICC.2002.996859},
+  File                     = {sombau_02.pdf:sombau_02.pdf:PDF},
+  Grade                    = {0},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@InProceedings{somwat_09,
+  Title                    = {{G}radient clock synchronization in wireless sensor networks},
+  Author                   = {Sommer, P. and Wattenhofer, R.},
+  Booktitle                = {Information Processing in Sensor Networks, 2009. IPSN 2009. International Conference on},
+  Year                     = {2009},
+  Month                    = {April},
+  Pages                    = {37-48},
+
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {5211944},
+  Ccr_topic                = {BLE_Sync},
+  Keywords                 = {BLE},
+  Keywords_original        = {clocks;gradient methods;protocols;synchronisation;telecommunication network topology;trees (mathematics);wireless sensor networks;GTSP;broadcast synchronization;gradient clock synchronization message;gradient time synchronization protocol;logical clock;tree topology;wireless sensor network;Acoustic sensors;Clocks;Computer networks;Hardware;Laboratories;Network topology;Protocols;Synchronization;Testing;Wireless sensor networks},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30}
+}
+
+@Article{soncru_03,
+  Title                    = {{R}educed-complexity decoding of {Q}-ary {LDPC} codes for magnetic recording},
+  Author                   = {Hongxin Song and Cruz, J. R.},
+  Journal                  = {IEEE Transactions on Magnetics},
+  Year                     = {2003},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {1081--1087},
+  Volume                   = {39},
+
+  Doi                      = {10.1109/TMAG.2003.808600},
+  File                     = {soncru_03.pdf:soncru_03.pdf:PDF},
+  Owner                    = {lehnigk},
+  Part                     = {2},
+  Timestamp                = {2009.08.21}
+}
+
+@Article{sonyu_02,
+  Title                    = {10-and 40-{G}b/s forward error correction devices for optical communications},
+  Author                   = {Song, LL and Yu, ML and Shaffer, MS},
+  Journal                  = {Ieee Journal of Solid-State Circuits},
+  Year                     = {2002},
+  Pages                    = {1565-1573},
+  Volume                   = {37},
+
+  Abstract                 = {Two standard forward error correction (FEC) devices for 10- and 40-Gb/s optical systems are presented. The first FEC device includes RS(255, 239) FEC, BCH(4359,4320) FEC, and standard compliant framing and performance monitoring functions. It can support a single 10-Gb/s channel or four asynchronous 2.5-Gb/s channels. The second FEC device implements RS(255,239) FEC at a data rate of 40 Gb/s. This paper presents the key ideas applied to the design of Reed-Solomon (RS) decoder blocks in these devices, especially those for achieving high throughput and reducing complexity and power. Implemented in a 1.5-V, 0.16-mum CMOS technology, the RS decoder in the 10-Gb/s, quad, 2.5-Gb/s device has a core gate count of 424 K and consumes 343 mW, the 40-Gb/s RS decoder has a core gate count of 364 K and an estimated power consumption of 360 mW. The 40-Gb/s RS FEC is the highest throughput implementation reported to date.},
+  Address                  = {345 E 47TH ST, NEW YORK, NY 10017-2394 USA},
+  Cds_grade                = {4},
+  Cds_keywords             = {forward error correction; low-power; optical communication systems; parallel processing; Reed-Solomon codes; RS; BCH; Euclidean Algorithm; Channel Code, VLSI},
+  Cds_read                 = {2008-07},
+  Date                     = {NOV 2002},
+  Date-added               = {2008-07-03 14:17:57 +0200},
+  Date-modified            = {2008-07-03 14:46:57 +0200},
+  Doi                      = {DOI 10.1109/JSSC.2002.803931},
+  File                     = {sonyu_02.pdf:sonyu_02.pdf:PDF},
+  Owner                    = {CdS},
+  Publisher                = {IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC},
+  Timescited               = {7},
+  Timestamp                = {2008.12.10},
+  Url                      = {http://dx.doi.org/10.1109/JSSC.2002.803931}
+}
+
+@InProceedings{sonhui_05,
+  Title                    = {{T}he implementation of turbo decoder on {DSP} in {W}-{CDMA} system},
+  Author                   = {Yuansheng Song and Gongyuan Liu and Huiyang},
+  Booktitle                = {Wireless Communications, Networking and Mobile Computing, 2005. Proceedings. 2005 International Conference on},
+  Year                     = {2005},
+  Month                    = {sept.},
+  Pages                    = { 1281 - 1283},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/WCNM.2005.1544288},
+  Keywords                 = {Concatenated codes;Convolutional codes;Decoding;Digital signalprocessing;Hydroelectric power generation;Instruments;Mobilecomputing;Multiaccess communication;Turbo codes;Water resources; 3Gmobile communication; code division multiple access; turbo codes;3G mobile systems; DSP; W-CDMA system; million instructions per second;turbo decoder;}
+}
+
+@InProceedings{sonsam_16,
+  Title                    = {{S}ingle-tier virtual queuing: {A}n efficacious memory controller architecture for {MPS}o{C}s with multiple realtime cores},
+  Author                   = {Y. Song and K. Samadi and B. Lin},
+  Booktitle                = {2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)},
+  Year                     = {2016},
+  Month                    = {June},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1145/2897937.2898093},
+  Keywords                 = {memory architecture;microprocessor chips;multiprocessing systems;performance evaluation;processor scheduling;queueing theory;system-on-chip;CPU;QoS;STVQ memory controller;efficacious memory controller architecture;heterogeneous MPSoC;memory interference;multiple realtime cores;scheduling policies;single-tier transaction queues;single-tier virtual queuing;system performance;two-tier queuing system;Bandwidth;Delays;Graphics processing units;Memory management;Quality of service;Random access memory;Scheduling},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-02}
+}
+
+@Article{sotcha_02,
+  Title                    = {{A Bus Energy Model for Deep Submicron Technology}},
+  Author                   = {Sotiriadis, P. P. and Chandrakasan, A. P.},
+  Journal                  = {IEEE Transactions onVery Large Scale Integration (VLSI) Systems)},
+  Year                     = {2002},
+
+  Month                    = jun,
+  Pages                    = {341--350},
+  Volume                   = {10},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Vol                      = {10}
+}
+
+@InProceedings{spamag_16,
+  Title                    = {{P}oster {A}bstract: {K}ineti{S}ee - {A} {P}erpetual {W}earable {C}amera {A}cquisition {S}ystem with a {K}inetic {H}arvester},
+  Author                   = {L. Spadaro and M. Magno and L. Benini},
+  Booktitle                = {2016 15th ACM/IEEE International Conference on Information Processing in Sensor Networks (IPSN)},
+  Year                     = {2016},
+  Month                    = {April},
+  Pages                    = {1-2},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7460706},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/IPSN.2016.7460706},
+  Keywords                 = {TCS},
+  Keywords_original        = {cameras;energy harvesting;KinetiSee;automatic quartz watch;battery;kinetic energy harvester;perpetual wearable camera acquisition system;power consumption;self-sustainable device;wearable smart object;Batteries;Cameras;Generators;Kinetic energy;Nonvolatile memory;Power demand;Wireless sensor networks},
+  Owner                    = {CCR}
+}
+
+@InProceedings{spamar_07,
+  Title                    = {{FPGA} {I}mplementations of {LDPC} over {GF}(2m) {D}ecoders},
+  Author                   = {Spagnol, Christian and Marnane, William and Popovici, Emanuel},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems},
+  Year                     = {2007},
+  Month                    = oct,
+  Pages                    = {273--278},
+
+  Doi                      = {10.1109/SIPS.2007.4387557},
+  Owner                    = {lehnigk},
+  Timestamp                = {2009.09.28}
+}
+
+@InProceedings{spamar_05,
+  Title                    = {{Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder}},
+  Author                   = {C. Spagnol and W. Marnane and E. Popovici},
+  Booktitle                = {Proc. European Conference on Circuit Theory and Design 2005},
+  Year                     = {2005},
+  Month                    = aug,
+  Pages                    = {289--292},
+  Volume                   = {1},
+
+  File                     = {spamar_05.pdf:spamar_05.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{spa_91,
+  Title                    = {{An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures}},
+  Author                   = {J. Sparsø and Jørgensen, H. N. and E. Paaske and S. Pedersen and T. Rübner-Petersen},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {1991},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {90--97},
+  Volume                   = {26},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{spezor_04,
+  Title                    = {{Scalable and area efficient concurrent interleaver for high throughput turbo-decoders}},
+  Author                   = {F. Speziali and J. Zory},
+  Booktitle                = {Euromicro Symposium on Digital System Design, 2004. DSD 2004},
+  Year                     = {2004},
+  Month                    = sep,
+  Pages                    = {334--341},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{BTspitz12,
+  Title                    = {{A}n evaluation of similarity measures for the projection of bipartite networks},
+  Author                   = {Andreas Spitz},
+  School                   = {Heidelberg University, Supervisor: G. Reinelt, K. A. Zweig},
+  Year                     = {2012},
+  Month                    = Sep,
+  Type                     = {Bachelor Thesis},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.23}
+}
+
+@Article{spigim_16,
+  Title                    = {{A}ssessing {L}ow-{I}ntensity {R}elationships in {C}omplex {N}etworks},
+  Author                   = {Andreas Spitz and Anna Gimmler and Thorsten Stoeck and Zweig, Katharina Anna and Emőke-Ágnes Horvát},
+  Journal                  = {PLOS ONE},
+  Year                     = {2016},
+
+  Month                    = apr,
+  Note                     = {e0152536},
+  Number                   = {4},
+  Volume                   = {11},
+
+  Abstract                 = {Many large network data sets are noisy and contain links representing low-intensity relationships that are difficult to differentiate from random interactions. This is especially relevant for high-throughput data from systems biology, large-scale ecological data, but also for Web 2.0 data on human interactions. In these networks with missing and spurious links, it is possible to refine the data based on the principle of structural similarity, which assesses the shared neighborhood of two nodes. By using similarity measures to globally rank all possible links and choosing the top-ranked pairs, true links can be validated, missing links inferred, and spurious observations removed. While many similarity measures have been proposed to this end, there is no general consensus on which one to use. In this article, we first contribute a set of benchmarks for complex networks from three different settings (e-commerce, systems biology, and social networks) and thus enable a quantitative performance analysis of classic node similarity measures. Based on this, we then propose a new methodology for link assessment called z* that assesses the statistical significance of the number of their common neighbors by comparison with the expected value in a suitably chosen random graph model and which is a consistently top-performing algorithm for all benchmarks. In addition to a global ranking of links, we also use this method to identify the most similar neighbors of each single node in a local ranking, thereby showing the versatility of the method in two distinct scenarios and augmenting its applicability. Finally, we perform an exploratory analysis on an oceanographic plankton data set and find that the distribution of microbes follows similar biogeographic rules as those of macroorganisms, a result that rejects the global dispersal hypothesis for microbes.},
+  Cds_keywords             = {Link Assessment},
+  Doi                      = {10.1371/journal.pone.0152536},
+  File                     = {spigim_16.pdf:spigim_16.pdf:PDF},
+  Owner                    = {CDS},
+  Timestamp                = {2016-12-14},
+  Url                      = {http://dx.doi.org/10.1371/journal.pone.0152536}
+}
+
+@Article{spr_01,
+  Title                    = {{A}utomatic generation of parallel {CRC} circuits},
+  Author                   = {M. Sprachmann},
+  Journal                  = {IEEE Design Test of Computers},
+  Year                     = {2001},
+
+  Month                    = {May},
+  Number                   = {3},
+  Pages                    = {108-114},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/54.922807},
+  ISSN                     = {0740-7475},
+  Keywords                 = {data communication;error detection;hardware description languages;logic design;automatic generation;generator polynomial;generic VHDL description;multiple data bits;parallel CRC circuits;Automatic logic units;Circuit synthesis;Circuit testing;Cyclic redundancy check;Decoding;Encoding;Logic circuits;Parallel processing;Polynomials;System testing},
+  Owner                    = {StW},
+  Timestamp                = {2016.05.23}
+}
+
+@InProceedings{spr_97,
+  Title                    = {{High Level Power Analysis and Optimization}},
+  Author                   = {J. Sproch},
+  Booktitle                = {Proc. 1997 International Symposium on Low Power Electronics and Design (ISLPED '97)},
+  Year                     = {1997},
+
+  Address                  = {Monterey, California, USA},
+  Month                    = aug,
+  Note                     = {Tutorial},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{srivin_10,
+  Title                    = {3{D}-{ICE}: {F}ast compact transient thermal modeling for 3{D} {IC}s with inter-tier liquid cooling},
+  Author                   = {Sridhar, A. and Vincenzi, A. and Ruggiero, M. and Brunschwiler, Thomas and Atienza, D.},
+  Booktitle                = {Proc. of ICCAD 2010},
+  Year                     = {2010},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.20}
+}
+
+@Article{srimis_16,
+  Title                    = {{C}heepsync: a time synchronization service for resource constrained bluetooth le advertisers},
+  Author                   = {Sridhar, S. and Misra, P. and Gill, G.S. and Warrior, J.},
+  Journal                  = {Communications Magazine, IEEE},
+  Year                     = {2016},
+
+  Month                    = {January},
+  Number                   = {1},
+  Pages                    = {136-143},
+  Volume                   = {54},
+
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7378439},
+  Ccr_keywords             = {Custom BLE stack},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1109/MCOM.2016.7378439},
+  ISSN                     = {0163-6804},
+  Keywords                 = {BLE},
+  Keywords_original        = {Bluetooth;Radio transmitters;Receivers;Smart phones;Synchronization},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30}
+}
+
+@InProceedings{srimis_15,
+  Title                    = {{C}heep{S}ync: {A} {T}ime {S}ynchronization {S}ervice for {R}esource {C}onstrained {B}luetooth {L}ow {E}nergy {A}dvertisers},
+  Author                   = {Sridhar, Sabarish and Misra, Prasant and Warrior, Jay},
+  Booktitle                = {Proceedings of the 14th International Conference on Information Processing in Sensor Networks},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {364--365},
+  Publisher                = {ACM},
+  Series                   = {IPSN '15},
+
+  Acmid                    = {2742925},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Sridhar:2015:CTS:2737095.2742925},
+  Ccr_keywords             = {Custom BLE stack},
+  Ccr_topic                = {BLE_Sync},
+  Doi                      = {10.1145/2737095.2742925},
+  ISBN                     = {978-1-4503-3475-4},
+  Keywords                 = {BLE},
+  Keywords_original        = {Android smartphones, bluetooth low energy, clock drift, time synchronization},
+  Location                 = {Seattle, Washington},
+  Numpages                 = {2},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30},
+  Url                      = {http://doi.acm.org/10.1145/2737095.2742925}
+}
+
+@Article{srimis_15a,
+  Title                    = {{C}heep{S}ync: {A} {T}ime {S}ynchronization {S}ervice for {R}esource {C}onstrained
+ {B}luetooth {L}ow {E}nergy {A}dvertisers},
+  Author                   = {Sabarish Sridhar and
+ Prasant Misra and
+ Jay Warrior},
+  Journal                  = {CoRR},
+  Year                     = {2015},
+  Volume                   = {abs/1501.06479},
+
+  Bibsource                = {dblp computer science bibliography, http://dblp.org},
+  Biburl                   = {http://dblp.uni-trier.de/rec/bib/journals/corr/SridharMW15},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {DBLP:journals/corr/SridharMW15},
+  Ccr_keywords             = {Custom BLE stack},
+  Ccr_topic                = {BLE_Sync},
+  Keywords                 = {BLE},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-30},
+  Url                      = {http://arxiv.org/abs/1501.06479}
+}
+
+@Article{srisha_07,
+  Title                    = {{Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes}},
+  Author                   = {Sridhara, Srinivasa R. and Shanbhag, Naresh R.},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems},
+  Year                     = {2007},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {977--982},
+  Volume                   = {26},
+
+  File                     = {srisha_07.pdf:srisha_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.30}
+}
+
+@Article{srisha_05,
+  Title                    = {{Coding for System-on-Chip Networks: A Unified Framework}},
+  Author                   = {Sridhara, Srinivasa R. and Shanbhag, Naresh R.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2005},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {655--667},
+  Volume                   = {13},
+
+  File                     = {srisha_05.pdf:srisha_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.05.04}
+}
+
+@InProceedings{srijr._02,
+  Title                    = {{A Construction for Low Density Parity Check Convolutional Codes Based on Quasi-Cyclic Block Codes}},
+  Author                   = {A. Sridharan and D.J. Costello Jr. and D. Sridhara and T.E. Fuja and R.M. Tanner},
+  Booktitle                = {Proc. 2002 IEEE International Symposium on Information Theory (ISIT)},
+  Year                     = {2002},
+
+  Address                  = {Lausanne,Switzerland},
+  Month                    = jul,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{sricoo_12,
+  Title                    = {{FPGA}-based {R}econfigurable {C}omputing for {P}ricing {M}ulti-asset {B}arrier {O}ptions},
+  Author                   = {Rahul Sridharan and Gregg Cooke and Kenneth Hill and Herman Lam and Alan George},
+  Journal                  = {Proceedings of Symposium on Application Accelerators in High-Performance Computing (SAAHPC)},
+  Year                     = {2012},
+
+  Cds_grade                = {0},
+  Cds_review               = {cites schsch_12},
+  File                     = {sricoo_12.pdf:sricoo_12.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2015-05-19}
+}
+
+@Article{srideb_15,
+  Title                    = {{M}emory {E}rrors in {M}odern {S}ystems: {T}he {G}ood, {T}he {B}ad, and {T}he {U}gly},
+  Author                   = {Sridharan, Vilas and DeBardeleben, Nathan and Blanchard, Sean and Ferreira, Kurt B. and Stearley, Jon and Shalf, John and Gurumurthi, Sudhanva},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {2015},
+
+  Month                    = mar,
+  Number                   = {1},
+  Pages                    = {297--310},
+  Volume                   = {43},
+
+  Acmid                    = {2694348},
+  Address                  = {New York, NY, USA},
+  Doi                      = {10.1145/2786763.2694348},
+  ISSN                     = {0163-5964},
+  Issue_date               = {March 2015},
+  Keywords                 = {field studies, large-scale systems, reliability},
+  Numpages                 = {14},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2018-05-03},
+  Url                      = {http://doi.acm.org/10.1145/2786763.2694348}
+}
+
+@InProceedings{srilib_12,
+  Title                    = {{A} study of {DRAM} failures in the field},
+  Author                   = {V. Sridharan and D. Liberty},
+  Booktitle                = {High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for},
+  Year                     = {2012},
+  Month                    = {Nov},
+  Pages                    = {1-11},
+
+  Doi                      = {10.1109/SC.2012.13},
+  ISSN                     = {2167-4329},
+  Keywords                 = {DRAM chips;error correction codes;performance evaluation;system recovery;DRAM array;DRAM devices;DRAM errors;DRAM failures;DRAM subsystems;ECC;board level circuitry;dynamic random access memory;error-correcting codes;hardware scrubber;high-performance computing cluster;memory storage;node failure rate;shared internal circuitry;Circuit faults;Error analysis;Error correction codes;Hardware;Random access memory;Reliability;Transient analysis;DRAM;hard error;memory;reliability;single-event upset;soft error},
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-03}
+}
+
+@Article{srimas_03,
+  Title                    = {{T}esting {P}arallel {R}andom {N}umber {G}enerators},
+  Author                   = {Ashok Srinivasan and Michael Mascagni and David Ceperley},
+  Journal                  = {Parallel Computing},
+  Year                     = {2003},
+  Number                   = {1},
+  Pages                    = {69--94},
+  Volume                   = {29},
+
+  Abstract                 = {Monte Carlo computations are considered easy to parallelize. However, the results can be adversely affected by defects in the parallel pseudorandom number generator used. A parallel pseudorandom number generator must be tested for two types of correlations––(i) intra-stream correlation, as for any sequential generator, and (ii) inter-stream correlation for correlations between random number streams on different processes. Since bounds on these correlations are difficult to prove mathematically, large and thorough empirical tests are necessary. Many of the popular pseudorandom number generators in use today were tested when computational power was much lower, and hence they were evaluated with much smaller test sizes. This paper describes several tests of pseudorandom number generators, both statistical and application-based. We show defects in several popular generators. We describe the implementation of these tests in the \{SPRNG\} [ACM Trans. Math. Software 26 (2000) 436; SPRNG––scalable parallel random number generators. \{SPRNG\} 1.0––http://www.ncsa.uiuc.edu/Apps/SPRNG; \{SPRNG\} 2.0––http://sprng.cs.fsu.edu] test suite and also present results for the tests conducted on the \{SPRNG\} generators. These generators have passed some of the largest empirical random number tests.},
+  Cds_grade                = {3},
+  Cds_keywords             = {test suite, RNG, test},
+  Cds_read                 = {2013-12-16},
+  Cds_review               = {basic approaches how parallel RNGs can be tested, compact summary of available tests, some LCG results},
+  Doi                      = {http://dx.doi.org/10.1016/S0167-8191(02)00163-1},
+  File                     = {srimas_03.pdf:srimas_03.pdf:PDF},
+  ISSN                     = {0167-8191},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.16},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S0167819102001631}
+}
+
+@InProceedings{sriadv_04,
+  Title                    = {{T}he case for lifetime reliability-aware microprocessors},
+  Author                   = {Srinivasan, J. and Adve, S. V. and Bose, P. and Rivers, J. A.},
+  Booktitle                = {Proc. 31st Annual International Symposium on Computer Architecture},
+  Year                     = {2004},
+  Month                    = jun,
+  Pages                    = {276--287},
+
+  Doi                      = {10.1109/ISCA.2004.1310781},
+  File                     = {sriadv_04.pdf:sriadv_04.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.04}
+}
+
+@InProceedings{sriadv_04a,
+  Title                    = {{T}he impact of technology scaling on lifetime reliability},
+  Author                   = {Srinivasan, J. and Adve, S. V. and Bose, P. and Rivers, J. A. },
+  Booktitle                = {Proc. International Conference on Dependable Systems and Networks},
+  Year                     = {2004},
+  Month                    = jun # {--} # jul,
+  Pages                    = {177--186},
+
+  Doi                      = {10.1109/DSN.2004.1311888},
+  File                     = {sriadv_04a.pdf:sriadv_04a.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.04}
+}
+
+@InProceedings{srikan_04,
+  Title                    = {{F}lashback: {A} lightweight extension for rollback and deterministic replay for software debugging},
+  Author                   = {Srinivasan, Sudarshan M and Kandula, Srikanth and Andrews, Christopher R and Zhou, Yuanyuan and others},
+  Booktitle                = {USENIX Annual Technical Conference, General Track},
+  Year                     = {2004},
+  Organization             = {Boston, MA, USA},
+  Pages                    = {29--44},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-08}
+}
+
+@Article{srikea_09,
+  Title                    = {{A}n {FPGA} {I}mplementation of a {P}arallelized {MT}19937 {U}niform {R}andom {N}umber {G}enerator},
+  Author                   = {Vinay Sriram and David Kearney},
+  Journal                  = {EURASIP Journal on Embedded Systems},
+  Year                     = {2009},
+  Number                   = {1},
+  Pages                    = {507426},
+  Volume                   = {2009},
+
+  Abstract                 = {Recent times have witnessed an increase in use of high-performance reconfigurable computing for accelerating large-scale simulations. A characteristic of such simulations, like infrared (IR) scene simulation, is the use of large quantities of uncorrelated random numbers. It is therefore of interest to have a fast uniform random number generator implemented in reconfigurable hardware. While there have been previous attempts to accelerate the MT19937 pseudouniform random number generator using FPGAs we believe that we can substantially improve the previous implementations to develop a higher throughput and more area-time efficient design. Due to the potential for parallel implementation of random numbers generators, designs that have both a small area footprint and high throughput are to be preferred to ones that have the high throughput but with significant extra area requirements. In this paper, we first present a single port design and then present an enhanced 624 port hardware implementation of the MT19937 algorithm. The 624 port hardware implementation when implemented on a Xilinx XC2VP70-6 FPGA chip has a throughput of 32bit random numbers per second which is more than 17x that of the previously best published uniform random number generator. Furthermore it has the lowest area time metric of all the currently published FPGA-based pseudouniform random number generators.},
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generator, FPGA},
+  Doi                      = {10.1155/2009/507426},
+  File                     = {srikea_09.pdf:srikea_09.pdf:PDF},
+  ISSN                     = {1687-3963},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.14},
+  Url                      = {http://jes.eurasipjournals.com/content/2009/1/507426}
+}
+
+@InProceedings{srikea_06,
+  Title                    = {{A}n {A}rea {T}ime {E}fficient {F}ield {P}rogrammable {M}ersenne {T}wister {U}niform {R}andom {N}umber {G}enerator},
+  Author                   = {Vinay Sriram and David Kearney},
+  Booktitle                = {Proceedings of the International Conference on Engineering of Reconfigurabe Systems and Algorithms},
+  Year                     = {2006},
+  Organization             = {Citeseer},
+
+  Cds_grade                = {1},
+  Cds_keywords             = {Mersenne Twister, FPGA, single-port},
+  Cds_read                 = {2014-04-02},
+  Cds_review               = {single-output MT without any architectural details, bad comparisons to CPU and non-uniform implementations},
+  File                     = {srikea_06.pdf:srikea_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.04.02}
+}
+
+@Book{sta_01,
+  Title                    = {{W}ireless {C}ommunications and {N}etworks},
+  Author                   = {Stallings, William},
+  Publisher                = {Prentice Hall Professional Technical Reference},
+  Year                     = {2001},
+
+  Address                  = {NJ, USA},
+  Edition                  = {1st},
+
+  ISBN                     = {0130408646}
+}
+
+@Misc{StandardECMA,
+  Title                    = {{High Rate Ultra Wideband PHY and MAC Standard}},
+
+  Author                   = {{Standard ECMA-368}},
+
+  Key                      = {uwb},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Url                      = {http://www.ecma-international.org}
+}
+
+@Misc{sthigh,
+  Title                    = {{High Rate Ultra Wideband PHY and MAC Standard}},
+
+  Author                   = {{Standard ECMA-368}},
+
+  Key                      = {uwb},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Url                      = {http://www.ecma-international.org}
+}
+
+@Article{stasud_20,
+  Title                    = {e{B}rain{II}: a 3 k{W} {R}ealtime {C}ustom 3{D} {DRAM} {I}ntegrated {ASIC} {I}mplementation of a {B}iologically {P}lausible {M}odel of a {H}uman {S}cale {C}ortex},
+  Author                   = {Stathis, Dimitrios
+and Sudarshan, Chirag
+and Yang, Yu
+and Jung, Matthias
+and Weis, Christian
+and Hemani, Ahmed
+and Lansner, Anders
+and Wehn, Norbert},
+  Journal                  = {Journal of Signal Processing Systems},
+  Year                     = {2020},
+
+  Month                    = {Jul},
+
+  Abstract                 = {The Artificial Neural Networks (ANNs), like CNN/DNN and LSTM, are not biologically plausible. Despite their initial success, they cannot attain the cognitive capabilities enabled by the dynamic hierarchical associative memory systems of biological brains. The biologically plausible spiking brain models, e.g., cortex, basal ganglia, and amygdala, have a greater potential to achieve biological brain like cognitive capabilities. Bayesian Confidence Propagation Neural Network (BCPNN) is a biologically plausible spiking model of the cortex. A human-scale model of BCPNN in real-time requires 162 TFlop/s, 50 TBs of synaptic weight storage to be accessed with a bandwidth of 200 TBs. The spiking bandwidth is relatively modest at 250 GBs/s. A hand-optimized implementation of rodent scale BCPNN has been done on Tesla K80 GPUs require 3 kWs, we extrapolate from that a human scale network will require 3 MWs. These power numbers rule out such implementations for field deployment as cognition engines in embedded systems.},
+  Day                      = {07},
+  Doi                      = {10.1007/s11265-020-01562-x},
+  ISSN                     = {1939-8115},
+  Owner                    = {MJ},
+  Timestamp                = {2020-09-19},
+  Url                      = {https://doi.org/10.1007/s11265-020-01562-x}
+}
+
+@InProceedings{stabri_11,
+  Title                    = {{F}ast and accurate resource conflict simulation for performance analysis of multi-core systems},
+  Author                   = {S. Stattelmann and O. Bringmann and W. Rosenstiel},
+  Booktitle                = {2011 Design, Automation Test in Europe},
+  Year                     = {2011},
+  Month                    = {March},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/DATE.2011.5763044},
+  ISSN                     = {1558-1101},
+  Keywords                 = {digital simulation;multiprocessing systems;optimisation;parallel programming;performance evaluation;program compilers;resource conflict simulation;performance analysis;multicore systems;SystemC based simulation;parallel software components;source code;low level timing properties;compiler optimizations;SystemC TLM 2.0 standard;Synchronization;Binary codes;Analytical models;Kernel;Predictive models;System analysis and design;Timing;Modeling;Software performance},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-13}
+}
+
+@InProceedings{stamen_17,
+  Title                    = {{I}ntroducing approximate memory support in {L}inux {K}ernel},
+  Author                   = {Giulia Stazi and F. Menichelli and A. Mastrandrea and M. Olivieri},
+  Booktitle                = {2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)},
+  Year                     = {2017},
+  Month                    = {June},
+  Pages                    = {97-100},
+
+  Doi                      = {10.1109/PRIME.2017.7974116},
+  Keywords                 = {Linux;operating system kernels;paged storage;Linux operating system kernel;OS level;allocation request management;approximate memory;approximate memory banks;approximate memory management;approximate physical memories;controlled probability;exact physical memories;fallback allocation policies;memory cells;memory fault probability;page pool management;read/write faults;Approximate computing;Hardware;Kernel;Linux;Memory management;Random access memory;Resource management},
+  Owner                    = {MJ},
+  Timestamp                = {2017-09-11}
+}
+
+@InProceedings{stebri_07,
+  Title                    = {{Autonomic MPSoCs for Reliable Systems}},
+  Author                   = {{Stechele},{Walter} and {Bringmann},{Oliver} and {Ernst}, {Rolf} and {Herkersdorf}, {Andreas} and {Hojenski},{Katharina} and {Janacik},{Peter} and {Rammig}, {Franz} and {Teich}, {Jürgen} and {Wehn},{Norbert} and {Zeppenfeld},{Johannes} and {Ziener}, {Daniel}},
+  Booktitle                = {Proceedings of Zuverlässigkeit und Entwurf ({ZuD} 2007)},
+  Year                     = {2007},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+  Pages                    = {137--138},
+
+  Date                     = {March 27--March 28},
+  File                     = {stebri_07.pdf:stebri_07.pdf:PDF;stebri_07_slides_draft_v2.ppt:stebri_07_slides_draft_v2.ppt:PowerPoint},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{stebri_07a,
+  Title                    = {{Concepts for Autonomic Integrated Systems}},
+  Author                   = {{Stechele},{Walter} and {Bringmann},{Oliver} and {Ernst}, {Rolf} and {Herkersdorf}, {Andreas} and {Hojenski},{Katharina} and {Janacik},{Peter} and {Rammig}, {Franz} and {Teich}, {Jürgen} and {Wehn},{Norbert} and {Zeppenfeld},{Johannes} and {Ziener}, {Daniel}},
+  Booktitle                = {Proceedings of edaWorkshop07},
+  Year                     = {2007},
+
+  Address                  = {Hannover, Germany},
+  Month                    = jun,
+
+  Date                     = {June 19--June 20},
+  File                     = {stebri_07a.pdf:stebri_07a.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{stezep_07,
+  Title                    = {{C}oncepts of {A}utonomous {I}ntegrated {S}ystems},
+  Author                   = {W. Stechele and J. Zeppenfeld and A. Herkersdorf and O. Bringmann and R. Ernst and K. Hojenski and P. Janacik and F. Ramming and J. Teich and D. Ziener and N. Wehn},
+  Booktitle                = {Proceedings of EDA Workshop 2007},
+  Year                     = {2007},
+
+  Address                  = {Hannover, Germany},
+  Month                    = jun,
+  Pages                    = {21--26},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@Electronic{ste_09,
+  Title                    = {{T}he art of benchmarking {HPC} systems},
+  Author                   = {Aad van der Steen},
+  HowPublished             = {\url{http://www.hpcresearch.nl/talks/benchm_tech.pdf}},
+  Language                 = {en},
+  Note                     = {last access 2015-02-14},
+  Organization             = {NCF/HPC Research},
+  Url                      = {http://www.hpcresearch.nl/talks/benchm_tech.pdf},
+  Year                     = {2009},
+
+  Cds_keywords             = {benchmarking, HPC},
+  File                     = {ste_09.pdf:ste_09.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2015-02-14}
+}
+
+@Article{stehwa_15,
+  Title                    = {{DRAM}’s {D}amning {D}efects - and {H}ow {T}hey {C}ripple {C}omputers},
+  Author                   = {Stefanovici, Ioan and Hwang, Andy and Schroeder, Bianca},
+  Journal                  = {IEEE Spectrum},
+  Year                     = {2015},
+
+  Month                    = {November},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-03}
+}
+
+@InProceedings{stejun_20,
+  Title                    = {{DRAMS}ys4.0: {A} {F}ast and {C}ycle-{A}ccurate {S}ystem{C}/{TLM}-{B}ased {DRAM} {S}imulator},
+  Author                   = {Steiner, Lukas and Jung, Matthias and Prado, Felipe S. and Bykov, Kyrill and Wehn, Norbert},
+  Booktitle                = {International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)},
+  Year                     = {2020},
+  Month                    = {July},
+  Publisher                = {Springer},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-07-14}
+}
+
+@Article{stewan_13a,
+  Title                    = {{A}ccelerating {O}pen{CV} {A}pplications with {Z}ynq-7000 {A}ll {P}rogrammable {S}o{C} using {V}ivado {HLS} {V}ideo {L}ibraries},
+  Author                   = {Stephen Neuendorffer, Thomas Li, and Devin Wang},
+  Year                     = {2013},
+
+  Owner                    = {Sadri},
+  Timestamp                = {2014.07.29}
+}
+
+@Article{stewan_13,
+  Title                    = {{XAPP}1167: {A}ccelerating {O}pen{CV} {A}pplications with {Z}ynq-7000 {A}ll {P}rogrammable {S}o{C} using {V}ivado {HLS} {V}ideo {L}ibraries},
+  Author                   = {Stephen Neuendorffer, Thomas Li, Devin Wang},
+  Year                     = {2013},
+
+  Month                    = {August},
+  Note                     = {last access 2015-01-13},
+
+  Owner                    = {Sadri},
+  Timestamp                = {2014.07.29},
+  Url                      = {http://www.xilinx.com/support/documentation/application_notes/xapp1167.pdf}
+}
+
+@Article{ste_74,
+  Title                    = {{EDF} {S}tatistics for {G}oodness of {F}it and {S}ome {C}omparisons},
+  Author                   = {Stephens, M. A.},
+  Journal                  = {Journal of the American Statistical Association},
+  Year                     = {1974},
+
+  Month                    = {September},
+  Number                   = {347},
+  Pages                    = {730-737},
+  Volume                   = {69},
+
+  Owner                    = {marxen},
+  Timestamp                = {2011.04.23}
+}
+
+@Misc{crazy_17,
+  Title                    = {{Self-Driving Cars use Crazy Amounts of Power, and it's Becoming a Problem}},
+
+  Author                   = {Jack Stewart},
+  HowPublished             = {https://www.wired.com/story/self-driving-cars-power-consumption-nvidia-chip/},
+  Year                     = {2018},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-07-27}
+}
+
+@Article{sto_71,
+  Title                    = {{Parallel Processing with Perfect Shuffle}},
+  Author                   = {H.S. Stone},
+  Journal                  = {IEEE Trans. Comput.},
+  Year                     = {1971},
+
+  Month                    = feb,
+  Pages                    = {153--161},
+  Volume                   = {C-20},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{stoibm14,
+  Title                    = {{IBM} and {A}ltera {D}evelop {FPGA} {POWER}8 {P}latform for {C}loud and {D}ata {A}nalytics {A}pplications},
+
+  Author                   = {Laura Stotler},
+  HowPublished             = {Transforming Network Infrastructure, \url{http://www.transformingnetworkinfrastructure.com/topics/hyperscale-data-centers/articles/393967-ibm-altera-develop-fpga-power8-platform-cloud-data.htm}},
+  Month                    = nov,
+  Note                     = {last access 2015-06-02},
+  Year                     = {2014},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.02}
+}
+
+@InProceedings{sto_09,
+  Title                    = {{LDPC} iteration control by partial parity check},
+  Author                   = {Stoye, William},
+  Booktitle                = {Proc. IEEE International Conference on Ultra-Wideband ICUWB 2009},
+  Year                     = {2009},
+  Month                    = sep,
+  Pages                    = {602--605},
+
+  Doi                      = {10.1109/ICUWB.2009.5288723},
+  File                     = {sto_09.pdf:sto_09.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.10.29}
+}
+
+@Electronic{ni_wallstreetfpga_optionpricing,
+  Title                    = {{H}ardware {A}cceleration of {M}onte {C}arlo {S}imulation for {O}ption {P}ricing},
+  Author                   = {John Stratoudakis},
+  HowPublished             = {https://decibel.ni.com/content/docs/DOC-9984},
+  Language                 = {en},
+  Month                    = mar,
+  Organization             = {Wall Street FPGA},
+  Year                     = {2012},
+
+  Cds_grade                = {2},
+  Cds_keywords             = {Monte Carlo, FPGA, option pricing, Black-Scholes},
+  Cds_read                 = {2010-03-07},
+  Cds_review               = {European call option pricer with Monte Carlo
+implemented with LabView on Virtex-5
+131x speedup against reference},
+  File                     = {ni_wallstreetfpga_optionpricing.pdf:ni_wallstreetfpga_optionpricing.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.07}
+}
+
+@Electronic{Stratoudakis2012,
+  Title                    = {{H}ardware {A}cceleration of {M}onte {C}arlo {S}imulation for {O}ption {P}ricing},
+  Author                   = {John Stratoudakis},
+  HowPublished             = {https://decibel.ni.com/content/docs/DOC-9984},
+  Language                 = {en},
+  Month                    = mar,
+  Organization             = {Wall Street FPGA},
+  Year                     = {2012},
+
+  Cds_grade                = {2},
+  Cds_keywords             = {Monte Carlo, FPGA, option pricing, Black-Scholes},
+  Cds_read                 = {2010-03-07},
+  Cds_review               = {European call option pricer with Monte Carlo
+implemented with LabView on Virtex-5
+131x speedup against reference},
+  File                     = {ni_wallstreetfpga_optionpricing.pdf:ni_wallstreetfpga_optionpricing.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.07}
+}
+
+@Electronic{Stratoudakis2012a,
+  Title                    = {{H}ardware {A}cceleration of {M}onte {C}arlo {S}imulation for {O}ption {P}ricing},
+  Author                   = {John Stratoudakis},
+  HowPublished             = {http://wallstreetfpga.com},
+  Language                 = {en},
+  Month                    = mar,
+  Organization             = {Wall Street FPGA},
+  Year                     = {2012},
+
+  Cds_grade                = {2},
+  Cds_keywords             = {Monte Carlo, FPGA, option pricing, Black-Scholes},
+  Cds_read                 = {2010-03-07},
+  Cds_review               = {European call option pricer with Monte Carlo
+implemented with LabView on Virtex-5
+131x speedup against reference},
+  File                     = {wallstreetfpga_optionpricing.pdf:wallstreetfpga_optionpricing.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.07}
+}
+
+@Electronic{wallstreetfpga_optionpricing,
+  Title                    = {{H}ardware {A}cceleration of {M}onte {C}arlo {S}imulation for {O}ption {P}ricing},
+  Author                   = {John Stratoudakis},
+  HowPublished             = {http://wallstreetfpga.com},
+  Language                 = {en},
+  Month                    = mar,
+  Organization             = {Wall Street FPGA},
+  Year                     = {2012},
+
+  Cds_grade                = {2},
+  Cds_keywords             = {Monte Carlo, FPGA, option pricing, Black-Scholes},
+  Cds_read                 = {2010-03-07},
+  Cds_review               = {European call option pricer with Monte Carlo
+implemented with LabView on Virtex-5
+131x speedup against reference},
+  File                     = {wallstreetfpga_optionpricing.pdf:wallstreetfpga_optionpricing.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.07}
+}
+
+@InProceedings{strgod_06,
+  Title                    = {{P}ipelined {M}ixed {P}recision {A}lgorithms on {FPGA}s for {F}ast and {A}ccurate {PDE} {S}olvers from {L}ow {P}recision {C}omponents},
+  Author                   = {Strzodka, R. and Goddeke, D.},
+  Booktitle                = {Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on},
+  Year                     = {2006},
+  Pages                    = {259-270},
+
+  Abstract                 = {FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing resource usage of multipliers depending on the operand size. Many research efforts have been devoted to the optimization of individual arithmetic and linear algebra operations. In this paper the authors take a higher level approach and seek to reduce the intermediate computational precision on the algorithmic level by optimizing the accuracy towards the final result of an algorithm. In our case this is the accurate solution of partial differential equations (PDEs). Using the Poisson problem as a typical PDE example the authors show that most intermediate operations can be computed with floats or even smaller formats and only very few operations (e.g. 1%) must be performed in double precision to obtain the same accuracy as a full double precision solver. Thus the FPGA can be configured with many parallel float rather than few resource hungry double operations. To achieve this, the authors adapt the general concept of mixed precision iterative refinement methods to FPGAs and develop a fully pipelined version of the conjugate gradient solver. The authors combine this solver with different iterative refinement schemes and precision combinations to obtain resource efficient mappings of the pipelined algorithm core onto the FPGA},
+  Cds_grade                = {0},
+  Cds_keywords             = {mixed-precision},
+  Doi                      = {10.1109/FCCM.2006.57},
+  File                     = {strgod_06.pdf:strgod_06.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.23}
+}
+
+@PhdThesis{Phdstude09,
+  Title                    = {{I}terative {MIMO} {D}ecoding: {A}lgorithms and {VLSI} {I}mplementation {A}spects},
+  Author                   = {Christoph Studer},
+  School                   = {ETH Zürich, Switzerland},
+  Year                     = {2009},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.12.01}
+}
+
+@Article{stuben_11,
+  Title                    = {{D}esign and {I}mplementation of a {P}arallel {T}urbo-{D}ecoder {ASIC} for 3{GPP}-{LTE}},
+  Author                   = {Christoph Studer and Christian Benkeser and Sandro Belfanti and Quiting Huang},
+  Journal                  = {IEEE Journal of Solid-state Circuits},
+  Year                     = {2011},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {8--17},
+  Volume                   = {46},
+
+  File                     = {stuben_11.pdf:stuben_11.pdf:PDF},
+  Owner                    = {May},
+  Timestamp                = {2011.03.28}
+}
+
+@InProceedings{stuben_10,
+  Title                    = {{A} 390{M}b/s 3.57mm{$^2$} 3{GPP}-{LTE} {T}urbo {D}ecoder {ASIC} in 0.13{$\mu$}m {CMOS}},
+  Author                   = {Christoph Studer and Christian Benkeser and Sandro Belfanti and Quiting Huang},
+  Booktitle                = {Proc. IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2010. ISSCC 2010},
+  Year                     = {2010},
+
+  Address                  = {San Francisco, USA},
+  Month                    = {Feb},
+  Pages                    = {274--275},
+  Volume                   = {53},
+
+  File                     = {stuben_10.pdf:stuben_10.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2010.02.25}
+}
+
+@Article{stubol_10,
+  Title                    = {{S}oft-{I}nput {S}oft-{O}utput {S}ingle {T}ree-{S}earch {S}phere {D}ecoding},
+  Author                   = {Studer, C. and Bolcskei, H.},
+  Journal                  = {Information Theory, IEEE Transactions on},
+  Year                     = {2010},
+  Number                   = {10},
+  Pages                    = {4827-4842},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TIT.2010.2059730},
+  File                     = {stubol_10.pdf:stubol_10.pdf:PDF},
+  ISSN                     = {0018-9448},
+  Keywords                 = {MIMO communication;computational complexity;iterative decoding;tree searching;MIMO communication system;SISO detection;computational complexity;iterative decoding;log-likelihood ratios;multiple-input multiple-output wireless communication systems;soft-input soft-output single tree-search sphere decoding;Computational complexity;Decoding;Detectors;Iterative decoding;MIMO;Measurement;Multiple–input multiple–output (MIMO) communication;iterative MIMO decoding;soft–input soft–output (SISO) detection;sphere decoding},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.10}
+}
+
+@Article{stubol_08,
+  Title                    = {{S}oft-{I}nput {S}oft-{O}utput {S}phere {D}ecoding},
+  Author                   = {Studer, C. and Bolcskei, H.},
+  Journal                  = {Information Theory, 2008. ISIT 2008. IEEE International Symposium on},
+  Year                     = {2008},
+
+  Month                    = {July},
+  Pages                    = {2007--2011},
+
+  Abstract                 = {Soft-input soft-output (SISO) detection algorithms form the basis for iterative decoding. The associated computational complexity often poses significant challenges for practical receiver implementations, in particular in the context of multiple- input multiple-output wireless systems. In this paper, we present a low-complexity SISO sphere decoder which is based on the single tree search paradigm, proposed originally for soft-output detection in Studer et al., IEEE J-SAC, 2008. The algorithm incorporates clipping of the extrinsic log-likelihood ratios in the tree search, which not only results in significant complexity savings, but also allows to cover a large performance/complexity trade-off region by adjusting a single parameter.},
+  Doi                      = {10.1109/ISIT.2008.4595341},
+  File                     = {stu_08.pdf:stu_08.pdf:PDF},
+  Keywords                 = {SISO detection algorithms;SISO sphere decoder;computational complexity;iterative decoding;log-likelihood ratios;multiple-input multiple-output wireless systems;single tree search paradigm;soft-input soft-output sphere decoding;soft-output detection;MIMO systems;computational complexity;iterative decoding;tree searching;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.18}
+}
+
+@Article{stubur_08,
+  Title                    = {{S}oft-output sphere decoding: algorithms and {VLSI} implementation},
+  Author                   = {Studer, C. and Burg, A. and Bölcskei, H.},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2008},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {290--300},
+  Volume                   = {26},
+
+  Doi                      = {10.1109/JSAC.2008.080206},
+  File                     = {stubur_08.pdf:stubur_08.pdf:PDF},
+  Owner                    = {kienle},
+  Timestamp                = {2009.08.03}
+}
+
+@Article{stufat_11,
+  Title                    = {{ASIC} {I}mplementation of {S}oft-{I}nput {S}oft-{O}utput {MIMO} {D}etection {U}sing {MMSE} {P}arallel {I}nterference {C}ancellation},
+  Author                   = {Studer, C. and Fateh, S. and Seethaler, D. },
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2011},
+  Number                   = {7},
+  Pages                    = {1754--1765},
+  Volume                   = {46},
+
+  Doi                      = {10.1109/JSSC.2011.2144470},
+  File                     = {stufat_11.pdf:stufat_11.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@InProceedings{stufat_10,
+  Title                    = {{A} 757{M}b/s 1.5 mm2 90nm {CMOS} soft-input soft-output {MIMO} detector for {IEEE} 802.11n},
+  Author                   = {Studer, C. and Fateh, S. and Seethaler, D. },
+  Booktitle                = {Proc. ESSCIRC},
+  Year                     = {2010},
+  Pages                    = {530--533},
+
+  Doi                      = {10.1109/ESSCIRC.2010.5619760},
+  File                     = {stufat_10.pdf:stufat_10.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@InProceedings{stupre_08,
+  Title                    = {{C}onfigurable high-throughput decoder architecture for quasi-cyclic {LDPC} codes},
+  Author                   = {Studer, C. and Preyss, N. and Roth, C. and Burg, A.},
+  Booktitle                = {Proc. 42nd Asilomar Conference on Signals, Systems and Computers},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {1137--1142},
+
+  Doi                      = {10.1109/ACSSC.2008.5074592},
+  File                     = {stupre_08.pdf:stupre_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.09.02}
+}
+
+@InProceedings{stuwen_06,
+  Title                    = {{S}oft-{O}utput {S}phere {D}ecoding: {P}erformance and {I}mplementation {A}spects},
+  Author                   = {Studer, C. and Wenk, M. and Burg, A. and Bolcskei, H. },
+  Booktitle                = {Proc. Fortieth Asilomar Conf. Signals, Systems and Computers ACSSC '06},
+  Year                     = {2006},
+  Pages                    = {2071--2076},
+
+  Doi                      = {10.1109/ACSSC.2006.355132},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@InProceedings{stukas_10,
+  Title                    = {{E}lastic {R}efresh: {T}echniques to {M}itigate {R}efresh {P}enalties in {H}igh {D}ensity {M}emory},
+  Author                   = {Stuecheli, J. and Kaseridis, D. and Hunter, H.C. and John, L.K.},
+  Booktitle                = {Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on},
+  Year                     = {2010},
+  Month                    = {Dec},
+  Pages                    = {375-384},
+
+  Doi                      = {10.1109/MICRO.2010.22},
+  ISSN                     = {1072-4451},
+  Keywords                 = {DRAM chips;multiprocessing systems;DRAM device;Elastic Refresh;GEMS;JEDEC DDRx SDRAM specification;SIMICS tool-set;dynamically reconfigurable predictive mechanism;execution stream;high density memory;refresh penalty mitigation;single chip many-core processor},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.13}
+}
+
+@InProceedings{suma_17,
+  Title                    = {{N}onvolatile processors: {W}hy is it trending?},
+  Author                   = {F. Su and K. Ma and X. Li and T. Wu and Y. Liu and V. Narayanan},
+  Booktitle                = {Design, Automation Test in Europe Conference Exhibition (DATE), 2017},
+  Year                     = {2017},
+  Month                    = {March},
+  Pages                    = {966-971},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7927131},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.23919/DATE.2017.7927131},
+  Keywords                 = {TCS},
+  Keywords_original        = {microprocessor chips;Internet-of-Things;NVP;intermittent power supply;next generation IoT edge devices;nonvolatile processor;Energy harvesting;Ferroelectric films;Logic gates;Nonvolatile memory;Program processors;Random access memory;TFETs;Internet of Things (IoT);energy harvesting;nonvolatile processor (NVP)},
+  Owner                    = {CCR}
+}
+
+@InProceedings{sulu_11,
+  Title                    = {{A} novel low complexity soft-decision demapper for {QPSK} 8{PSK} demodulation of {DVB}-{S}2 systems},
+  Author                   = {Jianing Su and Zhenghao Lu and Xiaopeng Yu and Changhui Hu},
+  Booktitle                = {International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2011},
+  Year                     = {2011},
+  Month                    = {Nov},
+  Pages                    = {1-2},
+
+  Doi                      = {10.1109/EDSSC.2011.6117701},
+  ISSN                     = {Pending},
+  Keywords                 = {digital video broadcasting;field programmable gate arrays;phase shift keying;standards;Altera FPGA;DVB-S2 standard;DVB-S2 systems;LLR;QPSK 8PSK demodulation;classical method;compare-select operations;linear complexity;log-likelihood-ratios;low complexity soft-decision demapper algorithm;multiple square operations;Approximation methods;Complexity theory;Demodulation;Digital video broadcasting;Field programmable gate arrays;Hardware;Silicon;DVB-S2;M-psk;demapper;log-likelihood-ratio;soft-decision},
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-12}
+}
+
+@InProceedings{suaker_15,
+  Title                    = {{F}ast {FPGA} prototyping toolbox for embedded optimization},
+  Author                   = {A. Suardi and E. C. Kerrigan and G. A. Constantinides},
+  Booktitle                = {2015 European Control Conference (ECC)},
+  Year                     = {2015},
+  Month                    = {July},
+  Pages                    = {2589-2594},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {HETEROGENEOUS PLATFORMS; cite number in presentation [54]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/ECC.2015.7330928},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {embedded systems;energy consumption;field programmable gate arrays;logic design;optimisation;{FPGA} prototyping toolbox;compute-intensive optimisation algorithm;{CPU} based machine;computing speed;energy consumption;{FPGA} technology;{FPGA} IP prototyping toolbox;PROTOIP;open source framework;prototype algorithm;{FPGA} platform;low-level {FPGA} design detail;custom template;embedded optimization application;Field programmable gate arrays;Algorithm design and analysis;Optimization;Prototypes;Software algorithms;MATLAB;Programming},
+  Owner                    = {CCR}
+}
+
+@InProceedings{subses_13,
+  Title                    = {{MISE}: {P}roviding {P}erformance {P}redictability and {I}mproving {F}airness in {S}hared {M}ain {M}emory {S}ystems},
+  Author                   = {Subramanian, Lavanya and Seshadri, Vivek and Kim, Yoongu and Jaiyen, Ben and Mutlu, Onur},
+  Booktitle                = {Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)},
+  Year                     = {2013},
+
+  Address                  = {Washington, DC, USA},
+  Pages                    = {639--650},
+  Publisher                = {IEEE Computer Society},
+  Series                   = {HPCA '13},
+
+  Acmid                    = {2495485},
+  Doi                      = {10.1109/HPCA.2013.6522356},
+  ISBN                     = {978-1-4673-5585-8},
+  Numpages                 = {12},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-02},
+  Url                      = {http://dx.doi.org/10.1109/HPCA.2013.6522356}
+}
+
+@InProceedings{sub_02,
+  Title                    = {{Shannon vs. Moore: Driving the Evolution of Signal Processing Platforms in Wireless Communications (Invited Talk)}},
+  Author                   = {R. Subramanian},
+  Booktitle                = {Proc. 2002 Workshop on Signal Processing Systems (SiPS '02)},
+  Year                     = {2002},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = oct,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{Sud_97,
+  Title                    = {{D}ecoding of {R}eed {S}olomon {C}odes {B}eyond the {E}rror-{C}orrection {B}ound},
+  Author                   = {Sudan, Madhu},
+  Journal                  = {Journal of Complexity},
+  Year                     = {1997},
+
+  Month                    = mar,
+  Number                   = {1},
+  Pages                    = {180--193},
+  Volume                   = {13},
+
+  Acmid                    = {270513},
+  Address                  = {Orlando, FL, USA},
+  Doi                      = {10.1006/jcom.1997.0439},
+  ISSN                     = {0885-064X},
+  Issue_date               = {March 1997},
+  Numpages                 = {14},
+  Publisher                = {Academic Press, Inc.},
+  Url                      = {http://dx.doi.org/10.1006/jcom.1997.0439}
+}
+
+@InProceedings{sudlap_19,
+  Title                    = {{NNDRAM}: {A} {D}eep {I}n-{DRAM} {C}omputing {A}rchitecture for {N}eural {N}etwork {P}rocessing},
+  Author                   = {Sudarshan, Chirag and Lappas, Jan and Ghaffar, Muhammad Mohsin and Rybalkin, Vladimir and Weis, Christian and Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2019},
+  Month                    = {May},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-04-26}
+}
+
+@InProceedings{sudlap_19a,
+  Title                    = {{A} {L}ean, {L}ow {P}ower, {L}ow {L}atency {DRAM} {M}emory {C}ontroller for {T}ransprecision {C}omputing},
+  Author                   = {Sudarshan, Chirag and Lappas, Jan and Weis, Christian and Mathew, Deepak M. and Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
+  Year                     = {2019},
+
+  Address                  = {Cham},
+  Editor                   = {Pnevmatikatos, Dionisios N.
+and Pelcat, Maxime
+and Jung, Matthias},
+  Pages                    = {429--441},
+  Publisher                = {Springer International Publishing},
+
+  Abstract                 = {Energy consumption is one of the major challenges for the advanced System on Chips (SoC). This is addressed by adopting heterogeneous and approximate computing techniques. One of the recent evolution in this context is transprecision computing paradigm. The idea of the transprecision computing is to consume adequate amount of energy for each operation by performing dynamic precision reduction. The impact of the memory subsystem plays a crucial role in such systems. Hence, the energy efficiency of a transprecision system can be further optimized by tailoring the memory subsystem to the transprecision computing. In this work, we present a lean, low power, low latency memory controller that is appropriate for transprecision methodology. The memory controller consumes an average power of 129.33 mW at a frequency of 500 MHz and has a total area of 4.71 mm2 for UMC 65 nm process.},
+  ISBN                     = {978-3-030-27562-4},
+  Owner                    = {MJ},
+  Timestamp                = {2019-08-12}
+}
+
+@InProceedings{sudsol_21,
+  Title                    = {{A} {N}ovel {DRAM}-{B}ased {P}rocess-in-{M}emory {A}rchitecture and its {I}mplementation for {CNN}s},
+  Author                   = {Sudarshan, Chirag and Soliman, Taha and de la Parra, C. and Weis, Christian and Ecco, Leonardo and Jung, Matthias and Wehn, Norbert and Guntoro, Andre},
+  Booktitle                = {26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021)},
+  Year                     = {2021},
+  Month                    = {Januar},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-09-19}
+}
+
+@Article{sug_75,
+  Title                    = {{A} method for solving key equation for decoding goppa codes},
+  Author                   = {Yasuo Sugiyama and Masao Kasahara and Shigeichi Hirasawa and Toshihiko Namekawa},
+  Journal                  = {Information and Control},
+  Year                     = {1975},
+  Number                   = {1},
+  Pages                    = {87 - 99},
+  Volume                   = {27},
+
+  Doi                      = {http://dx.doi.org/10.1016/S0019-9958(75)90090-X},
+  ISSN                     = {0019-9958},
+  Owner                    = {scholl},
+  Timestamp                = {2016.08.04},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S001999587590090X}
+}
+
+@InProceedings{sukmin_12,
+  Title                    = {{D}atabase {A}nalytics {A}cceleration {U}sing {FPGA}s},
+  Author                   = {Sukhwani, Bharat and Min, Hong and Thoennes, Mathew and Dube, Parijat and Iyer, Balakrishna and Brezzo, Bernard and Dillenberger, Donna and Asaad, Sameh},
+  Booktitle                = {Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques},
+  Year                     = {2012},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {411--420},
+  Publisher                = {ACM},
+  Series                   = {PACT '12},
+
+  Acmid                    = {2370874},
+  Doi                      = {10.1145/2370816.2370874},
+  ISBN                     = {978-1-4503-1182-3},
+  Keywords                 = {acceleration, analytics, fpga, relational database},
+  Location                 = {Minneapolis, Minnesota, USA},
+  Numpages                 = {10},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.01},
+  Url                      = {http://doi.acm.org/10.1145/2370816.2370874}
+}
+
+@Article{sumwil_98,
+  Title                    = {{SNR Mismatch and Online Estimation in Turbo Decoding}},
+  Author                   = {Summers, T. A. and Wilson, S. G.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1998},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {421--423},
+  Volume                   = {46},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{sunpet_08,
+  Title                    = {{H}igh-{P}erformance {M}ixed-{P}recision {L}inear {S}olver for {FPGA}s},
+  Author                   = {Junqing Sun and Peterson, G.D. and Storaasli, O.O.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {2008},
+  Number                   = {12},
+  Pages                    = {1614-1623},
+  Volume                   = {57},
+
+  Abstract                 = {Compared to higher-precision data formats, lower-precision data formats result in higher performance for computational intensive applications on FPGAs because of their lower resource cost, reduced memory bandwidth requirements, and higher circuit frequency. On the other hand, scientific computations usually demand highly accurate solutions. This paper seeks to utilize lower-precision data formats whenever possible for higher performance without losing the accuracy of higher-precision data formats by using mixed-precision algorithms and architectures. First, we analyze the floating-point performance of different data formats on FPGAs. Second, we introduce mixed-precision iterative refinement algorithms for linear solvers and give error analysis. Finally, we propose an innovative architecture for a mixed-precision direct solver for reconfigurable computing. Our results show that our mixed-precision algorithm and architecture significantly improve the performance of linear solvers on FPGAs.},
+  Cds_grade                = {0},
+  Cds_keywords             = {mixed-precision},
+  Doi                      = {10.1109/TC.2008.89},
+  File                     = {sunpet_08.pdf:sunpet_08.pdf:PDF},
+  ISSN                     = {0018-9340},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.23}
+}
+
+@Article{suntak_05,
+  Title                    = {{I}nterleavers for turbo codes using permutation polynomials over integer rings},
+  Author                   = {Sun, J. and Takeshita, O. Y.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2005},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {101--119},
+  Volume                   = {51},
+
+  Doi                      = {10.1109/TIT.2004.839478},
+  File                     = {suntak_05.pdf:suntak_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.08.19}
+}
+
+@Article{sunson_06,
+  Title                    = {{Field Programmable Gate Array (FPGA) for Iterative Code Evaluation}},
+  Author                   = {L. Sun and H. Song and Z. Keirn and B. Kumar},
+  Journal                  = {IEEE Transactions on Magnetics},
+  Year                     = {2006},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {226--231},
+  Volume                   = {42},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{sunzen_11,
+  Title                    = {{A} {N}ovel {S}implified {L}og-{L}ikelihood {R}atio for {S}oft-{O}utput {D}emapping of {CMMB}},
+  Author                   = {Xiangran Sun and Zhibin Zeng},
+  Booktitle                = {Advances in Computer Science and Education Applications},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2011},
+  Pages                    = {350-356},
+  Volume                   = {202},
+
+  ISBN                     = {978-3-642-22455-3},
+  Keywords                 = {demapping; log-likelihood ratio (LLR); quadrature amplitude modulation (QAM)},
+  Language                 = {English}
+}
+
+@Article{suncav_10,
+  Title                    = {{A} {F}lexible {LDPC}/{T}urbo {D}ecoder {A}rchitecture},
+  Author                   = {Sun, Yang and Cavallaro, Joseph},
+  Journal                  = {Journal of Signal Processing Systems},
+  Year                     = {2010},
+  Note                     = {10.1007/s11265-010-0477-6},
+  Pages                    = {1-16},
+
+  Affiliation              = {Rice University Department of Electrical and Computer Engineering 6100 Main Street Houston TX 77005 USA},
+  File                     = {suncav_10.pdf:suncav_10.pdf:PDF},
+  ISSN                     = {1939-8018},
+  Keyword                  = {Electrical Engineering},
+  Owner                    = {Brehm},
+  Publisher                = {Springer New York},
+  Timestamp                = {2010.10.12},
+  Url                      = {http://dx.doi.org/10.1007/s11265-010-0477-6}
+}
+
+@Article{sunlte_10,
+  Title                    = {{Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder}},
+  Author                   = {Y. Sun and J.R. Cavallaro},
+  Journal                  = {Integration VLSI Journal},
+  Year                     = {2010},
+
+  Doi                      = {10.1016/j.vlsi.2010.07.001},
+  File                     = {sunlte_10.pdf:sunlte_10.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {ilnseher},
+  Timestamp                = {2011.01.03}
+}
+
+@Article{suncav_12,
+  Title                    = {{H}igh-{T}hroughput {S}oft-{O}utput {MIMO} {D}etector {B}ased on {P}ath-{P}reserving {T}rellis-{S}earch {A}lgorithm},
+  Author                   = {Y. Sun and J. R. Cavallaro},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2012},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {1235-1247},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/TVLSI.2011.2147811},
+  ISSN                     = {1063-8210},
+  Keywords                 = {MIMO communication;trellis codes;CMOS technology;MIMO detector;QAM;TSMC;antenna;bit rate 2.1 Gbit/s;bit rate 6.4 Gbit/s;hardware-friendly data-parallel algorithm;high-speed VLSI architecture;log-likelihood ratio;parallel processing;path-preserving trellis-search algorithm;systolic-array detector;trellis nodes;voltage 1.08 V;wavelength 65 nm;Complexity theory;Detection algorithms;Detectors;MIMO;Throughput;Transmitting antennas;Very large scale integration;Application-specific integrated circuit (ASIC);VLSI architecture;multiple-input-multiple-output (MIMO) detection;shortest path algorithm;soft-output MIMO detector},
+  Owner                    = {MH},
+  Timestamp                = {2017-01-31}
+}
+
+@Article{suncav_12a,
+  Title                    = {{T}rellis-{S}earch {B}ased {S}oft-{I}nput {S}oft-{O}utput {MIMO} {D}etector: {A}lgorithm and {VLSI} {A}rchitecture},
+  Author                   = {Y. Sun and J. R. Cavallaro},
+  Journal                  = {IEEE Transactions on Signal Processing},
+  Year                     = {2012},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {2617-2627},
+  Volume                   = {60},
+
+  Doi                      = {10.1109/TSP.2012.2187646},
+  ISSN                     = {1053-587X},
+  Owner                    = {MH},
+  Timestamp                = {2017-05-30}
+}
+
+@InProceedings{suncav_08,
+  Title                    = {{U}nified decoder architecture for {LDPC}/turbo codes},
+  Author                   = {Yang Sun and Cavallaro, J. R.},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems SiPS 2008},
+  Year                     = {2008},
+  Month                    = oct,
+  Pages                    = {13--18},
+
+  Doi                      = {10.1109/SIPS.2008.4671730},
+  File                     = {suncav_08.pdf:suncav_08.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.11.24}
+}
+
+@InProceedings{sunkim_10,
+  Title                    = {{A} {P}ipelined {CRC} {C}alculation {U}sing {L}ookup {T}ables},
+  Author                   = {Yan Sun and Min Sik Kim},
+  Booktitle                = {Consumer Communications and Networking Conference (CCNC), 2010 7th IEEE},
+  Year                     = {2010},
+  Month                    = {Jan},
+  Pages                    = {1-2},
+
+  Abstract                 = {We present a fast cyclic redundancy check (CRC) algorithm that performs CRC computation for any length of message in parallel. Traditional CRC implementations have feedbacks, which make pipelining problematic. In the proposed approach, we eliminate feedbacks and implement a pipelined calculation of 32-bit CRC in the SMIC 0.13 ¿m CMOS technology. For a given message, the algorithm first chunks the message into blocks, each of which has a fixed size equal to the degree of the generator polynomial. Then it computes CRC for the chunked blocks in parallel using lookup tables, and the results are combined together by performing XOR operations. The simulation results show that our proposed pipelined CRC is more efficient than existing CRC implementations.},
+  Doi                      = {10.1109/CCNC.2010.5421679},
+  File                     = {sunkim_10.pdf:sunkim_10.pdf:PDF},
+  Keywords                 = {CMOS integrated circuits;cyclic redundancy check codes;pipeline arithmetic;polynomials;table lookup;CMOS technology;SMIC;XOR operations;cyclic redundancy check;generator polynomial;lookup tables;pipelined CRC calculation;CMOS technology;Concurrent computing;Cyclic redundancy check;Feedback;Parallel processing;Pipeline processing;Polynomials;Protocols;Table lookup;Throughput},
+  Owner                    = {StW},
+  Timestamp                = {2014.11.17}
+}
+
+@Article{sunyua_17,
+  Title                    = {{M}aximum {E}nergy {E}fficiency {T}racking {C}ircuits for {C}onverter-{L}ess {E}nergy {H}arvesting {S}ensor {N}odes},
+  Author                   = {Y. {Sun} and Z. {Yuan} and Y. {Liu} and X. {Li} and Y. {Wang} and Q. {Wei} and Y. {Wang} and V. {Narayanan} and H. {Yang}},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2017},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {670-674},
+  Volume                   = {64},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7725972},
+  Ccr_keywords             = {EH, MPPT (Converter-less and storage-less)},
+  Ccr_relevance            = {medium},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/TCSII.2016.2623354},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;frequency control;sensors;maximum energy efficiency tracking circuits;converterless energy harvesting sensor nodes;converterless supply architecture;maximum power point tracking;MPPT voltage;efficiency-driven frequency controller;Energy harvesting;Clocks;Frequency conversion;Computer architecture;Circuits and systems;DC-DC power converters;Maximum power point trackers;Converter-less;energy efficiency;energy harvesting (EH);sensor node},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27}
+}
+
+@InProceedings{sunzha_10a,
+  Title                    = {{RC}-{C}ache: {S}oft error mitigation techniques for low-leakage on-chip caches},
+  Author                   = {Yan Sun and Minxuan Zhang and Shaoqing Li and Chao Song and Yali Zhao},
+  Booktitle                = {Proc. 2nd Int Signal Processing Systems (ICSPS) Conf},
+  Year                     = {2010},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/ICSPS.2010.5555852},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{sunzha_10,
+  Title                    = {{C}ost effective soft error mitigation for parallel adders by exploiting inherent redundancy},
+  Author                   = {Yan Sun and Minxuan Zhang and Shaoqing Li and Yali Zhao},
+  Booktitle                = {Proc. IEEE Int IC Design and Technology (ICICDT) Conf},
+  Year                     = {2010},
+  Pages                    = {224--227},
+
+  Doi                      = {10.1109/ICICDT.2010.5510255},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@InProceedings{sunzha_09,
+  Title                    = {{FPGA} implementation of nonbinary quasi-cyclic {LDPC} decoder based on {EMS} algorithm},
+  Author                   = {Yue Sun and Yuyang Zhang and Jianhao Hu and Zhongpei Zhang},
+  Booktitle                = {Proc. Int. Conf. Communications, Circuits and Systems ICCCAS 2009},
+  Year                     = {2009},
+  Pages                    = {1061--1065},
+
+  Doi                      = {10.1109/ICCCAS.2009.5250325},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.06.09}
+}
+
+@InProceedings{sunzhu_08,
+  Title                    = {{C}onfigurable and scalable high throughput turbo decoder architecture for multiple 4{G} wireless standards},
+  Author                   = {Yang Sun and Yuming Zhu and Goel, M. and Cavallaro, J. R.},
+  Booktitle                = {Proc. International Conference on Application-Specific Systems, Architectures and Processors ASAP 2008},
+  Year                     = {2008},
+  Month                    = jul,
+  Pages                    = {209--214},
+
+  Doi                      = {10.1109/ASAP.2008.4580180},
+  File                     = {sunzhu_08.pdf:sunzhu_08.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.08.14}
+}
+
+@InProceedings{suzwan_00,
+  Title                    = {{A K=3, 2Mbps Low Power Turbo Decoder for 3rd Generation W-CDMA Systems}},
+  Author                   = {H. Suzuki and Z. Wang and K. K. Parhi},
+  Booktitle                = {Proc. 2000 Custom Integrated Circuits Conference (CICC '00)},
+  Year                     = {2000},
+
+  Address                  = {Orlando, Florida, USA},
+  Month                    = may,
+  Pages                    = {39--42},
+
+  File                     = {suzwan_00.pdf:suzwan_00.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{suzmit_97,
+  Title                    = {{A 300MIPS/W RISC Core Processor with Variable Supply-Voltage in Variable Threshold-Voltage CMOS}},
+  Author                   = {K. Suzuki and S. Mita and F. Yamane and F. Sano and A. Chiba and Y. Watanabe and K. Matsuda and T. Maeda and T. Kuroda},
+  Booktitle                = {Proc. 1997 Custom Integrated Circuits Conference (CICC '97)},
+  Year                     = {1997},
+  Pages                    = {587--590},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{sylbla_06,
+  Title                    = {{E}last{IC}: {A}n {A}daptive {S}elf-{H}ealing {A}rchitecture for {U}npredictable {S}ilicon},
+  Author                   = {Sylvester, D. and Blaauw, D. and Karl, E.},
+  Journal                  = {IEEE Design and Test of Computers},
+  Year                     = {2006},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {484--490},
+  Volume                   = {23},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/MDT.2006.145},
+  File                     = {sylbla_06.pdf:sylbla_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.04}
+}
+
+@Article{sylkeu_99,
+  Title                    = {{Rethinking Deep-Submicron Circuit Design}},
+  Author                   = {D. Sylvester and K. Keutzer},
+  Journal                  = {IEEE Computer},
+  Year                     = {1999},
+  Number                   = {11},
+  Pages                    = {25-33},
+  Volume                   = {32},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{sy,
+  Author                   = {{SystemC Community}},
+  HowPublished             = {{{www.systemc.org}}},
+
+  Key                      = {SystemC},
+  Opttitle                 = {{}},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{SystemCCommunity,
+  Author                   = {{SystemC Community}},
+  HowPublished             = {{{www.systemc.org}}},
+
+  Key                      = {SystemC},
+  Opttitle                 = {{}},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{szidim_09,
+  Title                    = {{A} parsimonious multi-asset {H}eston model: calibration and derivative pricing},
+  Author                   = {A. Szimayer and G. Dimitroff and S. Lorenz},
+  Booktitle                = {Berichte des Fraunhofer ITWM},
+  Publisher                = {Fraunhofer ITWM},
+  Year                     = {2009},
+  Volume                   = {171},
+
+  Cds_grade                = {0},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.07},
+  Url                      = {http://www.itwm.fraunhofer.de/fileadmin/ITWM-Media/Zentral/Pdf/Berichte_ITWM/2011/bericht_171.pdf}
+}
+
+@InProceedings{t.mk.y_01,
+  Title                    = {{High-Performance Programmable SISO Decoder VLSI Implementation for Decoding Turbo Codes}},
+  Author                   = {T.Miyauchi and K.Yamamoto and T. Yokokawa and M. Kan and Y. Mizutani and M. Hattori},
+  Booktitle                = {Global Telecommunications Conference, 2001 (GLOBECOM '01)},
+  Year                     = {2001},
+
+  Address                  = {San Antonio, TX ,USA},
+  Pages                    = {305 -- 309},
+  Volume                   = {1},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{tabcho_13,
+  Title                    = {{G}allager {B} {D}ecoder on {N}oisy {H}ardware},
+  Author                   = {Tabatabaei Yazdi, S.M.Sadegh and Cho, Hyungmin and Dolecek, Lara},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2013},
+  Number                   = {5},
+  Pages                    = {1660-1673},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCOMM.2013.031213.120153},
+  File                     = {tabcho_13.pdf:tabcho_13.pdf:PDF},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Decoding;Hardware;Iterative decoding;Logic gates;Noise measurement;Reliability;Error analysis;Gallager B algorithm;LDPC codes;faulty hardware;non-binary LDPC codes},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@Article{taf_03,
+  Title                    = {{G}eneralised stopping criterion for iterative decoders},
+  Author                   = {Taffin, A.},
+  Journal                  = {Electronics Letters},
+  Year                     = {2003},
+
+  Month                    = jun,
+  Number                   = {13},
+  Pages                    = {993--994},
+  Volume                   = {39},
+
+  Doi                      = {10.1049/el:20030555},
+  File                     = {taf_03.pdf:taf_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.15}
+}
+
+@Article{tagsho_11,
+  Title                    = {{E}fficient {I}mplementation of {L}inear {P}rogramming {D}ecoding},
+  Author                   = {Taghavi, M. and Shokrollahi, A. and Siegel, P.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2011},
+  Number                   = {9},
+  Pages                    = {5960--5982},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TIT.2011.2161920},
+  File                     = {tagsho_11.pdf:tagsho_11.pdf:PDF},
+  Keywords                 = {LPDecoding, interior point},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.08},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6006620}
+}
+
+@Electronic{tak_14,
+  Title                    = {{FFTE}: {A} {F}ast {F}ourier {T}ransform {P}ackage},
+  Author                   = {Takahash, Daisuke},
+  Url                      = {http://www.ffte.jp/},
+  Year                     = {2014},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-05-17}
+}
+
+@Article{tak_06,
+  Title                    = {{O}n maximum contention-free interleavers and permutation polynomials over integer rings},
+  Author                   = {Takeshita, O. Y.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2006},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {1249--1253},
+  Volume                   = {52},
+
+  Doi                      = {10.1109/TIT.2005.864450},
+  File                     = {tak_06.pdf:tak_06.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.09}
+}
+
+@InProceedings{takkoh_05,
+  Title                    = {{A}nalysis of iterative demapping and decoding for {MBOK} {DS}-{UWB} systems via {EXIT} chart},
+  Author                   = {Takizawa, K. and Kohno, R.},
+  Booktitle                = {Communications, 2005. ICC 2005. 2005 IEEE International Conference on},
+  Year                     = {2005},
+  Month                    = may,
+  Pages                    = {949--953Vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/ICC.2005.1494490},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@Article{talvar_15,
+  Title                    = {{L}ist {D}ecoding of {P}olar {C}odes},
+  Author                   = {I. Tal and A. Vardy},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2015},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {2213-2226},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TIT.2015.2410251},
+  File                     = {talvar_15.pdf:talvar_15.pdf:PDF},
+  ISSN                     = {0018-9448},
+  Keywords                 = {cyclic redundancy check codes;maximum likelihood decoding;parity check codes;precoding;CRC precoding;LDPC codes;algorithmic transformations;codeword;decoder output;decoding path;decoding process;decoding stage;information bit;integer parameter;list decoding;maximum-likelihood decoding;polar codes;pruning procedure;specific list-decoding algorithm;stark contrast;successive-cancellation list decoder;Arrays;Bit error rate;Complexity theory;Maximum likelihood decoding;Parity check codes;Vectors;List decoding;polar codes;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2017-03-30}
+}
+
+@Article{talvar_13,
+  Title                    = {{H}ow to {C}onstruct {P}olar {C}odes},
+  Author                   = {I. Tal and A. Vardy},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2013},
+
+  Month                    = {Oct},
+  Number                   = {10},
+  Pages                    = {6562-6582},
+  Volume                   = {59},
+
+  Abstract                 = {A method for efficiently constructing polar codes is presented and analyzed. Although polar codes are explicitly defined, straightforward construction is intractable since the resulting polar bit-channels have an output alphabet that grows exponentially with the code length. Thus, the core problem that needs to be solved is that of faithfully approximating a bit-channel with an intractably large alphabet by another channel having a manageable alphabet size. We devise two approximation methods which “sandwich” the original bit-channel between a degraded and an upgraded version thereof. Both approximations can be efficiently computed and turn out to be extremely close in practice. We also provide theoretical analysis of our construction algorithms, proving that for any fixed ε > 0 and all sufficiently large code lengths n, polar codes whose rate is within ε of channel capacity can be constructed in time and space that are both linear in n.},
+  Doi                      = {10.1109/TIT.2013.2272694},
+  ISSN                     = {0018-9448},
+  Keywords                 = {approximation theory;codes;alphabet size;approximation methods;channel capacity;construction algorithms;polar bit-channels;polar codes;Approximation algorithms;Approximation methods;Complexity theory;Convolutional codes;Decoding;Kernel;Quantization (signal);Channel degrading and upgrading;channel polarization;construction algorithms;polar codes},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-29}
+}
+
+@InProceedings{talsab_05,
+  Title                    = {{A} linear log-{MAP} algorithm for turbo decoding and turbo equalization},
+  Author                   = {Shahram Talakoub and Leila Sabeti and Behnam Shahrrava and Majid Ahmadi},
+  Booktitle                = {WiMob (1)'05},
+  Year                     = {2005},
+  Pages                    = {182-186},
+
+  File                     = {talsab_05.pdf:talsab_05.pdf:PDF},
+  Owner                    = {ilnseher},
+  Timestamp                = {2012.09.19}
+}
+
+@Article{tal_05,
+  Title                    = {{B}ounds on the capacity of the unidirectional channels},
+  Author                   = {Tallini, Luca G.},
+  Journal                  = {IEEE Transactions on Computers},
+  Year                     = {2005},
+  Number                   = {2},
+  Pages                    = {232--235},
+  Volume                   = {54},
+
+  Owner                    = {kraft},
+  Publisher                = {IEEE},
+  Timestamp                = {2017.09.12}
+}
+
+@InProceedings{taal_02,
+  Title                    = {{O}n the capacity and codes for the {Z}-channel},
+  Author                   = {Tallini, Luca G. and Al-Bassam, S. and Bose, B.},
+  Booktitle                = {IEEE International Symposium on Information Theory},
+  Year                     = {2002},
+  Organization             = {IEEE},
+  Pages                    = {422},
+
+  Owner                    = {kraft},
+  Timestamp                = {2017.08.14}
+}
+
+@InProceedings{tamzer_03,
+  Title                    = {{A}n efficient methodology and semi-automated flow for design and validation of complex digital signal processing {ASICS} macro-cells},
+  Author                   = {Tambour, L. and Zergainoh, N. and Urard, P. and Michel, H. and Jerraya, A. A. },
+  Booktitle                = {Proc. 14th IEEE International Workshop on Rapid Systems Prototyping},
+  Year                     = {2003},
+  Month                    = jun,
+  Pages                    = {56--63},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@Article{tammur_07,
+  Title                    = {{Timing-Error-Tolerant Network-on-Chip Design Methodology}},
+  Author                   = {Rutuparna Tamhankar and Srinivasan Murali and Stergios Stergiou and Antonio Pullini and Federico Angiolini and Luca Benini and De Micheli, Giovanni},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems},
+  Year                     = {2007},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {1297--1310},
+  Volume                   = {26},
+
+  File                     = {tammur_07.pdf:tammur_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2007.12.12}
+}
+
+@InProceedings{tanstu_00,
+  Title                    = {{A} {MAP} equivalent {SOVA} for non-binary turbo codes},
+  Author                   = {Tan, J. and Stuber, G. L. },
+  Booktitle                = {Proc. IEEE Int. Conf. Communications ICC 2000},
+  Year                     = {2000},
+  Pages                    = {602--606},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/ICC.2000.853567},
+  Owner                    = {m.alles},
+  Timestamp                = {2010.08.12}
+}
+
+@Article{tanruz_10a,
+  Title                    = {{A} {S}eparation {A}lgorithm for {I}mproved {LP}-{D}ecoding of {L}inear {B}lock {C}odes},
+  Author                   = {Tanatmis, A. and Ruzika, S. and Hamacher, H. W. and Punekar, M. and Kienle, F. and Wehn, N.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2010},
+  Number                   = {7},
+  Pages                    = {3277--3289},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TIT.2010.2048489},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.07.06}
+}
+
+@Conference{tanruz_09,
+  Title                    = {{Valid Inequalities for Binary Linear Codes}},
+  Author                   = {Akin Tanatmis and Stefan Ruzika and Horst W. Hamacher and Mayur Punekar and Frank Kienle and Norbert Wehn},
+  Booktitle                = {Proc. IEEE International Symposium on Information Theory ISIT 2009},
+  Year                     = {2009},
+
+  Address                  = {Seoul, Korea},
+  Month                    = jul,
+  Pages                    = {2216 -- 2220},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{tanruz_08,
+  Title                    = {{A} separation algorithm for improved {LP}-decoding of linear block codes},
+  Author                   = {Tanatmis, A. and Ruzika, S. and Hamacher, H. W. and Punekar, M. and Kienle, F. and Wehn, N.},
+  Booktitle                = {Proc. 5th International Symposium on Turbo Codes and Related Topics},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {37--42},
+
+  Doi                      = {10.1109/TURBOCODING.2008.4658669},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{tanruz_10,
+  Title                    = {{A} lagrangian relaxation based decoding algorithm for {LTE} turbo codes},
+  Author                   = {Tanatmis, A. and Ruzika, S. and Kienle, F. },
+  Booktitle                = {Proc. 6th Int Turbo Codes and Iterative Information Processing (ISTC) Symp},
+  Year                     = {2010},
+  Pages                    = {369--373},
+
+  Doi                      = {10.1109/ISTC.2010.5613906},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.07.06}
+}
+
+@InProceedings{tanruz_10b,
+  Title                    = {{N}umerical {C}omparison of {IP} {F}ormulations as {ML} {D}ecoders},
+  Author                   = {Tanatmis, A. and Ruzika, S. and Punekar, M. and Kienle, F. },
+  Booktitle                = {Proc. IEEE Int Communications (ICC) Conf},
+  Year                     = {2010},
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/ICC.2010.5502303},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.07.06}
+}
+
+@Article{tanliu_01,
+  Title                    = {{O}n combining {C}hase-2 and {GMD} decoding algorithms for nonbinary block codes},
+  Author                   = {Tang, H. and Liu, Y. and Fossorier, M. and Lin, S.},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2001},
+  Number                   = {5},
+  Pages                    = {209--211},
+  Volume                   = {5},
+
+  Doi                      = {10.1109/4234.922762},
+  File                     = {tanliu_01.pdf:tanliu_01.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ASD},
+  Owner                    = {Scholl},
+  Review                   = {Uprpaper zum CGA Algorithmus (Chase + GMD)},
+  Timestamp                = {2011.09.15}
+}
+
+@InProceedings{tanbha_06,
+  Title                    = {{Modified Min-Sum Algorithm for LDPC Decoders in UWB Communications}},
+  Author                   = {J. Tang and T. Bhatt and V. Stolpman},
+  Booktitle                = {Proc. IEEE International Conference on Ultra-Wideband 2006},
+  Year                     = {2006},
+
+  Address                  = {Boston, Massachusetts, USA},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{tanbha_06a,
+  Title                    = {{Reconfigurable Shuffle Network Design in LDPC Decoders}},
+  Author                   = {Jun Tang and Tejas Bhatt and Vishwas Sundaramurthy},
+  Booktitle                = {Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)},
+  Year                     = {2006},
+  Month                    = sep,
+  Pages                    = {81--86},
+
+  File                     = {tanbha_06a.pdf:tanbha_06a.pdf:PDF},
+  Owner                    = {alles},
+  Timestamp                = {2007.08.02}
+}
+
+@Article{tan_18,
+  Title                    = {{T}he {N}ew {D}eep {L}earning {M}emory {A}rchitectures {Y}ou {S}hould {K}now {A}bout},
+  Author                   = {Tang, Kar Yee},
+  Journal                  = {Whitepaper eSilicon},
+  Year                     = {2018},
+
+  Month                    = {April},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-24}
+}
+
+@Article{tan_81,
+  Title                    = {{A Recursive Approach to Low Complexity Codes}},
+  Author                   = {Tanner, R. M.},
+  Journal                  = {IEEE Transaction on Information Theory},
+  Year                     = {1981},
+
+  Month                    = sep,
+  Pages                    = {533--547},
+  Volume                   = {IT-27},
+
+  File                     = {tan_81.pdf:tan_81.pdf:PDF},
+  Optnote                  = {Introduction of the Tanner-graph},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{taonag_10,
+  Title                    = {{MIMO} and {C}o{MP} in {LTE}-{A}dvanced},
+  Author                   = {Hidekazu Taoka and Satoshi Nagata and Kazuaki Takeda and Yuichi Kakishima and Xiaoming She and Katsutoshi Kusume},
+  Journal                  = {NTT DOCOMO Technical Journal},
+  Year                     = {2010},
+  Number                   = {2},
+  Pages                    = {20--28},
+  Volume                   = {12},
+
+  File                     = {taonag_10.pdf:taonag_10.pdf:PDF},
+  Owner                    = {ilnseher},
+  Timestamp                = {2012.03.01}
+}
+
+@InProceedings{tarben_05,
+  Title                    = {{F}urther results on mapping functions},
+  Author                   = {Tarable, A. and Benedetto, S. },
+  Booktitle                = {Proc. IEEE Information Theory Workshop},
+  Year                     = {2005},
+  Month                    = aug # {--} # sep,
+  Pages                    = {5pp.},
+
+  Doi                      = {10.1109/ITW.2005.1531893},
+  File                     = {tarben_05.pdf:tarben_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@Article{tarben_04,
+  Title                    = {{M}apping interleaving laws to parallel turbo decoder architectures},
+  Author                   = {Alberto Tarable and Sergio Benedetto},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2004},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {162--164},
+  Volume                   = {8},
+
+  Abstract                 = {For high data rate applications, the implementation of iterative turbo-like decoders requires the use of parallel architectures posing some collision-free constraints to the reading/writing process in the soft-input soft-output (SISO) decoders. Contrary to the literature belief, we prove in this paper that the parallelism constraints can be met by any permutation law employed by the turbo-interleaver, and we give a constructive method to satisfy those constraints.},
+  Cds_grade                = {0},
+  File                     = {tarben_04.pdf:tarben_04.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{tarben_04a,
+  Title                    = {{M}apping interleaving laws to parallel turbo and {LDPC} decoder architectures},
+  Author                   = {Tarable, A. and Benedetto, S. and Montorsi, G.},
+  Journal                  = {IEEE TRANSACTIONS ON INFORMATION THEORY},
+  Year                     = {2004},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {2002--2009},
+  Volume                   = {50},
+
+  Doi                      = {10.1109/TIT.2004.833353},
+  File                     = {tarben_04a.pdf:tarben_04a.pdf:PDF},
+  Keywords                 = {Turbo, LDPC},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{tarben_03,
+  Title                    = {{M}apping interleaving laws to parallel {T}urbo decoder architectures},
+  Author                   = {Alberto Tarable and G. Montorsi and Sergio Benedetto},
+  Booktitle                = {Proc. 3rd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {153 -- 156},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{tarmon_01,
+  Title                    = {{Analysis and design of interleavers for CDMA systems}},
+  Author                   = {A. Tarable and G. Montorsi and S. Benedetto},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2001},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {420--422},
+  Volume                   = {5},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{taresk_17,
+  Title                    = {{D}esigning for {FPGA}s in the {C}loud},
+  Author                   = {Naif Tarafdar and Nariman Eskandari and Thomas Lin and Paul Chow},
+  Journal                  = {IEEE Design Test},
+  Year                     = {2017},
+  Number                   = {99},
+  Pages                    = {1-1},
+  Volume                   = {PP},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.22}
+}
+
+@Article{tarjaf_99,
+  Title                    = {{S}pace-time block codes from orthogonal designs},
+  Author                   = {Tarokh, V. and Jafarkhani, H. and Calderbank, A. R.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1999},
+  Number                   = {5},
+  Pages                    = {1456--1467},
+  Volume                   = {45},
+
+  Abstract                 = {We introduce space-time block coding, a new paradigm for communication over Rayleigh fading channels using multiple transmit antennas. Data is encoded using a space-time block code and the encoded data is split into n streams which are simultaneously transmitted using n transmit antennas. The received signal at each receive antenna is a linear superposition of the n transmitted signals perturbed by noise. Maximum-likelihood decoding is achieved in a simple way through decoupling of the signals transmitted from different antennas rather than joint detection. This uses the orthogonal structure of the space-time block code and gives a maximum-likelihood decoding algorithm which is based only on linear processing at the receiver. Space-time block codes are designed to achieve the maximum diversity order for a given number of transmit and receive antennas subject to the constraint of having a simple decoding algorithm. The classical mathematical framework of orthogonal designs is applied to construct space-time block codes. It is shown that space-time block codes constructed in this way only exist for few sporadic values of n. Subsequently, a generalization of orthogonal designs is shown to provide space-time block codes for both real and complex constellations for any number of transmit antennas. These codes achieve the maximum possible transmission rate for any number of transmit antennas using any arbitrary real constellation such as PAM. For an arbitrary complex constellation such as PSK and QAM, space-time block codes are designed that achieve 1/2 of the maximum possible transmission rate for any number of transmit antennas. For the specific cases of two, three, and four transmit antennas, space-time block codes are designed that achieve, respectively, all, 3/4, and 3/4 of maximum possible transmission rate using arbitrary complex constellations. The best tradeoff between the decoding delay and the number of transmit antennas is also computed and it is shown that many of the codes presented here are optimal in this sense as well},
+  Doi                      = {10.1109/18.771146},
+  File                     = {tarjaf_99.pdf:tarjaf_99.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {0018-9448},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@Article{tarses_98,
+  Title                    = {{S}pace-time codes for high data rate wireless communication: performance criterion and code construction},
+  Author                   = {Tarokh, V. and Seshadri, N. and Calderbank, A. R.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1998},
+  Number                   = {2},
+  Pages                    = {744--765},
+  Volume                   = {44},
+
+  Abstract                 = {We consider the design of channel codes for improving the data rate and/or the reliability of communications over fading channels using multiple transmit antennas. Data is encoded by a channel code and the encoded data is split into n streams that are simultaneously transmitted using n transmit antennas. The received signal at each receive antenna is a linear superposition of the n transmitted signals perturbed by noise. We derive performance criteria for designing such codes under the assumption that the fading is slow and frequency nonselective. Performance is shown to be determined by matrices constructed from pairs of distinct code sequences. The minimum rank among these matrices quantifies the diversity gain, while the minimum determinant of these matrices quantifies the coding gain. The results are then extended to fast fading channels. The design criteria are used to design trellis codes for high data rate wireless communication. The encoding/decoding complexity of these codes is comparable to trellis codes employed in practice over Gaussian channels. The codes constructed here provide the best tradeoff between data rate, diversity advantage, and trellis complexity. Simulation results are provided for 4 and 8 PSK signal sets with data rates of 2 and 3 bits/symbol, demonstrating excellent performance that is within 2-3 dB of the outage capacity for these channels using only 64 state encoders},
+  Doi                      = {10.1109/18.661517},
+  File                     = {tarses_98a.pdf:tarses_98a.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {0018-9448},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@Article{tau_65,
+  Title                    = {{R}andom {N}umbers {G}enerated by {L}inear {R}ecurrence {M}odulo {T}wo},
+  Author                   = {Tausworthe, Robert C.},
+  Journal                  = {Mathematics of Computation},
+  Year                     = {1965},
+  Number                   = {90},
+  Pages                    = {201--209},
+  Volume                   = {19},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {Tausworthe generation},
+  Cds_read                 = {2014-02-06},
+  Cds_review               = {Tausworthe algorithm},
+  Copyright                = {Copyright © 1965 American Mathematical Society},
+  File                     = {tau_65.pdf:tau_65.pdf:PDF},
+  ISSN                     = {00255718},
+  Jstor_articletype        = {research-article},
+  Jstor_formatteddate      = {Apr., 1965},
+  Keywords                 = {random numbers},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Publisher                = {American Mathematical Society},
+  Timestamp                = {2014.02.06},
+  Url                      = {http://www.jstor.org/stable/2003345}
+}
+
+@Article{tavkas_14,
+  Title                    = {{EFGR}: {A}n {E}nhanced {F}ine {G}ranularity {R}efresh {F}eature for {H}igh-{P}erformance {DDR}4 {DRAM} {D}evices},
+  Author                   = {Tavva, Venkata Kalyan and Kasha, Ravi and Mutyam, Madhu},
+  Journal                  = {ACM Trans. Archit. Code Optim.},
+  Year                     = {2014},
+
+  Month                    = oct,
+  Number                   = {3},
+  Pages                    = {31:1--31:26},
+  Volume                   = {11},
+
+  Acmid                    = {2656340},
+  Address                  = {New York, NY, USA},
+  Articleno                = {31},
+  Doi                      = {10.1145/2656340},
+  ISSN                     = {1544-3566},
+  Issue_date               = {October 2014},
+  Keywords                 = {DDR4, DRAM architecture, Fine-Granularity Refresh, activation energy, partial rank refresh, precharge, refresh, selective precharge},
+  Numpages                 = {26},
+  Owner                    = {MJ},
+  Publisher                = {ACM},
+  Timestamp                = {2015.07.13},
+  Url                      = {http://doi.acm.org/10.1145/2656340}
+}
+
+@InProceedings{taydey_01,
+  Title                    = {{Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies}},
+  Author                   = {C.N. Taylor and S. Dey and Y. Zhao},
+  Booktitle                = {Proc. Design Automation Conference, 2001},
+  Year                     = {2001},
+  Pages                    = {754--757},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{teapat_08,
+  Title                    = {{F}ield {R}esults on {MIMO} {P}erformance in {UMB} {S}ystems},
+  Author                   = {Teague, H. and Patel, C. and Gore, D. and Sampath, H. and Naguib, A. and Kadous, T. and Gorokhov, A. and Agrawal, A.},
+  Booktitle                = {Proc. IEEE Vehicular Technology Conference VTC Spring 2008},
+  Year                     = {2008},
+  Pages                    = {1009--1015},
+
+  Abstract                 = {The paper presents MIMO field performance results observed using a ultra mobile broadband (UMB) testbed network. We evaluate metrics such as antenna correlations and channel condition number to characterize the MIMO channel. Results show that low condition numbers, which are beneficial to MIMO, are prevalent for a majority of the coverage area in our network. We demonstrate that the use of MIMO provides gains of the order of 20-40% over SIMO transmissions. These gains are made possible by the use of cross-polarized transmit antennas and advanced UMB features that allow dynamic MIMO vs. SIMO transmission selection based on channel conditions. These results are obtained in a truly mobile, wireless wide-area deployment, which makes them unique. Our results point to the viability and value of MIMO in future mobile wireless networks.},
+  Doi                      = {10.1109/VETECS.2008.216},
+  File                     = {teapat_08.pdf:teapat_08.pdf:PDF},
+  Grade                    = {0},
+  ISSN                     = {1550-2252},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@TechReport{tec_14,
+  Title                    = {{U}sing {DDR}4 in {N}etworking {S}ubsystems},
+  Author                   = {Micron Technology},
+  Year                     = {2014},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-26}
+}
+
+@MastersThesis{MTteixe13,
+  Title                    = {{A} {W}eb {I}nterface for {A}ccessing {O}ption {P}ricer {I}mplementations {B}ased on the {H}eston {M}odel},
+  Author                   = {Guilherme Andrighetto Teixeira},
+  School                   = {Universidade Federal do Rio Grande do Sul, Brazil},
+  Year                     = {2013},
+  Month                    = oct,
+
+  Abstract                 = {This thesis shows the implementation of a flexible web-based framework to run option pricer algorithms over different architectures in order to compare speed and energy efficiency. With the increasing complexity of the algorithms and data analyzes for the financial market, a search for faster and more economical solutions has become necessary thus leading to the development of systems that fit these growing needs. Facing this context, this on-line demonstrator has been developed with the intention of allowing fair comparisons regarding to runtime and energy consumption by integrating a FPGAbased hardware accelerator for multi-level Monte Carlo simulations that is proven to be more efficient than other common solutions with respect to both attributes. In order to make the comparisons available, we present a web user interface working together with a Java back-end that implements a multi-thread job management system, which opens a TCP socket to communicate with a C++ application over the network. It uses XML as an information pattern with the purpose of providing data compatibility between the different programming languages, which are Java and C++. Although this approach is always challenging by the need to exchange information between systems based on either different languages or architectures, our solution allows everyone worldwide to trigger computations and retrieve results, that is, giving the chance to demonstrate the efficiency of the hardware accelerator. This solution has been developed intending to provide stable references to the public for the domain of financial mathematics.},
+  Cds_grade                = {4},
+  Cds_keywords             = {finance, Heston, web demonstrator},
+  Cds_read                 = {2013-10},
+  File                     = {MTteixe13.pdf:MTteixe13.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Article{tel_99,
+  Title                    = {{C}apacity of multi-antenna {G}aussian channels},
+  Author                   = {Telatar, I.E.},
+  Journal                  = {European Transactions on Telecommunications},
+  Year                     = {1999},
+  Pages                    = {585--595},
+  Volume                   = {10},
+
+  Owner                    = {kienle},
+  Timestamp                = {2008.03.20}
+}
+
+@Book{ten_01,
+  Title                    = {{Xtensa Microprocessor Data Book For Xtensa T1040 Processor Cores}},
+  Author                   = {{Tensilica Inc.}},
+  Publisher                = {Tensilica Inc.},
+  Year                     = {2001},
+
+  Optnote                  = {{http://www.tensilica.com}},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{tez_94,
+  Title                    = {{T}he k-dimensional {D}istribution of {C}ombined {GFSR} {S}equences},
+  Author                   = {Shu Tezuka},
+  Journal                  = {AMS Mathematics of Computation},
+  Year                     = {1994},
+  Pages                    = {809--817},
+  Volume                   = {62},
+
+  Abstract                 = {We develop an efficient method for analysis of the k-dimensional distribution of combinations of several GFSR sequences by bitwise exclusive-or operations. First, we introduce the notion of a resolution-wise lattice structure for GFSR sequences, and show that by applying a theorem of Couture to this type of lattice, we obtain a precise description of k-dimensional distribution of combined GFSR sequences in the same way as for combined Tausworthe sequences. Finally, we apply this method to the combination of two different Twisted GFSR generators, which were recently proposed by Matsumoto and Kurita, and investigate the order of equidistribution of the combined sequence.},
+  Cds_grade                = {0},
+  Cds_keywords             = {GFSR},
+  Doi                      = {10.1090/S0025-5718-1994-1223233-9},
+  File                     = {tez_94.pdf:tez_94.pdf:PDF},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.03}
+}
+
+@Misc{mathdl,
+  Title                    = {{HDL} {C}oder},
+
+  Author                   = {{The MathWorks, Inc.}},
+  HowPublished             = {\url{http://de.mathworks.com/products/hdl-coder}},
+  Note                     = {last access 2015-02-05},
+
+  Owner                    = {CDS},
+  Timestamp                = {2015-02-05}
+}
+
+@Misc{hpcchallenge,
+  Title                    = {{HPC} {C}hallenge {B}enchmark},
+
+  Author                   = {{The University of Tennessee Knoxville}},
+  HowPublished             = {\url{http://icl.cs.utk.edu/hpcc}},
+  Note                     = {last access 2015-02-14},
+
+  Language                 = {en},
+  Owner                    = {CDS},
+  Timestamp                = {2015-02-14},
+  Url                      = {http://icl.cs.utk.edu/hpcc}
+}
+
+@InProceedings{theg.l_05,
+  Title                    = {{Implementing LDPC Decoding on Network-On-Chip}},
+  Author                   = {T. Theocharides and G.Link and N. Vijaykrishnan and M.J.Irwin},
+  Booktitle                = {Proc. 18th International Conference on VLSI Design (VLSID'05)},
+  Year                     = {2005},
+
+  Address                  = {Taj Bengal, India},
+  Month                    = jan,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{thisig_17,
+  Title                    = {{H}uman body heat for powering wearable devices: {F}rom thermal energy to application},
+  Author                   = {Moritz Thielen and Lukas Sigrist and Michele Magno and Christofer Hierold and Luca Benini},
+  Journal                  = {Energy Conversion and Management},
+  Year                     = {2017},
+
+  Month                    = {Jan},
+  Pages                    = {44--54},
+  Volume                   = {131},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {noID20171},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Keywords                 = {TCS},
+  Owner                    = {CCR}
+}
+
+@Misc{3gpp,
+  Title                    = {{3GPP LTE (Long Term Evolution) Homepage}},
+
+  Author                   = {{Third Generation Partnership Project}},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2007.07.10},
+  Url                      = {{http://www.3gpp.org/Highlights/LTE/LTE.htm}}
+}
+
+@Misc{TGPP,
+  Title                    = {{3GPP LTE (Long Term Evolution) Homepage}},
+
+  Author                   = {{Third Generation Partnership Project}},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2007.07.10},
+  Url                      = {{http://www.3gpp.org/Highlights/LTE/LTE.htm}}
+}
+
+@Misc{TGPPa,
+  Title                    = {{3GPP home page}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3gpp,
+  Title                    = {{3GPP home page}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Manual{tgplte16,
+  Title                    = {{LTE; Evolved Universal Terrestrial Radio Access (E-UTRA); Physical layer procedures ((3GPP TS 36.213 version 13.1.1 Release 13) }},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = may,
+  Year                     = {2016},
+
+  Abstract                 = {3GPP LTE-Advanced Standard for channel coding, Release 13.1.1, 2016-05},
+  File                     = {tgplte16.pdf:tgplte16.pdf:PDF},
+  Keywords                 = {LTE, Standard, Turbo},
+  Owner                    = {StW},
+  Timestamp                = {2016.06.29}
+}
+
+@Manual{tgplte16a,
+  Title                    = {{LTE; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (3GPP TS 36.213 version 13.1.0 Release 13) }},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = apr,
+  Year                     = {2016},
+
+  Abstract                 = {3GPP LTE-Advanced Standard for channel coding, Release 13.1.0, 2016-04},
+  File                     = {tgplte16a.pdf:tgplte16a.pdf:PDF},
+  Keywords                 = {LTE, Standard, Turbo},
+  Owner                    = {StW},
+  Timestamp                = {2016.06.29}
+}
+
+@Manual{3gpp_lte_15,
+  Title                    = {{LTE; Evolved Universal Terrestrial Radio Access (E-UTRA); Physical layer procedures ((3GPP TS 36.213 version 12.4.0 Release 12) }},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = feb,
+  Year                     = {2015},
+
+  Abstract                 = {3GPP LTE-Advanced Standard for channel coding, Release 12.4.0, 2015-02},
+  File                     = {3pp_lte_14.pdf:3pp_lte_14.pdf:PDF},
+  Keywords                 = {LTE, Standard, Turbo},
+  Owner                    = {StW},
+  Timestamp                = {2015.11.19}
+}
+
+@Manual{3pp_lte_14,
+  Title                    = {{LTE; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (3GPP TS 36.212 version 11.5.1 Release 11) }},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = oct,
+  Year                     = {2014},
+
+  Abstract                 = {3GPP LTE-Advanced Standard for channel coding, Release 11.5.1, 2014-10},
+  File                     = {3pp_lte_14.pdf:3pp_lte_14.pdf:PDF},
+  Keywords                 = {LTE, Standard, Turbo},
+  Owner                    = {StW},
+  Timestamp                = {2014.11.18}
+}
+
+@Manual{th3gpp11,
+  Title                    = {{3GPP TS 36.212 V10.1.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (Release 10)}},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = apr,
+  Year                     = {2011},
+
+  Abstract                 = {3GPP LTE-Advanced Standard for channel coding, Release 10.1.0, 2011-04},
+  File                     = {th3gpp11.pdf:th3gpp11.pdf:PDF},
+  Keywords                 = {Standard, Turbo},
+  Owner                    = {may},
+  Timestamp                = {2011.11.30}
+}
+
+@Manual{3gpp_lte_10,
+  Title                    = {{3GPP TS 36.212 V10.0.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (Release 10)}},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = dec,
+  Year                     = {2010},
+
+  Abstract                 = {3GPP LTE Standard for channel coding},
+  Owner                    = {ilnseher},
+  Timestamp                = {2010.01.07}
+}
+
+@Manual{3gpp_lte,
+  Title                    = {{3GPP TS 36.212 V8.5.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (Release 8)}},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = dec,
+  Year                     = {2008},
+
+  Abstract                 = {3GPP LTE Standard for channel coding},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.01.07},
+  Url                      = {www.3gpp.org}
+}
+
+@Manual{th3gpp09,
+  Title                    = {{3GPP TS 25.212 V7.7.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD) (Release 7)}},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = nov,
+  Year                     = {2007},
+
+  Comment                  = {3GPP HSPA+ Standard},
+  HowPublished             = {{www.3gpp.org}},
+  Keywords                 = {Standard, Turbo},
+  Owner                    = {StW},
+  Timestamp                = {2011.11.30},
+  Url                      = {www.3gpp.org}
+}
+
+@Manual{th3gpp06,
+  Title                    = {{3GPP TS 25.212 V6.10.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD)}},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = dec,
+  Year                     = {2006},
+
+  Comment                  = {3GPP Release 6, HSPA (HSDPA and HSUPA) Standard},
+  File                     = {th3gpp06.pdf:th3gpp06.pdf:PDF},
+  HowPublished             = {{www.3gpp.org}},
+  Keywords                 = {Standard, Turbo},
+  Owner                    = {may},
+  Timestamp                = {2011.11.30},
+  Url                      = {www.3gpp.org}
+}
+
+@Manual{3gpp_gsm,
+  Title                    = {{3GPP TS 05.03 V8.9.0; 3rd Generation Partnership Project; Technical Specification Group GSM/EDGE Radio Access Network; Channel coding (Release 1999)}},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = jan,
+  Year                     = {2005},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.01.28},
+  Url                      = {{www.3gpp.org/ftp/Specs/archive/05\_series/05.03/0503-890.zip}}
+}
+
+@Misc{TGPP2002,
+  Title                    = {{3GPP TS 25.306 V5.0.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; UE Radio Access capabilities}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = mar,
+  Year                     = {2002},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{TGPP2002a,
+  Title                    = {{3GPP TS 25.302 V5.3.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Services provided by the physical layer}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = dec,
+  Year                     = {2002},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{TGPP2002b,
+  Title                    = {{3GPP TS 25.212 V5.3.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding(FDD) (Release 5)}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = dec,
+  Year                     = {2002},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{TGPP2002c,
+  Title                    = {{3GPP TS 25.101 V5.3.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; UE Radio Transmission and Reception (FDD)}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = jun,
+  Year                     = {2002},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3rd02,
+  Title                    = {{3GPP TS 25.306 V5.0.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; UE Radio Access capabilities}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = mar,
+  Year                     = {2002},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3rd02a,
+  Title                    = {{3GPP TS 25.302 V5.3.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Services provided by the physical layer}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = dec,
+  Year                     = {2002},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3rd02b,
+  Title                    = {{3GPP TS 25.212 V5.3.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding(FDD)}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = dec,
+  Year                     = {2002},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3rd02c,
+  Title                    = {{3GPP TS 25.101 V5.3.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; UE Radio Transmission and Reception (FDD)}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = jun,
+  Year                     = {2002},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{TGPP2000,
+  Title                    = {{3GPP TS 25.212 V3.4.0}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = sep,
+  Year                     = {2000},
+
+  Key                      = {3gppturbo},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3gpp00,
+  Title                    = {{3GPP TS 25.212 V3.4.0}},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = sep,
+  Year                     = {2000},
+
+  Key                      = {3gppturbo},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Manual{3gpp_r99,
+  Title                    = {{3GPP TS 25.212 V1.0.0; 3rd Generation Partnership Project (3GPP);Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD)}},
+  Author                   = {{Third Generation Partnership Project}},
+  Month                    = apr,
+  Year                     = {1999},
+
+  Comment                  = {3GPP UMTS Standard for channel coding first release},
+  HowPublished             = {{www.3gpp.org}},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.01.07},
+  Url                      = {www.3gpp.org}
+}
+
+@Misc{TGPP1999a,
+  Title                    = {{3GPP TS 25.213 V3.1.1; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Spreading and modulation(FDD) }},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = dec,
+  Year                     = {1999},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3rd99,
+  Title                    = {{3GPP TS 25.213 V3.1.1; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Spreading and modulation(FDD) }},
+
+  Author                   = {{Third Generation Partnership Project}},
+  HowPublished             = {{{www.3gpp.org}}},
+  Month                    = dec,
+  Year                     = {1999},
+
+  Key                      = {3gpp},
+  Optnote                  = {Standardization of UMTS},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{TGPPb,
+  Title                    = {{3GPP2 home page}},
+
+  Author                   = {{Third Generation Partnership Project 2}},
+  HowPublished             = {{{www.3gpp2.org}}},
+
+  Key                      = {3gpp2},
+  Optnote                  = {Standardization of CDMA2000},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3gpp2,
+  Title                    = {{3GPP2 home page}},
+
+  Author                   = {{Third Generation Partnership Project 2}},
+  HowPublished             = {{{www.3gpp2.org}}},
+
+  Key                      = {3gpp2},
+  Optnote                  = {Standardization of CDMA2000},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{TGPP2000a,
+  Title                    = {{3GPP2 C.S0002-A}},
+
+  Author                   = {{Third Generation Partnership Project 2}},
+  HowPublished             = {{{www.3gpp2.org}}},
+  Month                    = jun,
+  Year                     = {2000},
+
+  Key                      = {3gpp2turbo},
+  Optnote                  = {Standardization of cdma2000},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{th3gpp200,
+  Title                    = {{3GPP2 C.S0002-A}},
+
+  Author                   = {{Third Generation Partnership Project 2}},
+  HowPublished             = {{{www.3gpp2.org}}},
+  Month                    = jun,
+  Year                     = {2000},
+
+  Key                      = {3gpp2turbo},
+  Optnote                  = {Standardization of cdma2000},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{thokuh_07,
+  Title                    = {{MORPHEUS}: {H}eterogeneous {R}econfigurable {C}omputing},
+  Author                   = {Thoma, F. and Kuhnle, M. and Bonnot, P. and Panainte, E.M. and Bertels, K. and Goller, S. and Schneider, A. and Guyetant, S. and Schuler, E. and Müller-Glaser, K.D. and Becker, J.},
+  Booktitle                = {Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on},
+  Year                     = {2007},
+  Month                    = {Aug},
+  Pages                    = {409-414},
+
+  Doi                      = {10.1109/FPL.2007.4380681},
+  Keywords                 = {reconfigurable architectures;system-on-chip;MORPHEUS;heterogeneous reconfigurable SoC;heterogeneous reconfigurable computing;network-on-chip communication system;reconfigurable architecture;reconfiguration granularity;system-on-chip;Application software;Communication system control;Computer architecture;Control systems;Delay;Hardware;Network-on-a-chip;Reconfigurable architectures;Runtime;System-on-a-chip},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@InProceedings{tho_16,
+  Title                    = {{O}ptimal {DDR}4 {S}ystem with {D}ata {B}us {I}nversion ({DBI})},
+  Author                   = {Thomas To, Changyi Su},
+  Booktitle                = {Design Con},
+  Year                     = {2016},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-05-02}
+}
+
+@InBook{thobec_07,
+  Title                    = {it - {I}nformation {T}echnology},
+  Author                   = {Alexander Thomas and Jürgen Becker},
+  Chapter                  = {New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur)},
+  Pages                    = {165--173},
+  Year                     = {2007},
+  Number                   = {3},
+  Volume                   = {49},
+
+  Doi                      = {10.1524/itit.2007.49.3.165},
+  Owner                    = {CdS},
+  Timestamp                = {2011.09.27}
+}
+
+@InProceedings{thobec_05,
+  Title                    = {{Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment}},
+  Author                   = {Thomas, A. and Becker, J.},
+  Booktitle                = {SOC Conference, 2005. Proceedings. IEEE International},
+  Year                     = {2005},
+  Month                    = sep,
+  Pages                    = {239--242},
+
+  Doi                      = {10.1109/SOCC.2005.1554502},
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.26}
+}
+
+@Misc{Thomas2003,
+  Title                    = {{Multigranulare Datenpfadrekonfiguration unter Anwendung adaptiver Verdrahtung zur Laufzeit}},
+
+  Author                   = {A. Thomas and K.D. Mueller-Glaser and J. Becker},
+  HowPublished             = {{{www12.informatik.uni-erlangen.de/spprr/colloquium02/itiv-karlsruhe-AMURHA.pdf}}},
+  Month                    = jul,
+  Note                     = {{DFG-Colloquium}},
+  Year                     = {2003},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{thomultigranulare03,
+  Title                    = {{Multigranulare Datenpfadrekonfiguration unter Anwendung adaptiver Verdrahtung zur Laufzeit}},
+
+  Author                   = {A. Thomas and K.D. Mueller-Glaser and J. Becker},
+  HowPublished             = {{{www12.informatik.uni-erlangen.de/spprr/colloquium02/itiv-karlsruhe-AMURHA.pdf}}},
+  Month                    = jul,
+  Note                     = {{DFG-Colloquium}},
+  Year                     = {2003},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{thobic_03,
+  Title                    = {{Integrated Circuits for Channel Coding in 3G Cellular Mobile Wireless Systems}},
+  Author                   = {C. Thomas and Bickerstaff, M. A. and Davis, L. M. and T. Prokop and B. Widdup and G. Zhou and D. Garrett and C. Nicol},
+  Journal                  = {IEEE Communications Magazine},
+  Year                     = {2003},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {150--159},
+  Volume                   = {41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{tholuk_13,
+  Title                    = {{M}ultiplierless {A}lgorithm for {M}ultivariate {G}aussian {R}andom {N}umber {G}eneration in {FPGA}s},
+  Author                   = {Thomas, D.B. and Luk, W.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2013},
+
+  Month                    = dec,
+  Number                   = {12},
+  Pages                    = {2193-2205},
+  Volume                   = {21},
+
+  Abstract                 = {The multivariate Gaussian distribution is used to model random processes with distinct pair-wise correlations, such as stock prices that tend to rise and fall together. Multivariate Gaussian vectors with length n are usually produced by first generating a vector of n independent Gaussian samples, then multiplying with a correlation inducing matrix requiring O(n2) multiplications. This paper presents a method of generating vectors directly from the uniform distribution, removing the need for an expensive scalar Gaussian generator, and eliminating the need for any multipliers. The method relies only on small read-only memories and adders, and so can be implemented using only logic resources (lookup-tables and registers), saving multipliers, and block-memory resources for the numerical simulation that the multivariate generator is driving. The new method provides a ten times increase in performance (vectors/second) over the fastest existing field-programmable gate array generation method, and also provides a five times improvement in performance per resource over the most efficient existing method. Using this method, a single 400-MHz Virtex-5 FPGA can generate vectors ten times faster than an optimized implementation on a 1.2-GHz graphics processing unit, and a hundred times faster than vectorized software on a general purpose quad core 2.2-GHz processor.},
+  Cds_grade                = {0},
+  Cds_keywords             = {Gaussian random numbers},
+  Doi                      = {10.1109/TVLSI.2012.2228017},
+  File                     = {tholuk_13.pdf:tholuk_13.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@Article{tholuk_13a,
+  Title                    = {{T}he {LUT}-{SR} {F}amily of {U}niform {R}andom {N}umber {G}enerators for {FPGA} {A}rchitectures},
+  Author                   = {Thomas, D.B. and Luk, W.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2013},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {761-770},
+  Volume                   = {21},
+
+  Abstract                 = {Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. However, it is difficult to concisely describe FPGA-optimized RNGs, so they are not commonly used in real-world designs. This paper describes a type of FPGA RNG called a LUT-SR RNG, which takes advantage of bitwise xor operations and the ability to turn lookup tables (LUTs) into shift registers of varying lengths. This provides a good resource–quality balance compared to previous FPGA-optimized generators, between the previous high-resource high-period LUT-FIFO RNGs and low-resource low-quality LUT-OPT RNGs, with quality comparable to the best software generators. The LUT-SR generators can also be expressed using a simple C++ algorithm contained within this paper, allowing 60 fully-specified LUT-SR RNGs with different characteristics to be embedded in this paper, backed up by an online set of very high speed integrated circuit hardware description language (VHDL) generators and test benches.},
+  Cds_grade                = {0},
+  Cds_keywords             = {uniform random numbers, FPGA},
+  Doi                      = {10.1109/TVLSI.2012.2194171},
+  File                     = {tholuk_13a.pdf:tholuk_13a.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@InProceedings{tholuk_10,
+  Title                    = {{FPGA}-{O}ptimised {U}niform {R}andom {N}umber {G}enerators {U}sing {LUT}s and {S}hift {R}egisters},
+  Author                   = {Thomas, D.B. and Luk, W.},
+  Booktitle                = {Field Programmable Logic and Applications (FPL), 2010 International Conference on},
+  Year                     = {2010},
+  Month                    = aug,
+  Pages                    = {77-82},
+
+  Abstract                 = {FPGA-optimised Random Number Generators (RNGs) are more resource efficient than software-optimised RNGs, as they can take advantage of bit-wise operations and FPGA-specific features. However, it is difficult to concisely describe FPGA-optimised RNGs, so they are not commonly used in real-world designs. This paper describes a new type of FPGA RNG called a LUT-SR RNG, which takes advantage of bit-wise XOR operations and the ability to turn LUTs into shift-registers of varying lengths. This provides a good resource-quality balance compared to previous FPGA-optimised generators, between the previous high-resource high-quality LUT-FIFO RNGs and low-resource low-quality LUT-OPT RNGs. The LUT-SR generators can also be expressed using a simple C++ algorithm contained within the paper, allowing 60 fully-specified LUT-SR RNGs with different characteristics to be embedded in the paper, backed up by an online set of VHDL generators and test-benches.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPL.2010.25},
+  File                     = {tholuk_10.pdf:tholuk_10.pdf:PDF},
+  ISSN                     = {1946-1488},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@Misc{thorejection,
+  Title                    = {{Rejection methods on GPUs}},
+
+  Author                   = {David B. Thomas},
+  HowPublished             = {Online: \url{http://cas.ee.ic.ac.uk/people/dt10/research/rngs-gpu-rejection.html}},
+  Note                     = {Last access: 27 Nov 2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@Electronic{tho_11,
+  Title                    = {{E}xploiting spatial parallelism to improve both speed and accuracy in financial computing},
+  Author                   = {David B. Thomas},
+  Language                 = {en},
+  Note                     = {talk at DATE Conference 2011, last access 2014-01-24},
+  Url                      = {\url{http://cas.ee.ic.ac.uk/people/gac1/DATE2011/Thomas.pdf}},
+  Year                     = {2011},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {finance, HPC, Monte Carlo},
+  File                     = {tho_11.pdf:tho_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24}
+}
+
+@InProceedings{thobow_07,
+  Title                    = {{A}utomatic {G}eneration and {O}ptimisation of {R}econfigurable {F}inancial {M}onte-{C}arlo {S}imulations},
+  Author                   = {David B. Thomas and Jacob A. Bower and Wayne Luk},
+  Booktitle                = {Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on},
+  Year                     = {2007},
+  Month                    = jul,
+  Pages                    = {168 -173},
+
+  Abstract                 = {Monte-Carlo simulations are used in many applications, such as option pricing and portfolio evaluation. Due to their high computational load and intrinsic parallelism, they are ideal candidates for acceleration using reconfigurable hardware. However, for maximum efficiency the hardware configuration must be parametrised to match the characteristics of both the simulation task and the platform on which it will be executed. This paper presents a methodology for the automatic implementation of Monte-Carlo simulations, starting from a high-level mathematical description of the simulation and resulting in an optimised hardware configuration for a given platform. This process automatically generates fully-pipelined hardware for maximum performance; it also maximises thread-level parallelism by instantiating multiple pipelines to optimise device utilisation. The configured hardware is used by an associated software component to execute simulations using run-time supplied parameters. The proposed methodology is demonstrated by five different Monte-Carlo simulations, including log-normal price movements, correlated asset Value-at-Risk calculation, and price movements under the GARCH model. Our results show that hardware implementations from our approach, on a Xilinx Virtex-4 XC4VSX55 FPGA at 150 MHz, can run on-average 80 times faster than software on a 2.66 GHz Xeon PC.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/ASAP.2007.4429975},
+  File                     = {thobow_07.pdf:thobow_07.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.25}
+}
+
+@InProceedings{thobow_06,
+  Title                    = {{H}ardware {A}rchitectures for {M}onte-{C}arlo based {F}inancial {S}imulations},
+  Author                   = {David B. Thomas and Jacob A. Bower and Wayne Luk},
+  Booktitle                = {Proc. IEEE Int. Conf. Field Programmable Technology FPT 2006},
+  Year                     = {2006},
+  Pages                    = {377--380},
+
+  Abstract                 = {This paper presents a methodology and the results of implementing Monte-Carlo financial simulations in reconfigurable devices. Five different Monte-Carlo simulations are explored, including log-normal price movements, correlated asset value-at-risk calculation, and price movements under the GARCH model. Our results show that hardware implementations from our approach on a Xilinx Virtex-4 XC4VSX55 device run on-average 80 times faster than software on a 2.66GHz PC},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPT.2006.270352},
+  File                     = {thobow_06.pdf:thobow_06.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.23}
+}
+
+@InProceedings{thohow_09,
+  Title                    = {{A} {C}omparison of {CPU}s, {GPU}s, {FPGA}s, and {M}assively {P}arallel {P}rocessor {A}rrays for {R}andom {N}umber {G}eneration},
+  Author                   = {David Barrie Thomas and Lee Howes and Wayne Luk},
+  Booktitle                = {Proceeding of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
+  Year                     = {2009},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {63--72},
+  Publisher                = {ACM},
+  Series                   = {FPGA '09},
+
+  Abstract                 = {The future of high-performance computing is likely to rely on the ability to efficiently exploit huge amounts of parallelism. One way of taking advantage of this parallelism is to formulate problems as "embarrassingly parallel" Monte-Carlo simulations, which allow applications to achieve a linear speedup over multiple computational nodes, without requiring a super-linear increase in inter-node communication. However, such applications are reliant on a cheap supply of high quality random numbers, particularly for the three main maximum entropy distributions: uniform, used as a general source of randomness; Gaussian, for discrete-time simulations; and exponential, for discrete-event simulations. In this paper we look at four different types of platform: conventional multi-core CPUs (Intel Core2); GPUs (NVidia GTX 200); FPGAs (Xilinx Virtex-5); and Massively Parallel Processor Arrays (Ambric AM2000). For each platform we determine the most appropriate algorithm for generating each type of number, then calculate the peak generation rate and estimated power efficiency for each device.},
+  Acmid                    = {1508139},
+  Cds_grade                = {5},
+  Cds_keywords             = {random numbers, non-uniform random numbers, CPU, GPU, FPGA, comparison, evaluation, energy, performance, efficiency, Monte Carlo},
+  Cds_read                 = {2011-11-11},
+  Cds_review               = {+ use of metrics "computations per Joule" and "computations per time"
++ detailed description of random number generators used
++ summary of suitable generation methods for uniform and non-uniform RNs (table)
+
+- missing detailed descriptions for energy measurement scenario
+
+FPGA provides more than one decade energy efficiency than any other platform, and > 250 times more than 3 GHz quad-core CPU.},
+  Doi                      = {http://doi.acm.org/10.1145/1508128.1508139},
+  File                     = {thohow_09.pdf:thohow_09.pdf:PDF},
+  ISBN                     = {978-1-60558-410-2},
+  Keywords                 = {finance},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {10},
+  Owner                    = {CdS},
+  Timestamp                = {2011.01.05},
+  Url                      = {http://doi.acm.org/10.1145/1508128.1508139}
+}
+
+@InProceedings{tholuk_08,
+  Title                    = {{C}redit {R}isk {M}odelling using {H}ardware {A}ccelerated {M}onte-{C}arlo {S}imulation},
+  Author                   = {Thomas, D. B. and Wayne Luk},
+  Booktitle                = {Proc. 16th Int. Symp. Field-Programmable Custom Computing Machines FCCM '08},
+  Year                     = {2008},
+  Month                    = apr,
+  Pages                    = {229--238},
+
+  Abstract                 = {The recent turmoil in global credit markets has demonstrated the need for advanced modeling of credit risk, which can take into account the effects of changing economic conditions on portfolios of loans. Such models are most easily described as Monte-Carlo simulations, but take too long to converge in software based simulators. This paper describes a hardware implementation of a loan portfolio simulator, which uses an event based model to describe changes both in prevailing economic conditions, and the behaviour of individual loans within the portfolio. Three distinct variants of the simulator are developed using transformations of the simulation algorithm, with each variant trading off area utilisation against the efficiency with which different event types can be processed. As the distribution of event types is highly dependent on the input data, each of the three variants provides the highest overall performance per FPGA for some set of input data characteristics. The hardware simulators are implemented using a Virtex-4 xc4vsx55 device running at 233 MHz in an RC2000 PCI card, and compared to four parallel software simulation threads running in a quad-core Pentium-4 Core2 at 2.4 GHz, providing a speed-up of between 60 and 100 times.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FCCM.2008.41},
+  File                     = {tholuk_08.pdf:tholuk_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.23}
+}
+
+@InProceedings{tholuk_08a,
+  Title                    = {{FPGA}-{O}ptimised {H}igh-{Q}uality {U}niform {R}andom {N}umber {G}enerators},
+  Author                   = {David Barrie Thomas and Wayne Luk},
+  Booktitle                = {Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays},
+  Year                     = {2008},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {235--244},
+  Publisher                = {ACM},
+  Series                   = {FPGA '08},
+
+  Abstract                 = {This paper introduces a method of constructing random numbergenerators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. The construction methodis designed to ensure maximum clock rates, while using the minimum of resources, and providing statistical quality at the level of the best software generators. In all platforms tested, the generators are limited in speed only by the clock distribution network or the maximum clockspeed of the underlying RAM primitives, using a platform independent VHDL description with no placement or other hints. The area utilisation is also very low, with a Virtex-5 generator requiring just one Block-RAMand 41 slices to produce 48Gb/s at 550MHz: over 14 times faster than the commonly used Mersenne-Twister RNG on an Opteron at 2.2GHz, while providing the same level of quality},
+  Acmid                    = {1344706},
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generator, FPGA},
+  Doi                      = {10.1145/1344671.1344706},
+  File                     = {tholuk_08a.pdf:tholuk_08a.pdf:PDF},
+  ISBN                     = {978-1-59593-934-0},
+  Keywords                 = {finance},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {10},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.14},
+  Url                      = {http://doi.acm.org/10.1145/1344671.1344706}
+}
+
+@InProceedings{tholuk_07a,
+  Title                    = {{A} {D}omain {S}pecific {L}anguage for {R}econfigurable {P}ath-based {M}onte {C}arlo {S}imulations},
+  Author                   = {David B. Thomas and Wayne Luk},
+  Booktitle                = {Field-Programmable Technology, 2007. ICFPT 2007. International Conference on},
+  Year                     = {2007},
+  Month                    = dec,
+  Pages                    = {97 -104},
+
+  Abstract                 = {FPGAs have been successfully used to accelerate many computationally bound applications, such as high-performance Monte-Carlo simulations, but the amount of programmer effort required in development, testing, and tuning is also very high, requiring a new custom design for each application. This paper presents Contessa, a pure-functional continuation-based language for describing path-based Monte-Carlo simulations, and a completely automated method for turning platform-independent Contessa programs into high-performance hardware implementations. Our approach exploits the large degree of thread-based parallelism available in Monte-Carlo simulations, allowing data-dependent control-flow and loop-carried dependencies to be expressed, while retaining high-performance. The Contessa toolchain is evaluated using five different simulation kernels, in comparison to both software and manually described hardware. When compared to an existing FPGA implementation, Contessa requires a quarter of the Handel-C source-code length, and doubles the clock rate to over 300MHz while requiring a similar number of resources, and also provides a 35 times speedup over a C++ implementation using an Opteron 2.2GHz.},
+  Cds_grade                = {0},
+  Cds_keywords             = {GARCH},
+  Doi                      = {10.1109/FPT.2007.4439237},
+  File                     = {tholuk_07a.pdf:tholuk_07a.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.25}
+}
+
+@Article{tholuk_07,
+  Title                    = {{G}aussian {R}andom {N}umber {G}enerators},
+  Author                   = {Thomas, David B. and Luk, Wayne and Leong, Philip H.W. and Villasenor, John D.},
+  Journal                  = {ACM Comput. Surv.},
+  Year                     = {2007},
+
+  Month                    = oct,
+  Number                   = {4},
+  Pages                    = {11},
+  Volume                   = {39},
+
+  Abstract                 = {Rapid generation of high quality Gaussian random numbers is a key capability for simulations across a wide range of disciplines. Advances in computing have brought the power to conduct simulations with very large numbers of random numbers and with it, the challenge of meeting increasingly stringent requirements on the quality of Gaussian random number generators (GRNG). This article describes the algorithms underlying various GRNGs, compares their computational requirements, and examines the quality of the random numbers with emphasis on the behaviour in the tail region of the Gaussian probability density function.},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {5},
+  Cds_keywords             = {random numbers, RNGs, test, Box-Muller, ICDF, Ziggurat},
+  Cds_read                 = {2010-07-21},
+  Cds_review               = {compact overview over Gaussian RNGs, floating point conversion and tests for random numbers with a lot of references},
+  Doi                      = {http://doi.acm.org/10.1145/1287620.1287622},
+  File                     = {tholuk_07.pdf:tholuk_07.pdf:PDF},
+  ISSN                     = {0360-0300},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2010.07.21}
+}
+
+@InProceedings{thocha_12,
+  Title                    = {{A} {P}redictor-{B}ased {P}ower-{S}aving {P}olicy for {DRAM} {M}emories},
+  Author                   = {G. Thomas and K. Chandrasekar and B. Åkesson and B. Juurlink and K. Goossens},
+  Booktitle                = {2012 15th Euromicro Conference on Digital System Design},
+  Year                     = {2012},
+  Month                    = {Sept},
+  Pages                    = {882-889},
+
+  Doi                      = {10.1109/DSD.2012.11},
+  Keywords                 = {DRAM chips;power aware computing;battery-driven handheld devices;computer systems;energy consumption;energy savings;history-based predictor;marginal performance penalty;off-chip DRAM memory;power saving modes;power-down mode;power-hungry components;power-up latency;predictor-based power-saving policy;self-refresh mode;Clocks;Energy consumption;History;Memory management;Prediction algorithms;Random access memory;Servers;DRAM-Memory;Power-Down;Predictor;Predictor-based Power Saving Policy;Self-Refresh},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-22}
+}
+
+@InProceedings{thoahn_08,
+  Title                    = {{A} {C}omprehensive {M}emory {M}odeling {T}ool and {I}ts {A}pplication to the {D}esign and {A}nalysis of {F}uture {M}emory {H}ierarchies},
+  Author                   = {Thoziyoor, S. and Ahn, Jung-Ho and Monchiero, M. and Brockman, J.B. and Jouppi, N.P.},
+  Booktitle                = {Computer Architecture, 2008. ISCA '08. 35th International Symposium on},
+  Year                     = {2008},
+  Month                    = jun,
+  Pages                    = {51--62},
+
+  Abstract                 = {In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs. We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logic process based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.},
+  Cds_grade                = {0},
+  Cds_keywords             = {power, scaling, GPU},
+  Doi                      = {10.1109/ISCA.2008.16},
+  File                     = {thoahn_08.pdf:thoahn_08.pdf:PDF},
+  ISSN                     = {1063-6897},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@PhdThesis{Phdthul05,
+  Title                    = {{P}arallel {I}nterleaving {A}rchitectures for {H}igh {T}hroughput {T}urbo-{D}ecoders},
+  Author                   = {Thul, M. J.},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2005},
+  Note                     = {ISBN 3-936890-62-5},
+
+  Cds_grade                = {0},
+  File                     = {Phdthul05.pdf:Phdthul05.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{thu_01,
+  Title                    = {{Exploration of the Interleaver Bottleneck in Iterative Decoding using Parallel Architectures and a Proposal How to Overcome It}},
+  Author                   = {M. J. Thul},
+  Institution              = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2001},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTthul00,
+  Title                    = {{Exploration of a Reduced-Search MAP-Algorithm for Optimized Memory Schemes}},
+  Author                   = {M. J. Thul},
+  School                   = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2000},
+  Month                    = oct,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{thugil_05,
+  Title                    = {{A Scalable System Architecture for High-Throughput Turbo-Decoders}},
+  Author                   = {Thul, M. J. and F. Gilbert and T. Vogt and G. Kreiselmaier and N. Wehn},
+  Journal                  = {Journal of VLSI Signal Processing Systems (Special Issue on Signal Processing for Broadband Communications)},
+  Year                     = {2005},
+  Note                     = {Springer Science and Business Media, Netherlands},
+  Number                   = {1/2},
+  Pages                    = {63--77},
+  Volume                   = {39},
+
+  File                     = {thugil_05.pdf:thugil_05.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{thugil_02,
+  Title                    = {{A Scalable System Architecture for High-Throughput Turbo-Decoders}},
+  Author                   = {M. J. Thul and F. Gilbert and T. Vogt and G. Kreiselmaier and N. Wehn},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems (SIPS '02)},
+  Year                     = {2002},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = oct,
+  Pages                    = {152--158},
+
+  File                     = {thugil_02.pdf:thugil_02.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{thugil_03,
+  Title                    = {{Concurrent Interleaving Architectures for High-Throughput Channel Coding}},
+  Author                   = {M. J. Thul and F. Gilbert and N. Wehn},
+  Booktitle                = {Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '03)},
+  Year                     = {2003},
+
+  Address                  = {Hong Kong, P.R.China},
+  Month                    = apr,
+  Pages                    = {613--616},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{thugil_02a,
+  Title                    = {{Optimized Concurrent Interleaving Architecture for High-Throughput Turbo-Decoding}},
+  Author                   = {M. J. Thul and F. Gilbert and N. Wehn},
+  Booktitle                = {Proc. 9th International Conference on Electronics, Circuits and Systems},
+  Year                     = {2002},
+
+  Address                  = {Dubrovnik, Croatia},
+  Month                    = sep,
+  Pages                    = {1099--1102},
+
+  File                     = {thugil_02a.pdf:thugil_02a.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{thukie_03,
+  Title                    = {{A Survey on LDPC- and Turbo-Decoder Implementations}},
+  Author                   = {M. J. Thul and F. Kienle and N. Wehn},
+  Booktitle                = {International Conference on Software, Telecommunications and Computer Networks (SoftCOM 2003)},
+  Year                     = {2003},
+
+  Address                  = {Venice, Italy},
+  Pages                    = {122-126},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{thuvog_02,
+  Title                    = {{Evaluation of Algorithm Optimizations for Low-Power Turbo-Decoder Implementations}},
+  Author                   = {M. J. Thul and T. Vogt and F. Gilbert and N. Wehn},
+  Booktitle                = {Proc. 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '02)},
+  Year                     = {2002},
+
+  Address                  = {Orlando, Florida, USA},
+  Month                    = may,
+  Pages                    = {3101--3104},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{thuweh_04,
+  Title                    = {{FPGA Implementation of Parallel Turbo Decoders}},
+  Author                   = {M. J. Thul and N. Wehn},
+  Booktitle                = {Proc. 17th Symposium on Integrated Circuits and Systems Design SBCCI 2004},
+  Year                     = {2004},
+
+  Address                  = {Porto de Galinhas, Brazil},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{thuweh_02,
+  Title                    = {{Enabling High-Speed Turbo-Decoding Through Concurrent Interleaving}},
+  Author                   = {M. J. Thul and N. Wehn and L. P. Rao},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2002},
+  Year                     = {2002},
+
+  Address                  = {Phoenix, Arizona, USA},
+  Month                    = may,
+  Pages                    = {897--900},
+
+  File                     = {thuweh_02.pdf:thuweh_02.pdf:PDF},
+  Keywords                 = {AGWehn, Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{thudan_12,
+  Title                    = {{F}ast {M}orphological {I}mage {P}rocessing {O}pen-{S}ource {E}xtensions for {GPU} {P}rocessing {W}ith {CUDA}},
+  Author                   = {Thurley, M.J. and Danell, V.},
+  Journal                  = {Selected Topics in Signal Processing, IEEE Journal of},
+  Year                     = {2012},
+
+  Month                    = {Nov},
+  Number                   = {7},
+  Pages                    = {849-855},
+  Volume                   = {6},
+
+  Doi                      = {10.1109/JSTSP.2012.2204857},
+  ISSN                     = {1932-4553},
+  Keywords                 = {graphics processing units;image processing;image sensors;parallel architectures;public domain software;shared memory systems;3D range sensors;CUDA NPP library;CUDA multiprocessors;GPU architectures;GPU processing;LTU-CUDA;NVIDIA CUDA architecture;dilation operation;fast morphological image processing;generic morphological erosion;horizontal structuring element;open-source extensions;shared memory;structuring element size;transpose function;vHGW algorithm;Application software;Graphics processing unit;Image processing;Libraries;Message systems;Signal processing algorithms;Timing;CUDA;GPU;Morphological image processing;NVIDIA;dilation;erosion},
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.27}
+}
+
+@Article{tiajon_04,
+  Title                    = {{Selective Avoidance of Cycles in Irregular LDPC Code Construction}},
+  Author                   = {T. Tian and Jones, C.R. and Villasenor, J. D. and Wesel, R. D.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2004},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {1242--1247},
+  Volume                   = {52},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{tiaben_12,
+  Title                    = {{I}mplementation of the {L}ongstaff and {S}chwartz {A}merican {O}ption {P}ricing {M}odel on {FPGA}},
+  Author                   = {Xiang Tian and Benkrid, K.},
+  Journal                  = {Journal of Signal Processing Systems},
+  Year                     = {2012},
+  Number                   = {1},
+  Pages                    = {79--91},
+  Volume                   = {67},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {finance, American options, Longstaff-Schwartz},
+  Doi                      = {10.1007/s11265-010-0550-1},
+  File                     = {tiaben_12.pdf:tiaben_12.pdf:PDF},
+  ISSN                     = {1939-8018},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Owner                    = {CdS},
+  Publisher                = {Springer US},
+  Timestamp                = {2014.01.24}
+}
+
+@InProceedings{tiaben_10,
+  Title                    = {{F}ixed-{P}oint {A}rithmetic {E}rror {E}stimation in {M}onte-{C}arlo {S}imulations},
+  Author                   = {Xiang Tian and Benkrid, K.},
+  Booktitle                = {2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
+  Year                     = {2010},
+  Pages                    = {202-207},
+
+  Abstract                 = {As Field Programmable Gate Arrays (FPGAs) get faster and denser, the scope of their applications is getting wider. High performance computing applications, for instance, are an example of such application expansion driven by FPGAs' increasing computational power coupled with their relatively low power consumption compared to state-of-the-art microprocessor technology. However, one major hurdle facing FPGAs in the high performance computing arena, in addition to their low level programming model, is their low efficiency in implementing double precision floating-point arithmetic, which is often considered essential in many high performance applications. This paper attempts to dispel the latter perceived limitation in the area of Monte-Carlo based stochastic process simulation through a rigorous estimation of fixed-point arithmetic error in a hardware implementation of the Monte-Carlo based European option pricing model. Representations of the mean and variance of quantisation and rounding-off errors due to fixed-point arithmetic show this error to be negligible when compared to the variance of the Monte-Carlo simulation method itself. Not only does this allow us to avoid full double precision arithmetic implementation, but also to minimise the fixed-point word length used without practically affecting the precision of the final result. This in turn results in considerable area savings and throughput increases.},
+  Cds_keywords             = {Monte Carlo, fixed point, error},
+  Doi                      = {10.1109/ReConFig.2010.14},
+  File                     = {tiaben_10.pdf:tiaben_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.10.09}
+}
+
+@InProceedings{tiaben_09,
+  Title                    = {{M}ersenne {T}wister {R}andom {N}umber {G}eneration on {FPGA}, {CPU} and {GPU}},
+  Author                   = {Xiang Tian and Khaled Benkrid},
+  Booktitle                = {Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS)},
+  Year                     = {2009},
+  Month                    = {29 2009-aug. 1},
+  Pages                    = {460 -464},
+
+  Abstract                 = {Random number generation is a very important operation in computational science e.g. in Monte Carlo simulations methods. It is also a computationally intensive operation especially for high quality random number generation. In this paper, we present the design and implementation of a parallel implementation of one of the most widely used random number generators, namely the Mersenne Twister. The latter is very widely used in high performance computing applications such as financial computing. Implementations of our parallel Mersenne Twister number generator core on Xilinx Virtex4 FPGAs achieve a throughput of 26.13 billion random samples per second. The paper also reports equivalent parallel software implementations running on an Intel Core 2 Quad Q9300 CPU with 8 GB RAM, using multi-threading technology and the Intelreg Math Kernel Library (MKL), as well as on an NVIDIA 8800 GTX GPU. Comparative results show that our FPGA-based implementation outperforms equivalent CPU and GPU implementations by ~25times and ~9times respectively. Moreover, when using the same amount of energy, the FPGA can generate 37times and 35times more Mersenne Twister random samples than the CPU and the GPU, respectively.},
+  Cds_grade                = {0},
+  Cds_keywords             = {random numbers, generator, Mersenne Twister},
+  Doi                      = {10.1109/AHS.2009.11},
+  File                     = {tiaben_09.pdf:tiaben_09.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.19}
+}
+
+@InProceedings{tiaben_09a,
+  Title                    = {{A}merican {O}ption {P}ricing on {R}econfigurable {H}ardware {U}sing {L}east-{S}quares {M}onte {C}arlo {M}ethod},
+  Author                   = {Xiang Tian and Benkrid, K.},
+  Booktitle                = {Field-Programmable Technology, 2009. FPT 2009. International Conference on},
+  Year                     = {2009},
+  Month                    = dec,
+  Pages                    = {263 -270},
+
+  Abstract                 = {The valuation of optimal exercise of American-style options is one of the most important problems in option pricing theory. Unlike European options, American options have the feature of early exercise, which makes it hard to simulate using the simple Monte Carlo method. A number of extended Monte Carlo methods have been published recently; the Least-Squares Monte Carlo (LSMC) suggested by Longstaff and Schwartz is one of the most adopted algorithms in the industry. Although hardware acceleration technique has been used in financial computing for several years, there has not been any published hardware implementation of the LSMC method. In this paper, we present an FPGA hardware architecture for the acceleration of the LSMC method. In it, the Quasi-Monte Carlo method is adopted for stock price paths generation. Our real FPGA hardware implementation on a Xilinx Virtex-4 XC4VSX55 chip achieves 25x and 18x speed-ups in the Monte Carlo simulation and regression steps of the American option pricing, respectively, compared to an equivalent pure software implementation captured in C++ and run on an Intel Xeon 2.8 GHz CPU. This results in an overall speed-up figure of 20x compared to a CPU-based implementation. Given that the FPGA implementation is clocked at only 75MHz, the FPGA implementation also exhibits considerable energy savings.},
+  Cds_grade                = {0},
+  Cds_keywords             = {FPGA, option pricing, Monte Carlo},
+  Doi                      = {10.1109/FPT.2009.5377662},
+  File                     = {tiaben_09a.pdf:tiaben_09a.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.06.22}
+}
+
+@InProceedings{tiaben_08,
+  Title                    = {{M}assively {P}arallelized {Q}uasi-{M}onte {C}arlo {F}inancial {S}imulation on a {FPGA} {S}upercomputer},
+  Author                   = {Xiang Tian and Khaled Benkrid},
+  Booktitle                = {High-Performance Reconfigurable Computing Technology and Applications, 2008. HPRCTA 2008. Second International Workshop on},
+  Year                     = {2008},
+  Month                    = nov,
+  Pages                    = {1 -8},
+
+  Abstract                 = {Quasi-Monte Carlo simulation is a specialized Monte Carlo method which uses quasi-random, or low-discrepancy, numbers as the stochastic parameters. In many applications, this method has proved advantageous compared to the traditional Monte Carlo simulation method, which uses pseudo-random numbers, as it converges relatively quickly, and with a better level of accuracy. We implemented a massively parallelized Quasi-Monte Carlo simulation engine on a FPGA-based supercomputer, called Maxwell, and developed at the University of Edinburgh. Maxwell consists of 32 IBM Intel Xeon blades each hosting two Virtex-4 FPGA nodes through PCI-X interface. Real hardware implementation of our FPGA-based quasi-Monte Carlo engine on the Maxwell machine outperforms equivalent software implementations running on the Xeon processors by 3 orders of magnitude, with the speed-up figure scaling linearly with the number of processing nodes. The paper presents the detailed design and implementation of our Quasi-Monte Carlo engine in the context of financial derivatives pricing.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/HPRCTA.2008.4745684},
+  File                     = {tiaben_08.pdf:tiaben_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.25}
+}
+
+@Article{tiaben_08a,
+  Title                    = {{H}igh {P}erformance {M}onte-{C}arlo {B}ased {O}ption {P}ricing on {FPGA}s},
+  Author                   = {Xiang Tian and Khaled Benkrid and Xiaochen Gu},
+  Journal                  = {Engineering Letters},
+  Year                     = {2008},
+  Number                   = {3},
+  Pages                    = {434--442},
+  Volume                   = {16},
+
+  Abstract                 = {High performance computing is becomingincreasingly important in the field of financial computing,as the complexity of financial models continues to increase.Many of these financial models do not have a practicalclose form solution in which case numerical methods arethe only alternative. Monte-Carlo simulation is one ofmost commonly used numerical methods, in scientificcomputing in general, with huge computation benefits insolving problems where close form solutions areimpossible to derive. As the Monte-Carlo method relies onthe average result of thousands of independent stochasticpaths, massive parallelism can be adopted to accelerate thecomputation. Computer clusters with off-the-shelfaccelerator hardware are increasingly being proposed asan economic high performance implementation platformfor many scientific computing applications. This paper ispart of this trend as it presents an implementation of aMonte-Carlo simulation engine for option pricing on anFPGA-based supercomputer, called Maxwell, developed atthe University of Edinburgh. The latter consists of a 32CPU cluster augmented with 64 Virtex-4 Xilinx FPGAsconnected in a 2D torus. Our engine can implementvarious Monte-Carlo simulations on the Maxwell machinewith speed-ups in excess of 100x compared to equivalentsoftware implementations. This is illustrated in this paperin the context of an implementation of the GARCH optionpricing model. Real hardware implementation shows thatour FPGA-based implementation of the GARCH modeloutperforms an equivalent software implementationrunning on a workstation cluster with the same number ofcomputing nodes (CPU/FPGA) by a factor of 340.},
+  Cds_grade                = {0},
+  File                     = {tiaben_08a.pdf:tiaben_08a.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.25}
+}
+
+@InProceedings{tieweh_08,
+  Title                    = {{Power Measurement in Cycling using Inductive Coupling of Energy and Data}},
+  Author                   = {R. Tielert and N. Wehn and T. Jaitner and R. Volk},
+  Booktitle                = {The 7th ISEA conference 2008},
+  Year                     = {2008},
+
+  Address                  = {Biarritz, France},
+  Month                    = jun,
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{tirboa_00,
+  Title                    = {{M}inimal non-orthogonality rate 1 space-time block code for 3+ {T}x antennas},
+  Author                   = {Tirkkonen, O. and Boariu, A. and Hottinen, A. },
+  Booktitle                = {Proc. IEEE Sixth International Symposium on Spread Spectrum Techniques and Applications},
+  Year                     = {2000},
+  Pages                    = {429--432 vol.2},
+  Volume                   = {2},
+
+  Abstract                 = {We propose a full rate space-time block code for 3+ Tx antennas. The code is chosen to minimize the non-orthonormality that arises from increasing the rate above the maximum allowed by orthogonality. A linear decoding based on iterative interference cancellation between parts of the code approaches the maximal likelihood decoding performance},
+  Doi                      = {10.1109/ISSSTA.2000.876470},
+  File                     = {tirboa_00.pdf:tirboa_00.pdf:PDF},
+  Grade                    = {0},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@Misc{tizmem_17,
+  Title                    = {{M}emory and {S}torage for {L}5 {A}utonomy from {A}utomotive {JEDEC} {F}orum},
+
+  Author                   = {Tiziani, Federico},
+  Month                    = {November},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-03},
+  Url                      = {https://www.micron.com/about/blogs/2017/november/memory-and-storage-for-l5-autonomy-from-automotive-jedec-forum}
+}
+
+@InProceedings{todmue_12,
+  Title                    = {{A}utomated {C}onstruction of a {C}ycle-approximate {T}ransaction {L}evel {M}odel of a {M}emory {C}ontroller},
+  Author                   = {Todorov, Vladimir and Mueller-Gritschneder, Daniel and Reinig, Helmut and Schlichtmann, Ulf},
+  Booktitle                = {Proceedings of the Conference on Design, Automation and Test in Europe},
+  Year                     = {2012},
+
+  Address                  = {San Jose, CA, USA},
+  Pages                    = {1066--1071},
+  Publisher                = {EDA Consortium},
+  Series                   = {DATE '12},
+
+  Acmid                    = {2492972},
+  ISBN                     = {978-3-9810801-8-6},
+  Location                 = {Dresden, Germany},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2019-09-11},
+  Url                      = {http://dl.acm.org/citation.cfm?id=2492708.2492972}
+}
+
+@InProceedings{tohpau_99,
+  Title                    = {{Low-Power Logic Styles: Branch-based Logic Versus Topological Dual CMOS in Sub-Micron Technologies}},
+  Author                   = {U. Tohsche and S. Paul and N. Wehn},
+  Booktitle                = {Proceedings of the 8th International Symposium on Integrated Circuits, Devices and Systems},
+  Year                     = {1999},
+
+  Address                  = {Singapore},
+  Month                    = sep,
+  Pages                    = {94-97},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{tohweh_00,
+  Title                    = {{Power and Area Optimized Flip-Flops for the ARTISAN Library}},
+  Author                   = {U. Tohsche and N. Wehn},
+  Institution              = {Infineon AG},
+  Year                     = {2000},
+  Month                    = jul,
+
+  Optnote                  = {Internal report},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{toiehr_13,
+  Title                    = {{L}ocal {V}olatility {FX} {B}asket {O}ption on {CPU} and {GPU}},
+  Author                   = {Jacques du Toit and Isabel Ehrlich},
+  Institution              = {The Numerical Algorithms Group Ltd},
+  Year                     = {2013},
+  Note                     = {last access: 2015-02-09},
+
+  Abstract                 = {We study a basket option written on 10 FX rates driven by a 10 factor local volatility model. We price the option using Monte Carlo simulation and develop high performance implementations of the algorithm on a top end Intel CPU and an NVIDIA GPU. We obtain the following performance figures:
+The width of the 98% confidence interval is 0.05% of the option price. We confirm that the algorithm runs stably and accurately in single precision, and this gives a 2x performance improvement on both platforms. Lastly, we experiment with GPU texture memory and reduce the GPU runtime to 153ms. This gives a price with an error of 2.60e-7 relative to the double precision price.},
+  Cds_grade                = {0},
+  Cds_keywords             = {GPU},
+  File                     = {toiehr_13.pdf:toiehr_13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.02},
+  Url                      = {http://www.nag.co.uk/numeric/gpus/local-volatility-fx-basket-option-on-cpu-and-gpu.pdf}
+}
+
+@TechReport{toilot_13,
+  Title                    = {{A}djoint {A}lgorithmic {D}ifferentiation of a {GPU} {A}ccelerated {A}pplication},
+  Author                   = {Jacques du Toit and Johannes Lotz and Uwe Naumann},
+  Institution              = {The Numerical Algorithms Group Ltd},
+  Year                     = {2013},
+
+  Abstract                 = {We consider a GPU accelerated program using Monte Carlo simulation to price a basket call option on 10 FX rates driven by a 10 factor local volatility model. We develop an adjoint version of this program using algorithmic differentiation. The code uses mixed precision. For our test problem of 10,000 sample paths with 360 Euler time steps, we obtain a runtime of 522ms to compute the gradient of the price with respect to the 438 input parameters, the vast majority of which are the market observed implied volatilities (the equivalent single threaded tangent-linear code on a CPU takes 2hrs).},
+  Cds_grade                = {0},
+  Cds_keywords             = {GPU},
+  File                     = {toilot_13.pdf:toilot_13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.02},
+  Url                      = {http://www.nag.co.uk/Market/articles/adjoint-algorithmic-differentiation-of-gpu-accelerated-app.pdf}
+}
+
+@Article{tonler_16,
+  Title                    = {{L}owering the {E}rror {F}loor of {T}urbo {C}odes {W}ith {CRC} {V}erification},
+  Author                   = {T. Tonnellier and C. Leroux and B. Le Gal and B. Gadat and C. Jego and N. Van Wambeke},
+  Journal                  = {IEEE Wireless Communications Letters},
+  Year                     = {2016},
+
+  Month                    = {Aug},
+  Number                   = {4},
+  Pages                    = {404-407},
+  Volume                   = {5},
+
+  Doi                      = {10.1109/LWC.2016.2571283},
+  ISSN                     = {2162-2337},
+  Keywords                 = {concatenated codes;cyclic redundancy check codes;error detection codes;error statistics;iterative decoding;turbo codes;CRC verification;Long-Term Evolution turbo code;cyclic redundancy check detector;decoded codeword identificaion;error detection code;frame error rate;iterative decoding process;low complexity method;serially concatenated code;signal-to-noise ratio;turbo code error floor;Cyclic redundancy check codes;Decoding;Error analysis;Iterative decoding;Measurement;Standards;Turbo codes;CRC codes;Turbo codes;error floor region;extrinsic information;iterative decoding process},
+  Owner                    = {StW},
+  Timestamp                = {2016.11.15}
+}
+
+@Electronic{top_13,
+  Title                    = {{TOP}500 {S}upercomputer {S}ites},
+  Author                   = {{TOP500 project}},
+  HowPublished             = {\url{http://www.top500.org/lists/2013/11}},
+  Language                 = {en},
+  Month                    = nov,
+  Year                     = {2013},
+
+  Owner                    = {CdS},
+  Timestamp                = {2012.06.20}
+}
+
+@Electronic{top500.org,
+  Title                    = {{TOP}500 {S}upercomputer {S}ites},
+  Author                   = {{TOP500 project}},
+  HowPublished             = {\url{http://www.top500.org/lists/2012/06}},
+  Language                 = {en},
+  Month                    = jun,
+  Year                     = {2012},
+
+  Owner                    = {CdS},
+  Timestamp                = {2012.06.20}
+}
+
+@Electronic{top_10,
+  Title                    = {{TOP}500 {S}upercomputer {S}ites},
+  Author                   = {{TOP500 project}},
+  HowPublished             = {\url{http://www.top500.org/lists/2010/11/}},
+  Language                 = {en},
+  Month                    = nov,
+  Year                     = {2010},
+
+  Owner                    = {CdS},
+  Timestamp                = {2012.06.20}
+}
+
+@Electronic{top_08,
+  Title                    = {{TOP}500 {S}upercomputer {S}ites},
+  Author                   = {{TOP500 project}},
+  HowPublished             = {\url{http://www.top500.org/lists/2008/11}},
+  Language                 = {en},
+  Month                    = nov,
+  Year                     = {2008},
+
+  Owner                    = {CdS},
+  Timestamp                = {2012.06.20}
+}
+
+@MastersThesis{MTtorre14,
+  Title                    = {{A}n in {D}epth {C}omparison of {U}ltra {H}igh {S}peed {LDPC} {D}ecoder {A}rchitectures},
+  Author                   = {Romel Torres},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2014},
+  Type                     = {Master Thesis},
+
+  Owner                    = {Schläfer},
+  Timestamp                = {2014.07.23}
+}
+
+@MastersThesis{MTtorru12,
+  Title                    = {{FPGA} {B}ased {M}ulti-{L}evel {M}onte-{C}arlo {H}ardware {A}ccelerator for the {H}eston {M}odel: an implementation proposal},
+  Author                   = {Pedro Torruella},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2012},
+  Month                    = oct,
+
+  Cds_grade                = {5},
+  Cds_keywords             = {multilevel, FPGA, hardware architecture},
+  File                     = {MTtorru12.pdf:MTtorru12.pdf:PDF},
+  Keywords                 = {finance, AG Wehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@InProceedings{tosbis_02,
+  Title                    = {{S}implified soft-output demapper for binary interleaved {COFDM} with application to {HIPERLAN}/2},
+  Author                   = {Filippo Tosato and Paola Bisaglia},
+  Booktitle                = {IEEE International Conference on Communications (ICC)},
+  Year                     = {2002},
+  Pages                    = {664-668 vol.2},
+  Volume                   = {2},
+
+  Keywords                 = {OFDM modulation;Viterbi decoding;binary codes;interleaved codes;maximum likelihood decoding;modulation coding;quadrature amplitude modulation;telecommunication standards;wireless LAN;16-QAM constellation;64-QAM constellation;ETSI BRAN;European standard;HIPERLAN/2 standard;binary interleaved COFDM;bit-interleaved coded modulation;channel state information;hard-decision Viterbi decoding;maximum likelihood decoding;performance;soft-decision Viterbi decoding;soft-decision information;soft-decision method;soft-output demapper algorithm;Binary phase shift keying;Convolution;Convolutional codes;Decoding;Modulation coding;OFDM modulation;Physical layer;Quadrature amplitude modulation;Quadrature phase shift keying;Viterbi algorithm}
+}
+
+@Article{toumcc_97,
+  Title                    = {{L}ogic synthesis of multilevel circuits with concurrent error detection},
+  Author                   = {Touba, N. A. and McCluskey, E. J.},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {1997},
+  Number                   = {7},
+  Pages                    = {783--789},
+  Volume                   = {16},
+
+  Doi                      = {10.1109/43.644041},
+  File                     = {toumcc_97.pdf:toumcc_97.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2011.08.03}
+}
+
+@Misc{TransmetaCorporation2000,
+  Title                    = {{The Crusoe Processor}},
+
+  Author                   = {{Transmeta Corporation}},
+  HowPublished             = {{{http://www.transmeta.com}}},
+  Year                     = {2000},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{trcrusoe00,
+  Title                    = {{The Crusoe Processor}},
+
+  Author                   = {{Transmeta Corporation}},
+  HowPublished             = {{{http://www.transmeta.com}}},
+  Year                     = {2000},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{trasch_13,
+  Title                    = {{A} {S}afety {R}oadmap to {C}yber-{P}hysical {S}ystems},
+  Author                   = {Trapp, Mario
+and Schneider, Daniel
+and Liggesmeyer, Peter},
+  Editor                   = {M{\"u}nch, J{\"u}rgen
+and Schmid, Klaus},
+  Pages                    = {81--94},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2013},
+
+  Address                  = {Berlin, Heidelberg},
+
+  Abstract                 = {In recent years, the term cyber-physical systems has emerged to characterize a new generation of embedded systems. In cyber-physical systems, embedded systems will be open in the sense that they will dynamically interconnect with other systems and will be able to dynamically adapt to changing runtime contexts. Such open adaptive systems provide a huge potential for society and for the economy. On the other hand, however, openness and adaptivity make it hard or even impossible for developers to predict a system's dynamic structure and behavior. This impedes the assurance of important system quality properties, especially safety and reliability. Safety assurance of cyber-physical systems will therefore be both one of the most urgent and one of the most challenging research questions of the next decade. This chapter analyzes the state of the art in order to identify open gaps and suggests a runtime safety assurance framework for cyber-physical systems to structure ongoing and future research activities.},
+  Booktitle                = {Perspectives on the Future of Software Engineering: Essays in Honor of Dieter Rombach},
+  Doi                      = {10.1007/978-3-642-37395-4_6},
+  ISBN                     = {978-3-642-37395-4},
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-02},
+  Url                      = {https://doi.org/10.1007/978-3-642-37395-4_6}
+}
+
+@Book{tre_68,
+  Title                    = {{Detection, Estimation and Modulation Theory}},
+  Author                   = {H. L. van Trees},
+  Publisher                = {John Wiley \& Sons, Inc.},
+  Year                     = {1968},
+
+  Address                  = {New York},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{trellisware,
+  Title                    = {{THE} {F} {LDPC} {FAMILY}},
+
+  Author                   = {TrellisWare},
+  HowPublished             = {{{http://www.trellisware.com/}}},
+  Year                     = {2007},
+
+  Keywords                 = {Reliability},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.07.06}
+}
+
+@Misc{TrellisWare2007,
+  Title                    = {{THE} {F} {LDPC} {FAMILY}},
+
+  Author                   = {TrellisWare},
+  HowPublished             = {{{http://www.trellisware.com/}}},
+  Year                     = {2007},
+
+  Keywords                 = {Reliability},
+  Owner                    = {Kienle},
+  Timestamp                = {2009.07.06}
+}
+
+@Article{Tretter1985,
+  Title                    = {{E}stimating the {F}requency of a {N}oisy {S}inusoid by {L}inear {R}egression ({C}orresp.)},
+  Author                   = {Tretter, S.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1985},
+
+  Month                    = {Nov},
+  Number                   = {6},
+  Pages                    = {832-835},
+  Volume                   = {31},
+
+  Doi                      = {10.1109/TIT.1985.1057115},
+  ISSN                     = {0018-9448},
+  Keywords                 = {Frequency estimation;Phase estimation;Additive noise;Frequency estimation;Linear regression;Maximum likelihood detection;Maximum likelihood estimation;Parameter estimation;Phase estimation;Phase noise;Predictive models;Signal to noise ratio},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.25}
+}
+
+@InProceedings{tri_14,
+  Title                    = {{B}inary successive cancellation decoding of polar codes with {R}eed-{S}olomon kernel},
+  Author                   = {P. Trifonov},
+  Booktitle                = {Information Theory (ISIT), 2014 IEEE International Symposium on},
+  Year                     = {2014},
+  Month                    = {June},
+  Pages                    = {2972-2976},
+
+  Doi                      = {10.1109/ISIT.2014.6875379},
+  Keywords                 = {Reed-Solomon codes;binary codes;block codes;computational complexity;decoding;error correction codes;linear codes;Arikan polar codes;Reed-Solomon codes;Reed-Solomon kernel;binary successive cancellation decoding algorithm;complexity reduction;dynamic frozen symbols;list successive cancellation decoding algorithm;Complexity theory;Decoding;Heuristic algorithms;Kernel;Reed-Solomon codes;Vectors},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Article{tri_12,
+  Title                    = {{E}fficient {D}esign and {D}ecoding of {P}olar {C}odes},
+  Author                   = {P. Trifonov},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2012},
+
+  Month                    = {November},
+  Number                   = {11},
+  Pages                    = {3221-3227},
+  Volume                   = {60},
+
+  Doi                      = {10.1109/TCOMM.2012.081512.110872},
+  File                     = {tri_12.pdf:tri_12.pdf:PDF},
+  ISSN                     = {0090-6778},
+  Keywords                 = {Gaussian processes;concatenated codes;design;maximum likelihood decoding;Gaussian approximation;concatenated codes;density evolution;design;maximum likelihood decoding;multilevel codes;multistage decoding algorithm;polar codes;Approximation algorithms;Concatenated codes;Constellation diagram;Error probability;Maximum likelihood decoding;Vectors;Polar codes;concatenated codes;multilevel codes},
+  Owner                    = {StW},
+  Timestamp                = {2016.04.04}
+}
+
+@Article{tri_15,
+  Title                    = {{T}hree {A}ges of {FPGA}s: {A} {R}etrospective on the {F}irst {T}hirty {Y}ears of {FPGA} {T}echnology},
+  Author                   = {Stephen M. Trimberger},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2015},
+
+  Month                    = {March},
+  Number                   = {3},
+  Pages                    = {318-331},
+  Volume                   = {103},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.17}
+}
+
+@Article{trushi_92,
+  Title                    = {{A VLSI Design for a Trace-Back Viterbi Decoder}},
+  Author                   = {Truong, T. K. and Shih, M.-T. and Reed, I. S. and Satorius, E. H.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1992},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {616--624},
+  Volume                   = {40},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{tsalin_05,
+  Title                    = {{A} memory-reduced log-{MAP} kernel for turbo decoder},
+  Author                   = {Tsung-Han Tsai and Cheng-Hung Lin and An-Yeu Wu},
+  Booktitle                = {Proc. IEEE International Symposium on Circuits and Systems ISCAS 2005},
+  Year                     = {2005},
+  Month                    = may,
+  Pages                    = {1032--1035},
+
+  Doi                      = {10.1109/ISCAS.2005.1464767},
+  File                     = {tsalin_05.pdf:tsalin_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.09}
+}
+
+@InProceedings{tscbow_09,
+  Title                    = {{R}esilient circuits --- {E}nabling energy-efficient performance and reliability},
+  Author                   = {Tschanz, J. and Bowman, K. and Wilkerson, C. and Shih-Lien Lu and Karnik, T.},
+  Booktitle                = {Proc. IEEE/ACM Int. Conf. Computer-Aided Design - Digest of Technical Papers ICCAD 2009},
+  Year                     = {2009},
+  Pages                    = {71--73},
+
+  Cb_grade                 = {- ungelesen
+- Resilience
+- Intel, Tunable replica circuits (TRC), processor, redundancy},
+  File                     = {tscbow_09.pdf:tscbow_09.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{tsetho_12,
+  Title                    = {{D}esign {E}xploration of {Q}uadrature {M}ethods in {O}ption {P}ricing},
+  Author                   = {Tse, A.H.T. and Thomas, D. and Luk, W.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2012},
+
+  Month                    = may,
+  Number                   = {5},
+  Pages                    = {818-826},
+  Volume                   = {20},
+
+  Abstract                 = {This paper presents a novel parallel architecture for accelerating quadrature methods used for pricing complex multi-dimensional options, such as discrete barrier, Bermudan and American options. We explore different designs of the quadrature evaluation core including optimized pipelined hardware designs in reconfigurable logic and a compute unified device architecture (CUDA)-based graphics processing unit (GPU) design. A parametrizable automated system is presented for generating hardware quadrature evaluation cores with an arbitrary number of dimensions. The performance and energy consumption of field-programmable gate arrays (FPGAs), GPUs, and central processing units (CPUs) are compared across different number of dimensions and precisions. Our evaluation shows that the 100 MHz Virtex-4 xc4vlx160 FPGA design is 4.6 times faster and 25.9 times more energy efficient than a multi-threaded optimized software implementation running on a Xeon W3504 dual-core CPU. It is also 2.6 times faster and 25.4 times more energy efficient than a GPU with comparable silicon process technology.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TVLSI.2011.2128354},
+  File                     = {tsetho_12.pdf:tsetho_12.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@InProceedings{tsetho_10,
+  Title                    = {{D}ynamic scheduling {M}onte-{C}arlo framework for multi-accelerator heterogeneous clusters},
+  Author                   = {Tse, A.H.T. and Thomas, D.B. and Tsoi, K.H. and Luk, W.},
+  Booktitle                = {Field-Programmable Technology (FPT), 2010 International Conference on},
+  Year                     = {2010},
+  Month                    = dec,
+  Pages                    = {233-240},
+
+  Abstract                 = {Monte-Carlo (MC) simulation is an effective tool for solving complex problems such as many-body simulation, exotic option pricing and partial differential equation solving. The huge amount of computation in MC makes it a good candidate for acceleration using hardware and distributed computing platforms. We propose a novel MC simulation framework suitable for a wide range of problems. This framework enables different hardware accelerators in a multi-accelerator heterogeneous cluster to work collaboratively on a single application. It also provides scheduling interfaces to adaptively balance the workload according to the cluster status. Two financial applications, involving asset simulation and option pricing, are built using this framework to demonstrate its capability and flexibility. A cluster with 8 Virtex-5 xc5vlx330t FPGAs and 8 Tesla C1060 GPUs using the proposed framework provides 44 times speedup and 19.6 times improved energy efficiency over a cluster with 16 AMD Phenom 9650 quad-core 2.4GHz CPUs for the GARCH asset simulation application. The Efficient Allocation Line (EAL) is proposed for determining the most efficient allocation of accelerators for either performance or energy consumption.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPT.2010.5681495},
+  File                     = {tsetho_10.pdf:tsetho_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.06.13}
+}
+
+@InProceedings{tsetho_09,
+  Title                    = {{A}ccelerating quadrature methods for option valuation},
+  Author                   = {Tse, Anson HT and Thomas, David B and Luk, Wayne},
+  Booktitle                = {Field Programmable Custom Computing Machines, 2009. FCCM'09. 17th IEEE Symposium on},
+  Year                     = {2009},
+  Organization             = {IEEE},
+  Pages                    = {29--36},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.02}
+}
+
+@Article{tsetho_11,
+  Title                    = {{E}fficient {R}econfigurable {D}esign for {P}ricing {A}sian {O}ptions},
+  Author                   = {Tse, Anson H.T. and Thomas, David B. and Tsoi, K. H. and Luk, Wayne},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {2011},
+
+  Month                    = jan,
+  Number                   = {4},
+  Pages                    = {14--20},
+  Volume                   = {38},
+
+  Abstract                 = {Arithmetic Asian options are financial derivatives which have the feature of path-dependency: they depend on the entire price path of the underlying asset, rather than just the instantaneous price. This path-dependency makes them difficult to price, as only computationally intensive Monte-Carlo methods can provide accurate prices. This paper proposes an FPGA-accelerated Asian option pricing solution, using a highly-optimised parallel Monte-Carlo architecture. The proposed pipelined design is described parametrically, facilitating its re-use for different technologies. An implementation of this architecture in a Virtex-5 xc5vlx330t FPGA at 200MHz is 313 times faster than a multi-threaded software implementation running on a Intel Xeon E5420 quad-core CPU at 2.5GHz; it is also 2.2 times faster than the Tesla C1060 GPU at 1.3 GHz.},
+  Acmid                    = {1926371},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Cds_keywords             = {Asian options, CPU, GPU},
+  Doi                      = {10.1145/1926367.1926371},
+  File                     = {tsetho_11.pdf:tsetho_11.pdf:PDF},
+  ISSN                     = {0163-5964},
+  Issue_date               = {September 2010},
+  Keywords                 = {finance},
+  Numpages                 = {7},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2014.06.13},
+  Url                      = {http://doi.acm.org/10.1145/1926367.1926371}
+}
+
+@Electronic{tse_09,
+  Title                    = {{A}rchitecture {E}xploration of {D}istributed {R}econfigurable {F}inancial {C}omputing {S}ystems - {T}ransfer {R}eport},
+  Author                   = {Anson Hong Tak Tse},
+  HowPublished             = {\url{http://www.doc.ic.ac.uk/~htt08/9monthat.pdf}},
+  Language                 = {en},
+  Month                    = aug,
+  Note                     = {last access 2014-07-02},
+  Url                      = {http://www.doc.ic.ac.uk/~htt08/9monthat.pdf},
+  Year                     = {2009},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {finance},
+  File                     = {tse_09.pdf:tse_09.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24}
+}
+
+@Unpublished{anstho_12unpublished,
+  Title                    = {{D}esign {E}xploration of {Q}uadrature {M}ethods in {O}ption {P}ricing},
+  Author                   = {Anson H. T. Tse and David Thomas and Wayne Luk},
+  Note                     = {Accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2012},
+
+  Cds_grade                = {0},
+  File                     = {anstho_12unpublished.pdf:anstho_12unpublished.pdf:PDF},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.02.14}
+}
+
+@InProceedings{tucob_17,
+  Title                    = {{A}rchitectural optimizations for high performance and energy efficient {S}mith-{W}aterman implementation on {FPGAs} using {OpenCL}},
+  Author                   = {L. Di Tucci and K. O'Brien and M. Blott and M. D. Santambrogio},
+  Booktitle                = {Design, Automation Test in Europe Conference Exhibition (DATE), 2017},
+  Year                     = {2017},
+  Month                    = {March},
+  Pages                    = {716-721},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {paper stating that FPGAs have the highest energy efficiency among all other platforms},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.23919/DATE.2017.7927082},
+  ISSN                     = {1558-1101},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {bioinformatics;data compression;dynamic programming;field programmable gate arrays;genomics;shift registers;systolic arrays;architectural optimization;high-performance energy efficient Smith-Waterman implementation;dynamic programming algorithm;genomics pipeline;optimal local alignment;data strings;hardware acceleration;Berkeley roofline model;systolic arrays;data compression features;shift registers;port mapping strategy;OpenCL-based design entry;Xilinx SDAccel;Xilinx Virtex 7;Kintex Ultrascale platform;FPGA implementation;Field programmable gate arrays;Performance evaluation;Optimization;Hardware;Computer architecture;Graphics processing units;Algorithm design and analysis},
+  Owner                    = {CCR}
+}
+
+@Article{t_04,
+  Title                    = {{Design of Serially Concatenated Systems Depending on the Block Length}},
+  Author                   = {M. Tüchler},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2004},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {209--218},
+  Volume                   = {52},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{tuckoe_02,
+  Title                    = {{Turbo equalization: principles and new results}},
+  Author                   = {M. Tüchler and R. Kötter and A. Singer},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2002},
+
+  Month                    = may,
+  Pages                    = {754--767},
+  Volume                   = {50},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{tzikac_ed,
+  Title                    = {{A} {S}urvey on {FEC} {C}odes for 100{G} and {B}eyond {O}ptical {N}etworks},
+  Author                   = {Tzimpragos, G. and Kachris, C. and Djordjevic, I.B. and Cvijetic, M. and Soudris, D. and Tomkos, I.},
+  Journal                  = {IEEE Communications Surveys \& Tutorials},
+  Year                     = {to be published},
+  Note                     = {Early Access},
+
+  Doi                      = {10.1109/COMST.2014.2361754},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.10.07},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6917198}
+}
+
+@TechReport{dep_12,
+  Title                    = {{T}he {F}inancial {C}risis {R}esponse: {I}n {C}harts},
+  Author                   = {{U.S. Department of the Treasury}},
+  Year                     = {2012},
+  Month                    = {Apr},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.04},
+  Url                      = {https://www.treasury.gov/resource-center/data-chart-center/Documents/20120413_FinancialCrisisResponse.pdf}
+}
+
+@Article{uch_08,
+  Title                    = {{H}ardware-{B}ased {TCP} {P}rocessor for {G}igabit {E}thernet},
+  Author                   = {Uchida, T.},
+  Journal                  = {Nuclear Science, IEEE Transactions on},
+  Year                     = {2008},
+  Number                   = {3},
+  Pages                    = {1631--1637},
+  Volume                   = {55},
+
+  Abstract                 = {Transmission control protocol (TCP) and Ethernet have been widely used in readout systems. These protocols are de facto standards and have been implemented on standard operating systems. However, some small devices, e.g., front-end devices and detectors, are not capable of employing these protocols because of hardware size limitations. This paper describes a TCP processor for gigabit Ethernet with a circuit size suitable for implementing on a single field programmable gate array. The only peripheral device required is a single Ethernet physical layer device. The hardware was implemented and its TCP throughput was measured. The throughputs in both directions simultaneously were at the upper limits of gigabit Ethernet. A mechanism for slow control over user datagram protocol (UDP) is also provided. The processor described here allows adoption of TCP/Ethernet in small devices that have hardware size limitations.},
+  Cds_grade                = {4},
+  Cds_keywords             = {FPGA, TCP/IP, ethernet, rapid Prototyping},
+  Cds_read                 = {2013-10-02},
+  Cds_review               = {fast Gigabit ethernet core for FPGA implementation handling TCP/IP, not all TCP/IP features supported
+used for fast data transmission away from detector engines},
+  Doi                      = {10.1109/TNS.2008.920264},
+  File                     = {uch_08.pdf:uch_08.pdf:PDF},
+  ISSN                     = {0018-9499}
+}
+
+@InProceedings{uemtan_08,
+  Title                    = {{U}sing {L}ow {P}ass {F}ilters in {M}itigation {T}echniques against {S}ingle-{E}vent {T}ransients in 45nm {T}echnology {LSI}s},
+  Author                   = {Uemura, T. and Tanabe, R. and Tosaka, Y. and Satoh, S. },
+  Booktitle                = {Proc. 14th IEEE Int. On-Line Testing Symp. IOLTS '08},
+  Year                     = {2008},
+  Pages                    = {117--122},
+
+  Doi                      = {10.1109/IOLTS.2008.28},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{uhlman_12,
+  Title                    = {{G}lobal mi{RNA} {R}egulation of {A} {L}ocal {P}rotein {N}etwork: {C}ase {S}tudy with the {EGFR}-{D}riven {C}ell {C}ycle {N}etwork in {B}reast {C}ancer},
+  Author                   = {Stefan Uhlmann and Heiko Mannsperger and Jitao David Zhang and Em{\H o}ke-{\'A}gnes Horvat and Christian Schmidt and Moritz K{\"u}blbeck and Aoife Ward and Ulrich Tschulena and Katharina Zweig and Ulrike Korf and Stefan Wiemann and {\"O}zg{\"u}r Sahin},
+  Journal                  = {Molecular Systems Biology},
+  Year                     = {2012},
+  Pages                    = {570},
+  Volume                   = {8},
+
+  Owner                    = {nina},
+  Timestamp                = {2011.08.31}
+}
+
+@Article{uht_04,
+  Title                    = {{Going Beyond Worst-Case Specs with TEAtime}},
+  Author                   = {Uht, Augustus K.},
+  Journal                  = {Computer},
+  Year                     = {2004},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {51--56},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{ung_82,
+  Title                    = {{Channel Coding with Multilevel/Phase Signals}},
+  Author                   = {Gottfried Ungerboeck},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1982},
+
+  Month                    = jan,
+  Pages                    = {55--67},
+  Volume                   = {28},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{unstsc_06,
+  Title                    = {{I}mpact of {P}arameter {V}ariations on {C}ircuits and {M}icroarchitecture},
+  Author                   = {Unsal, O. S. and Tschanz, J. W. and Bowman, K. and De, V. and Vera, X. and Gonzalez, A. and Ergin, O.},
+  Journal                  = {IEEE Micro},
+  Year                     = {2006},
+
+  Month                    = nov,
+  Number                   = {6},
+  Pages                    = {30--39},
+  Volume                   = {26},
+
+  Doi                      = {10.1109/MM.2006.122},
+  File                     = {unstsc_06.pdf:unstsc_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.04}
+}
+
+@InProceedings{uramaa_08,
+  Title                    = {{L}everaging sequential equivalence checking to enable system-level to {RTL} flows},
+  Author                   = {Urard, P. and Maalej, A. and Guizzetti, R. and Chawla, N. and Krishnaswamy, V. },
+  Booktitle                = {Proc. 45th ACM/IEEE Design Automation Conference DAC 2008},
+  Year                     = {2008},
+  Month                    = jun,
+  Pages                    = {816--821},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{urapau_05,
+  Title                    = {{A 135Mbps DVB-S2 Compliant Codec Based on 64800-bit LDPC and BCH Codes}},
+  Author                   = {P. Urard and L. Paumier and P. Georgelin and T. Michel and V. Lebars and E. Yeo and B. Gupta},
+  Booktitle                = {Proc. 2005 Design Automation Conference (DAC)},
+  Year                     = {2005},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{urapau_08,
+  Title                    = {{A} 360m{W} 105{M}b/s {DVB}-{S}2 {C}ompliant {C}odec based on 64800b {LDPC} and {BCH} {C}odes enabling {S}atellite-{T}ransmission {P}ortable {D}evices},
+  Author                   = {Urard, P. and Paumier, L. and Heinrich, V. and Raina, N. and Chawla, N.},
+  Booktitle                = {Proc. Digest of Technical Papers. IEEE International Solid-State Circuits Conference ISSCC 2008},
+  Year                     = {2008},
+  Month                    = feb,
+  Pages                    = {310--311},
+
+  Doi                      = {10.1109/ISSCC.2008.4523181},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{urapau_04,
+  Title                    = {{A} generic 350 {M}b/s turbo-codec based on a 16-states {SISO} decoder},
+  Author                   = {Urard, P. and Paumier, L. and Viollet, M. and Lantreibecq, E. and Michel, H. and Muroor, S. and Coates, B. and Gupta, B. },
+  Booktitle                = {Proc. Digest of Technical Papers Solid-State Circuits Conference ISSCC. 2004 IEEE International},
+  Year                     = {2004},
+  Month                    = feb,
+  Pages                    = {424--536},
+
+  Doi                      = {10.1109/ISSCC.2004.1332775},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{urayeo_05,
+  Title                    = {{A} 135{M}b/s {DVB}-{S}2 compliant codec based on 64800b {LDPC} and {BCH} codes},
+  Author                   = {Urard, P. and Yeo, E. and Paumier, L. and Georgelin, P. and Michel, T. and Lebars, V. and Lantreibecq, E. and Gupta, B.},
+  Booktitle                = {Proc. Digest of Technical Papers Solid-State Circuits Conference ISSCC. 2005 IEEE International},
+  Year                     = {2005},
+  Month                    = feb,
+  Pages                    = {446--609},
+
+  Doi                      = {10.1109/ISSCC.2005.1494061},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@Misc{valren_17,
+  Title                    = {{R}enault, {N}issan and {M}itsubishi team up on self-driving and electric cars},
+
+  Author                   = {Valdes-Dapena, Peter},
+  HowPublished             = {http://money.cnn.com/2017/09/15/technology/renault-nissan-mitsubishi-alliance-electric-self-driving-cars/index.html},
+  Month                    = {September},
+  Year                     = {2017},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-01}
+}
+
+@Article{valfos_04,
+  Title                    = {{B}ox and match techniques applied to soft-decision decoding},
+  Author                   = {Valembois, A. and Fossorier, M. },
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2004},
+  Number                   = {5},
+  Pages                    = {796--810},
+  Volume                   = {50},
+
+  Doi                      = {10.1109/TIT.2004.826644},
+  File                     = {valfos_04.pdf:valfos_04.pdf:PDF},
+  Keywords                 = {BCH, OSD, Box and Match},
+  Owner                    = {Scholl},
+  Review                   = {BMA Urpaper, Erweiterung des OSD},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{valwoe_98,
+  Title                    = {{Performance of Turbo-Codes in Interleaved Flat Fading Channels with Estimated Channel State Information}},
+  Author                   = {M. C. Valenti and B. D. Woerner},
+  Booktitle                = {Proc. 1998 Vehicular Technology Conference (VTC '98)},
+  Year                     = {1998},
+
+  Address                  = {Ottawa, Canada},
+  Month                    = may,
+  Pages                    = {66--70},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{valsaf_07,
+  Title                    = {{F}ault {T}olerant {A}rithmetic {O}perations with {M}ultiple {E}rror {D}etection and {C}orrection},
+  Author                   = {Valinataj, M. and Safari, S.},
+  Booktitle                = {Proc. 22nd IEEE Int. Symp. Defect and Fault-Tolerance in VLSI Systems DFT '07},
+  Year                     = {2007},
+  Pages                    = {188--196},
+
+  Doi                      = {10.1109/DFT.2007.56},
+  File                     = {valsaf_07.pdf:valsaf_07.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2011.08.04}
+}
+
+@InProceedings{valgey_16,
+  Title                    = {{FPGA} implementation of model predictive direct current control},
+  Author                   = {J. Vallone and T. Geyer and E. R. Rohr},
+  Booktitle                = {2016 IEEE Energy Conversion Congress and Exposition (ECCE)},
+  Year                     = {2016},
+  Month                    = {Sept},
+  Pages                    = {1-8},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [29]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/ECCE.2016.7855125},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {asynchronous machines;capacitors;electric current control;field programmable gate arrays;invertors;logic design;predictive control;stators;voltage control;{FPGA} implementation;model predictive direct current control;central scheduler;switching sequences;system response prediction;scalable {FPGA} design;modular {FPGA} design;five-level active neutral point clamped inverter;medium-voltage induction machine;MPDCC;stator current controls;neutral point potential;phase capacitor voltage control;Switches;Inverters;Field programmable gate arrays;Stators;Predictive models;Computational modeling},
+  Owner                    = {CCR}
+}
+
+@InProceedings{van_05,
+  Title                    = {{T}owards achieving relentless reliability gains in a server marketplace of teraflops, laptops, kilowatts, and {``cost, Cost, COST''}...: making peace between a black art and the bottom line},
+  Author                   = {Van Horn, J.},
+  Booktitle                = {Proc. IEEE International Test Conference ITC 2005},
+  Year                     = {2005},
+  Month                    = nov,
+  Pages                    = {8pp.--678},
+
+  Doi                      = {10.1109/TEST.2005.1584029},
+  File                     = {van_05.pdf:van_05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.22}
+}
+
+@InProceedings{vanros_99,
+  Title                    = {{Tailbiting and Decoding Recursive Systematic Codes}},
+  Author                   = {Van Stralen, N.A. and Ross, J.A.F. and Anderson, J.B.},
+  Booktitle                = {Electronics Letters},
+  Year                     = {1999},
+  Month                    = aug,
+  Pages                    = {1461--1462},
+
+  Doi                      = {10.1049/el:19991020},
+  Owner                    = {vogt},
+  Timestamp                = {2006.11.07}
+}
+
+@Article{vanbuc_88,
+  Title                    = {{B}eamforming: a versatile approach to spatial filtering},
+  Author                   = {Van Veen, B.D. and Buckley, K.M.},
+  Journal                  = {ASSP Magazine, IEEE},
+  Year                     = {1988},
+
+  Month                    = {april },
+  Number                   = {2},
+  Pages                    = {4 -24},
+  Volume                   = {5},
+
+  Doi                      = {10.1109/53.665},
+  File                     = {vanbuc_88.pdf:vanbuc_88.pdf:PDF},
+  ISSN                     = {0740-7467},
+  Keywords                 = {adaptive beamforming;beamformer implementations;data independent beamforming;notation;overview;partially adaptive beamforming;signal-processing;spatial filtering;statistically optimum beamforming;terminology;filtering and prediction theory;reviews;signal processing;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.05}
+}
+
+@InProceedings{vanvit_14,
+  Title                    = {{A} new multiple folded successive cancellation decoder for polar codes},
+  Author                   = {H. Vangala and E. Viterbo and Y. Hong},
+  Booktitle                = {Information Theory Workshop (ITW), 2014 IEEE},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {381-385},
+
+  Doi                      = {10.1109/ITW.2014.6970858},
+  ISSN                     = {1662-9019},
+  Keywords                 = {graph theory;maximum likelihood decoding;IMFSCD;SCD;computational complexity;graph representation;improved multiple folded successive cancellation decoder;maximum-likelihood decoding;multiple folding operation;new multiple folded successive cancellation decoder;polar codes;polar encoding graphs;Complexity theory;Concatenated codes;Encoding;Maximum likelihood decoding;Standards;Vectors;Successive cancellation decoder;low latency decoder;multiple folded successive cancellation decoder;partial ML decoding of polar codes;polar code concatenation;two stage polar decoder;two stage polar encoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Electronic{vangoo_08,
+  Title                    = {{D}eveloping {T}ransaction-level {M}odels in {S}ystem{C}},
+  Author                   = {Bart Vanthournout and Serge Goossens and Tim Kogel and CoWare, Inc.},
+  Language                 = {english},
+  Month                    = aug,
+  Organization             = {CoWare, Inc.},
+  Url                      = {www.coware.com/PDF/COWARETLMWHITEPAPER-AUG04.PDF},
+  Year                     = {2008},
+
+  Abstract                 = {The purpose of this white paper is to give an overview of the support that transaction level modeling (TLM) in SystemC provides for System level modeling. More specifically we will address how TLM supports different SoC design and verification tasks. In this document we will first give an introduction of transaction level modeling describing what the purpose of TLM is, how it is standardized and give an overview of different design tasks it solves. In the other sections of this document we give an overview of TLM modeling styles for programmers view, architects view and verification view.},
+  Cds_grade                = {0},
+  Cds_keywords             = {TLM, Transaction-Level-Modeling, OSCI},
+  File                     = {vangoo_08.pdf:vangoo_08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.10.23}
+}
+
+@Electronic{Vanthournout2008,
+  Title                    = {{D}eveloping {T}ransaction-level {M}odels in {S}ystem{C}},
+  Author                   = {Bart Vanthournout and Serge Goossens and Tim Kogel and CoWare, Inc.},
+  Language                 = {english},
+  Month                    = aug,
+  Organization             = {CoWare, Inc.},
+  Url                      = {www.coware.com/PDF/COWARETLMWHITEPAPER-AUG04.PDF},
+  Year                     = {2008},
+
+  Abstract                 = {The purpose of this white paper is to give an overview of the support that transaction level modeling (TLM) in SystemC provides for System level modeling. More specifically we will address how TLM supports different SoC design and verification tasks. In this document we will first give an introduction of transaction level modeling describing what the purpose of TLM is, how it is standardized and give an overview of different design tasks it solves. In the other sections of this document we give an overview of TLM modeling styles for programmers view, architects view and verification view.},
+  Cds_grade                = {0},
+  Cds_keywords             = {TLM, Transaction-Level-Modeling, OSCI},
+  File                     = {vangoo_08.pdf:vangoo_08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.10.23}
+}
+
+@Article{varsha_08,
+  Title                    = {{E}rror-{R}esilient {M}otion {E}stimation {A}rchitecture},
+  Author                   = {Varatkar, G. V. and Shanbhag, N. R.},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2008},
+  Number                   = {10},
+  Pages                    = {1399--1412},
+  Volume                   = {16},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/TVLSI.2008.2000675},
+  File                     = {varsha_08.pdf:varsha_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.07.26}
+}
+
+@Article{VardyMD_NP,
+  Title                    = {{T}he intractability of computing the minimum distance of a code},
+  Author                   = {Vardy, A.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1997},
+  Pages                    = {1757--1766},
+  Volume                   = {43},
+
+  Owner                    = {punekar}
+}
+
+@Article{varbe_91,
+  Title                    = {{B}it-level soft-decision decoding of {R}eed-{S}olomon codes},
+  Author                   = {Vardy, A. and Be'ery, Y.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {1991},
+  Number                   = {3},
+  Pages                    = {440--444},
+  Volume                   = {39},
+
+  Doi                      = {10.1109/26.79287},
+  File                     = {varbe'_91.pdf:varbe'_91.pdf:PDF},
+  Keywords                 = {Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {Subfield Subcode Zerlegung von RS Codes (in BCH Subcodes und den "gluevector")},
+  Timestamp                = {2011.07.14}
+}
+
+@MastersThesis{MTvarel14,
+  Title                    = {{E}mbedded {A}rchitecture to value {A}merican {O}ptions on the {S}tock {M}arket},
+  Author                   = {Javier Alejandro Varela},
+  School                   = {{M}icroelectronic {S}ystems {D}esign {R}eseach {G}roup, {D}epartment of {E}lectrical {E}ngineering and {I}nformation {T}echnology, {U}niversity of {K}aiserslautern},
+  Year                     = {2014},
+  Month                    = {aug},
+
+  Owner                    = {varela},
+  Timestamp                = {2014.12.20}
+}
+
+@InProceedings{varbru_15a,
+  Title                    = {{E}xploiting the {B}rownian {B}ridge {T}echnique to improve {L}ongstaff-{S}chwartz {A}merican {O}ption {P}ricing on {FPGA} {S}ystems},
+  Author                   = {Varela, Javier Alejandro and Brugger, Christian and De Schryver, Christian and Wehn, Norbert and Tang, Songyin and Omland, Steffen},
+  Booktitle                = {Proceedings of the 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig)},
+  Year                     = {2015},
+  Month                    = dec,
+  Pages                    = {1-6},
+
+  Abstract                 = {Risk analysis and management is a very compute intensive task that needs to be performed on a regular (daily) basis. FPGAs have already shown acceleration potential in financial applications with high energy efficiency. In this paper, we present a novel way to price multi-dimensional American options (highly involved in risk management) targeting heterogeneous CPU/FPGA systems. We demonstrate how an architectural limitation of the Longstaff-Schwartz algorithm is solved by means of an algorithmic transformation employing the Brownian Bridge technique. Based on this, we present a new pricing system on FPGAs that achieves a 2x improvement in runtime compared to the state-of-the-art solution in the same technology, with a maximum resources overhead of 15%. On top of that, our proposed architecture is 1.8x more energy efficient than the same reference.},
+  Doi                      = {10.1109/ReConFig.2015.7393306},
+  File                     = {varbru_15a.pdf:varbru_15a.pdf:PDF},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2016-07-28}
+}
+
+@InCollection{varbru_15,
+  Title                    = {{P}ricing {H}igh-{D}imensional {A}merican {O}ptions on {H}ybrid {CPU}/{FPGA} {S}ystems},
+  Author                   = {Javier Alejandro Varela and Christian Brugger and Songyin Tang and Norbert Wehn and Ralf Korn},
+  Booktitle                = {FPGA Based Accelerators for Financial Applications},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2015},
+  Edition                  = {1st},
+  Editor                   = {De Schryver, Christian},
+  Month                    = jul,
+  Pages                    = {143--166},
+
+  Abstract                 = {In today’s markets, high-speed and energy-efficient computations are mandatory in the financial and insurance industry. As American options are amongst the most frequently traded products in the derivatives market, it becomes essential to place the focus on their pricing process. Calculating the price of an American option in particular is a challenging task due to the freedom the holder is given in terms of exercise date and the involved trading strategy. A well known algorithm that solves this task is the Longstaff-Schwartz (LS) algorithm, which applies least-squares linear regression on simulated Monte Carlo (MC) paths. This work presents a novel way to price high-dimensional American options, coined Reverse LS, using techniques of the embedded community. The proposed architecture targets hybrid Central Processing Unit (CPU)/Field Programmable Gate Array (FPGA) systems, and it exploits the FPGA reconfiguration to deliver high-throughput. With a bit-true algorithmic transformation based on recomputation, it is possible to eliminate the memory bottleneck and access costs present in a straightforward implementation. The result is a pricing system that is 16× faster and 268× more energy-efficient than an optimized Intel CPU implementation.},
+  Doi                      = {10.1007/978-3-319-15407-7_7},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-08-21}
+}
+
+@InProceedings{varkes_15,
+  Title                    = {{O}ptimization {S}trategies for {P}ortable {C}ode for {M}onte {C}arlo-{B}ased {V}alue-at-{R}isk {S}ystems},
+  Author                   = {Varela, Javier Alejandro and Kestel, Claus and De Schryver, Christian and Wehn, Norbert and Desmettre, Sascha and Korn, Ralf},
+  Booktitle                = {Proceedings of the 8th Workshop on High Performance Computational Finance (WHPCF '15)},
+  Year                     = {2015},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {3:1--3:8},
+  Publisher                = {ACM},
+  Series                   = {WHPCF '15},
+
+  Abstract                 = {Value-at-risk (VaR) computations are one important basic element of risk analysis and management applications. On the one hand, risk management systems need to be flexible and maintainable, but on the other hand they require a very high computational power. In general, accelerators provide high speedups, but come with a limited flexibility. In this work, we investigate two approaches towards portable and fast code for VaR computations on heterogeneous platforms: operator tuning and the use of OpenCL. We show that operator tuning can save up one third of run time on CPU-based systems in the calibration step. For OpenCL, we present a detailed analysis of run time on CPU, GPU, and Xeon Phi, and evaluate its portability. We also find that the same code runs up to 12x faster in a VaR setting with an accelerator card being present, without any code changes required.},
+  Acmid                    = {2830559},
+  Articleno                = {3},
+  Cds_grade                = {5},
+  Doi                      = {10.1145/2830556.2830559},
+  File                     = {varkes_15.pdf:varkes_15.pdf:PDF},
+  ISBN                     = {978-1-4503-4015-1},
+  Keywords                 = {AGWehn, finance},
+  Location                 = {Austin, Texas},
+  Numpages                 = {8},
+  Owner                    = {varela},
+  Timestamp                = {2016-01-04},
+  Url                      = {http://doi.acm.org/10.1145/2830556.2830559}
+}
+
+@InProceedings{varweh_17,
+  Title                    = {{N}ear {R}eal-{T}ime {R}isk {S}imulation of {C}omplex {P}ortfolios on {H}eterogeneous {C}omputing {S}ystems with {O}pen{CL}},
+  Author                   = {Javier Alejandro Varela and Norbert Wehn},
+  Booktitle                = {Proceedings of the 5th International Workshop on OpenCL},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Number                   = {2},
+  Pages                    = {2:1--2:10},
+  Publisher                = {ACM},
+  Series                   = {IWOCL 2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22},
+  Url                      = {http://doi.acm.org/10.1145/3078155.3078161}
+}
+
+@Unpublished{varweh_17c,
+  Title                    = {{R}unning {F}inancial {R}isk {M}anagement {A}pplications on {FPGA} in the {A}mazon {C}loud},
+  Author                   = {Javier Alejandro Varela and Norbert Wehn},
+  Note                     = {(whitepaper)},
+
+  Month                    = {Dec.},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.09}
+}
+
+@InProceedings{varweh_17b,
+  Title                    = {{R}eal-{T}ime {F}inancial {R}isk {M}easurement of {D}ynamic {C}omplex {P}ortfolios with {P}ython and {P}y{O}pen{CL}},
+  Author                   = {Javier Alejandro Varela and Norbert Wehn and Sascha Desmettre and Ralf Korn},
+  Booktitle                = {Proceedings of the 7th Workshop on Python for High-Performance and Scientific Computing},
+  Year                     = {2017},
+
+  Address                  = {Denver, CO, USA},
+  Number                   = {3},
+  Pages                    = {3:1--3:10},
+  Publisher                = {ACM},
+  Series                   = {PyHPC'17},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.07}
+}
+
+@InProceedings{varweh_17a,
+  Title                    = {{E}xploiting {D}ecoupled {O}pen{CL} {W}ork-{I}tems with {D}ata {D}ependencies on {FPGA}s: {A} {C}ase {S}tudy},
+  Author                   = {Javier Alejandro Varela and Norbert Wehn and Qian Liang and Songyin Tang},
+  Booktitle                = {2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
+  Year                     = {2017},
+  Month                    = {May},
+  Pages                    = {124-131},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.22}
+}
+
+@InProceedings{varfos_04,
+  Title                    = {{B}elief-propagation with information correction: improved near maximum-likelihood decoding of low-density parity-check codes},
+  Author                   = {N. Varnica and M. Fossorier},
+  Booktitle                = {Proc. Int. Symp. Information Theory ISIT 2004},
+  Year                     = {2004},
+
+  Doi                      = {10.1109/ISIT.2004.1365380},
+  File                     = {varfos_04.pdf:varfos_04.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {Scholl},
+  Review                   = {Paper zur information correction technik},
+  Timestamp                = {2011.07.14}
+}
+
+@Article{varfos_07,
+  Title                    = {{A}ugmented {B}elief {P}ropagation {D}ecoding of {L}ow-{D}ensity {P}arity {C}heck {C}odes},
+  Author                   = {Varnica, N. and Fossorier, M. P. C. and Kavcic, A.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2007},
+  Number                   = {7},
+  Pages                    = {1308--1317},
+  Volume                   = {55},
+
+  Doi                      = {10.1109/TCOMM.2007.900611},
+  File                     = {varfos_07.pdf:varfos_07.pdf:PDF},
+  Keywords                 = {LDPC},
+  Owner                    = {Scholl},
+  Review                   = {LDPC Decodieralgorithmus mit verbesserter nachrichtentech. Performanz},
+  Timestamp                = {2012.03.09}
+}
+
+@Article{var_11,
+  Title                    = {{P}erformance of {LDPC} {C}odes {U}nder {F}aulty {I}terative {D}ecoding},
+  Author                   = {Varshney, L.R.},
+  Journal                  = {Information Theory, IEEE Transactions on},
+  Year                     = {2011},
+  Number                   = {7},
+  Pages                    = {4427-4444},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TIT.2011.2145870},
+  File                     = {var_11.pdf:var_11.pdf:PDF},
+  ISSN                     = {0018-9448},
+  Keywords                 = {error statistics;iterative decoding;message passing;nonlinear estimation;parity check codes;LDPC codes;communication channels;communication theory;density evolution equations;faulty iterative decoding;low-density parity-check codes;message-passing;nonlinear estimation thresholds;probability of error;Circuit faults;Decoding;Iterative decoding;Noise;Noise measurement;Wires;Communication system fault tolerance;decoding;density evolution;low-density parity-check (LDPC) codes;memories},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@Article{vazgon_06,
+  Title                    = {{Design of Serially-Concatenated LDGM Coded MIMO Systems}},
+  Author                   = {Vázquez-Araújo, F. J. and Gonzáles-López, M. and Castedo, L. and Garcia-Frias, J.},
+  Journal                  = {Signal Processing Advances in Wireless Communications, 2006. SPAWC '06. IEEE 7th Workshop on},
+  Year                     = {2006},
+  Pages                    = {1--5},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{Vega2013,
+  Title                    = {{AXI}4-{S}tream {U}psizing/{D}ownsizing {D}ata {W}idth {C}onverters for {H}ardware-{I}n-the-{L}oop {S}imulations},
+  Author                   = {Luis Vega and Philipp Schläfer and Christian de Schry},
+  Institution              = {University of Kaiserslautern, Germany},
+  Year                     = {2013},
+  Month                    = apr,
+
+  Abstract                 = {Hardware prototyping is an essential part in the hardware design flow. Furthermore, hardware prototyping usually relies on system-level design and hardware-in-the-loop simulations in order to develop, test and evaluate intellectual property cores. One common task in this process consist on interfacing cores with different port specifications. Data width conversion is used to overcome this issue. This work presents two open source hardware cores compliant with AXI4-Stream bus protocol, where each core performs upsizing/downsizing data width conversion.},
+  Cds_grade                = {5},
+  Cds_keywords             = {FPGA; Hardware-in-the-loop; Streaming, downsizing, upsizing, data width converter, AXI4-Stream},
+  Cds_read                 = {2013-04-22},
+  File                     = {vegsch_13.pdf:vegsch_13.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2013.04.23},
+  Url                      = {http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:hbz:386-kluedo-34903}
+}
+
+@TechReport{vegsch_13,
+  Title                    = {{AXI}4-{S}tream {U}psizing/{D}ownsizing {D}ata {W}idth {C}onverters for {H}ardware-{I}n-the-{L}oop {S}imulations},
+  Author                   = {Luis Vega and Philipp Schläfer and Christian de Schryver},
+  Institution              = {University of Kaiserslautern, Germany},
+  Year                     = {2013},
+  Month                    = apr,
+
+  Abstract                 = {Hardware prototyping is an essential part in the hardware design flow. Furthermore, hardware prototyping usually relies on system-level design and hardware-in-the-loop simulations in order to develop, test and evaluate intellectual property cores. One common task in this process consist on interfacing cores with different port specifications. Data width conversion is used to overcome this issue. This work presents two open source hardware cores compliant with AXI4-Stream bus protocol, where each core performs upsizing/downsizing data width conversion.},
+  Cds_grade                = {5},
+  Cds_keywords             = {FPGA; Hardware-in-the-loop; Streaming, downsizing, upsizing, data width converter, AXI4-Stream},
+  Cds_read                 = {2013-04-22},
+  File                     = {vegsch_13.pdf:vegsch_13.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2013.04.23},
+  Url                      = {http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:hbz:386-kluedo-34903}
+}
+
+@InProceedings{venher_06,
+  Title                    = {{Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM}},
+  Author                   = {Venkatesan, Ravi K. and Herr, S. and Rotenberg, E.},
+  Booktitle                = {Proc. of HPCA},
+  Year                     = {2006}
+}
+
+@InProceedings{vendec_08,
+  Title                    = {{Randomized Progressive Edge-Growth (RandPEG)}},
+  Author                   = {A. Venkiah and D. Declercq and C. Poulliat},
+  Booktitle                = {Proc. 5th International Symposium on Turbo Codes and Related Topics},
+  Year                     = {2008},
+
+  Address                  = {Lausanne, Switzerland},
+  Month                    = sep,
+  Pages                    = {283--287},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{verwyn_10,
+  Title                    = {{R}eduction {R}ules for {R}eset/{I}nhibitor {N}ets},
+  Author                   = {Verbeek, H. M. W. and Wynn, M. T. and van der Aalst, W. M. P. and ter Hofstede, A. H. M.},
+  Journal                  = {J. Comput. Syst. Sci.},
+  Year                     = {2010},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {125--143},
+  Volume                   = {76},
+
+  Acmid                    = {1660380},
+  Address                  = {Orlando, FL, USA},
+  Doi                      = {10.1016/j.jcss.2009.06.003},
+  ISSN                     = {0022-0000},
+  Issue_date               = {March, 2010},
+  Keywords                 = {Boundedness, Inhibitor arcs, Liveness, Petri nets, Reduction rules, Reset arcs},
+  Numpages                 = {19},
+  Owner                    = {MJ},
+  Publisher                = {Academic Press, Inc.},
+  Timestamp                = {2016-12-05},
+  Url                      = {http://dx.doi.org/10.1016/j.jcss.2009.06.003}
+}
+
+@Article{verdec_06,
+  Title                    = {{A low-cost parallel scalable FPGA architecture for regular and irregular LDPC decoding}},
+  Author                   = {F. Verdier and D. Declercq},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2006},
+
+  Month                    = dec,
+  Number                   = {7},
+  Pages                    = {1215--1223},
+  Volume                   = {54},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{verintel15,
+  Title                    = {{I}ntel {L}ooks to {F}uture {D}ata {C}enter {M}arket {W}ith \$16.7{B} {A}ltera {A}cquisition},
+
+  Author                   = {Jason Verge},
+  HowPublished             = {Data Center Knowledge, \url{http://www.datacenterknowledge.com/archives/2015/06/01/intel-bets-on-server-fpgas-with-16-7b-altera-acquisition/}},
+  Month                    = jun,
+  Note                     = {last access 2015-10-19},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.06.02}
+}
+
+@Article{verbal_19,
+  Title                    = {{S}elective policies for efficient state retention in transiently-powered embedded systems: {E}xploiting properties of {NVM} technologies},
+  Author                   = {Theodoros D. Verykios and Domenico Balsamo and Geoff V. Merrett},
+  Journal                  = {Sustainable Computing: Informatics and Systems},
+  Year                     = {2019},
+  Pages                    = {167 - 178},
+  Volume                   = {22},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {VERYKIOS2019167},
+  Ccr_keywords             = {todo},
+  Ccr_relevance            = {in general},
+  Ccr_topic                = {CP},
+  Doi                      = {https://doi.org/10.1016/j.suscom.2018.07.003},
+  ISSN                     = {2210-5379},
+  Keywords                 = {TCS},
+  Keywords_original        = {Selective state retention, Energy harvesting, Non-Volatile Memory, Transient computing},
+  Owner                    = {CCR},
+  Url                      = {http://www.sciencedirect.com/science/article/pii/S2210537917304365}
+}
+
+@InProceedings{vesmyn_17,
+  Title                    = {{M}odel predictive control of {SPMSM} based on {FPGA} and processor},
+  Author                   = {L. Vesely and Z. Mynar},
+  Booktitle                = {2017 IEEE International Conference on Industrial Technology (ICIT)},
+  Year                     = {2017},
+  Month                    = {March},
+  Pages                    = {324-329},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {HETEROGENEOUS PLATFORMS; cite number in presentation [30]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/ICIT.2017.7913104},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {constraint handling;field programmable gate arrays;linearisation techniques;machine vector control;multiprocessing systems;permanent magnet motors;predictive control;surface mount technology;synchronous motors;linear model predictive control;surface mounted permanent magnet synchronous motor;field-programmable gate array;dual-core processor;{MPC} algorithm;field weakening ability;modified linearization;constraint handling;computational complexity;high-performing hardware;SPMSM;{FPGA};Mathematical model;Field programmable gate arrays;Stators;Optimization;Computational modeling;Voltage control;Heuristic algorithms},
+  Owner                    = {CCR}
+}
+
+@InProceedings{viatho_14,
+  Title                    = {{R}esistive {M}emories for {U}ltra-{L}ow-{P}ower embedded computing design},
+  Author                   = {E. Vianello and O. Thomas and G. Molas and O. Turkyilmaz and N. Jovanović and D. Garbin and G. Palma and M. Alayan and C. Nguyen and J. Coignus and B. Giraud and T. Benoist and M. Reyboz and A. Toffoli and C. Charpin and F. Clermidy and L. Perniola},
+  Booktitle                = {2014 IEEE International Electron Devices Meeting},
+  Year                     = {2014},
+  Month                    = {Dec},
+  Pages                    = {6.3.1-6.3.4},
+
+  Doi                      = {10.1109/IEDM.2014.7046995},
+  ISSN                     = {2156-017X},
+  Keywords                 = {bridge circuits;field programmable gate arrays;flip-flops;hafnium compounds;leakage currents;logic CAD;low-power electronics;power consumption;resistive RAM;titanium;OxRAM cell;fast switching time;nonvolatile flip-flop;low operating voltage;power on-off operations;zero standby leakage;operating mode;leakage current minimization;resistance ratio;dual-layer electrolyte stack;CBRAM cell;conductive bridge RAM cell;HRS value;high resistive state value;run time;standby power consumption suppression;saving area;ReRAM;SRAM based configuration memory;fixed-logic IC design;FPGA;device optimization;ultra low power embedded computing design;resistive memory;voltage 1 V;HfO2-Ti;Hafnium compounds;Field programmable gate arrays;Switches;CMOS integrated circuits;Programming;Leakage currents;Resistance},
+  Timestamp                = {2018-09-11}
+}
+
+@InProceedings{viespi_08,
+  Title                    = {{A Technical View on the URANUS Validation Plattform}},
+  Author                   = {A. Viessmann and C. Spiegel and A. Burnic and Z. Bau and K. Statnikov and A. Waadt and S. Wang and X. Popon, R and Rodriguez Velilla and H. Saarnisaari and M. Alles and T. Brack and F. Kienle and F. Berens and S. Rotolo and F. Scalise, G and Bruck and N. Wehn and P. Jung},
+  Booktitle                = {Proceedings of ICT-MobileSummit 2008},
+  Year                     = {2008},
+
+  Address                  = {Stockholm, Sweden},
+  Month                    = jun,
+  Pages                    = {10--12},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@InProceedings{vigmas_00,
+  Title                    = {{A 50 Mbit/s Iterative Turbo-Decoder}},
+  Author                   = {F. Viglione and G. Masera and G. Piccinini and M. Ruo Roch and M. Zamboni},
+  Booktitle                = {Proc. 2000 Design, Automation and Test in Europe (DATE '00)},
+  Year                     = {2000},
+  Month                    = mar,
+  Pages                    = {176--180},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{vikhas_06,
+  Title                    = {{O}n joint detection and decoding of linear block codes on {G}aussian vector channels},
+  Author                   = {Vikalo, H. and Hassibi, B.},
+  Journal                  = {Signal Processing, IEEE Transactions on},
+  Year                     = {2006},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {3330--3342},
+  Volume                   = {54},
+
+  Doi                      = {10.1109/TSP.2006.877675},
+  Owner                    = {Kienle},
+  Timestamp                = {2010.01.08}
+}
+
+@Article{vikhas_04,
+  Title                    = {{Iterative Decoding for MIMO Channels Via Modified Sphere Decoding}},
+  Author                   = {H. Vikalo and B. Hassibi and T. Kailath},
+  Journal                  = {Wireless Communications, IEEE Transactions on},
+  Year                     = {2004},
+
+  Month                    = nov,
+  Number                   = {6},
+  Pages                    = { 2299--2311},
+  Volume                   = {3},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{viljoh_14,
+  Title                    = {{S}caling the {P}ower {W}all: {A} {P}ath to {E}xascale},
+  Author                   = {O. Villa and D. R. Johnson and M. Oconnor and E. Bolotin and D. Nellans and J. Luitjens and N. Sakharnykh and P. Wang and P. Micikevicius and A. Scudiero and S. W. Keckler and W. J. Dally},
+  Booktitle                = {SC14: International Conference for High Performance Computing, Networking, Storage and Analysis},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {830-841},
+
+  Doi                      = {10.1109/SC.2014.73},
+  ISSN                     = {2167-4329},
+  Keywords                 = {multiprocessing systems;parallel machines;performance evaluation;power aware computing;ExaFlops;HPC application;energy efficiency improvement;exascale system;performance projection;supercomputer development;Bandwidth;Computer architecture;Graphics processing units;Instruction sets;Kernel;Registers;Supercomputers},
+  Owner                    = {scholl},
+  Timestamp                = {2016.04.26}
+}
+
+@InProceedings{vinwit_16,
+  Title                    = {{T}owards {G}reen {A}viation with {P}ython at {P}etascale},
+  Author                   = {Peter Vincent and Freddie Witherden and Brian Vermeire and Jin Seok Park and Arvind Iyer},
+  Booktitle                = {SC16: International Conference for High Performance Computing, Networking, Storage and Analysis},
+  Year                     = {2016},
+  Month                    = {Nov},
+  Pages                    = {1-11},
+
+  Doi                      = {10.1109/SC.2016.1},
+  Owner                    = {varela},
+  Timestamp                = {2017.08.16}
+}
+
+@TechReport{vin_02,
+  Title                    = {{M}aximum $k$-{I}ntersection, {E}dge {L}abeled {M}ultigraph {M}ax {C}apacity $k$-{P}ath, and {M}ax {F}actor $k$-gcd are all {NP}-hard},
+  Author                   = {Vinterbo, S.A.},
+  Institution              = {Decision Systems Group, Harvard Medical School},
+  Year                     = {2002},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-25}
+}
+
+@InCollection{virmac_13,
+  Title                    = {{G}eneration of {R}eliable {R}andomness via {S}ocial {P}henomena},
+  Author                   = {Virgilio, Roberto and Maccioni, Antonio},
+  Booktitle                = {Model and Data Engineering},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2013},
+  Editor                   = {Cuzzocrea, Alfredo and Maabout, Sofian},
+  Pages                    = {65-77},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {8216},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {random number generation, social phenomena},
+  Doi                      = {10.1007/978-3-642-41366-7_6},
+  File                     = {virmac_13.pdf:virmac_13.pdf:PDF},
+  ISBN                     = {978-3-642-41365-0},
+  Keywords                 = {random numbers},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24},
+  Url                      = {http://dx.doi.org/10.1007/978-3-642-41366-7_6}
+}
+
+@Article{vit_98,
+  Title                    = {{An Intuitive Justification and a Simplified Implementation of the MAP Decoder for Convolutional Codes}},
+  Author                   = {A. Viterbi},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {1998},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {260--264},
+  Volume                   = {16},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{vit_67,
+  Title                    = {{E}rror {B}ounds for {C}onvolutional {C}odes and an {A}symptotically {O}ptimum {D}ecoding {A}lgorithm},
+  Author                   = {A. J. Viterbi},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1967},
+
+  Month                    = apr,
+  Number                   = {2},
+  Pages                    = {260--269},
+  Volume                   = {13},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{vitomu_79,
+  Title                    = {{Principles of Digital Communication and Coding}},
+  Author                   = {A. J. Viterbi and J. K. Omura},
+  Publisher                = {McGraw-Hill},
+  Year                     = {1979},
+
+  Address                  = {New York},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{vitvit_83,
+  Title                    = {{Nonlinear Estimation of PSK Modulated Carrier Phase with Application to Burst Digital Transmission}},
+  Author                   = {Viterbi, A. J. and Viterbi, A. M.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1983},
+
+  Month                    = jul,
+  Pages                    = {543--551},
+  Volume                   = {32},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{vitbou_99,
+  Title                    = {{A} universal lattice code decoder for fading channels},
+  Author                   = {Viterbo, E. and Boutros, J.},
+  Journal                  = {Information Theory, IEEE Transactions on},
+  Year                     = {1999},
+
+  Month                    = {jul},
+  Number                   = {5},
+  Pages                    = {1639 -1642},
+  Volume                   = {45},
+
+  Doi                      = {10.1109/18.771234},
+  ISSN                     = {0018-9448},
+  Keywords                 = {arbitrary lattice code;bounded distance search;channel state information;decoding radius;fading channels;lattice points;maximum-likelihood decoding algorithm;received point;receiver;universal lattice code decoder;combined source-channel coding;fading channels;lattice theory;maximum likelihood decoding;search problems;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.12}
+}
+
+@InProceedings{vivbei_10,
+  Title                    = {{O}n {L}ine {P}ower {O}ptimization of {D}ata {F}low {M}ulti-core {A}rchitecture {B}ased on {V}dd-{H}opping for {L}ocal {DVFS}.},
+  Author                   = {Pascal Vivet and Edith Beigné and Hugo Lebreton and Nacer-Eddine Zergainoh},
+  Booktitle                = {PATMOS'10},
+  Year                     = {2010},
+  Pages                    = {94-104}
+}
+
+@InProceedings{vivlat_07,
+  Title                    = {{FAUST, an Asynchronous Network-on-Chip based Architecture for Telecom Applications}},
+  Author                   = {Pascal Vivet and Didier Lattard and Fabien Clermidy and Edith Beigne and Christian Bernard and Yves Durand and Jean Durupt and Didier Varreau},
+  Booktitle                = {Proc. 2007 Design, Automation and Test in Europe (DATE '07)},
+  Year                     = {2007},
+
+  Owner                    = {vogt},
+  Timestamp                = {2007.05.30}
+}
+
+@Misc{Vogt2003,
+  Title                    = {{Z}yklische {B}lockcodes ({E}inf{Ã}¼hrung)},
+
+  Author                   = {J�rn Vogt},
+  Month                    = jul,
+  Year                     = {2003},
+
+  Cds_grade                = {3},
+  Cds_read                 = {2008-10},
+  Cds_review               = {block codes, cyclic block codes, BCH, circuit},
+  Date-added               = {2008-10-15 10:53:00 +0200},
+  Date-modified            = {2008-10-15 10:54:43 +0200},
+  File                     = {vogzyklische03.pdf:vogzyklische03.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Misc{vogzyklische03,
+  Title                    = {{Z}yklische {B}lockcodes ({E}inführung)},
+
+  Author                   = {J�rn Vogt},
+  Month                    = jul,
+  Year                     = {2003},
+
+  Cds_grade                = {3},
+  Cds_read                 = {2008-10},
+  Cds_review               = {block codes, cyclic block codes, BCH, circuit},
+  Date-added               = {2008-10-15 10:53:00 +0200},
+  Date-modified            = {2008-10-15 10:54:43 +0200},
+  File                     = {vogzyklische03.pdf:vogzyklische03.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Article{vogert_00,
+  Title                    = {{Reducing Bit Width of Extrinsic Memory in Turbo Decoder Realizatian}},
+  Author                   = {J. Vogt and J. Ertek and A. Finger},
+  Journal                  = {Electronics Letters},
+  Year                     = {2000},
+
+  Month                    = aug,
+  Number                   = {20},
+  Pages                    = {1714--1716},
+  Volume                   = {36},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{vogfin_01,
+  Title                    = {{Increasing Throughput of Iterative Decoders}},
+  Author                   = {J. Vogt and A. Finger},
+  Journal                  = {IEEE Electronic Letters},
+  Year                     = {2001},
+
+  Month                    = jun,
+  Number                   = {12},
+  Pages                    = {770--771},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{vogfin_00,
+  Title                    = {{Improving the Max-Log-MAP Turbo Decoder}},
+  Author                   = {J. Vogt and A. Finger},
+  Journal                  = {IEEE Electronic Letters},
+  Year                     = {2000},
+  Pages                    = {1937--1939},
+  Volume                   = {36},
+
+  File                     = {vogfin_00.pdf:vogfin_00.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{vogkoo_99,
+  Title                    = {{Comparison of Different Turbo Decoder Realizations for IMT-2000}},
+  Author                   = {J. Vogt and K. Koora and A. Finger and G. Fettweis},
+  Booktitle                = {Proc. 1999 Global Telecommunications Conference (GLOBECOM '99)},
+  Year                     = {1999},
+
+  Address                  = {Rio de Janeiro, Brazil},
+  Month                    = dec,
+  Pages                    = {2704--2708},
+  Volume                   = {5},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{vogkoo_99a,
+  Title                    = {{C}omparison of different turbo decoder realizations for {IMT}-2000},
+  Author                   = {J. Vogt and K. Koors and A. Finger and G. Fettweis},
+  Booktitle                = {Global Telecommunications Conference, 1999. GLOBECOM '99},
+  Year                     = {1999},
+  Pages                    = {2704-2708 vol.5},
+  Volume                   = {5},
+
+  Doi                      = {10.1109/GLOCOM.1999.831790},
+  Keywords                 = {computational complexity;decoding;land mobile radio;turbo codes;IMT-2000;SISO decoder;hardware implementation;mobile communications standard;performance;power consumption;reduced complexity algorithms;soft-input-soft-output decoder;throughput;turbo coding;turbo decoder algorithms;turbo decoder architectures;Convolutional codes;Energy consumption;Fingers;Hardware;Iterative decoding;Laboratories;Mobile communication;Table lookup;Telecommunication standards;Turbo codes},
+  Owner                    = {StW},
+  Timestamp                = {2018.06.25}
+}
+
+@PhdThesis{Phdvogt08,
+  Title                    = {{A} {R}econfigurable {A}pplication-specific {I}nstruction-set {P}rocessor for {T}rellis-based {C}hannel {D}ecoding},
+  Author                   = {Timo Vogt},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2008},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {ASIP, Channel Code, reconfiguration},
+  Keywords                 = {ASIP Turbo AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@MastersThesis{MTvogt01,
+  Title                    = {{Thesis in preparation}},
+  Author                   = {T. Vogt},
+  School                   = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2001},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{vognee_06,
+  Title                    = {{A} {R}econfigurable {O}uter {M}odem {P}latform for {F}uture {C}ommunications {S}ystems},
+  Author                   = {Timo Vogt and Christian Neeb and Norbert Wehn},
+  Booktitle                = {Dynamically Reconfigurable Architectures},
+  Year                     = {2006},
+
+  Address                  = {Dagstuhl, Germany},
+  Editor                   = {Peter M. Athanas and Jürgen Becker and Gordon Brebner and Jürgen Teich},
+  Month                    = apr,
+  Number                   = {06141},
+  Publisher                = {Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany},
+  Series                   = {Dagstuhl Seminar Proceedings},
+
+  Abstract                 = {Future mobile and wireless communications networks require flexible modem architectures with high performance. Efficient utilization of application specific flexibility is key to fulfill these requirements. For high throughput a single processor can not provide the necessary computational power. Hence multi-processor architectures become necessary. This paper presents a multi-processor platform based on a new dynamically reconfigurable application specific instruction set processor (dr-ASIP) for the application domain of channel decoding. Inherently parallel decoding tasks can be mapped onto individual processing nodes. The implied challenging inter-processor communication is efficiently handled by a Network-on-Chip (NoC) such that the throughput of each node is not degraded. The dr-ASIP features Viterbi and Log-MAP decoding for support of convolutional and turbo codes of more than 10 currently specified mobile and wireless standards. Furthermore, its flexibility allows for adaptation to future systems.},
+  File                     = {vognee_06.pdf:vognee_06.pdf:PDF},
+  ISSN                     = {1862-4405},
+  Keywords                 = {ASIP Turbo AGWehn},
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24},
+  Url                      = {http://drops.dagstuhl.de/opus/volltexte/2006/730}
+}
+
+@InProceedings{vognee_06a,
+  Title                    = {{A} {R}econfigurable {M}ulti-{P}rocessor {P}latform for {C}onvolutional and {T}urbo {D}ecoding},
+  Author                   = {Timo Vogt and Christian Neeb and Norbert Wehn},
+  Booktitle                = {Reconfigurable Communication-centric SoCs (ReCoSoC)},
+  Year                     = {2006},
+
+  Address                  = {Montpellier, France},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {NoC, ASIP, turbo code},
+  Cds_read                 = {2008-11},
+  File                     = {vognee_06a.pdf:vognee_06a.pdf:PDF},
+  Keywords                 = {ASIP Turbo AGWehn},
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Article{vogweh_08,
+  Title                    = {{A} {R}econfigurable {ASIP} for {C}onvolutional and {T}urbo {D}ecoding in a {SDR} {E}nvironment},
+  Author                   = {T. Vogt and N. Wehn},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2008},
+
+  Month                    = oct,
+  Pages                    = {1309-1320},
+  Volume                   = {16},
+
+  Abstract                 = {Future mobile and wireless communication networks require flexible modem architectures to support seamless services between different network standards. Hence, a common hardware platform that can support multiple protocols implemented or controlled by software, generally referred to as software defined radio (SDR), is essential. This paper presents a family of dynamically reconfigurable application-specific instruction-set processors (ASIPs) for channel coding in wireless communication systems. As a weakly programmable intellectual property (IP) core, it can implement trellis-based channel decoding in a SDR environment. It features binary convolutional decoding, and turbo decoding for binary as well as duobinary turbo codes for all current and upcoming standards. The ASIP consists of a specialized pipeline with 15 stages and a dedicated communication and memory infrastructure. Logic synthesis revealed a maximum clock frequency of 400 MHz and an area of 0.11 mm$^{2}$ for the processor's logic using a low power 65-nm technology. Memories require another 0.31 mm$^{2}$ . Simulation results for Viterbi and turbo decoding demonstrate maximum throughput of 196 and 34 Mb/s, respectively. The ASIP hence outperforms state-of-the-art decoder architectures targeting software defined radio by at least a factor of three while consuming only 60% or less of the logic area.},
+  Cds_grade                = {4},
+  Cds_read                 = {2008-10},
+  Cds_review               = {Introduction to ASIP FlexiTreP repeating general coding basics},
+  File                     = {vogweh_08.pdf:vogweh_08.pdf:PDF},
+  Keywords                 = {ASIP Turbo AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{vogweh_08a,
+  Title                    = {{A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment}},
+  Author                   = {Timo Vogt and Norbert Wehn},
+  Booktitle                = {Proc. Design, Automation and Test in Europe DATE '08},
+  Year                     = {2008},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+  Pages                    = {38--43},
+
+  File                     = {vogweh_08a.pdf:vogweh_08a.pdf:PDF},
+  Keywords                 = {Turbo, Convolutional, AGWehn},
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.31}
+}
+
+@InProceedings{vogweh_06,
+  Title                    = {{A Reconfigurable Application Specific Instruction Set Processor for Viterbi and Log-MAP Decoding}},
+  Author                   = {T. Vogt and N. Wehn},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems Design and Implementation SIPS '06},
+  Year                     = {2006},
+
+  Address                  = {Banff, Canada},
+  Month                    = oct,
+  Pages                    = {142-147},
+
+  File                     = {vogweh_06.pdf:vogweh_06.pdf:PDF},
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.01}
+}
+
+@InProceedings{vogweh_04,
+  Title                    = {{A Multi-Standard Channel-Decoder for Base-Station Applications}},
+  Author                   = {T. Vogt and N. Wehn and P. Alves},
+  Booktitle                = {Proc. 17th Symposium on Integrated Circuits and Systems Design SBCCI2004},
+  Year                     = {2004},
+
+  Address                  = {Porto de Galinhas, Brazil},
+  Month                    = sep,
+  Pages                    = {192--197},
+
+  File                     = {vogweh_04.pdf:vogweh_04.pdf:PDF},
+  Keywords                 = {Convolutional, AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{voidec_10,
+  Title                    = {{L}ow-complexity decoding for non-binary {LDPC} codes in high order fields},
+  Author                   = {Voicila, A. and Declercq, D. and Verdier, F. and Fossorier, M. and Urard, P.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2010},
+  Number                   = {5},
+  Pages                    = {1365--1375},
+  Volume                   = {58},
+
+  Doi                      = {10.1109/TCOMM.2010.05.070096},
+  Owner                    = {PS},
+  Timestamp                = {2014.09.23},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5464236}
+}
+
+@InProceedings{voidec_08,
+  Title                    = {{S}plit non-binary {LDPC} codes},
+  Author                   = {Voicila, A. and Declercq, D. and Verdier, F. and Fossorier, M. and Urard, P. },
+  Booktitle                = {Proc. IEEE International Symposium on Information Theory ISIT 2008},
+  Year                     = {2008},
+  Month                    = jul,
+  Pages                    = {955--959},
+
+  Doi                      = {10.1109/ISIT.2008.4595128},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{voidec_08a,
+  Title                    = {{A}rchitecture of a low-complexity non-binary {LDPC} decoder},
+  Author                   = {Voicila, A. and Declercq, D. and Verdier, F. and Fossorierl, M. and Urard, P.},
+  Booktitle                = {Proc. Digest of Technical Papers. International Conference on Consumer Electronics ICCE 2008},
+  Year                     = {2008},
+  Month                    = jan,
+  Pages                    = {1--2},
+
+  Doi                      = {10.1109/ICCE.2008.4587946},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{voidec_07,
+  Title                    = {{L}ow-{C}omplexity, {L}ow-{M}emory {EMS} {A}lgorithm for {N}on-{B}inary {LDPC} {C}odes},
+  Author                   = {Voicila, A. and Declereq, D. and Verdier, F. and Fossorier, M. and Urard, P.},
+  Booktitle                = {Proc. IEEE International Conference on Communications ICC '07},
+  Year                     = {2007},
+  Month                    = jun,
+  Pages                    = {671--676},
+
+  Doi                      = {10.1109/ICC.2007.115},
+  File                     = {voidec_07.pdf:voidec_07.pdf:PDF},
+  Keywords                 = {non binary LDPC},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@InProceedings{voiver_07,
+  Title                    = {{A}rchitecture of a low-complexity non-binary {LDPC} decoder for high order fields},
+  Author                   = {Voicila, A. and Verdier, F. and Declercq, D. and Fossorier, M. and Urard, P. },
+  Booktitle                = {Proc. International Symposium on Communications and Information Technologies ISCIT '07},
+  Year                     = {2007},
+  Month                    = oct,
+  Pages                    = {1201--1206},
+
+  Doi                      = {10.1109/ISCIT.2007.4392200},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@Article{vol_59,
+  Title                    = {{The CORDIC Trigonometric Computing Technique}},
+  Author                   = {J. Volder},
+  Journal                  = {IRE Transactions on Electronic Computing},
+  Year                     = {1959},
+
+  Month                    = sep,
+  Pages                    = {330-334},
+  Volume                   = {8},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InBook{volweh_92,
+  Title                    = {{The Synthesis Approach to Digital System Design}},
+  Author                   = {Vollmer, H. and Wehn, N.},
+  Chapter                  = {Register-Transfer Level Synthesis},
+  Pages                    = {87--114},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {1992},
+
+  Address                  = {Norwell, MA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{von_08,
+  Title                    = {{I}nterior-point algorithms for linear-programming decoding},
+  Author                   = {Vontobel, P.O.},
+  Booktitle                = {Information Theory and Applications Workshop, 2008},
+  Year                     = {2008},
+  Month                    = {Jan},
+  Pages                    = {433-437},
+
+  File                     = {von_08.pdf:von_08.pdf:PDF},
+  Keywords                 = {LPDecoding, interior point},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.08}
+}
+
+@InProceedings{vonkoe_06,
+  Title                    = {{T}owards {L}ow-{C}omplexity {L}inear-{P}rogramming {D}ecoding},
+  Author                   = {Vontobel, Pascal O. and Koetter, Ralf},
+  Booktitle                = {Turbo Codes Related Topics; 6th International ITG-Conference on Source and Channel Coding (TURBOCODING), 2006 4th International Symposium on},
+  Year                     = {2006},
+  Month                    = {April},
+  Pages                    = {1-9},
+
+  File                     = {vonkoe_06.pdf:vonkoe_06.pdf:PDF},
+  Keywords                 = {LPDecoding},
+  Owner                    = {Scholl},
+  Timestamp                = {2014.04.08}
+}
+
+@Article{vonkoe_05,
+  Title                    = {{G}raph-{C}over {D}ecoding and {F}inite-{L}ength {A}nalysis of {M}essage-{P}assing
+ {I}terative {D}ecoding of {LDPC} {C}odes},
+  Author                   = {Pascal O. Vontobel and
+ Ralf Koetter},
+  Journal                  = {CoRR},
+  Year                     = {2005},
+  Volume                   = {abs/cs/0512078},
+
+  Bibsource                = {dblp computer science bibliography, http://dblp.org},
+  Biburl                   = {http://dblp.uni-trier.de/rec/bib/journals/corr/abs-cs-0512078},
+  Timestamp                = {Wed, 10 Oct 2012 21:28:57 +0200},
+  Url                      = {http://arxiv.org/abs/cs/0512078}
+}
+
+@Book{vorros_09,
+  Title                    = {{D}ynamic {S}ystem {R}econfiguration in {H}eterogeneous {P}latforms {T}he {MORPHEUS} {A}pproach},
+  Author                   = {Nikolaos Voros and Alberto Rosti and Michael Hübner},
+  Publisher                = {Springer},
+  Year                     = {2009},
+  Note                     = {ISBN: 978-90-481-2426-8},
+  Number                   = {24},
+  Series                   = {Lecture Notes in Electrical Engineering},
+  Volume                   = {40},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.09.27}
+}
+
+@InBook{wacwin_16,
+  Title                    = {{T}he {R}elease of {A}utonomous {V}ehicles},
+  Author                   = {Wachenfeld, Walther
+and Winner, Hermann},
+  Editor                   = {Maurer, Markus
+and Gerdes, J. Christian
+and Lenz, Barbara
+and Winner, Hermann},
+  Pages                    = {425--449},
+  Publisher                = {Springer Berlin Heidelberg},
+  Year                     = {2016},
+
+  Address                  = {Berlin, Heidelberg},
+
+  Abstract                 = {In the future, the functions of autonomous driving could fundamentally change all road traffic; to do so, it would have to be implemented on a large scale, in series production.},
+  Booktitle                = {Autonomous Driving: Technical, Legal and Social Aspects},
+  Doi                      = {10.1007/978-3-662-48847-8_21},
+  ISBN                     = {978-3-662-48847-8},
+  Owner                    = {MJ},
+  Timestamp                = {2020-06-09},
+  Url                      = {https://doi.org/10.1007/978-3-662-48847-8_21}
+}
+
+@Article{wag_58,
+  Title                    = {{T}he dual simplex algorithm for bounded variables},
+  Author                   = {Wagner, Harvey M.},
+  Journal                  = {Naval Research Logistics Quarterly},
+  Year                     = {1958},
+  Number                   = {3},
+  Pages                    = {257--261},
+  Volume                   = {5},
+
+  Doi                      = {10.1002/nav.3800050306},
+  ISSN                     = {1931-9193},
+  Owner                    = {scholl},
+  Publisher                = {Wiley Subscription Services, Inc., A Wiley Company},
+  Timestamp                = {2016.08.03},
+  Url                      = {http://dx.doi.org/10.1002/nav.3800050306}
+}
+
+@Article{wak_68,
+  Title                    = {{A Permutation Network}},
+  Author                   = {A. Waksman},
+  Journal                  = {In Journal of the ACM},
+  Year                     = {1968},
+  Pages                    = {159-163},
+  Volume                   = {15},
+
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.14}
+}
+
+@Misc{wal_03,
+  Title                    = {{MDMC} {S}oftware - {R}andom {N}umber {G}enerators},
+
+  Author                   = {Wallace, C. S.},
+  HowPublished             = {\url{http://www.datamining.monash.edu.au/software/random/index.shtml}},
+  Month                    = jun,
+  Year                     = {2003},
+
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.20}
+}
+
+@Misc{Wallace2003,
+  Title                    = {{MDMC} {S}oftware - {R}andom {N}umber {G}enerators},
+
+  Author                   = {Wallace, C. S.},
+  HowPublished             = {\url{http://www.datamining.monash.edu.au/software/random/index.shtml}},
+  Month                    = jun,
+  Year                     = {2003},
+
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.04.20}
+}
+
+@Article{wal_96,
+  Title                    = {{F}ast {P}seudorandom {G}enerators for {N}ormal and {E}xponential {V}ariates},
+  Author                   = {Wallace, C. S.},
+  Journal                  = {ACM Trans. Math. Softw.},
+  Year                     = {1996},
+
+  Month                    = mar,
+  Pages                    = {119--127},
+  Volume                   = {22},
+
+  Acmid                    = {225554},
+  Address                  = {New York, NY, USA},
+  Cds_grade                = {0},
+  Cds_keywords             = {random numbers, generator},
+  Doi                      = {10.1145/225545.225554},
+  File                     = {wal_96.pdf:wal_96.pdf:PDF},
+  ISSN                     = {0098-3500},
+  Issue                    = {1},
+  Keywords                 = {finance},
+  Numpages                 = {9},
+  Owner                    = {CdS},
+  Publisher                = {ACM},
+  Timestamp                = {2011.04.20},
+  Url                      = {http://doi.acm.org/10.1145/225545.225554}
+}
+
+@InProceedings{waljoh_05,
+  Title                    = {{A} refined information geometric interpretation of turbo decoding},
+  Author                   = {Walsh, J.M. and Johnson, C.R., Jr. and Regalia, P.A.},
+  Booktitle                = {Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on},
+  Year                     = {2005},
+  Month                    = mar,
+  Pages                    = {iii/481--iii/484Vol.3},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/ICASSP.2005.1415751},
+  Owner                    = {kienle},
+  Timestamp                = {2007.07.09}
+}
+
+@InProceedings{walfet_00,
+  Title                    = {{DSP Implementation Issues for UMTS-Channel Coding}},
+  Author                   = {U. Walther and G. P. Fettweis},
+  Booktitle                = {Proc. 2000 Conference on Acoustics, Speech, and Signal Processing (ICASSP '00)},
+  Year                     = {2000},
+  Pages                    = {3219-3222},
+  Volume                   = {6},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wancha_14,
+  Title                    = {{S}torage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor},
+  Author                   = {C. {Wang} and N. {Chang} and Y. {Kim} and S. {Park} and Y. {Liu} and H. G. {Lee} and R. {Luo} and H. {Yang}},
+  Booktitle                = {2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)},
+  Year                     = {2014},
+  Month                    = {Jan},
+  Pages                    = {379-384},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {6742919},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/ASPDAC.2014.6742919},
+  ISSN                     = {2153-6961},
+  Keywords                 = {TCS},
+  Keywords_original        = {maximum power point trackers;microprocessor chips;solar cells;voltage regulators;converter-less maximum power point tracking;storage-less maximum power point tracking;photovoltaic cells;nonvolatile microprocessor;PV cells;MPPT charger;voltage regulator;energy storage element;energy buffer;microprocessor power management;DC-DC converter;dynamic power management;DPM;Microprocessors;Capacitors;Energy harvesting;Switches;Maximum power point trackers;Energy storage;Energy loss},
+  Owner                    = {CCR}
+}
+
+@InProceedings{wancha_01,
+  Title                    = {{Design of Viterbi Decoders with In-place State Metric Update and Hybrid Traceback Processing}},
+  Author                   = {Ching-Wen Wang and Yun-Nan Chang},
+  Booktitle                = {Signal Processing Systems, 2001 IEEE Workshop on},
+  Year                     = {2001},
+  Month                    = sep,
+  Pages                    = {5--15},
+
+  Doi                      = {10.1109/SIPS.2001.957325},
+  Owner                    = {vogt},
+  Timestamp                = {2007.02.28}
+}
+
+@Misc{shadie15,
+  Title                    = {{D}ie {P}hoto {A}nalysis},
+
+  Author                   = {Emma Wang and Sophia Shao},
+  HowPublished             = {Harvard Architecture, Circuits, and Compilers Group, \url{http://vlsiarch.eecs.harvard.edu/accelerators/die-photo-analysis}},
+  Note                     = {last access 2015-08-15},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.08.15}
+}
+
+@InProceedings{wanagr_08,
+  Title                    = {{S}ingle {E}vent {U}pset: {A}n {E}mbedded {T}utorial},
+  Author                   = {Fan Wang and Agrawal, V. D. },
+  Booktitle                = {Proc. 21st Int. Conf. VLSI Design VLSID 2008},
+  Year                     = {2008},
+  Pages                    = {429--434},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- SEU, Technology, Basics},
+  Doi                      = {10.1109/VLSI.2008.28},
+  File                     = {wanagr_08.pdf:wanagr_08.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{wanshe_14,
+  Title                    = {{P}arallel {I}nterleaver {D}esign for a {H}igh throughput {HSPA}+/{LTE} {M}ulti-{S}tandard {T}urbo {D}ecoder},
+  Author                   = {G. Wang and H. Shen and Y. Sun and J. R. Cavallaro and A. Vosoughi and Y. Guo},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2014},
+
+  Month                    = {May},
+  Number                   = {5},
+  Pages                    = {1376-1389},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCSI.2014.2309810},
+  ISSN                     = {1549-8328},
+  Keywords                 = {3G mobile communication;4G mobile communication;Long Term Evolution;decoding;memory architecture;packet radio networks;parallel architectures;CMOS technology;LTE-LTE-advanced mode;Long Term Evolution;Radix-4 MAP decoder cores;VLSI architecture;bit rate 1.6 Gbit/s;bit rate 826 Mbit/s;chip core area;concurrent reading-writing memory;frequency 600 MHz;high throughput HSPA-LTE multistandard turbo decoder;high-speed packet access evolution;multistandard 3G-4G wireless communication systems;parallel architectures;parallel interleaver design;Clocks;Computer architecture;Decoding;Hardware;Long Term Evolution;Throughput;ASIC implementation;HSPA$+$;LTE/LTE-advanced;VLSI architecture;interleaver;memory contention;parallel processing;turbo decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.11.04}
+}
+
+@InProceedings{wandon_14,
+  Title                    = {{P}roactive{DRAM}: {A} {DRAM}-initiated retention management scheme},
+  Author                   = {Jue Wang and Xiangyu Dong and Yuan Xie},
+  Booktitle                = {32nd IEEE International Conference on Computer Design (ICCD)},
+  Year                     = {2014},
+  Month                    = {Oct},
+  Pages                    = {22-27},
+
+  Doi                      = {10.1109/ICCD.2014.6974657},
+  Keywords                 = {DRAM chips;scheduling;DRAM scaling;ProactiveDRAM;command scheduling;energy overhead;multirate DRAM refresh scheme;smart retention-aware refresh;weak cell refresh management;Amplitude modulation;Capacitors;DRAM chips;Radiation detectors;Standards;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@InProceedings{wanbro_02,
+  Title                    = {{Optimal Blind Transport Format Detection for UMTS uplink}},
+  Author                   = {M. M. Wang and T. Brown},
+  Booktitle                = {Proc. of the 5th International Symposium on Wireless Personal Multimedia Coomunications (WPMC 2002)},
+  Year                     = {2002},
+
+  Address                  = {Honolulu, Hawaii, USA},
+  Pages                    = {102--106},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wanyi_10,
+  Title                    = {{D}esign of turbo decoder based on {M}in-{S}um decoding algorithm of {LDPC} code},
+  Author                   = {Pengjun Wang and Fanglong Yi},
+  Booktitle                = {Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on},
+  Year                     = {2010},
+  Month                    = {Dec},
+  Pages                    = {430-433},
+
+  Doi                      = {10.1109/APCCAS.2010.5774882},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@InProceedings{wangia_04,
+  Title                    = {{A}pproaching {MIMO} channel capacity with reduced-complexity soft sphere decoding},
+  Author                   = {Wang, R. and Giannakis, G.B.},
+  Booktitle                = {Wireless Communications and Networking Conference, 2004. WCNC. 2004 IEEE},
+  Year                     = {2004},
+  Month                    = {march},
+  Pages                    = { 1620 - 1625 Vol.3},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/WCNC.2004.1311795},
+  File                     = {wangia_04.pdf:wangia_04.pdf:PDF},
+  ISSN                     = {1525-3511},
+  Keywords                 = {Block codes;Channel capacity;Demodulation;Iterative algorithms;Iterative decoding;MIMO;Maximum likelihood decoding;Quadrature amplitude modulation;Quadrature phase shift keying;Transmitters; MIMO systems; antennas; channel capacity; decoding; multiuser detection; quadrature amplitude modulation; quadrature phase shift keying; MIMO channel capacity; QPSK-QAM signalling; bit-level multistream transmitter; block single-antenna; cancellation module; exact max-log; hard sphere-decoding; interference estimation; layered space-time systems; near-optimal multiuser demodulation; reduced-complexity soft sphere decoding;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.02.19}
+}
+
+@Article{wanhu_16,
+  Title                    = {{MEMRES}: {A} {F}ast {M}emory {S}ystem {R}eliability {S}imulator},
+  Author                   = {S. Wang and H. C. Hu and H. Zheng and P. Gupta},
+  Journal                  = {IEEE Transactions on Reliability},
+  Year                     = {2016},
+  Number                   = {99},
+  Pages                    = {1-15},
+  Volume                   = {PP},
+
+  Doi                      = {10.1109/TR.2016.2608357},
+  ISSN                     = {0018-9529},
+  Keywords                 = {Analytical models;Circuit faults;Error correction codes;Memory management;Monte Carlo methods;Reliability engineering;Memory fault;magnetic random access memory (MRAM);memory mirroring;memory page retirement;memory reliability;reliability management;retention error;simulator;sparing;spin-transfer torque random access memory (STT-RAM);write error},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-24}
+}
+
+@Article{wanliu_16,
+  Title                    = {{S}torage-{L}ess and {C}onverter-{L}ess {P}hotovoltaic {E}nergy {H}arvesting {W}ith {M}aximum {P}ower {P}oint {T}racking for {I}nternet of {T}hings},
+  Author                   = {Y. {Wang} and Y. {Liu} and C. {Wang} and Z. {Li} and X. {Sheng} and H. G. {Lee} and N. {Chang} and H. {Yang}},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2016},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {173-186},
+  Volume                   = {35},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {7128333},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/TCAD.2015.2446937},
+  ISSN                     = {0278-0070},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;maximum power point trackers;radio transceivers;solar cells;converter-less photovoltaic energy harvesting;storage-less photovoltaic energy harvesting;maximum power point tracking;internet of things;photovoltaic cells;PV cells;power density;MPPT charger;switching-mode power converter;energy storage element;maximum power point current;converter-less PV power system;nonvolatile microprocessor;fine-grain dynamic power management;energy harvesting system;radio frequency transceiver;Nonvolatile memory;Maximum power point trackers;Microprocessors;Switches;DC-DC power converters;Energy storage;Energy harvesting;Photovoltaic systems;Maximum-power-point tracking (MPPT);Energy efficiency;Storage-less and converter-less;Energy efficiency;energy harvesting;maximum power point tracking (MPPT);photovoltaic (PV) systems;storage- and converter-less},
+  Owner                    = {CCR}
+}
+
+@Article{wanser_03,
+  Title                    = {{Optimal Blind Carrier Recovery for MPSK Burst Transmissions}},
+  Author                   = {Y. Wang and E. Serpedin and P. Ciblat},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2003},
+
+  Month                    = sep,
+  Number                   = {9},
+  Pages                    = {1571--1581},
+  Volume                   = {51},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wanzha_05,
+  Title                    = {{R}educed latency turbo decoding},
+  Author                   = {Wang, Y. and Zhang, J. and Fossorier, M. and Yedidia, J. S. },
+  Booktitle                = {Proc. IEEE 6th Workshop on Signal Processing Advances in Wireless Communications},
+  Year                     = {2005},
+  Month                    = jun,
+  Pages                    = {930--934},
+
+  Doi                      = {10.1109/SPAWC.2005.1506276},
+  File                     = {wanzha_05.pdf:wanzha_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.09}
+}
+
+@InProceedings{wanzho_06,
+  Title                    = {{A} {MDA} based {S}o{C} {M}odeling {A}pproach using {UML} and {S}ystem{C}},
+  Author                   = {Ying Wang and Xue-Gong Zhou and Bo Zhou and Liang Liang and Cheng-Lian Peng},
+  Booktitle                = {Proceedings of The Sixth IEEE International Conference on Computer and Information Technology (CIT'06)},
+  Year                     = {2006},
+  Organization             = {Department of Computing and Information Technology
+Fudan University
+Shanghai, CHINA},
+
+  Cds_grade                = {0},
+  File                     = {wanzho_06.pdf:wanzho_06.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.04.06}
+}
+
+@InProceedings{wanchi_01,
+  Title                    = {{Area-efficient high speed decoding schemes for turbo/MAP decoders}},
+  Author                   = {Z. Wang and Z. Chi and K.K. Parhi},
+  Booktitle                = {Proc. 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '01)},
+  Year                     = {2001},
+
+  Address                  = {Salt Lake City, UT , USA},
+  Pages                    = {2633 -- 2636},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{wanchi_02,
+  Title                    = {{Area-efficient high speed decoding schemes for turbo decoders}},
+  Author                   = {Z. Wang and Z. Chi and Parhi, K. K.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2002},
+
+  Month                    = dec,
+  Number                   = {6},
+  Pages                    = {902--912},
+  Volume                   = {10},
+
+  File                     = {wanchi_02.pdf:wanchi_02.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{wanpar_03,
+  Title                    = {{High performance, high throughput turbo/SOVA decoder design}},
+  Author                   = {Z. Wang and Parhi, K. K.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2003},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {570--579},
+  Volume                   = {51},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wanpar_00,
+  Title                    = {{Decoding Metrics and their Applications in VLSI Turbo Decoders}},
+  Author                   = {Z. Wang and K. K. Parhi},
+  Booktitle                = {Proc. 2000 Conference on Acoustics, Speech, and Signal Processing (ICASSP '00)},
+  Year                     = {2000},
+  Month                    = sep,
+  Pages                    = {3370--3373},
+
+  Optvolume                = {6},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wansin_13,
+  Title                    = {{Accurate and Efficient Reliability Estimation Techniques during ADL-Driven Embedded Processor Design}},
+  Author                   = {Wang, Z. and Singh, K. and Chao, C. and Chattopadhyay, A.},
+  Booktitle                = {Proc. 2013 Design, Automation and Test in Europe (DATE '13)},
+  Year                     = {2013},
+
+  File                     = {wansin_13.pdf:wansin_13.pdf:PDF},
+  Keywords                 = {Reliability}
+}
+
+@InProceedings{wansuz_99,
+  Title                    = {{VLSI Implementation Issues of Turbo Decoder Design For Wireless Applications}},
+  Author                   = {Z. Wang and H. Suzuki and K. K. Parhi},
+  Booktitle                = {Proc. 1999 Workshop in Signal Processing Systems (SiPS '99)},
+  Year                     = {1999},
+
+  Address                  = {Taipei, Taiwan ROC},
+  Month                    = oct,
+  Pages                    = {503--512},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wantan_03,
+  Title                    = {{Low hardware complexity parallel turbo decoder architecture}},
+  Author                   = {Z. Wang and Y. Tang and Y. Wang},
+  Booktitle                = {Proc. 2003 IEEE International Symposium on Circuits and Systems (ISCAS '03)},
+  Year                     = {2003},
+
+  Address                  = {Bangkok, Thailand},
+  Month                    = may,
+  Pages                    = {53--56},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{war_08,
+  Title                    = {{C}ity business races the {G}ames for power},
+  Author                   = {Pete Warren},
+  Journal                  = {The Guardian},
+  Year                     = {2008},
+
+  Month                    = may,
+
+  Cds_grade                = {4},
+  Cds_keywords             = {finance, energy, power},
+  Cds_read                 = {2011-01-05},
+  Cds_review               = {good power consumption estimation of London canary warth},
+  File                     = {war_08.pdf:war_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.01.05},
+  Url                      = {http://www.guardian.co.uk/technology/2008/may/29/energy.olympics2012}
+}
+
+@Article{Wasenmueller2008,
+  Title                    = {{A}nalysis of communications and implementation performance of {FFT} based carrier synchronization of {BPSK}/{QPSK} bursts},
+  Author                   = {Wasenm\"uller, U. and Brack, T. and Wehn, N.},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2008},
+  Pages                    = {95--100},
+  Volume                   = {6},
+
+  Doi                      = {10.5194/ars-6-95-2008},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27},
+  Url                      = {http://www.adv-radio-sci.net/6/95/2008/}
+}
+
+@Article{wasgim_10,
+  Title                    = {{L}ow complexity {T}urbo synchronization without initial carrier synchronization},
+  Author                   = {Wasenm\"uller, U. and Gimmler, C. and Wehn, N.},
+  Journal                  = {Advances in Radio Science},
+  Year                     = {2010},
+  Pages                    = {123--128},
+  Volume                   = {8},
+
+  Doi                      = {10.5194/ars-8-123-2010},
+  Url                      = {http://www.adv-radio-sci.net/8/123/2010/}
+}
+
+@Conference{wasbra_11,
+  Title                    = {{A} {D}esign {S}tudy on {C}omplexity {R}educed {M}ultipath {M}itigation},
+  Author                   = {U. Wasenmüller and T. Brack and I. Groh and E. Staudinger and S. Sand and Norbert Wehn},
+  Booktitle                = {Kleinheubacher Tagung},
+  Year                     = {2011},
+
+  Address                  = {Miltenberg, Germany},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@InProceedings{wasbra_04,
+  Title                    = {{D}esign {S}pace {E}xploration for {F}requency {S}ynchronization of {BPSK}/{QPSK} {B}ursts},
+  Author                   = {Uwe Wasenmüller and Torben Brack and Daniel Schmidt and Norbert Wehn},
+  Booktitle                = {Advances in Radio Science},
+  Year                     = {2004},
+  Month                    = mar,
+  Pages                    = {337--341},
+  Volume                   = {3},
+
+  File                     = {wasbra_04.pdf:wasbra_04.pdf:PDF},
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@InProceedings{wasbra_07,
+  Title                    = {{Analysis of Communication and Implementation Performance of FFT Based Carrier Synchronization of BPSK/QPSK Bursts}},
+  Author                   = {Uwe Wasenmüller and Torben Brack and Norbert Wehn},
+  Booktitle                = {Advances in Radio Science},
+  Year                     = {2007},
+
+  Address                  = {Miltenberg, Germany},
+  Pages                    = {95--100},
+  Volume                   = {6},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2008.01.30}
+}
+
+@InProceedings{weamar_03,
+  Title                    = {{P}ost-{P}lacement {C}-slow {R}etiming for the {X}ilinx {V}irtex {FPGA}s},
+  Author                   = {Weaver, Nicholas and Markovskiy, Yury and Patel, Yatish and John Wawrzynek},
+  Booktitle                = {Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays},
+  Year                     = {2003},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {185--194},
+  Publisher                = {ACM},
+  Series                   = {FPGA '03},
+
+  Abstract                 = {C-slow retiming is a process of automatically increasing the throughput of a design by enabling fine grained pipelining of problems with feedback loops. This transformation is especially appropriate when applied to FPGA designs because of the large number of available registers. To demonstrate and evaluate the benefits of C-slow retiming, we constructed an automatic tool which modifies designs targeting the Xilinx Virtex family of FPGAs. Applying our tool to three benchmarks: AES encryption, Smith/Waterman sequence matching, and the LEON 1 synthesized microprocessor core, we were able to substantially increase the total throughput. For some parameters, throughput is effectively doubled.},
+  Acmid                    = {611845},
+  Cds_grade                = {0},
+  Doi                      = {http://doi.acm.org/10.1145/611817.611845},
+  File                     = {weamar_03.pdf:weamar_03.pdf:PDF},
+  ISBN                     = {1-58113-651-X},
+  Keywords                 = {finance},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {10},
+  Owner                    = {CdS},
+  Timestamp                = {2011.09.30},
+  Url                      = {http://doi.acm.org/10.1145/611817.611845}
+}
+
+@InProceedings{wedmag_13,
+  Title                    = {{A} survey of multi-source energy harvesting systems},
+  Author                   = {A. S. Weddell and M. Magno and G. V. Merrett and D. Brunelli and B. M. Al-Hashimi and L. Benini},
+  Booktitle                = {2013 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2013},
+  Month                    = {March},
+  Pages                    = {905-908},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {6513636},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.7873/DATE.2013.190},
+  ISSN                     = {1530-1591},
+  Keywords                 = {TCS},
+  Keywords_original        = {Computer architecture;Energy harvesting;Energy storage;Hardware;Microcontrollers;Monitoring;Power conditioning},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-26}
+}
+
+@Misc{wehembedded15,
+  Title                    = {{A}n {E}mbedded {C}omputing {A}rchitecture for {F}inding {S}imilarities in {L}arge {N}etworks, {HPC} on {E}mbedded {C}omputing {D}evices - a {C}ase {S}tudy},
+
+  Author                   = {Norbert Wehn},
+  HowPublished             = {Invited talk at the 15th International Forum on Embedded MPSoC and Multicore (MPSoC 2015), Ventura, California},
+  Month                    = jul,
+  Year                     = {2015},
+
+  File                     = {schtowards15.pptx:schtowards15.pptx:PPTX},
+  Keywords                 = {AG_Wehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-06-30}
+}
+
+@Misc{wehhpc14,
+  Title                    = {{HPC} on {E}mbedded {C}omputing {D}evices - {A} {C}ase {S}tudy},
+
+  Author                   = {Norbert Wehn},
+  HowPublished             = {Invited talk at the 14th International Forum on Embedded MPSoC and Multicore (MPSoC 2014), Margaux, France},
+  Month                    = jul,
+  Year                     = {2014},
+
+  File                     = {schtowards15.pptx:schtowards15.pptx:PPTX},
+  Keywords                 = {AG_Wehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-06-30}
+}
+
+@Misc{weh_12,
+  Title                    = {{E}rror {R}esilience in {W}ireless {C}ommunication {S}ystems},
+
+  Author                   = {Norbert Wehn},
+  HowPublished             = {DATE 2012 Friday Workshop W7: Facing Dependability Challenges at Nanoscale: From Devices to Systems},
+  Month                    = apr,
+  Note                     = {To appear},
+  Year                     = {2012},
+
+  Location                 = {Dresden, Germany}
+}
+
+@Misc{Wehn2012,
+  Title                    = {{E}rror {R}esilience in {W}ireless {C}ommunication {S}ystems},
+
+  Author                   = {Norbert Wehn},
+  HowPublished             = {DATE 2012 Friday Workshop W7: Facing Dependability Challenges at Nanoscale: From Devices to Systems},
+  Month                    = apr,
+  Note                     = {To appear},
+  Year                     = {2012},
+
+  Location                 = {Dresden, Germany},
+  Owner                    = {scholl},
+  Timestamp                = {2015.06.11}
+}
+
+@InProceedings{weh_11,
+  Title                    = {{R}eliability: {A} {C}ross-{D}isciplinary and {C}ross-{L}ayer {A}pproach},
+  Author                   = {Norbert Wehn},
+  Booktitle                = {Proceedings of IEEE 20th Asian Test Symposium},
+  Year                     = {2011},
+
+  Address                  = {Okhla, New Delhi, India},
+  Month                    = nov
+}
+
+@Conference{weh_09,
+  Title                    = {{F}lexibility/{C}ost {T}rade-off in {W}ireless {B}aseband {P}rocessing},
+  Author                   = {N. Wehn},
+  Booktitle                = {IEEE/IFIP International Conference on Very Large Scale VLSI-SoC (Invited Keynote)},
+  Year                     = {2009},
+
+  Address                  = {Florianopolis, Brasil},
+  Month                    = oct,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@Conference{weh_09a,
+  Title                    = {{S}imulation and {V}alidation: {C}hallenges in {W}ireless {B}aseband {P}rocessing},
+  Author                   = {Norbert Wehn},
+  Booktitle                = {Invited Talk, HIPEAC 2009 Rapid Simulation and Performance Evaluation Workshop},
+  Year                     = {2009},
+
+  Address                  = {Cypress, Greek},
+  Month                    = jan,
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@Conference{weh_09b,
+  Title                    = {{E}nergy {M}odelling and {O}ptimization - {A} {C}ritical {A}ssessment with two {C}ase {S}tudies},
+  Author                   = {N. Wehn},
+  Booktitle                = {9th International Forum on Embedded MPSoC and Multicore (MPSoC'09)},
+  Year                     = {2009},
+
+  Address                  = {Savannah, Georgia, USA},
+  Month                    = jul,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@Conference{weh_08,
+  Title                    = {{System-on-Chip Design - Herausforderungen und Lösungsansätze}},
+  Author                   = {Norbert Wehn},
+  Booktitle                = {Invited Keynote, edaWorkshop 2008},
+  Year                     = {2008},
+
+  Address                  = {Hannover, Germany},
+  Month                    = may,
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@Conference{weh_08a,
+  Title                    = {{F}lexibility/{R}econfigurability {T}rade-offs in {SDR} {A}rchitectures},
+  Author                   = {Norbert Wehn},
+  Booktitle                = {Workshop Reconfigurable Computing, IEEE Conference Design, Automation and Test in Europe (DATE'08)},
+  Year                     = {2008},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.30}
+}
+
+@Misc{wehadvanced06,
+  Title                    = {{Advanced Channel Decoding Algorithms and their Implementaion for Future Communication Systems}},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {IEEE Annual Symposium on VLSI (invited keynote), Karsruhe, Germany},
+  Month                    = mar,
+  Year                     = {2006},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@Misc{wehambient06,
+  Title                    = {{A}mbient {I}ntelligence (invited talk)},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {4th GMM Workshop, Energieautarke Sensorik, Karlsruhe, Germany},
+  Month                    = sep,
+  Year                     = {2006},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@Misc{wehchannel06,
+  Title                    = {{Channel Decoding in Software Defined Radio}},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {MPSoC 2006, Estes Park, Colorado, USA},
+  Month                    = aug,
+  Year                     = {2006},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Misc{Wehn2006,
+  Title                    = {{Advanced Channel Decoding Algorithms and their Implementaion for Future Communication Systems}},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {IEEE Annual Symposium on VLSI (invited keynote), Karsruhe, Germany},
+  Month                    = mar,
+  Year                     = {2006},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@Misc{Wehn2006a,
+  Title                    = {{A}mbient {I}ntelligence (invited talk)},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {4th GMM Workshop, Energieautarke Sensorik, Karlsruhe, Germany},
+  Month                    = sep,
+  Year                     = {2006},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@Misc{Wehn2006b,
+  Title                    = {{Channel Decoding in Software Defined Radio}},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {MPSoC 2006, Estes Park, Colorado, USA},
+  Month                    = aug,
+  Year                     = {2006},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@InProceedings{weh_05,
+  Title                    = {{Power Optimization in Advanced Channel Coding}},
+  Author                   = {N. Wehn},
+  Booktitle                = {Dagstuhl Seminar Power Aware Computing Systems Dagstuhl Seminar Proceedings 05141},
+  Year                     = {2005},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Conference{weh_05a,
+  Title                    = {{I}mplementation {T}rade-{O}ffs of {A}dvanced {C}hannel {D}ecoding for 3{G} and 4{G} {C}ommunication {S}ystems},
+  Author                   = {N. Wehn},
+  Booktitle                = {2005 Reconfigurable Communication-Centric SoCs (invited keynote)},
+  Year                     = {2005},
+
+  Address                  = {Montpellier, France},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@Misc{wehbridging05,
+  Title                    = {{Bridging the Interleaving Bottleneck in Communication Applications for Efficient SoC Implementations}},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {MPSoC 2005 Margaux France},
+  Month                    = jul,
+  Year                     = {2005},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Misc{Wehn2005b,
+  Title                    = {{Bridging the Interleaving Bottleneck in Communication Applications for Efficient SoC Implementations}},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {MPSoC 2005 Margaux France},
+  Month                    = jul,
+  Year                     = {2005},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Misc{Wehn2004,
+  Title                    = {{Network-Centric Approach for Parallel Decoder Architectures}},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {MPSoC 2004, Saint-Maximin la Sainte Baume, France},
+  Month                    = jul,
+  Year                     = {2004},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Misc{wehnetwork-centric04,
+  Title                    = {{Network-Centric Approach for Parallel Decoder Architectures}},
+
+  Author                   = {N. Wehn},
+  HowPublished             = {MPSoC 2004, Saint-Maximin la Sainte Baume, France},
+  Month                    = jul,
+  Year                     = {2004},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.01.08}
+}
+
+@Article{weh_03,
+  Title                    = {{Hardware-/Software Trade-Offs in Digital Communication Systems with Special Emphasis on Channel-Coding}},
+  Author                   = {N. Wehn},
+  Journal                  = {IT -- Information Technology Journal},
+  Year                     = {2003},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {336--343},
+  Volume                   = {45},
+
+  Optmonth                 = {#sep#},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Conference{weh_03a,
+  Title                    = {{S}o{C}-{N}etwork for {I}nterleaving in {W}ireless {C}ommunications},
+  Author                   = {N. Wehn},
+  Booktitle                = {3rd edition of the International Seminar on Application-Specific Multi-Processor SoC (MPSOC'03)},
+  Year                     = {2003},
+
+  Address                  = {Chamonix, France},
+  Month                    = jul,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@Conference{weh_02,
+  Title                    = {{H}ardware-/{S}oftware {T}rade-{O}ffs in {D}igital {C}ommunication {S}ystems with {S}pecial {E}mphasis on {C}hannel-{C}oding},
+  Author                   = {N. Wehn},
+  Booktitle                = {SoC-Design Workshop},
+  Year                     = {2002},
+
+  Address                  = {Taiwan},
+  Month                    = oct,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.02.01}
+}
+
+@Book{weh_00,
+  Title                    = {{Entwurf Mikroelektronischer Schaltungen und Systeme I und II}},
+  Author                   = {N. Wehn},
+  Publisher                = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2000},
+  Note                     = {Lecture notes (In German)},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{weh_95,
+  Title                    = {{Verfahren zur Archtektursynthese mikroelektronischer Systeme}},
+  Author                   = {N. Wehn},
+  Booktitle                = {Habilitationsschrift},
+  Publisher                = {Technische Hochschule Damstadt},
+  Year                     = {1995},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{weh_95a,
+  Title                    = {{High-Level Synthesis: A Critical Assessment}},
+  Author                   = {N. Wehn},
+  Booktitle                = {Logic and Architecture Synthesis -- State-of-the-art and novel approaches},
+  Publisher                = {Chapman \& Hall},
+  Year                     = {1995},
+  Pages                    = {289--299},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehbie_94,
+  Title                    = {{Scheduling of Behavioral VHDL by Retiming Techniques}},
+  Author                   = {N. Wehn and J. Biesenack and T. Langmaier and M. Münch and M. Pilsl and S. Rumler and P. Duzy},
+  Booktitle                = {Proceedings of the EURO-DAC '94},
+  Year                     = {1994},
+
+  Address                  = {Grenoble},
+  Month                    = sep,
+  Pages                    = {546--551},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehbie_91,
+  Title                    = {{ A New Approach to Multiplexor Minimization in the CALLAS Synthesis Environment}},
+  Author                   = {N.~Wehn and J.~Biesenack and M.~Pilsl},
+  Booktitle                = {IFIP Transactions A-1: VLSI91},
+  Year                     = {1991},
+  Pages                    = {203--213},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_91,
+  Title                    = {{ A Low-Cost Microelectronic Lab integrated on a single Chip}},
+  Author                   = {N.~Wehn and M.~Glesner},
+  Booktitle                = {Proc.\ Second Eurochip Workshop on VLSI Design Training},
+  Year                     = {1991},
+
+  Address                  = {Grenoble},
+  Pages                    = {272-275},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_91a,
+  Title                    = {{ A New Approach to Timing Driven Partitioning of Combinational Logic}},
+  Author                   = {N.~Wehn and M.~Glesner},
+  Booktitle                = {Proc. Euro ASIC '91},
+  Year                     = {1991},
+
+  Address                  = {Paris},
+  Pages                    = {106--111},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_91b,
+  Title                    = {{Timing Driven Partitioning of Combinational Logic}},
+  Author                   = {N.~Wehn and M.~Glesner},
+  Booktitle                = {Informatik-Fachberichte: Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme},
+  Year                     = {1991},
+  Pages                    = {96--101},
+  Publisher                = {Springer-Verlag},
+  Volume                   = {255},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{wehgle_86,
+  Title                    = {{S}tatische und {D}ynamische {CMOS}-{S}chaltungstechniken im {V}ergleich},
+  Author                   = {N. Wehn and M. Glesner},
+  Journal                  = {Informationstechnik},
+  Year                     = {1986},
+  Pages                    = {142--149},
+  Volume                   = {3/86},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_85,
+  Title                    = {{TEDMOSF - A New fault-Simulator for MOS-VLSI Circuits}},
+  Author                   = {N.~Wehn and M.~Glesner},
+  Booktitle                = {Proc.\ European Conference on Circuit Theory and Design},
+  Year                     = {1985},
+
+  Address                  = {Prag},
+  Pages                    = {78--81},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_88,
+  Title                    = {{Design of a Defect-Tolerant and Fully Testable PLA}},
+  Author                   = {N.~Wehn and M.~Glesner and K.~Caesar and P.~Mann and A.~Roth},
+  Booktitle                = {Proc.\ ISCAS 88},
+  Year                     = {1988},
+
+  Address                  = {Helsinki},
+  Pages                    = {213--216},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_88a,
+  Title                    = {{A Defect-Tolerant and Fully Testable PLA}},
+  Author                   = {N.~Wehn and M.~Glesner and K.~Caesar and P.~Mann and A.~Roth},
+  Booktitle                = {Proc. th ACM/IEEE Design Automation Conference},
+  Year                     = {1988},
+
+  Address                  = {Anaheim},
+  Pages                    = {22--27},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_88b,
+  Title                    = {{Design of a Controller based on Defect-Tolerant and Fully Testable PLAs}},
+  Author                   = {N.~Wehn and M.~Glesner and K.~Caesar and P.~Mann and A.~Roth},
+  Booktitle                = {Wafer Scale Integration II},
+  Year                     = {1988},
+  Pages                    = {179--187},
+  Publisher                = {Elsevier Science Publishers},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_87,
+  Title                    = {{A Floorplanner for Hierarchical Macrocell Design}},
+  Author                   = {N.~Wehn and M.~Glesner and K.~Gebauer and T.~Kropf},
+  Booktitle                = {Proc.\ European Conference on Circuit Theory and Design},
+  Year                     = {1987},
+
+  Address                  = {Paris},
+  Pages                    = {351--356},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_91c,
+  Title                    = {{A Novel Scheduling Allocation Approach for Datapath Synthesis based on Genetic Paradigms}},
+  Author                   = {N.~Wehn and M.~Glesner and M.~Held},
+  Booktitle                = {Logic and Architecture Synthesis},
+  Year                     = {1991},
+  Pages                    = {47--56},
+  Publisher                = {Elsevier Science Publishers},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_86a,
+  Title                    = {{Reconfiguration Strategies for the Architecture of a Defect-Tolerant General Purpose Microprocessor}},
+  Author                   = {N.~Wehn and M.~Glesner and J.~Sauerbrey and B.O.~Schneider},
+  Booktitle                = {Proc.\ Integrated Circuit Technology},
+  Year                     = {1986},
+
+  Address                  = {Limerick},
+  Pages                    = {403--414},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehgle_93,
+  Title                    = {{ Estimating Lower Hardware Bounds in High-Level Synthesis }},
+  Author                   = { N.~Wehn and M.~Glesner and C.~Vielhauer },
+  Booktitle                = { IFIP Transactions A-42: VLSI93 },
+  Year                     = {1993},
+
+  Address                  = {Grenoble},
+  Pages                    = {261-270},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehhei_98,
+  Title                    = {{Embedded DRAM Architectural Trade-Offs}},
+  Author                   = {N. Wehn and S. Hein},
+  Booktitle                = {Proc. Design, Automation and Test in Europe},
+  Year                     = {1998},
+
+  Address                  = {Paris, France},
+  Month                    = feb,
+  Pages                    = {704--708},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{wehhei_96,
+  Title                    = {{Design of Multimedia Systems: a Case Study - Anatomy of an MPEG2 Decoder}},
+  Author                   = {N. Wehn and S. Hein},
+  Booktitle                = {Hardware Software Codesign for Telecom and Multimedia Systems},
+  Publisher                = {Tutorial, 33rd Design Automation Conference, Las Vegas},
+  Year                     = {1996},
+  Month                    = jun,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehher_92,
+  Title                    = {{ High-Level Synthesis in a Rapid-Prototype Environment for Mechatronic Systems}},
+  Author                   = {N. Wehn and H. Herpel and T. Hollstein and P. Pöchmüller and M. Glesner},
+  Booktitle                = {Proc. European Design Automation Conference EURO-VHDL '92 EURO-DAC '92},
+  Year                     = {1992},
+
+  Address                  = {Hamburg},
+  Pages                    = {188--193},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{wehldpc05,
+  Title                    = {{LDPC decoder, in particular for DVB-S2 LDPC code decoding}},
+
+  Author                   = {N. Wehn and F. Kienle and T. Brack},
+  HowPublished             = {European Patent Application No.05 290 468.7},
+  Month                    = mar,
+  Year                     = {2005},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{wehmethod05,
+  Title                    = {{Method and device for controlling the decoding of a LDPC encoded codeword, in particular for DVB-S2 LDPC encoded codewords}},
+
+  Author                   = {N. Wehn and F. Kienle and T. Brack},
+  HowPublished             = {European Patent Application No.05 009 477.0},
+  Month                    = apr,
+  Year                     = {2005},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{wehmethod05a,
+  Title                    = {{Method and device for decoding LDPC encoded codewords, in particular DVB-S2 LDPC encoded codewords }},
+
+  Author                   = {N. Wehn and F. Kienle and T. Brack},
+  HowPublished             = {European Patent Application No.05 290 469.5},
+  Month                    = mar,
+  Year                     = {2005},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Wehn2005c,
+  Title                    = {{LDPC decoder, in particular for DVB-S2 LDPC code decoding}},
+
+  Author                   = {N. Wehn and F. Kienle and T. Brack},
+  HowPublished             = {European Patent Application No.05 290 468.7},
+  Month                    = mar,
+  Year                     = {2005},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Wehn2005d,
+  Title                    = {{Method and device for controlling the decoding of a LDPC encoded codeword, in particular for DVB-S2 LDPC encoded codewords}},
+
+  Author                   = {N. Wehn and F. Kienle and T. Brack},
+  HowPublished             = {European Patent Application No.05 009 477.0},
+  Month                    = apr,
+  Year                     = {2005},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Wehn2005e,
+  Title                    = {{Method and device for decoding LDPC encoded codewords, in particular DVB-S2 LDPC encoded codewords }},
+
+  Author                   = {N. Wehn and F. Kienle and T. Brack},
+  HowPublished             = {European Patent Application No.05 290 469.5},
+  Month                    = mar,
+  Year                     = {2005},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehmic_00,
+  Title                    = {{VLSI Architectures for Soft-Output Decoders}},
+  Author                   = {N. Wehn and H. Michel},
+  Booktitle                = {{Proc. ITG Workshop 2000 ''Mikroelektronik für die Informationstechnik''}},
+  Year                     = {2000},
+
+  Address                  = {Darmstadt, Germany},
+  Month                    = nov,
+  Pages                    = {81--86},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehm_99,
+  Title                    = {{Minimizing power consumption in digital circuits and systems: an overview}},
+  Author                   = {N. Wehn and M. Münch},
+  Booktitle                = {{Kleinheubacher Berichte}},
+  Year                     = {1999},
+  Month                    = sep,
+  Pages                    = {308--319},
+  Volume                   = {43},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wehpay_92,
+  Title                    = {{ High-Level Design Strategies for Architectural Synthesis }},
+  Author                   = {N.~Wehn and M.~Payer},
+  Booktitle                = {Proc.\ ESSCIRC 92},
+  Year                     = {1992},
+
+  Address                  = {Kopenhagen},
+  Note                     = {(invited paper)},
+  Pages                    = {61--70},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{weigan_01,
+  Title                    = {{A flexible datapath generator for physical oriented design}},
+  Author                   = {O. Wei\ss and M. Gansen and T. G. Noll},
+  Booktitle                = {Proceedings of the 27th European Solid-State Circuits Conference (ESSCIRC 2001)},
+  Year                     = {2001},
+
+  Address                  = {Villach, Austria},
+  Month                    = sep,
+  Pages                    = {408--411},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{weimat_11,
+  Title                    = {{LDPC} decoder architecture for high-data rate personal-area networks},
+  Author                   = {Weiner and Matthew and Nikolic and Borivoje and Zhang and Zhengya},
+  Booktitle                = {Proc. IEEE Int Circuits and Systems (ISCAS) Symp},
+  Year                     = {2011},
+  Pages                    = {1784--1787},
+
+  Doi                      = {10.1109/ISCAS.2011.5937930},
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.01.26}
+}
+
+@InProceedings{weileu_15,
+  Title                    = {{P}arallel {S}ystem{C} simulation for {ESL} design using flexible time decoupling},
+  Author                   = {J. H. Weinstock and R. Leupers and G. Ascheid},
+  Booktitle                = {2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
+  Year                     = {2015},
+  Month                    = {July},
+  Pages                    = {378-383},
+
+  Doi                      = {10.1109/SAMOS.2015.7363702},
+  Keywords                 = {discrete event simulation;embedded systems;parallel architectures;ESL design;flexible time decoupling;next generation embedded systems;parallel SystemC simulators;cross-thread communication;Timing;Instruction sets;Time-domain analysis;Time-varying systems;Embedded systems;Kernel},
+  Owner                    = {MJ},
+  Timestamp                = {2018-09-11}
+}
+
+@InProceedings{weijun_15,
+  Title                    = {{R}etention {T}ime {M}easurements and {M}odelling of {B}it {E}rror {R}ates of {WIDE} {I}/{O} {DRAM} in {MPS}o{C}s},
+  Author                   = {Weis, Christian and Jung, Matthias and Ehses, Peter and Santos, Cristiano and Vivet, Pascal and Goossens, Sven and Koedam, Martijn and Wehn, Norbert},
+  Booktitle                = {Proceedings of the IEEE Conference on Design, Automation \& Test in Europe (DATE)},
+  Year                     = {2015},
+  Organization             = {European Design and Automation Association},
+
+  Keywords                 = {AGWehn},
+  Owner                    = {MJ},
+  Timestamp                = {2016-02-17}
+}
+
+@InProceedings{weijun_15a,
+  Title                    = {{T}hermal {A}spects and {H}igh-level {E}xplorations of 3{D} stacked {DRAM}s},
+  Author                   = {Weis, Christian and Jung, Matthias and Santos, Christiano and Vivet, Pascal and Naji, Omar and Hansson, Andreas and Wehn, Norbert},
+  Booktitle                = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
+  Year                     = {2015},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.08.11}
+}
+
+@Book{weijun_16,
+  Title                    = {3{D} {S}tacked {DRAM} {M}emories ({B}ook chapter in the {H}andbook of 3{D} {I}ntegration)},
+  Author                   = {Weis, Christian and Jung, Matthias and Wehn, Norbert},
+  Publisher                = {Wiley-VCH},
+  Year                     = {2019},
+  Volume                   = {4},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-25}
+}
+
+@InProceedings{weijun_15b,
+  Title                    = {{R}eliability and {T}hermal {C}hallenges in 3{D} {I}ntegrated {E}mbedded {S}ystems},
+  Author                   = {Weis, Christian and Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, Amsterdam, The Netherlands.},
+  Year                     = {2015},
+  Month                    = {October},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.12.18}
+}
+
+@InProceedings{weijun_18,
+  Title                    = {{T}he {R}ole of {M}emories in {T}ransprecision {C}omputing},
+  Author                   = {Weis, Christian and Jung, Matthias and Zulian, Éder F. and Sudarshan, Chirag and Mathew, Deepak and Wehn, Norbert},
+  Booktitle                = {IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2018},
+  Month                    = {May},
+
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-25}
+}
+
+@Article{weiloi_13,
+  Title                    = {{E}xploration and {O}ptimization of 3-{D} {I}ntegrated {DRAM} {S}ubsystems},
+  Author                   = {Weis, Christian and Loi, Igor and Benini, Luca and Wehn, Norbert},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2013},
+
+  Month                    = {April},
+  Number                   = {4},
+  Pages                    = {597-610},
+  Volume                   = {32},
+
+  Doi                      = {10.1109/TCAD.2012.2235125},
+  File                     = {weiloi_13.pdf:weiloi_13.pdf:PDF},
+  ISSN                     = {0278-0070},
+  Keywords                 = {DRAM chips;next generation networks;system-on-chip;three-dimensional integrated circuits;controller architecture;3D DRAM model;design space exploration;3D DRAM subsystem;power estimation engine;3D stacked DRAM;SDR/DDR 3D DRAM channel controller;synthesizable model;flexible interface;fine grained access;3D DRAM cube;SDR/DDR 3D DRAM controller;next generation 3D integrated SoC;energy efficient DRAM subsystem;3D DRAM architecture design space;dies;3D integration;TSV technology;through silicon via technology;tablets;smartphones;mobile device;systems on chip;optimization criterion;energy efficiency;3D integrated DRAM subsystems;Random access memory;Computer architecture;Integrated circuit modeling;Through-silicon vias;Bandwidth;Organizations;3-D integration;channel;controller;DRAM},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.09}
+}
+
+@InProceedings{weiloi_12,
+  Title                    = {{An energy efficient DRAM subsystem for 3D integrated SoCs}},
+  Author                   = {Weis, C. and Loi, I. and Benini, L. and Wehn, N.},
+  Booktitle                = {{proc. DATE 2012}},
+  Year                     = {2012},
+  Month                    = {march},
+
+  Keywords                 = {LPDDR2; SDR-DDR 3D-DRAM channel controller; TSV technology; WIDE-IO interface; attached 3D-stacked DRAM cube; energy consumption; energy efficient DRAM subsystem; fine-grained access; logic layers stacking; memory cooptimization; memory interface; mobile terminal; multiple memory stacking; next-generation 3D integrated SoC; optimization design; power estimation engine; power saving; smartphone; storage capacity 256 Mbit to 4 Gbit; tablet; through silicon via technology; DRAM chips; energy conservation; integrated circuit design; network synthesis; optimisation; system-on-chip; three-dimensional integrated circuits},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.10}
+}
+
+@Article{weimut_16,
+  Title                    = {{DRAMS}pec: {A} {H}igh-{L}evel {DRAM} {T}iming, {P}ower and {A}rea {E}xploration {T}ool},
+  Author                   = {Weis, Christian and Mutaal, Abdul and Naji, Omar and Jung, Matthias and Hansson, Andreas and Wehn, Norbert},
+  Journal                  = {International Journal of Parallel Programming},
+  Year                     = {2017},
+
+  Month                    = {Dec},
+  Number                   = {6},
+  Pages                    = {1566--1591},
+  Volume                   = {45},
+
+  Abstract                 = {In systems ranging from mobile devices to servers, DRAM has a big impact on performance and contributes a significant part of the total consumed power. The performance and power of the system depends on the architecture of the DRAM chip, the design of the memory controller and the access patterns received by the memory controller. Thus, evaluating the impact of DRAM design decisions requires a holistic approach that includes an appropriate model of the DRAM bank, a realistic controller and DRAM power model, and a representative workload, which requires a full system simulator running a complete software stack. In this paper, we introduce DRAMSpec, a high-level DRAM bank/chip modeling tool. Our contribution is to move the DRAM modeling abstraction level from the circuit level to the DRAM bank and by the integration in full system simulators we allow system or processor designers (non-DRAM experts) to tune future DRAM architectures for their target applications. We demonstrate the merits of DRAMSpec by exploring the influence of DRAM row-buffer (page) size and the number of banks on performance and power of a server application (memcached). Our new DRAM design offers a 16{\%} DRAM performance improvement and 13{\%} DRAM energy saving compared to standard comodity DDR3 devices. Additionally, we demonstrate how our tool is able to aid in evaluating novel DRAM architectures, such as the Hybrid Memory Cube (HMC), for which no DRAM datasheets are available. Finally, we highlight the DRAM technology scaling for a specific HMC architecture and we quantify the impact on latency and power.},
+  Day                      = {01},
+  Doi                      = {10.1007/s10766-016-0473-y},
+  ISSN                     = {1573-7640},
+  Url                      = {https://doi.org/10.1007/s10766-016-0473-y}
+}
+
+@InProceedings{weiweh_11,
+  Title                    = {{D}esign space exploration for 3{D}-stacked {DRAM}s},
+  Author                   = {Weis, Christian and Wehn, Norbert and Igor, Loi and Benini, Luca},
+  Booktitle                = {Proc. Design, Automation \& Test in Europe Conf. \& Exhibition (DATE)},
+  Year                     = {2011},
+  Pages                    = {1--6},
+
+  Owner                    = {Weis},
+  Timestamp                = {2011.05.16}
+}
+
+@InProceedings{weiweh_12,
+  Title                    = {{A}n {E}nergy {E}fficient {DRAM} {S}ubsystem for 3{D} integrated {S}o{C}s},
+  Author                   = {C. Weis and N. Wehn and I. Loi and L. Benini},
+  Booktitle                = {IEEE Conference Design, Automation and Test in Europe (DATE)},
+  Year                     = {2012},
+
+  Address                  = {Dresden, Germany},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@Article{wei_91,
+  Title                    = {{T}he {C}omputer for the 21st {C}entury},
+  Author                   = {Weiser, Mark},
+  Journal                  = {Scientific American},
+  Year                     = {1991},
+
+  Month                    = sep,
+  Number                   = {3},
+  Pages                    = {94--104},
+  Volume                   = {265},
+
+  Cds_grade                = {0},
+  Doi                      = {10.1038/scientificamerican0991-94},
+  File                     = {wei_91.pdf:wei_91.pdf:PDF},
+  Owner                    = {CdS},
+  Publisher                = {Nature Publishing Group},
+  Timestamp                = {2014.06.27}
+}
+
+@InProceedings{weiwel_94,
+  Title                    = {{Scheduling for Reduced CPU Energy}},
+  Author                   = {M. Weiser and B. Welch and A. Demers and S. Shenker},
+  Booktitle                = {Proc. 1994 Symposium on Operating Systems Design and Implementation},
+  Year                     = {1994},
+  Month                    = nov,
+  Pages                    = {13--23},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{weibet_98,
+  Title                    = {{T}urbo decoding with tail-biting trellises},
+  Author                   = {Weiss, C. and Bettstetter, C. and Riedel, S. and Costello, D.J., Jr},
+  Booktitle                = {Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI International Symposium on},
+  Year                     = {1998},
+  Month                    = {Oct},
+  Pages                    = {343-348},
+
+  Doi                      = {10.1109/ISSSE.1998.738095},
+  File                     = {weibet_98.pdf:weibet_98.pdf:PDF},
+  Keywords                 = {block codes;computational complexity;concatenated codes;feedback;iterative decoding;trellis codes;turbo codes;code complexity;code length;code rate;component codes;design criterion;iterative decoding;minimum distance;parallel concatenated block codes;performance;simulation;systematic feedback encoders;tail-biting codes;tail-biting trellises;two-dimensional weight distribution;Block codes;Carbon capture and storage;Concatenated codes;Convolution;Convolutional codes;Degradation;Feedback;Guidelines;Iterative decoding;Protection},
+  Owner                    = {StW},
+  Timestamp                = {2016.02.23}
+}
+
+@MastersThesis{MTweith12,
+  Title                    = {{D}esign, {I}mplementation and {E}valuation of {F}lexible {P}arallel {P}seudo {R}andom {N}umber {G}enerators},
+  Author                   = {Stefan Weithoffer},
+  School                   = {Microelectronic Systems Design Research Group, University of Kaiserslautern, Germany},
+  Year                     = {2012},
+  Month                    = mar,
+
+  Cds_grade                = {5},
+  Cds_keywords             = {random number generators},
+  File                     = {MTweith12.pdf:MTweith12.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.06}
+}
+
+@InProceedings{weiher_17,
+  Title                    = {{A}dvanced wireless digital baseband signal processing beyond 100 {G}bit/s},
+  Author                   = {S. Weithoffer and M. Herrmann and C. Kestel and N. Wehn},
+  Booktitle                = {2017 IEEE International Workshop on Signal Processing Systems (SiPS)},
+  Year                     = {2017},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/SiPS.2017.8109974},
+  Keywords                 = {MIMO communication;decoding;radio transceivers;signal processing;turbo codes;advanced wireless digital baseband signal processing;bit rate 100.0 Gbit/s;energy efficiency;higher spectral efficiency;lowest signal processing latencies;size 28.0 nm;wireless communication systems;wireless transceivers;Baseband;Decoding;Iterative decoding;Mobile communication;Throughput;Turbo codes},
+  Owner                    = {StW},
+  Timestamp                = {2018.01.03}
+}
+
+@InProceedings{weiweh_17c,
+  Title                    = {{B}it-level {P}ipelining for {H}ighly {P}arallel {T}urbo-{C}ode {D}ecoders: {A} {C}ritical {A}ssessment},
+  Author                   = {Weithoffer, Stefan and Kraft, Kira and Wehn, Norbert},
+  Booktitle                = {IEEE Africon 2017},
+  Year                     = {2017},
+  Pages                    = {138-143},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.10.18}
+}
+
+@InProceedings{weinou_18,
+  Title                    = {25 {Y}ears of {T}urbo {C}odes: {F}rom {M}b/s to beyond 100 {G}b/s},
+  Author                   = {Weithoffer, Stefan and Nour, Charbel Abdel and Wehn, Norbert and Douillard, Catherine and Berrou, Claude},
+  Booktitle                = {2018 IEEE 10th International Symposium on Turbo Codes \& Iterative Information Processing (ISTC)},
+  Year                     = {2018},
+  Organization             = {IEEE},
+  Pages                    = {1--6}
+}
+
+@InProceedings{weiweh_16,
+  Title                    = {{O}n the applicability of trellis compression to {T}urbo-{C}ode decoder hardware architectures},
+  Author                   = {S. Weithoffer and F. Pohl and N. Wehn},
+  Booktitle                = {2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)},
+  Year                     = {2016},
+  Month                    = {Sept},
+  Pages                    = {61-65},
+
+  Doi                      = {10.1109/ISTC.2016.7593077},
+  Keywords                 = {Long Term Evolution;codecs;decoding;error statistics;turbo codes;LTEILTE-A puncturing pattern;LTEILTE-A standard;MAP decoding;Trellis compression;XMAP architecture;frame error rate;max-log-MAP algorithm;parallel serial MAP architecture;throughput demands;turbo-code decoder architectures;turbo-code decoder hardware architectures;Decoding;Iterative decoding;Mathematical model;Measurement;Pipelines;Turbo codes}
+}
+
+@Article{weiweh_18,
+  Title                    = {{W}here to go from {H}ere? {N}ew {C}ross {L}ayer {T}echniques for {LTE}
+{T}urbo-{C}ode {D}ecoding at {H}igh {C}ode {R}ates},
+  Author                   = {Stefan Weithoffer and Norbert Wehn},
+  Journal                  = {Accepted for publication in: Advances in Radio Science},
+  Year                     = {2018},
+
+  Owner                    = {StW},
+  Timestamp                = {2018.02.20}
+}
+
+@InProceedings{weiweh_17,
+  Title                    = {{L}atency {R}educed {LTE}-{A} {T}urbo-{C}ode {D}ecoding with {I}teration {B}alancing on {T}ransport {B}lock {L}evel},
+  Author                   = {S. Weithoffer and N. Wehn},
+  Booktitle                = {SCC 2017; 11th International ITG Conference on Systems, Communications and Coding},
+  Year                     = {2017},
+
+  Owner                    = {StW},
+  Timestamp                = {2016.12.12}
+}
+
+@InProceedings{weiweh_17a,
+  Title                    = {{E}nhanced decoding for high-rate {LTE} {T}urbo-{C}odes with short block lengths},
+  Author                   = {S. Weithoffer and N. Wehn},
+  Booktitle                = {2017 IEEE International Conference on Communications Workshops (ICC)},
+  Year                     = {2017},
+  Month                    = {May}
+}
+
+@Article{weiweh_17b,
+  Title                    = {{L}ow-{L}atency {CRC} {C}alculation in {T}urbo-{C}ode {D}ecoding},
+  Author                   = {Weithoffer, Stefan
+and Wehn, Norbert},
+  Journal                  = {International Journal of Wireless Information Networks},
+  Year                     = {2017},
+
+  Month                    = {Oct},
+
+  Abstract                 = {Design of Turbo-Code decoders for the 3GPP LTE/LTE-A standard focuses on achieving a high-throughput of up to 1 Gbps with low decoding latencies at very high code rates. At code rates close to one, as specified in LTE/LTE-A, the decoding process can oscillate. Although the decoder converges to a valid code word after half-iteration i, after half-iteration {\$}{\$}i+1{\$}{\$} i + 1 the decoded code word is invalid again. To circumvent this, the CRC that is attached to each code word must be evaluated after each half-iteration. We present a generalized architecture for calculating the CRC On-the-fly during both non-interleaved and interleaved half-iterations and thus explicitly taking into account the requirements for low-latency Turbo-Code decoding. Further, we investigate the latency-, and energy savings provided by employing this calculation scheme. Lastly, we give post layout synthesis results for a case study implementation in state-of-the-art 28 nm FDSOI technology.},
+  Day                      = {13},
+  Doi                      = {10.1007/s10776-017-0374-z},
+  ISSN                     = {1572-8129},
+  Owner                    = {StW},
+  Timestamp                = {2017.10.16},
+  Url                      = {https://doi.org/10.1007/s10776-017-0374-z}
+}
+
+@InProceedings{weiweh_15,
+  Title                    = {{L}atency reduction for {LTE}/{LTE}-{A} turbo-code decoders by on-the-fly calculation of {CRC}},
+  Author                   = {Weithoffer, Stefan and Wehn, Norbert},
+  Booktitle                = {Personal, Indoor, and Mobile Radio Communications (PIMRC), 2015 IEEE 26th Annual International Symposium on},
+  Year                     = {2015},
+  Month                    = {Aug},
+  Pages                    = {1409-1414},
+
+  Doi                      = {10.1109/PIMRC.2015.7343519},
+  File                     = {weiweh_15.pdf:weiweh_15.pdf:PDF},
+  Keywords                 = {Decoding;Iterative decoding;Land mobile radio;Mobile computing;Polynomials;Throughput;Turbo codes},
+  Owner                    = {StW},
+  Timestamp                = {2015.12.08}
+}
+
+@Article{wel_15,
+  Title                    = {{The} {Future} {X} {Network:} {A} {B}ell {L}abs {P}erspective},
+  Author                   = {Weldon, Marcus},
+  Year                     = {2015},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.10.20}
+}
+
+@PhdThesis{Phdwelli07,
+  Title                    = {{Design Space Exploration of Memory-dominated 3G Baseband Receivers}},
+  Author                   = {A. Wellig},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2007},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{welzor_04,
+  Title                    = {{Novel Optimum Reduced Search MLSE decoding algorithm enabling System-aware Power Savings}},
+  Author                   = { A. Wellig and J. Zory and N. Wehn},
+  Booktitle                = {Proc. IEEE Radio and Wireless Conference},
+  Year                     = {2004},
+
+  Address                  = {Atlanta,USA},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{welzor_04a,
+  Title                    = {{Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications}},
+  Author                   = { A. Wellig and J. Zory and N. Wehn},
+  Booktitle                = {Proc. 2004 International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS '04)},
+  Year                     = {2004},
+
+  Address                  = {Santorini, Greece},
+  Month                    = sep,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wenbru_10,
+  Title                    = {{A}rea- and throughput-optimized {VLSI} architecture of sphere decoding},
+  Author                   = {Wenk, M. and Bruderer, L. and Burg, A. and Studer, C. },
+  Booktitle                = {Proc. 18th IEEE/IFIP VLSI System Chip Conf. (VLSI-SoC)},
+  Year                     = {2010},
+  Pages                    = {189--194},
+
+  Doi                      = {10.1109/VLSISOC.2010.5642593},
+  File                     = {wenbru_10.pdf:wenbru_10.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.10.14}
+}
+
+@Article{wenfos_08,
+  Title                    = {{T}owards {M}aximum {L}ikelihood {S}oft {D}ecision {D}ecoding of the (255,239) {R}eed {S}olomon {C}ode},
+  Author                   = {Jin Wenyi and Fossorier, M.},
+  Journal                  = {IEEE Transactions on Magnetics},
+  Year                     = {2008},
+  Number                   = {3},
+  Pages                    = {423--428},
+  Volume                   = {44},
+
+  Doi                      = {10.1109/TMAG.2008.916381},
+  File                     = {wenfos_08.pdf:wenfos_08.pdf:PDF},
+  Keywords                 = {Reed-Solomon, OSD, Box and Match},
+  Owner                    = {Scholl},
+  Review                   = {Box and Match für den RS(255,239) sehr gute Performance},
+  Timestamp                = {2011.07.14}
+}
+
+@InProceedings{wersti_10,
+  Title                    = {{E}lastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing},
+  Author                   = {Wernsing, John Robert and Stitt, Greg},
+  Booktitle                = {ACM SIGPLAN Notices},
+  Year                     = {2010},
+  Number                   = {4},
+  Organization             = {ACM},
+  Pages                    = {115--124},
+  Volume                   = {45},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.30}
+}
+
+@Book{wes_11,
+  Title                    = {{CMOS} {VLSI} {D}esign: {A} {C}ircuits and {S}ystems {P}erspective},
+  Author                   = {Neil H. E. Weste and David Money Harris},
+  Editor                   = {{M. Hirsch}},
+  Publisher                = {{Addison-Wesley, Pearson}},
+  Year                     = {2011},
+  Edition                  = {4},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.05.19}
+}
+
+@InProceedings{wesmar_10,
+  Title                    = {{A}ccelerating the {C}omputation of {P}ortfolios of {T}ranched {C}redit {D}erivatives},
+  Author                   = {Stephen Weston and Jean-Tristan Marin and James Spooner and Oliver Pell and Oskar Mencer},
+  Booktitle                = {High Performance Computational Finance (WHPCF), 2010 IEEE Workshop on},
+  Year                     = {2010},
+  Month                    = nov,
+  Pages                    = {1--8},
+
+  Abstract                 = {Huge growth in the trading and complexity of credit derivative instruments over the past five years has driven the need for ever more computationally demanding mathematical models. This has led to massive growth in data center compute capacity, power and cooling requirements. We report the results of an on-going joint project between J.P. Morgan and specialist acceleration solutions provider Maxeler Technologies to improve the price-performance for calculating the value and risk of a large complex credit derivatives portfolio. Our results show that valuing tranches of Collateralized Default Obligations (CDOs) on Maxeler accelerated systems is over 30 times faster per cubic foot and per Watt than solutions using standard multi-core Intel Xeon processors. We also report some preliminary results of further work that extends the approach to classes of interest rate derivatives.},
+  Cds_grade                = {5},
+  Cds_keywords             = {FPGA, copula, CDO, Monte Carlo, speed comparison, fixed point},
+  Cds_read                 = {2011-11-13},
+  Cds_review               = {CDO pricing on hybrid FPGA-CPU rack
+fixed point computations on FPGA
+2 scenarios: full and reduced precision
+speedup to CPU only: 31x (full) and 37x (reduced)
+
++good summary of design flow with commercial Maxeler tools
++detailed speed up results
++power measurements with named measurement devices},
+  Doi                      = {10.1109/WHPCF.2010.5671822},
+  File                     = {wesmar_10.pdf:wesmar_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.06.22}
+}
+
+@Article{wesspo_11,
+  Title                    = {{FPGA}s {S}peed the {C}omputation of {C}omplex {C}redit {D}erivatives},
+  Author                   = {Stephen Weston and James Spooner and Jean-Tristan Marin and Oliver Pell and Oskar Mencer},
+  Journal                  = {Xcell Journal},
+  Year                     = {2011},
+
+  Month                    = mar,
+  Number                   = {74},
+  Pages                    = {18--25},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {Monte Carlo, copula, speed comparison, CDO, fixed point, FPGA},
+  Cds_read                 = {2011-11-11},
+  Cds_review               = {based on wesmar_10
+they use Maxeler MaxCompiler for Java -> VHDL generation
+fixed-point implementations
+hybrid MaxRack has shown a 31x acceleration compared to an identically sized system that uses only 8-core Intel CPUs
+
++ numbers for speed comparison
++ numbers for implementation complexity (C++: 898 lines of code, FPGA: 3,696)
++ good motivation why energy saving architectures are needed in finance},
+  File                     = {wesspo_11.pdf:wesspo_11.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.13}
+}
+
+@PhdThesis{Phdwiber96,
+  Title                    = {{Codes and Decoding on General Graphs}},
+  Author                   = {N. Wiberg},
+  School                   = {Linköping University, Sweden},
+  Year                     = {1996},
+  Month                    = oct,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{wiesul_03,
+  Title                    = {{O}verview of the {H}.264/{AVC} video coding standard},
+  Author                   = {Wiegand, T. and Sullivan, G.J. and Bjontegaard, G. and Luthra, A.},
+  Journal                  = {Circuits and Systems for Video Technology, IEEE Transactions on},
+  Year                     = {2003},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {560-576},
+  Volume                   = {13},
+
+  Cds_grade                = {0},
+  Date-added               = {2008-10-15 10:49:06 +0200},
+  Date-modified            = {2008-10-15 10:49:12 +0200},
+  Doi                      = {10.1109/TCSVT.2003.815165},
+  File                     = {wiesul_03.pdf:wiesul_03.pdf:PDF},
+  ISSN                     = {1051-8215},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Misc{wiki:semi,
+  Title                    = {{S}emiconductor device fabrication --- {W}ikipedia{,} {T}he {F}ree {E}ncyclopedia},
+
+  Author                   = {Wikipedia},
+  Note                     = {[Online; accessed 23-Feb-2012]},
+  Year                     = {2011},
+
+  Url                      = {http://en.wikipedia.org/wiki/Semiconductor_device_fabrication}
+}
+
+@Misc{Wikipedi2011,
+  Title                    = {{S}emiconductor device fabrication --- {W}ikipedia{,} {T}he {F}ree {E}ncyclopedia},
+
+  Author                   = {Wikipedia},
+  Note                     = {[Online; accessed 23-Feb-2012]},
+  Year                     = {2011},
+
+  Owner                    = {scholl},
+  Timestamp                = {2015.06.11},
+  Url                      = {http://en.wikipedia.org/wiki/Semiconductor_device_fabrication}
+}
+
+@Article{wilbla_17,
+  Title                    = {{E}nergy-{N}eutral {D}ata {C}ollection {R}ate {C}ontrol for {IoT} {A}nimal {B}ehavior {M}onitors},
+  Author                   = {Wilhelm, Jay and Blackshire, Sheldon and Lanzone, Michael},
+  Journal                  = {Applied Sciences},
+  Year                     = {2017},
+  Number                   = {11},
+  Volume                   = {7},
+
+  Article_number           = {1169},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {app7111169},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.3390/app7111169},
+  ISSN                     = {2076-3417},
+  Keywords                 = {TCS},
+  Owner                    = {CCR},
+  Url                      = {http://www.mdpi.com/2076-3417/7/11/1169}
+}
+
+@Article{wilkau_98,
+  Title                    = {{A} new scalable {VLSI} architecture for {R}eed-{S}olomon decoders},
+  Author                   = {Wolfgang Wilhelm and A. Kaufmann and Noll, Tobias G.},
+  Journal                  = {Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998},
+  Year                     = {1998},
+
+  Month                    = may,
+  Pages                    = {13-16},
+
+  Abstract                 = {A scalable VLSI architecture for Reed-Solomon decoding suited for data rates from 10 Mbit/s to 1.2 Gbit/s in a 0.5 micrometer-CMOS technology is presented. New regular, time-shared architectures have been derived for solving the key equation and performing finite field divisions. A small silicon area in comparison with state-of-the-art decoder implementations demonstrates the efficiency of the proposed architecture},
+  Booktitle                = {Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998},
+  Cds_grade                = {0},
+  Cds_keywords             = {BCH, Reed-Solomon, RS, VLSI},
+  Doi                      = {10.1109/CICC.1998.694898},
+  File                     = {wilkau_98.pdf:wilkau_98.pdf:PDF},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2009.06.22}
+}
+
+@InBook{wilshc_12,
+  Title                    = {{A}mbient {A}ssisted {L}iving},
+  Author                   = {S. Wille and I. Shcherbakov and L. de Souza and N. Wehn},
+  Chapter                  = {TinySEP - A tiny platform for Ambient Assisted Living},
+  Publisher                = {Springer Verlag},
+  Year                     = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@InBook{wilshc_12a,
+  Title                    = {{T}echnik f\"{u}r ein selbstbestimmtes {L}eben},
+  Author                   = {S. Wille and I. Shcherbakov and L. de Souza and N. Wehn},
+  Chapter                  = {TinySEP - Eine kompakte Plattform für Ambient Assisted Living},
+  Publisher                = {VDE-Verlag},
+  Year                     = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.05.14}
+}
+
+@InProceedings{wilweh_12,
+  Title                    = {{Combining Robotic Frameworks with a Smart Environment Framework: MCA2/SimVis3D and TinySEP}},
+  Author                   = {Wille, S. and Wehn, N. and Arndt, M. and Berns, K and de Souza, L.},
+  Booktitle                = {Proc. Ubirobots 2012 Workshop conducted at the 14th International Conference on Ubiquitous Computing (Ubicomp 2012)},
+  Year                     = {2012},
+  Month                    = sep
+}
+
+@InProceedings{Wille2010,
+  Title                    = {{A}m{ICA} - {A} fexible, compact, easy-to-program and low-power {WSN} platform},
+  Author                   = {Wille, Sebastian and Wehn, Norbert and Martinovic, Ivan and Kunz, Simon and Goehner, Peter},
+  Booktitle                = {Springer LNICST series (Mobiquitous 2010)},
+  Year                     = {2010},
+
+  Address                  = {{http://ems.eit.uni-kl.de/uploads/tx\_uniklwehn/AmICA\_A\_flexible\_compact\_easy-to-program\_and\_low-power\_WSN\_platform.pdf}},
+  Month                    = {dec.},
+
+  Abstract                 = {In this paper, we present AmICA: a fexible, compact, easy-to-program, and low-power WSN platform. Developed from scratch and including a node, a basic communication protocol, and a debugging toolkit, it assists in a user-friendly rapid application development. Our analysis shows that AmICA nodes are 67% smaller than BTnodes, have five times more sensors than Mica2Dot and consume 72% less energy than the state-of-the-art TelosB mote in sleep mode.},
+  Owner                    = {Sebastian Wille},
+  Timestamp                = {2010.12.15},
+  Url                      = {http://ems.eit.uni-kl.de/uploads/tx\_uniklwehn/AmICA\_A\_flexible\_compact\_easy-to-program\_and\_low-power\_WSN\_platform.pdf}
+}
+
+@TechReport{Wille2010a,
+  Title                    = {{A}m{ICA} - {D}esign and implementation of a flexible, compact, easy-to-program and low-power {WSN} platform},
+  Author                   = {Wille, Sebastian and Wehn, Norbert and Martinovic, Ivan and Kunz, Simon and Goehner, Peter},
+  Year                     = {2010},
+
+  Address                  = {{http://ems.eit.uni-kl.de/uploads/tx\_uniklwehn/AmICATechReport2010.pdf}},
+  Month                    = {oct.},
+
+  Owner                    = {Sebastian Wille},
+  Timestamp                = {2010.10.31},
+  Url                      = {http://ems.eit.uni-kl.de/uploads/tx\_uniklwehn/AmICATechReport2010.pdf}
+}
+
+@Book{wil_10a,
+  Title                    = {{U}ncontrolled {R}isk: {T}he lessons of {L}ehman {B}rothers and how systemic risk can still bring down the world financial system},
+  Author                   = {Mark T. Williams},
+  Publisher                = {McGraw-Hill},
+  Year                     = {2010},
+
+  Address                  = {New York, USA},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.04}
+}
+
+@Article{wilkna_12,
+  Title                    = {{F}ast {L}inear {M}odel {P}redictive {C}ontrol {V}ia {C}ustom {I}ntegrated {C}ircuit {A}rchitecture},
+  Author                   = {A. G. Wills and G. Knagge and B. Ninness},
+  Journal                  = {IEEE Transactions on Control Systems Technology},
+  Year                     = {2012},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {59-71},
+  Volume                   = {20},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [55]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/TCST.2010.2096224},
+  ISSN                     = {1063-6536},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {CMOS logic circuits;field programmable gate arrays;integrated circuit design;linear systems;low-power electronics;microprocessor chips;predictive control;linear model predictive control;custom integrated circuit architecture design;linear {MPC} problem;serial architecture processor;field programmable gate array;14th-order resonant structure control;sample prediction horizon;CMOS technology;{FPGA};low-power computing hardware;size 130 nm;Computer architecture;Observers;Field programmable gate arrays;Integrated circuit modeling;Predictive models;Optimization;Predictive control;Field-programmable gate array ({FPGA});model predictive control ({MPC});very large scale integration (VLSI)},
+  Owner                    = {CCR}
+}
+
+@Book{wil_10,
+  Title                    = {{F}requently asked questions in quantitative finance},
+  Author                   = {Wilmott, Paul},
+  Publisher                = {John Wiley \& Sons},
+  Year                     = {2010},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.03}
+}
+
+@Misc{allmultiband09,
+  Title                    = {{Multiband OFDM Physical Layer Specification, Release Candidate 1.5}},
+
+  Author                   = {{WiMedia Alliance}},
+  Month                    = mar,
+  Year                     = {2009},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.04}
+}
+
+@Misc{WiMediaAlliance2009,
+  Title                    = {{Multiband OFDM Physical Layer Specification, Release Candidate 1.5}},
+
+  Author                   = {{WiMedia Alliance}},
+  Month                    = mar,
+  Year                     = {2009},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.04}
+}
+
+@Misc{winavr,
+  Title                    = {http://winavr.sourceforge.net/},
+
+  Author                   = {WinAVR},
+
+  Owner                    = {Wille},
+  Timestamp                = {2010.08.21},
+  Url                      = {http://winavr.sourceforge.net/}
+}
+
+@Article{winhow_09,
+  Title                    = {{A} {P}robabilistic {LDPC}-{C}oded {F}ault {C}ompensation {T}echnique for {R}eliable {N}anoscale {C}omputing},
+  Author                   = {Winstead, C. and Howard, S.},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2009},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {484--488},
+  Volume                   = {56},
+
+  Doi                      = {10.1109/TCSII.2009.2020946},
+  File                     = {winhow_09.pdf:winhow_09.pdf:PDF},
+  Keywords                 = {Reliability, LDPC},
+  Owner                    = {May},
+  Timestamp                = {2009.08.07}
+}
+
+@InProceedings{wirvie_06,
+  Title                    = {{G}eneration and {P}ropagation of {S}ingle {E}vent {T}ransients in {CMOS} {C}ircuits},
+  Author                   = {Wirth, G.I. and Vieira, M.G. and Neto, E.H. and Kastensmidt, F.L.},
+  Booktitle                = {Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE},
+  Year                     = {2006},
+  Pages                    = {196--201},
+
+  Doi                      = {10.1109/DDECS.2006.1649611},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.08.18},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1649611}
+}
+
+@PhdThesis{Phdwitte12,
+  Title                    = {{E}fficiency and {F}lexibility {T}rade-{O}ffs for {S}oft-{I}nput {S}oft-{O}utput {S}phere-{D}ecoding {A}rchitectures},
+  Author                   = {Ernst Martin Witte},
+  School                   = {RWTH Aachen},
+  Year                     = {2012},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.09.09}
+}
+
+@Article{witbor_10,
+  Title                    = {{A} {S}calable {VLSI} {A}rchitecture for {S}oft-{I}nput {S}oft-{O}utput {S}ingle {T}ree-{S}earch {S}phere {D}ecoding},
+  Author                   = {Witte, E. M. and Borlenghi, F. and Ascheid, G. and Leupers, R. and Meyr, H. },
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2010},
+  Number                   = {9},
+  Pages                    = {706--710},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TCSII.2010.2056014},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.07.19}
+}
+
+@Article{wol_78,
+  Title                    = {{E}fficient maximum likelihood decoding of linear block codes using a trellis},
+  Author                   = {Wolf, J.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {1978},
+  Number                   = {1},
+  Pages                    = {76--80},
+  Volume                   = {24},
+
+  Doi                      = {10.1109/TIT.1978.1055821},
+  File                     = {wol_78.pdf:wol_78.pdf:PDF},
+  Keywords                 = {InfTheory, Trellis},
+  Owner                    = {Scholl},
+  Review                   = {one of the first papers about trellises for linear block codes},
+  Timestamp                = {2011.04.27}
+}
+
+@InProceedings{wolfos_98,
+  Title                    = {{V}-{BLAST}: an architecture for realizing very high data rates over the rich-scattering wireless channel},
+  Author                   = {Wolniansky, P.W. and Foschini, G.J. and Golden, G.D. and Valenzuela, R.A.},
+  Booktitle                = {Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI International Symposium on},
+  Year                     = {1998},
+  Month                    = {sep-2 oct},
+  Pages                    = {295 -300},
+
+  Doi                      = {10.1109/ISSSE.1998.738086},
+  File                     = {wolfos_98.pdf:wolfos_98.pdf:PDF},
+  Keywords                 = {Information theory;Laboratories;Prototypes;Quadrature amplitude modulation;Rayleigh scattering;Receiving antennas;Space technology;Transfer functions;Transmitters;Transmitting antennas;Rayleigh channels;channel capacity;electromagnetic wave scattering;indoor radio;multipath channels;radiowave propagation;signal detection;Bell Laboratories Layered Space-Time;Rayleigh scattering;SNR;V-BLAST;channel capacity;error rates;indoor propagation environment;information theory research;laboratory prototype;multipath;real-time implementation;rich-scattering wireless channel;signal detection;spectral efficiencies;vertical BLAST;very high data rates;wire dipole array;wireless communication architecture;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.01.30}
+}
+
+@Book{wolnem_99,
+  Title                    = {{I}nteger and {C}ombinatorial {O}ptimization},
+  Author                   = {Laurence A. Wolsey and George L. Nemhauser},
+  Publisher                = {Wiley-Interscience},
+  Year                     = {1999},
+
+  Owner                    = {Kienle},
+  Timestamp                = {2012.11.14}
+}
+
+@Article{woncha_11,
+  Title                    = {{H}igh-{E}fficiency {P}rocessing {S}chedule for {P}arallel {T}urbo {D}ecoders {U}sing {QPP} {I}nterleaver},
+  Author                   = {Cheng-Chi Wong and Chang, Hsie-Chia},
+  Journal                  = {Circuits and Systems I: Regular Papers, IEEE Transactions on},
+  Year                     = {2011},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {1412-1420},
+  Volume                   = {58},
+
+  Doi                      = {10.1109/TCSI.2010.2097690},
+  ISSN                     = {1549-8328},
+  Keywords                 = {codecs;interleaved codes;polynomials;scheduling;turbo codes;QPP interleaver;SISO decoders;bit rate 1.4 Gbit/s;efficiency 100 percent;high-efficiency processing schedule;parallel turbo decoders;pipeline delays;quadratic permutation polynomial interleaver;size 90 nm;Decoding;Indexes;Measurement;Pipelines;Schedules;Throughput;Turbo codes;Parallel turbo decoder and quadratic permutation polynomial (QPP) interleaver},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@Article{woncha_10,
+  Title                    = {{R}econfigurable {T}urbo {D}ecoder {W}ith {P}arallel {A}rchitecture for 3{GPP} {LTE} {S}ystem},
+  Author                   = {Cheng-Chi Wong and Chang, Hsie-Chia},
+  Journal                  = {Circuits and Systems II: Express Briefs, IEEE Transactions on},
+  Year                     = {2010},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {566-570},
+  Volume                   = {57},
+
+  Doi                      = {10.1109/TCSII.2010.2048481},
+  ISSN                     = {1549-7747},
+  Owner                    = {StW},
+  Timestamp                = {2015.09.22}
+}
+
+@Article{wonlai_10,
+  Title                    = {{T}urbo {D}ecoder {U}sing {C}ontention-{F}ree {I}nterleaver and {P}arallel {A}rchitecture},
+  Author                   = {Cheng-Chi Wong and Ming-Wei Lai and Chien-Ching Lin and Hsie-Chia Chang and Chen-Yi Lee},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2010},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {422--432},
+  Volume                   = {45},
+
+  Doi                      = {10.1109/JSSC.2009.2038428},
+  File                     = {wonlai_10.pdf:wonlai_10.pdf:PDF},
+  ISSN                     = {0018-9200},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2012.05.11}
+}
+
+@Article{wonlee_12,
+  Title                    = {{M}etal–{O}xide {RRAM}},
+  Author                   = {H. -. P. Wong and H. Lee and S. Yu and Y. Chen and Y. Wu and P. Chen and B. Lee and F. T. Chen and M. Tsai},
+  Journal                  = {Proceedings of the IEEE},
+  Year                     = {2012},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {1951-1970},
+  Volume                   = {100},
+
+  Doi                      = {10.1109/JPROC.2012.2190369},
+  ISSN                     = {0018-9219},
+  Keywords                 = {random-access storage;metal-oxide RRAM;binary metal-oxide resistive switching random access memory;binary metal-oxide resistive switching RRAM;nonvolatile memory application;large-scale RRAM arrays;Resistance;Nonvolatile memory;Electrodes;Hafnium compounds;Electron traps;Random access memory;Solid state circuits;Emerging memory;metal oxide;multibit memory;nonvolatile memory;OxRAM;ReRAM;resistance change memory;resistive switching memory;resistive switching random access memory (RRAM);solid-state memory},
+  Timestamp                = {2018-09-07}
+}
+
+@InProceedings{wontsu_02,
+  Title                    = {{A} {VLSI} architecture of a {K}-best lattice decoding algorithm for {MIMO} channels},
+  Author                   = {K.W. Wong and C.Y. Tsui and R.S.K. Cheng and W.H. Mow},
+  Booktitle                = {Proc. IEEE Int. Symp. Circuits and Systems ISCAS 2002},
+  Year                     = {2002},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/ISCAS.2002.1010213},
+  Owner                    = {Gimmler},
+  Timestamp                = {2011.12.02}
+}
+
+@InProceedings{wonhor_06,
+  Title                    = {{S}oft {E}rror {R}esilience of {P}robabilistic {I}nference {A}pplications},
+  Author                   = {V. Wong and M. Horowitz},
+  Booktitle                = {Proc. The Second Workshop on System Effects of Logic Soft Errors (SELSE)},
+  Year                     = {2006},
+  Month                    = apr,
+
+  File                     = {wonhor_06.pdf:wonhor_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.01.20}
+}
+
+@Article{woohan_00,
+  Title                    = {{Comparative Study of Turbo Decoding Techniques: An Overview}},
+  Author                   = {Woodard, J. P. and L. Hanzo},
+  Journal                  = {IEEE Transactions on Vehicular Technology},
+  Year                     = {2000},
+
+  Month                    = nov,
+  Number                   = {6},
+  Pages                    = {2208--2233},
+  Volume                   = {49},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{woovan_08,
+  Title                    = {{FPGA} {A}cceleration of {Q}uasi-{M}onte {C}arlo in {F}inance},
+  Author                   = {Woods, N. A. and VanCourt, T.},
+  Booktitle                = {Proc. Int. Conf. Field Programmable Logic and Applications FPL 2008},
+  Year                     = {2008},
+  Pages                    = {335--340},
+
+  Abstract                 = {Today, quasi-Monte Carlo (QMC) methods are widely used in finance to price derivative securities. The QMC approach is popular because for many types of derivatives it yields an estimate of the price, to a given accuracy, faster than other competitive approaches, like Monte Carlo (MC) methods. The calculation of the large number of underlying asset pathways consumes a significant portion of the overall run-time and energy of modern QMC derivative pricing simulations. Therefore, we present an FPGA-based accelerator for the calculation of asset pathways suitable for use in the QMC pricing of several types of derivative securities. Although this implementation uses constructs (recursive algorithms and double-precision floating point) not normally associated with successful FPGA computing, we demonstrate performance in excess of 50times that of a 3 GHz multi-core processor.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPL.2008.4629954},
+  File                     = {woovan_08.pdf:woovan_08.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {Schmidt},
+  Timestamp                = {2010.08.03}
+}
+
+@PhdThesis{Phdworm01,
+  Title                    = {{I}mplementation {I}ssues of {T}urbo-{D}ecoders},
+  Author                   = {A. Worm},
+  School                   = {University of Kaiserslautern},
+  Year                     = {2001},
+  Note                     = {ISBN 3-925178-72-4},
+
+  Cds_grade                = {0},
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{wor_00,
+  Title                    = {{Implementing a Turbo-Decoder on the ARC Core}},
+  Author                   = {A. Worm},
+  Institution              = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2000},
+  Month                    = aug,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{woralgorithm01,
+  Title                    = {{Algorithm Manipulation for Low-Power Communication Circuit Implementation} (invited talk)},
+
+  Author                   = {A. Worm and F. Gilbert and M. Thul and N. Wehn},
+  HowPublished             = {SoC-Seminar 2001, Tampere, Finland},
+  Month                    = nov,
+  Year                     = {2001},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@Misc{Worm2001a,
+  Title                    = {{Algorithm Manipulation for Low-Power Communication Circuit Implementation} (invited talk)},
+
+  Author                   = {A. Worm and F. Gilbert and M. Thul and N. Wehn},
+  HowPublished             = {SoC-Seminar 2001, Tampere, Finland},
+  Month                    = nov,
+  Year                     = {2001},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@Article{worhoe_00,
+  Title                    = {{T}urbo-{D}ecoding without {SNR} {E}stimation},
+  Author                   = {Alexander Worm and Peter Hoeher and Norbert Wehn},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2000},
+
+  Month                    = jun,
+  Number                   = {6},
+  Pages                    = {193--195},
+  Volume                   = {4},
+
+  Abstract                 = {Theoretically, it is necessary to estimate the SNR when using
+a MAP or Log-MAP constituent decoder. The effect of an SNR mismatch
+on the bit error rate performance of Turbo-Codes and the design of good
+variance estimators have been addressed by several authors.
+In this letter, we study the SNR sensitivity of Turbo-decoding with Log-
+MAP and Max-Log-MAP constituent decoders, respectively, for AWGN
+and Rayleigh fading channels. Our theoretical and simulation results indicate
+that an estimation of the SNR is not necessary from a practical point
+of view. Our setup is aligned with decoder implementation aspects of future
+mobile communication systems.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Turbo-Code, SNR estimation, Max-Log-MAP, Log-MAP},
+  Cds_read                 = {2008-12-10},
+  Cds_review               = {Theoretical background of Log-MAP and Max-Log-MAP decoder is explained
+Conclusion:
+- Turbo-Decoding with Max-Log-MAP decoder is theoretically SNR independent
+- Turbo-Decoding with Log-MAP decoder is theoretically SNR dependent, but simulations show that it is not necessary},
+  File                     = {worhoe_00.pdf:worhoe_00.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{worlam_01,
+  Title                    = {{D}esign of {L}ow-{P}ower {H}igh-{S}peed {M}aximum a {P}osteriori {D}ecoder {A}rchitectures},
+  Author                   = {Alexander Worm and H. Lamm and Norbert Wehn},
+  Booktitle                = {Proc. Design, Automation and Test in Europe Conference and Exhibition 2001},
+  Year                     = {2001},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+  Pages                    = {258--265},
+
+  File                     = {worlam_01.pdf:worlam_01.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{worlam_01a,
+  Title                    = {{VLSI} {A}rchitectures for {H}igh-{S}peed {MAP} {D}ecoders},
+  Author                   = {Alexander Worm and Holger Lamm and Norbert Wehn},
+  Booktitle                = {Proc. Fourteenth International Conference on VLSI Design},
+  Year                     = {2001},
+
+  Address                  = {Bangalore, India},
+  Month                    = jan,
+  Pages                    = {446--453},
+
+  Cds_grade                = {3},
+  Cds_read                 = {2008-12-05},
+  Cds_review               = {D-MAP versus X-MAP
+memory and data lifeline considerations
+"rectangled" architecture},
+  File                     = {worlam_01a.pdf:worlam_01a.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Worm2001d,
+  Title                    = {{Shared High-Speed Maximum A Posteriori (MAP) Architectures with Optimized Memory Size and Power Consumption}},
+
+  Author                   = {A. Worm and H. Lamm and N. Wehn},
+  HowPublished             = {US Patent Application},
+  Month                    = jul,
+  Year                     = {2001},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{worshared01,
+  Title                    = {{Shared High-Speed Maximum A Posteriori (MAP) Architectures with Optimized Memory Size and Power Consumption}},
+
+  Author                   = {A. Worm and H. Lamm and N. Wehn},
+  HowPublished             = {US Patent Application},
+  Month                    = jul,
+  Year                     = {2001},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{worhigh-speed00,
+  Title                    = {{High-Speed Maximum A Posteriori (MAP) Architecture with Optimized Memory Size and Power Consumption}},
+
+  Author                   = {A. Worm and H. Lamm and N. Wehn},
+  HowPublished             = {UK Patent Application},
+  Month                    = mar,
+  Year                     = {2000},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{worlam_00,
+  Title                    = {{A} {H}igh-{S}peed {MAP} {A}rchitecture with {O}ptimized {M}emory {S}ize and {P}ower {C}onsumption},
+  Author                   = {Alexander Worm and Holger Lamm and Norbert Wehn},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems SiPS 2000},
+  Year                     = {2000},
+
+  Address                  = {Lafayette, Louisiana, USA},
+  Month                    = oct,
+  Pages                    = {265--274},
+
+  Cds_grade                = {4},
+  Cds_read                 = {2008-11},
+  File                     = {worlam_00.pdf:worlam_00.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Worm2000b,
+  Title                    = {{High-Speed Maximum A Posteriori (MAP) Architecture with Optimized Memory Size and Power Consumption}},
+
+  Author                   = {A. Worm and H. Lamm and N. Wehn},
+  HowPublished             = {UK Patent Application},
+  Month                    = mar,
+  Year                     = {2000},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wormic_00,
+  Title                    = {{A}dvanced {I}mplementation {I}ssues of {T}urbo-{D}ecoders},
+  Author                   = {Alexander Worm and Heiko Michel and Frank Gilbert and Gerd Kreiselmaier and Michael J. Thul and Norbert Wehn},
+  Booktitle                = {Proc. 2nd International Symposium on Turbo Codes \& Related Topics},
+  Year                     = {2000},
+
+  Address                  = {Brest, France},
+  Month                    = sep,
+  Pages                    = {351--354},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {turbo code, Implementation, renormalization, modulo arithmetic, rescaling},
+  Cds_read                 = {2008-11-20},
+  Cds_review               = {first section: modulo arithmetic instead of renormalization is presented for the first time
+
+second section:
+new early stop criterion for undecodable frames
+considering FER instead of BER
+mean of saturated LLRs serves as a measure of confidence in the decoding result},
+  File                     = {wormic_00.pdf:wormic_00.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@TechReport{wormic_00a,
+  Title                    = {{Kurzstudie zum Forschungsauftrag ``Aufwandsabschätzung zur vereinfachten sequentiellen Detektion''}},
+  Author                   = {A. Worm and H. Michel and F. Gilbert and N. Wehn},
+  Institution              = {Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern},
+  Year                     = {2000},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{Worm2001e,
+  Title                    = {{A Method and Apparatus for Decoding a Bit Sequence}},
+
+  Author                   = {A. Worm and H. Michel and N. Wehn},
+  HowPublished             = {Patent Application},
+  Month                    = jun,
+  Year                     = {2001},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{wormethod01,
+  Title                    = {{A Method and Apparatus for Decoding a Bit Sequence}},
+
+  Author                   = {A. Worm and H. Michel and N. Wehn},
+  HowPublished             = {Patent Application},
+  Month                    = jun,
+  Year                     = {2001},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wormic_99,
+  Title                    = {{P}ower minimization by optimizing data transfers in {T}urbo-decoders},
+  Author                   = {Alexander Worm and Heiko Michel and Norbert Wehn},
+  Booktitle                = {{Kleinheubacher Berichte}},
+  Year                     = {1999},
+  Month                    = sep,
+  Pages                    = {343--350},
+  Volume                   = {43},
+
+  Abstract                 = {The power consumption of (embedded) microelectronic systems is dominated by energy-consuming accesses to memories, both on-chip and o-chip. An o-chip memory-access consumes up to 33 times more energy compared to an arithmetic operation. Therefore, the potential to minimize power consumption by rearranging (and eventually avoiding) memory accesses has to be exploited before addressing data-path optimizations. Since their invention in 1993, Turbo-Codes have been a hot topic among coding theorists. The anticipated use in future mobile radio systems also raises interest among implementation specialists. However, although the computational complexity of Turbo-Code's MAP component decoders is well known, the memory accessing scheme is the real bottleneck for low-power implementations, which are essential for building cheap batteryoperated mobile devices. This paper therefore focuses on data-transfer optimizations. The number of data-transfers is a function of system-level parameters, algorithmic transformations, and implementation parameters. It will be shown how the data-transfer related energy consumption of Turbo-decoders can be signicantly reduced by taking proper design choices. Especially the eects of algorithmic transformations like windowing and some control/data- ow transformations will be discussed.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Turbo-Code, power, Log-MAP, Max-Log-MAP, windowing},
+  Cds_read                 = {2008-12-10},
+  Cds_review               = {general overview, not very detailed
+good introduction into Turbo-Codes, Log-MAP and max-Log-MAP
+model for memory power consumption
+examples for power reduction in Turbo-Decoders:
+- sliding window technique (serial / parallel)
+- MAP sub-task parallelization: combining recursions with metric calculation
+- recomputation: only a fraction of the metrics is stored in RAM, others calculated on-the-fly resp. stored in register file
+- algorithmic transformations: reduced-search MAP, early detection & trellis splicing
+- voltage scheduling, quantization (for reduced bit-width)},
+  File                     = {wormic_99.pdf:wormic_99.pdf:PDF},
+  Keywords                 = {AGWehn},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{worien_04,
+  Title                    = {{On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations}},
+  Author                   = {Worm, F. and Ienne, P. and Thiran, P. and De Micheli, G.},
+  Journal                  = {IEEE Design \& Test of Computers},
+  Year                     = {2004},
+
+  Month                    = nov,
+  Number                   = {6},
+  Pages                    = {524--535},
+  Volume                   = {21},
+
+  Cb_grade                 = {- ungelesen
+- Reliability
+- synchronization, technology},
+  File                     = {worien_04.pdf:worien_04.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {Brehm, may},
+  Timestamp                = {2011.10.18}
+}
+
+@Article{wushi_05,
+  Title                    = {{VLSI} architectural design tradeoffs for sliding-window log-{MAP} decoders},
+  Author                   = {Chien-Ming Wu and Ming-Der Shieh and Chien-Hsing Wu and Yin-Tsung Hwang and Jun-Hong Chen},
+  Journal                  = {IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS},
+  Year                     = {2005},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {439--447},
+  Volume                   = {13},
+
+  Doi                      = {10.1109/TVLSI.2004.842917},
+  File                     = {wushi_05.pdf:wushi_05.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.03.17}
+}
+
+@InProceedings{wu_01,
+  Title                    = {{On the Complexity of Turbo Decoding Algorithms}},
+  Author                   = {Wu, P.H.-Y.},
+  Booktitle                = {Vehicular Technology Conference, 2001. VTC 2001 Spring. IEEE VTS 53rd},
+  Year                     = {2001},
+  Month                    = may,
+  Pages                    = {1439--1443vol.2},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/VETECS.2001.944625},
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.28}
+}
+
+@Article{wusad_05,
+  Title                    = {{A} new adaptive two-stage maximum-likelihood decoding algorithm for linear block codes},
+  Author                   = {Xianren Wu and H. R. Sadjadpour and Zhi Tian},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2005},
+
+  Month                    = {June},
+  Number                   = {6},
+  Pages                    = {909-913},
+  Volume                   = {53},
+
+  Doi                      = {10.1109/TCOMM.2005.849790},
+  ISSN                     = {0090-6778},
+  Keywords                 = {adaptive codes;algebraic codes;block codes;computational complexity;linear codes;maximum likelihood decoding;adaptive two-stage maximum-likelihood decoding algorithm;bounded block error rate;decoding complexity;linear block code;minimum sufficient set;ordered algebraic decoding algorithm;signal-to-noise ratio;Block codes;Convergence;Error analysis;Iterative decoding;Maximum likelihood decoding;Maximum likelihood estimation;Signal to noise ratio;Student members;System analysis and design;Testing;Adaptive decoding complementary decoding;maximum-likelihood decoding;ordered algebraic decoding}
+}
+
+@Article{wuzhu_14,
+  Title                    = {{D}ata {M}ining with {B}ig {D}ata},
+  Author                   = {Xindong Wu and Xingquan Zhu and Gong-Qing Wu and Wei Ding},
+  Journal                  = {Knowledge and Data Engineering, IEEE Transactions on},
+  Year                     = {2014},
+
+  Month                    = jan,
+  Number                   = {1},
+  Pages                    = {97--107},
+  Volume                   = {26},
+
+  Abstract                 = {Big Data concern large-volume, complex, growing data sets with multiple, autonomous sources. With the fast development of networking, data storage, and the data collection capacity, Big Data are now rapidly expanding in all science and engineering domains, including physical, biological and biomedical sciences. This paper presents a HACE theorem that characterizes the features of the Big Data revolution, and proposes a Big Data processing model, from the data mining perspective. This data-driven model involves demand-driven aggregation of information sources, mining and analysis, user interest modeling, and security and privacy considerations. We analyze the challenging issues in the data-driven model and also in the Big Data revolution.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TKDE.2013.109},
+  File                     = {wuzhu_14.pdf:wuzhu_14.pdf:PDF},
+  ISSN                     = {1041-4347},
+  Owner                    = {CdS},
+  Timestamp                = {2014.03.03}
+}
+
+@InProceedings{wuebe_00,
+  Title                    = {{Forward Computation of Backward Path Metrics for MAP Decoder}},
+  Author                   = {Y. Wu and W. J. Ebel and B. D. Woerner},
+  Booktitle                = {Proc. 2000-Spring Vehicular Technology Conference (VTC Spring '00)},
+  Year                     = {2000},
+
+  Address                  = {Tokyo, Japan},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{wuhad_07,
+  Title                    = {{S}oft-{D}ecision {D}ecoding of {L}inear {B}lock {C}odes {U}sing {P}reprocessing and {D}iversification},
+  Author                   = {Y. Wu and C. N. Hadjicostis},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2007},
+
+  Month                    = {Jan},
+  Number                   = {1},
+  Pages                    = {378-393},
+  Volume                   = {53},
+
+  Doi                      = {10.1109/TIT.2006.887478},
+  ISSN                     = {0018-9448},
+  Keywords                 = {BCH codes;Reed-Solomon codes;binary codes;block codes;concatenated codes;decoding;linear codes;Reed-Solomon concatenated code;binary linear block codes;extended BCH code;generalized minimum distance decoding algorithm;multibasis order-w reprocessing scheme;soft-decision decoding approach;Block codes;Computational efficiency;Concatenated codes;Engineering profession;Iterative algorithms;Iterative decoding;Maximum likelihood decoding;Performance gain;Signal to noise ratio;Testing;Asymptotic performance;binary linear block codes;most reliable basis;multibasis;preprocessing;soft-decision decoding}
+}
+
+@InProceedings{wusun_18,
+  Title                    = {{P}rototyping {E}nergy {H}arvesting {P}owered {S}ystems with {N}onvolatile {P}rocessor ({I}nvited {P}aper)},
+  Author                   = {Y. {Wu} and Y. {Sun} and Z. {Jia} and L. {Zhang} and Y. {Liu} and J. {Hu}},
+  Booktitle                = {2018 International Symposium on Rapid System Prototyping (RSP)},
+  Year                     = {2018},
+  Month                    = {Oct},
+  Pages                    = {49-55},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8631991},
+  Ccr_keywords             = {NVP},
+  Ccr_relevance            = {low},
+  Ccr_topic                = {n.a.},
+  Doi                      = {10.1109/RSP.2018.8631991},
+  Keywords                 = {TCS},
+  Keywords_original        = {energy harvesting;Internet of Things;iterative methods;optimisation;telecommunication power management;Internet-of-Things devices;energy efficiency;nonvolatile processor;processor states;NVP-based system design process;rapid system prototyping flow;NVP system-level simulator;harvester power trace;energy harvesting powered systems;Hardware;Nonvolatile memory;Energy harvesting;Software;Computer architecture;Optimization;System analysis and design},
+  Owner                    = {CCR}
+}
+
+@Article{wuwoe_01,
+  Title                    = {{Data Width Requirements in SISO Decoding with Modulo Normalization}},
+  Author                   = {Yufei Wu and Woerner, B.D. and Blankenship, T.K.},
+  Journal                  = {Communications, IEEE Transactions on},
+  Year                     = {2001},
+
+  Month                    = nov,
+  Number                   = {11},
+  Pages                    = {1861--1868},
+  Volume                   = {49},
+
+  Doi                      = {10.1109/26.966047},
+  File                     = {wuwoe_01.pdf:wuwoe_01.pdf:PDF},
+  Keywords                 = {modulo normalisierung turbo},
+  Owner                    = {vogt},
+  Timestamp                = {2007.02.01}
+}
+
+@InProceedings{wuwoe_00,
+  Title                    = {{Analysis of Internal Data Width Requirements for SISO Decoding Modules}},
+  Author                   = {Y. Wu and B. D. Woerner},
+  Booktitle                = {Proc. 2000-Fall Vehicular Technology Conference (VTC Fall '00)},
+  Year                     = {2000},
+
+  Address                  = {Boston, Massachusetts, USA},
+  Month                    = sep,
+  Pages                    = {2265--2270},
+
+  Optvolume                = {5},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wuwoe_00a,
+  Title                    = {{Internal Data Width in SISO Decoding Module with Modular Renormalization}},
+  Author                   = {Y. Wu and B. D. Woerner},
+  Booktitle                = {Proc. 2000-Spring Vechicular Technology Conference (VTC Spring '00)},
+  Year                     = {2000},
+
+  Address                  = {Tokyo, Japan},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wuwoe_99,
+  Title                    = {{The Influence of Quantization and Fixed Point Arithmetic upon the BER Performance of Turbo Codes}},
+  Author                   = {Y. Wu and B. D. Woerner},
+  Booktitle                = {Proc. 1999 International Conference on Vehicular Technology (VTC '99)},
+  Year                     = {1999},
+  Month                    = may,
+  Pages                    = {1683--1687},
+
+  Optvolume                = {2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{wuwoe_00b,
+  Title                    = {{A Simple Stopping Criterion for Turbo Decoding}},
+  Author                   = {Y. Wu and Woerner, B. D. and Ebel, W. J.},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2000},
+
+  Month                    = aug,
+  Number                   = {8},
+  Pages                    = {258--260},
+  Volume                   = {4},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wubboh_03,
+  Title                    = {{MMSE} extension of {V}-{BLAST} based on sorted {QR} decomposition},
+  Author                   = {Wubben, D. and Bohnke, R. and Kuhn, V. and Kammeyer, K.-D.},
+  Year                     = {2003},
+  Month                    = {oct.},
+  Pages                    = { 508 - 512 Vol.1},
+  Volume                   = {1},
+
+  Abstract                 = { In rich-scattering environments, layered space-time architectures like the BLAST system may exploit the capacity advantage of multiple antenna systems. We present a novel, computationally efficient algorithm for detecting V-BLAST architectures with respect to the MMSE criterion. It utilizes a sorted QR decomposition of the channel matrix and leads to a simple successive detection structure. The new algorithm needs only a fraction of computational effort compared to the standard V-BLAST algorithm and achieves the same error performance.},
+  File                     = {wubboh_03.pdf:wubboh_03.pdf:PDF},
+  ISSN                     = {1090-3038},
+  Journal                  = {Vehicular Technology Conference, 2003. VTC 2003-Fall. 2003 IEEE 58th},
+  Keywords                 = { MIMO systems; MMSE; V-BLAST; channel matrix; error performance; layered space-time architectures; multiple antenna systems; sorted QR decomposition; successive detection structure; MIMO systems; least mean squares methods; matrix decomposition; radio links; signal detection; telecommunication channels;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.03.03}
+}
+
+@Article{wubboh_01,
+  Title                    = {{E}fficient algorithm for decoding layered space-time codes},
+  Author                   = {Wubben, D. and Bohnke, R. and Rinas, J. and Kuhn, V. and Kammeyer, K.D.},
+  Journal                  = {Electronics Letters},
+  Year                     = {2001},
+
+  Month                    = {oct},
+  Number                   = {22},
+  Pages                    = {1348 -1350},
+  Volume                   = {37},
+
+  Abstract                 = {Layered space-time codes have been designed to exploit the capacity advantage of multiple antenna systems in Rayleigh fading environments. A new efficient decoding algorithm based on QR decomposition is presented, which requires only a fraction of the computational effort compared with the standard decoding algorithm requiring the multiple calculation of the pseudo inverse of the channel matrix},
+  Doi                      = {10.1049/el:20010899},
+  File                     = {wubboh_01.pdf:wubboh_01.pdf:PDF},
+  ISSN                     = {0013-5194},
+  Keywords                 = {Gram-Schmidt algorithm;QR decomposition;Rayleigh fading environments;decoding algorithm;layered space-time codes;multiple antenna systems;Rayleigh channels;channel coding;decoding;matrix decomposition;transmitting antennas;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.03.03}
+}
+
+@Article{wulmck_95,
+  Title                    = {{Hitting the memory wall: implications of the obvious}},
+  Author                   = {Wulf, Wm. A. and McKee, Sally A.},
+  Journal                  = {SIGARCH Comput. Archit. News},
+  Year                     = {1995},
+
+  Month                    = mar,
+
+  Acmid                    = {216588},
+  Doi                      = {10.1145/216585.216588},
+  Issue_date               = {March 1995},
+  Numpages                 = {5},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.10},
+  Url                      = {http://doi.acm.org/10.1145/216585.216588}
+}
+
+@InCollection{wurweh_95,
+  Title                    = {{Multiple-Level Logic Optimization with Boolean Relations}},
+  Author                   = {Wurth, B. and Wehn, N.},
+  Booktitle                = {Logic and Architecture Synthesis -- State-of-the-art and novel approaches},
+  Publisher                = {Chapman \& Hall},
+  Year                     = {1995},
+  Pages                    = {15--25},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wurweh_94,
+  Title                    = {{Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization}},
+  Author                   = {Wurth, B. and Wehn, N.},
+  Booktitle                = {Proc. European Design and Test Conference EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design},
+  Year                     = {1994},
+
+  Address                  = {Paris},
+  Pages                    = {630--634},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@PhdThesis{Phdwuyta98,
+  Title                    = {{System-Level Power Optimization of Data Storage and Transfer}},
+  Author                   = {S. Wuytack},
+  School                   = {Katholieke Universiteit Leuven},
+  Year                     = {1998},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{wymste_04b,
+  Title                    = {{L}og-domain decoding of {LDPC} codes over {GF}(q)},
+  Author                   = {Wymeersch, H. and Steendam, H. and Moeneclaey, M.},
+  Booktitle                = {Proc. IEEE International Conference on Communications},
+  Year                     = {2004},
+  Month                    = jun,
+  Pages                    = {772--776},
+  Volume                   = {2},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2009.10.07}
+}
+
+@InProceedings{wynmag_09,
+  Title                    = {{P}ricing the {A}merican {O}ption using {R}econfigurable {H}ardware},
+  Author                   = {Chris Wynnyk and Malik Magdon-Ismail},
+  Booktitle                = {Computational Science and Engineering, 2009. CSE '09. International Conference on},
+  Year                     = {2009},
+  Month                    = aug,
+  Pages                    = {532 -536},
+  Volume                   = {2},
+
+  Abstract                 = {We present a novel reconfigurable hardware architecture for accelerating American option pricing using the binomial lattice algorithm. The architecture provides double precision floating point pricing, evaluating up to N = 64,000 time steps in the binomial lattice. Advanced memory management techniques and optimized control logic allow for 4-way parallelism on a single-asset evaluation. These techniques achieve a 73-times speedup over an optimized CPU implementation, and a considerable improvement over the best previous reconfigurable hardware implementation. A significant advantage of our approach is that the speed up is on a per asset basis whereas all previous approaches on FPGA and GPU architectures achieve their speed up by evaluating many assets in parallel.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/CSE.2009.496},
+  File                     = {wynmag_09.pdf:wynmag_09.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.25}
+}
+
+@Article{xav_12,
+  Title                    = {{A} note on a {M}aximum k-{S}ubset {I}ntersection {P}roblem},
+  Author                   = {Xavier, Eduardo C.},
+  Journal                  = {Information Processing Letters},
+  Year                     = {2012},
+  Number                   = {12},
+  Pages                    = {471-472},
+  Volume                   = {112},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-02-25}
+}
+
+@InProceedings{xidew_15,
+  Title                    = {{A} mixed-integer quadratic programming solver based on {GPU}},
+  Author                   = {W. Xi and L. Dewei and X. Yugeng},
+  Booktitle                = {2015 34th Chinese Control Conference (CCC)},
+  Year                     = {2015},
+  Month                    = {July},
+  Pages                    = {2686-2691},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{GPU} PLATFORM; cite number in presentation [21]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/ChiCC.2015.7260048},
+  ISSN                     = {1934-1768},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {graphics processing units;integer programming;mathematics computing;multi-threading;quadratic programming;tree searching;mixed-integer quadratic programming solver;{GPU};MI{QP} problem;parallel branch-and-bound algorithm;multipoint radiation;multithreading parallel structure;discrete-time simplified dual neural network;Graphics processing units;Instruction sets;Algorithm design and analysis;Neural networks;Neurons;Approximation algorithms;Quadratic programming;{GPU};Mix-integer Quadratic Programming;Branch and Bound Algorithm;Parallel Structure},
+  Owner                    = {CCR}
+}
+
+@Article{xiacru_07,
+  Title                    = {{P}erformance of {R}eliability-{B}ased {I}terative {S}oft-{D}ecision {R}eed-{S}olomon {D}ecoding on {M}agnetic {R}ecording {C}hannels},
+  Author                   = {Haitao Xia and Cruz, J. R. },
+  Journal                  = {IEEE Transactions on Magnetics},
+  Year                     = {2007},
+  Number                   = {7},
+  Pages                    = {3320--3323},
+  Volume                   = {43},
+
+  Doi                      = {10.1109/TMAG.2007.895130},
+  File                     = {xiacru_07.pdf:xiacru_07.pdf:PDF},
+  Keywords                 = {ABP, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {ABP mit Chase-aehnlichem Algorithmus},
+  Timestamp                = {2011.06.21}
+}
+
+@Article{xiacru_06,
+  Title                    = {{R}eliability-{B}ased {R}eed-{S}olomon {D}ecoding for {M}agnetic {R}ecording {C}hannels},
+  Author                   = {Haitao Xia and Cruz, J. R.},
+  Journal                  = {IEEE Transactions on Magnetics},
+  Year                     = {2006},
+  Number                   = {10},
+  Pages                    = {2603--2605},
+  Volume                   = {42},
+
+  Doi                      = {10.1109/TMAG.2006.878651},
+  File                     = {xiacru_06.pdf:xiacru_06.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ABP},
+  Owner                    = {Scholl},
+  Review                   = {ABP mit Chase-aehnlichem Algorithmus},
+  Timestamp                = {2011.06.21}
+}
+
+@Article{xiabre_19,
+  Title                    = {{A}rbitrarily {P}arallel {T}urbo {D}ecoding for {U}ltra-{R}eliable {L}ow {L}atency {C}ommunication in 3{GPP} {LTE}},
+  Author                   = {L. {Xiang} and M. F. {Brejza} and R. G. {Maunder} and B. M. {Al-Hashimi} and L. {Hanzo}},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2019},
+
+  Month                    = {April},
+  Number                   = {4},
+  Pages                    = {826-838},
+  Volume                   = {37},
+
+  Doi                      = {10.1109/JSAC.2019.2898654},
+  ISSN                     = {0733-8716},
+  Keywords                 = {decoding;Long Term Evolution;telecommunication network reliability;turbo codes;APTD;SOTA LTE turbo decoder;SOTA turbo decoder;SOTA decoder;ultra-reliable low latency communication mode;decoding information bits;decoding throughput;LTE turbo decoder;arbitrarily parallel turbo decoder;turbo decoding algorithms;Decoding;Throughput;Long Term Evolution;Parallel processing;Microsoft Windows;Hardware;Program processors;Turbo decoding;FPTD;parallel algorithms;latency;throughput}
+}
+
+@Article{xiaban_04,
+  Title                    = {{Improved Progressive-Edge-Growth (PEG) Construction of Irregular LDPC Codes}},
+  Author                   = {H. Xiao and A. Banihashemi},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2004},
+
+  Month                    = dec,
+  Number                   = {12},
+  Pages                    = {715--717},
+  Volume                   = {8},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{xiepan_18,
+  Title                    = {{A}voiding {D}ata {I}nconsistency in {E}nergy {H}arvesting {P}owered {E}mbedded {S}ystems},
+  Author                   = {Xie, Mimi and Pan, Chen and Zhao, Mengying and Liu, Yongpan and Xue, Chun Jason and Hu, Jingtong},
+  Journal                  = {ACM Trans. Des. Autom. Electron. Syst.},
+  Year                     = {2018},
+
+  Month                    = mar,
+  Number                   = {3},
+  Pages                    = {38:1--38:25},
+  Volume                   = {23},
+
+  Acmid                    = {3182170},
+  Address                  = {New York, NY, USA},
+  Articleno                = {38},
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {Xie:2018:ADI:3184476.3182170},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1145/3182170},
+  ISSN                     = {1084-4309},
+  Issue_date               = {April 2018},
+  Keywords                 = {TCS},
+  Keywords_original        = {Energy harvesting, adaptive checkpointing, inconsistency},
+  Numpages                 = {25},
+  Owner                    = {CCR},
+  Publisher                = {ACM},
+  Url                      = {http://doi.acm.org/10.1145/3182170}
+}
+
+@Misc{xilaws17,
+  Title                    = {{AWS Cloud: Xilinx FPGAs in World’s Largest Cloud}},
+
+  Author                   = {Xilinx},
+  HowPublished             = {Online: \url{https://www.xilinx.com/products/design-tools/acceleration-zone/aws.html}},
+  Note                     = {Last access: 08 Jan. 2018},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.08},
+  Url                      = {https://www.xilinx.com/products/design-tools/acceleration-zone/aws.html}
+}
+
+@Misc{xilbaidu17,
+  Title                    = {{Baidu Deploys Xilinx FPGAs in New Public Cloud Acceleration Services}},
+
+  Author                   = {Xilinx},
+  HowPublished             = {Online: \url{https://www.xilinx.com/news/press/2017/baidu-deploys-xilinx-fpgas-in-new-public-cloud-acceleration-services.html}},
+  Month                    = {Jul.},
+  Note                     = {Last access: 08 Jan. 2018},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.08},
+  Url                      = {https://www.xilinx.com/news/press/2017/baidu-deploys-xilinx-fpgas-in-new-public-cloud-acceleration-services.html}
+}
+
+@Manual{Xilinx2017,
+  Title                    = {{SDA}ccel {E}nvironment - {P}latform {D}evelopment {G}uide ({UG}1164)},
+  Author                   = {Xilinx},
+  Edition                  = {v2017.2},
+  Month                    = {Aug.},
+  Note                     = {Online: \url{https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1164-sdaccel-platform-development.pdf} Last access: 16 Dec. 2017},
+  Year                     = {2017},
+
+  Url                      = {https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1164-sdaccel-platform-development.pdf}
+}
+
+@Manual{Xilinx2017a,
+  Title                    = {{SDA}ccel {E}nvironment {U}ser {G}uide ({UG}1023)},
+  Author                   = {Xilinx},
+  Edition                  = {v2017.2},
+  Month                    = {Aug.},
+  Note                     = {Online: \url{https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1023-sdaccel-user-guide.pdf} Last access: 16 Dec. 2017},
+  Year                     = {2017},
+
+  Url                      = {https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1023-sdaccel-user-guide.pdf}
+}
+
+@Manual{Xilinx2017b,
+  Title                    = {{SDA}ccel {E}nvironment {O}ptimization {G}uide ({UG}1207)},
+  Author                   = {Xilinx},
+  Edition                  = {v2017.2},
+  Month                    = {Aug.},
+  Note                     = {Online: \url{https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1207-sdaccel-optimization-guide.pdf} Last access: 16 Dec. 2017},
+  Year                     = {2017},
+
+  Url                      = {https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1207-sdaccel-optimization-guide.pdf}
+}
+
+@Manual{Xilinx2017c,
+  Title                    = {{SD}x {P}ragma {R}eference {G}uide ({UG}1253)},
+  Author                   = {Xilinx},
+  Edition                  = {v2017.2},
+  Month                    = {Aug.},
+  Note                     = {Online: \url{https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1207-sdaccel-optimization-guide.pdf} Last access: 16 Dec. 2017},
+  Year                     = {2017},
+
+  Url                      = {https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1253-sdx-pragma-reference.pdf}
+}
+
+@Misc{xilsdaccel17,
+  Title                    = {{SDAccel Examples (github repository)}},
+
+  Author                   = {Xilinx},
+  HowPublished             = {Online: \url{https://github.com/Xilinx/SDAccel_Examples/tree/51416734fd694773a2ab4991f027e5c78e09c9a8}},
+  Note                     = {Last access: 05 Jan 2018},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.05}
+}
+
+@Manual{xilultrascale17,
+  Title                    = {{U}ltra{S}cale {A}rchitecture and {P}roduct {D}ata {S}heet: {O}verview ({DS}890)},
+  Author                   = {Xilinx},
+  Edition                  = {v3.1 ({Preliminary Product Specification})},
+  Month                    = {Nov.},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.12.15}
+}
+
+@Misc{xilxilinx17,
+  Title                    = {{Xilinx Selected by Alibaba Cloud for Next-Gen FPGA Cloud Acceleration}},
+
+  Author                   = {Xilinx},
+  HowPublished             = {Online: \url{https://www.xilinx.com/news/press/2017/xilinx-selected-by-alibaba-cloud-for-next-gen-fpga-cloud-acceleration.html}},
+  Month                    = {Oct.},
+  Note                     = {Last access: 08 Jan. 2018},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2018.01.08},
+  Url                      = {https://www.xilinx.com/news/press/2017/xilinx-selected-by-alibaba-cloud-for-next-gen-fpga-cloud-acceleration.html}
+}
+
+@Manual{xilsdaccel16,
+  Title                    = {{SDAccel Development Environment User Guide}},
+  Author                   = {Xilinx},
+  Edition                  = {{2015.4}},
+  Month                    = {Feb.},
+  Note                     = {{UG1023} \url{http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2015\_4/ug1023-sdaccel-user-guide.pdf}. Last access: 23 May 2016},
+  Organization             = {Xilinx},
+  Year                     = {2016},
+
+  Comment                  = {Last access: 23 May 2016},
+  HowPublished             = {\url{http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2015\_4/ug1023-sdaccel-user-guide.pdf}},
+  Owner                    = {varela},
+  Timestamp                = {2016.05.23},
+  Url                      = {\url{http://www.xilinx.com/support/documentation/sw\_manuals/xilinx2015\_4/ug1023-sdaccel-user-guide.pdf}}
+}
+
+@Manual{xilsdaccel16a,
+  Title                    = {{SDAccel Development Environment Methodology Guide: Performance Optimization}},
+  Author                   = {Xilinx},
+  Edition                  = {v2.0},
+  Month                    = {August},
+  Note                     = {{UG1207} \url{https://www.xilinx.com/support/documentation/sw_manuals/ug1207-sdaccel-performance-optimization.pdf}. Last access: 27 Nov. 2016},
+  Organization             = {Xilinx},
+  Year                     = {2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@Manual{xilsdaccel16b,
+  Title                    = {{SDAccel Development Environment User Guide: Features and Development Flows}},
+  Author                   = {Xilinx},
+  Edition                  = {{2015.4}},
+  Month                    = {Feb.},
+  Note                     = {{UG1023}, Last access: 27 Nov. 2016},
+  Organization             = {Xilinx},
+  Year                     = {2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27},
+  Url                      = {https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug1023-sdaccel-user-guide.pdf}
+}
+
+@Manual{boxzynq15a,
+  Title                    = {{Z}ynq-7000 {A}ll {P}rogrammable {S}o{C} {O}verview: {P}roduct {S}pecification {(DS190)}},
+  Author                   = {Xilinx},
+  Edition                  = {v1.8},
+  Month                    = {may},
+  Year                     = {2015},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.10.06}
+}
+
+@Electronic{xil_15,
+  Title                    = {{F}ast {F}ourier {T}ransform {V}9.0},
+  Author                   = {Xilinx},
+  Month                    = {April},
+  Url                      = {http://www.xilinx.com/products/intellectual-property/fft.html},
+  Year                     = {2015},
+
+  Owner                    = {Ali},
+  Timestamp                = {2015-05-13}
+}
+
+@Misc{xil_sdsoc,
+  Title                    = {{SDS}o{C} {D}evelopment {E}nvironment},
+
+  Author                   = {Xilinx},
+  HowPublished             = {\url{http://www.xilinx.com/products/design-tools/sdx/sdsoc.html}},
+  Note                     = {last access 2015-04-27},
+  Year                     = {2015},
+
+  Address                  = {http://www.xilinx.com/products/design-tools/sdx/sdsoc.html},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.04.27}
+}
+
+@Misc{xilinx_powerestimator_2014,
+  Title                    = {{XP}ower {E}stimator ({XPE})},
+
+  Author                   = {Xilinx},
+  Month                    = jun,
+  Note                     = {last access: 2014-09-16},
+  Year                     = {2014},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2014.07.03},
+  Url                      = {http://www.xilinx.com/products/design_tools/logic_design/xpe.htm}
+}
+
+@Manual{xilvivado14,
+  Title                    = {{V}ivado {D}esign {S}uite {U}ser {G}uide: {H}igh-{L}evel {S}ynthesis ({UG}902)},
+  Author                   = {Xilinx},
+  Edition                  = {v2014.3},
+  Month                    = {oct},
+  Organization             = {Xilinx},
+  Year                     = {2014},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.11}
+}
+
+@Misc{xidesigning12,
+  Title                    = {{Designing Software Applications with an Extensible Virtual Platform}},
+
+  Author                   = {{Xilinx}},
+  Year                     = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.10.04},
+  Url                      = {http://www.xilinx.com/products/zynq-7000/extensible-virtual-platform.htm}
+}
+
+@Misc{Xilinx2012a,
+  Title                    = {{Designing Software Applications with an Extensible Virtual Platform}},
+
+  Author                   = {{Xilinx}},
+  Year                     = {2012},
+
+  Owner                    = {schlaefer},
+  Timestamp                = {2012.10.04},
+  Url                      = {http://www.xilinx.com/products/zynq-7000/extensible-virtual-platform.htm}
+}
+
+@Misc{xil1026,
+  Title                    = {{L}ight{W}eight {IP} (lw{IP}) {A}pplication {E}xamples},
+
+  Author                   = {xilinx},
+  HowPublished             = {www.xilinx.com},
+  Year                     = {2011},
+
+  Owner                    = {Schlaefer},
+  Timestamp                = {2012.08.03}
+}
+
+@Misc{xilinx_powerestimator,
+  Title                    = {{XP}ower {E}stimator ({XPE})},
+
+  Author                   = {Xilinx},
+  HowPublished             = {\url{http://www.xilinx.com/products/design_tools/logic_design/xpe.htm}},
+  Month                    = jul,
+  Note                     = {last access 2014-07-02},
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.07.21},
+  Url                      = {http://www.xilinx.com/products/technology/power/index.htm}
+}
+
+@Misc{xillightweight11,
+  Title                    = {{L}ight{W}eight {IP} (lw{IP}) {A}pplication {E}xamples},
+
+  Author                   = {xilinx},
+  HowPublished             = {www.xilinx.com},
+  Year                     = {2011},
+
+  Owner                    = {Schlaefer},
+  Timestamp                = {2012.08.03}
+}
+
+@Misc{xilxpower11,
+  Title                    = {{XP}ower {E}stimator ({XPE})},
+
+  Author                   = {Xilinx},
+  Month                    = jul,
+  Year                     = {2011},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.07.21},
+  Url                      = {http://www.xilinx.com/products/technology/power/index.htm}
+}
+
+@Misc{xiautoesl,
+  Title                    = {{AutoESL High-Level Synthesis}},
+
+  Author                   = {{XILINX Inc.}},
+
+  Owner                    = {brehm},
+  Timestamp                = {2012.09.19},
+  Url                      = {http://www.xilinx.com/tools/autoesl_instructions.htm}
+}
+
+@Misc{xilinx-viterbi,
+  Title                    = {{Viterbi Decoder V6.0, Data Sheet}},
+
+  Author                   = {{Xilinx Inc.}},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2015-07-21}
+}
+
+@Misc{xiviterbi,
+  Title                    = {{Viterbi Decoder V6.0, Data Sheet}},
+
+  Author                   = {{Xilinx Inc.}},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2007.03.16}
+}
+
+@Misc{xilsdaccel14,
+  Title                    = {{SDA}ccel {D}evelopment {E}nvironment},
+
+  Author                   = {{Xilinx Inc.}},
+  HowPublished             = {\url{http://www.xilinx.com/products/design-tools/sdx/sdaccel.html}},
+  Month                    = nov,
+  Note                     = {last access 2015-02-05},
+  Year                     = {2014},
+
+  Owner                    = {CDS},
+  Timestamp                = {2015-02-05}
+}
+
+@Electronic{xil_12,
+  Title                    = {{AWGN} {IP} {C}ore {D}escription},
+  Author                   = {{Xilinx Inc.}},
+  HowPublished             = {\url{http://www.xilinx.com/products/intellectual-property/DO-DI-AWGN.htm}},
+  Language                 = {en},
+  Month                    = mar,
+  Note                     = {last access 2012-03-22},
+  Year                     = {2012},
+
+  Cds_read                 = {2012-03-22},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@Electronic{Xilinx2012,
+  Title                    = {{AWGN} {IP} {C}ore {D}escription},
+  Author                   = {{Xilinx Inc.}},
+  HowPublished             = {\url{http://www.xilinx.com/products/intellectual-property/DO-DI-AWGN.htm}},
+  Language                 = {en},
+  Month                    = mar,
+  Year                     = {2012},
+
+  Cds_read                 = {2012-03-22},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.22}
+}
+
+@InProceedings{xinwan_13,
+  Title                    = {{A} reduced-complexity successive-cancellation decoding algorithm for polar codes},
+  Author                   = {Chao Xing and Bei Wang and Shengmei Zhao},
+  Booktitle                = {Image and Signal Processing (CISP), 2013 6th International Congress on},
+  Year                     = {2013},
+  Month                    = {Dec},
+  Pages                    = {1221-1225},
+  Volume                   = {03},
+
+  Doi                      = {10.1109/CISP.2013.6743858},
+  Keywords                 = {computational complexity;decoding;error statistics;parity check codes;transforms;BER;LDPC codes;arbitrary symmetric binary-input channels;bit-error-rate;involution transform function;log-likelihood ratio domain;low density parity check codes;numerical simulations;piece-wise linear algorithm;polar code decoding;reduced complexity SC decoding algorithm;reduced-complexity successive-cancellation decoding algorithm;Algorithm design and analysis;Approximation algorithms;Bit error rate;Complexity theory;Decoding;Parity check codes;Signal processing algorithms;Piecewise-Linear Functions;Polar codes;Reduced-Complexity Decoding;Successive-Cancelation Algorithm},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{xiolin_15,
+  Title                    = {{E}fficient approximate {ML} decoding units for polar list decoders},
+  Author                   = {Chenrong Xiong and Jun Lin and Zhiyuan Yan},
+  Booktitle                = {Signal Processing Systems (SiPS), 2015 IEEE Workshop on},
+  Year                     = {2015},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/SiPS.2015.7344981},
+  Keywords                 = {approximation theory;channel coding;forward error correction;maximum likelihood decoding;AML decoding unit;ML decoding units;SCL decoders;additive white Gaussian noise channel;approximate ML decoding units;binary erasure channel;decoding unit;forward error correction codes;frozen bits;maximum likelihood;polar codes;polar list decoders;successive cancellation list;AWGN channels;Computational complexity;Maximum likelihood decoding;Probability;Throughput;Error control codes;ML decoding;polar codes;successive cancellation list decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{xiolin_14,
+  Title                    = {{S}ymbol-based successive cancellation list decoder for polar codes},
+  Author                   = {Chenrong Xiong and Jun Lin and Zhiyuan Yan},
+  Booktitle                = {Signal Processing Systems (SiPS), 2014 IEEE Workshop on},
+  Year                     = {2014},
+  Month                    = {Oct},
+  Pages                    = {1-6},
+
+  Doi                      = {10.1109/SiPS.2014.6986086},
+  Keywords                 = {channel capacity;channel coding;decoding;SC list decoding algorithm;bit-based decoding algorithm;channel capacity;generalized symbol-based successive cancellation;polar codes;symbol-based channel transition probability;symbol-based polar decoding;symbol-based recursive channel combination;symbol-based successive cancellation list decoder;two-stage list pruning network;Complexity theory;Detectors;Maximum likelihood decoding;Probability;Sorting;Vectors;Error control codes;list decoding;polar codes;successive cancellation decoding},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{xuniu_15,
+  Title                    = {{O}vercoming the challenges of crossbar resistive memory architectures},
+  Author                   = {C. Xu and D. Niu and N. Muralimanohar and R. Balasubramonian and T. Zhang and S. Yu and Y. Xie},
+  Booktitle                = {2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)},
+  Year                     = {2015},
+  Month                    = {Feb},
+  Pages                    = {476-488},
+
+  Doi                      = {10.1109/HPCA.2015.7056056},
+  ISSN                     = {1530-0897},
+  Keywords                 = {memory architecture;phase change memories;resistive RAM;crossbar resistive memory architecture;DRAM;power consumption;high aspect ratio capacitor;phase change memory;PCM;spin-transfer torque RAM;STT-RAM;resistive RAM;ReRAM-based memory system;peripheral circuit;write voltage;switching latency;voltage drop;microarchitectural enhancement;double-sided ground biasing;multiphase reset operation;compression based data encoding scheme;Arrays;Random access memory;Phase change materials;Switches;Resistance;Transistors}
+}
+
+@Article{xukim_16,
+  Title                    = {{A}pproximate {C}omputing: {A} {S}urvey},
+  Author                   = {Qiang Xu and Nam Sung Kim and Mytkowicz, T.},
+  Journal                  = {IEEE Design \& Test},
+  Year                     = {2016},
+
+  Month                    = feb,
+  Number                   = {1},
+  Pages                    = {8-22},
+  Volume                   = {33},
+
+  Abstract                 = {As one of the most promising energy-efficient computing paradigms, approximate computing has gained a lot of research attention in the past few years. This paper presents a survey of state-of-the-art work in all aspects of approximate computing and highlights future research challenges in this field.},
+  Doi                      = {10.1109/MDAT.2015.2505723},
+  ISSN                     = {2168-2356},
+  Owner                    = {CDS},
+  Timestamp                = {2016-02-16}
+}
+
+@Article{xu_96,
+  Title                    = {{A} modified {E}uclidean algorithm and the {VLSI} implementation},
+  Author                   = {Youshi Xu},
+  Journal                  = {Electrotechnical Conference, 1996. MELECON '96., 8th Mediterranean},
+  Year                     = {1996},
+
+  Month                    = may,
+  Pages                    = {1324-1327 vol.3},
+  Volume                   = {3},
+
+  Cds_grade                = {3},
+  Cds_read                 = {2008-07},
+  Date-added               = {2008-07-31 13:53:44 +0200},
+  Date-modified            = {2008-08-08 10:37:28 +0200},
+  Doi                      = {10.1109/MELCON.1996.551191},
+  File                     = {xu_96.pdf:xu_96.pdf:PDF},
+  Owner                    = {CdS},
+  Rating                   = {3},
+  Read                     = {Yes},
+  Timestamp                = {2008.12.10},
+  Url                      = {http://dx.doi.org/10.1109/MELCON.1996.551191}
+}
+
+@InProceedings{xulee_18,
+  Title                    = {{P}uppet: {E}nergy {E}fficient {T}ask {M}apping {F}or {S}torage-{L}ess and {C}onverter-{L}ess {S}olar-{P}owered {N}on-{V}olatile {S}ensor {N}odes},
+  Author                   = {Y. {Xu} and H. G. {Lee} and X. {Chen} and B. {Peng} and D. {Liu} and L. {Liang}},
+  Booktitle                = {2018 IEEE 36th International Conference on Computer Design (ICCD)},
+  Year                     = {2018},
+  Month                    = {Oct},
+  Pages                    = {226-233},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8615692},
+  Ccr_keywords             = {solarEH, PN, only simulation-based results, task finalization based on knowledge of solar input},
+  Ccr_relevance            = {medium},
+  Ccr_topic                = {ATC, PCP},
+  Doi                      = {10.1109/ICCD.2018.00042},
+  Keywords                 = {TCS},
+  Keywords_original        = {computerised instrumentation;energy conservation;energy harvesting;learning (artificial intelligence);quality of service;sensors;solar power;DMR reduction;deadline miss ratii reduction;reinforcement learning;quality of services;QoS;storage-less solar-powered nonvolatile sensor nodes;energy loss reduction;converterless solar-powered nonvolatile sensor nodes;energy source;energy utilization;energy harvesting;solar variations;energy buffers;solar powered sensor nodes;Puppet;energy efficient task mapping strategy;Task analysis;Quality of service;Power demand;Resource management;Computer architecture;Energy harvesting;Processor scheduling;Energy Harvesting, Storage-less and Converter-less, Task Scheduling, Task Allocation, Reinforcement Learning},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-27}
+}
+
+@InProceedings{xuewie_10,
+  Title                    = {{I}mplementation of an {SDFG} based parallel depth-first complex sphere decoding algorithm},
+  Author                   = {Wenyao Xue and Wiegand, T. and Paul, S.},
+  Booktitle                = {Smart Antennas (WSA), 2010 International ITG Workshop on},
+  Year                     = {2010},
+  Month                    = {feb.},
+  Pages                    = {213 -217},
+
+  Doi                      = {10.1109/WSA.2010.5456449},
+  Keywords                 = {Bit error rate;Communication standards;Equations;Iterative algorithms;Iterative decoding;MIMO;Maximum likelihood decoding;Maximum likelihood detection;Mobile communication;Wireless communication;MIMO communication;iterative decoding;tree searching;SDFG;complex transmit symbols;iterative tree search algorithms;multiple input multiple output transmission;orthogonality;parallel depth-first complex sphere decoding algorithm;square root and division free givens rotation algorithm;wireless communications systems;QR-decomposition;SDFG;Sphere decoder;complex;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.01.17}
+}
+
+@Article{yanwei_16,
+  Title                    = {{S}uppression of {R}ow {H}ammer {E}ffect by {D}oping {P}rofile {M}odification in {S}addle-{F}in {A}rray {D}evices for {S}ub-30-nm {DRAM} {T}echnology},
+  Author                   = {C. M. Yang and C. K. Wei and Y. J. Chang and T. C. Wu and H. P. Chen and C. S. Lai},
+  Journal                  = {IEEE Transactions on Device and Materials Reliability},
+  Year                     = {2016},
+
+  Month                    = {Dec},
+  Number                   = {4},
+  Pages                    = {685-687},
+  Volume                   = {16},
+
+  Doi                      = {10.1109/TDMR.2016.2607174},
+  ISSN                     = {1530-4388},
+  Keywords                 = {DRAM chips;doping profiles;integrated circuit reliability;isolation technology;phosphorus;DRAM technology;access device;array device;buried word lines;channel leaking;doping profile modification;dosage modification;dynamic random-access memory;electric field;energy adjustment;fabrication process optimization;gate-induced electron;isolation spacing;localized shielding effect;phosphorus implantation;reliability issue;row hammer effect suppression;saddle-fin array device;Doping profiles;Junctions;Logic gates;Materials reliability;Random access memory;Resistance;Transistors;DRAM;Row hammer;implantation},
+  Owner                    = {MJ},
+  Timestamp                = {2018-05-03}
+}
+
+@InProceedings{yanlee_14,
+  Title                    = {{A}rea-efficient {TFM}-based stochastic decoder design for non-binary {LDPC} codes},
+  Author                   = {Chih-Wen Yang and Xin-Ru Lee and Chih-Lung Chen and Hsie-Chia Chang and Chen-Yi Lee},
+  Booktitle                = {Circuits and Systems (ISCAS), 2014 IEEE International Symposium on},
+  Year                     = {2014},
+  Pages                    = {409--412},
+
+  Doi                      = {10.1109/ISCAS.2014.6865152},
+  Owner                    = {PS},
+  Timestamp                = {2014.10.07},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6865152}
+}
+
+@InProceedings{yanwan_09,
+  Title                    = {{A} {M}emory {R}eduction {M}onte {C}arlo {S}imulation for {P}ricing {M}ulti-assets {A}merican {O}ptions},
+  Author                   = {Haijun Yang and Cui Wang},
+  Booktitle                = {Proceedings of the 2009 WRI World Congress on Computer Science and Information Engineering},
+  Year                     = {2009},
+  Pages                    = {312 - 316},
+  Volume                   = {2},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.03.25}
+}
+
+@InProceedings{yanzha_15,
+  Title                    = {{L}ow-complexity adaptive successive cancellation list polar decoder based on relaxed sorting},
+  Author                   = {Junmei Yang and Chuan Zhang and Shugong Xu and Xiaohu You},
+  Booktitle                = {Wireless Communications Signal Processing (WCSP), 2015 International Conference on},
+  Year                     = {2015},
+  Month                    = {Oct},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/WCSP.2015.7341298},
+  Keywords                 = {adaptive codes;computational complexity;decoding;numerical analysis;RS approach;TMPC;adaptive SCL polar decoder;computational complexity;low-complexity adaptive successive cancellation list polar decoder;numerical simulation;relaxed sorting approach;trade-off metric performance and complexity;Bit error rate;Computational complexity;Decoding;Degradation;Measurement;Sorting;Polar codes;low-complexity;relaxed sorting (RS);scaling factor;successive cancellation list (SCL) decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{yanshe_05,
+  Title                    = {{An FPGA implementation of low-density parity-check code decoder with multi-rate capability}},
+  Author                   = {L. Yang and M. Shen and H. Liu and C. Shi},
+  Booktitle                = {Proc. IEEE Asia and South Pacific Design Automation Conference 2005 (ASP-DAC)},
+  Year                     = {2005},
+
+  Address                  = {Yokohama, Japan},
+  Month                    = jan,
+  Pages                    = {760--763},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{yanrya_04,
+  Title                    = {{Design of Efficiently Encodable Moderate-Length High-Rate Irregular LDPC Codes}},
+  Author                   = {M. Yang and Ryan, W. E. and Y. Li},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2004},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {564--571},
+  Volume                   = {52},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{shekhu_11,
+  Title                    = {{R}eliable {S}tate {R}etention-{B}ased {E}mbedded {P}rocessors {T}hrough {M}onitoring and {R}ecovery},
+  Author                   = {Sheng Yang and Syed Saqib Khursheed and Bashir Al-Hashimi and David Flynn and Sachin Idgunji},
+  Journal                  = {IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS},
+  Year                     = {2011},
+
+  Month                    = {August},
+
+  Abstract                 = {State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software respectively. To validate the methodology, ARM Cortex-M0 embedded microprocessor (provided by our industrial project partner) is implemented in FPGA and further synthesized using 65-nm technology to quantify the cost in terms of area, latency and energy. It is shown that the proposed methodology has a small area overhead (8.6\%) with less than 4\% worst-case increase in critical path and is capable of detecting and correcting both single bit and multi bit errors for a wide range of fault rates.},
+  Cb_grade                 = {- gelesen 22/10/19
+- Reliability
+- Empfehlung Norbert
+- Reliability for Power Gating
+- Hamming Code for Protection
+- http://eprints.ecs.soton.ac.uk/22714/},
+  File                     = {shekhu_11.pdf:shekhu_11.pdf:PDF},
+  Owner                    = {Brehm},
+  Publisher                = {IEEE},
+  Timestamp                = {2011.10.19},
+  Url                      = {http://eprints.ecs.soton.ac.uk/22714/}
+}
+
+@InProceedings{yanqia_05,
+  Title                    = {{A} new {HW}/{SW} co-design methodology to generate a system level platform based on {LISA}},
+  Author                   = {Shao Yang and Yu Qian and Zhang Tie-Jun and Shan Rui and Hou Chao-Huan},
+  Booktitle                = {Proc. 6th Int. Conf. On ASIC ASICON 2005},
+  Year                     = {2005},
+  Pages                    = {163--167},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ICASIC.2005.1611288},
+  File                     = {yanqia_05.pdf:yanqia_05.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2010.09.28}
+}
+
+@Article{yanlia_11,
+  Title                    = {{T}he {T}ian{H}e-1{A} {S}upercomputer: {I}ts {H}ardware and {S}oftware},
+  Author                   = {Yang, Xue-Jun and Liao, Xiang-Ke and Lu, Kai and Hu, Qing-Feng and Song, Jun-Qiang and Su, Jin-Shu},
+  Journal                  = {Journal of Computer Science and Technology},
+  Year                     = {2011},
+  Number                   = {3},
+  Pages                    = {344-351},
+  Volume                   = {26},
+
+  Doi                      = {10.1007/s02011-011-1137-8},
+  ISSN                     = {1000-9000},
+  Keywords                 = {TianHe-1A supercomputer; hybrid architecture; Kylin operating system; power computing},
+  Language                 = {English},
+  Owner                    = {Brugger},
+  Publisher                = {Springer US},
+  Timestamp                = {2014.06.15},
+  Url                      = {http://dx.doi.org/10.1007/s02011-011-1137-8}
+}
+
+@InProceedings{yanjia_09,
+  Title                    = {{A}n investigation in iterative decoding of {R}eed-{S}olomon codes based on adaptive belief propagation},
+  Author                   = {Yushan Yang and Ming Jiang and Xiaofu Wu},
+  Booktitle                = {Proc. Int. Conf. Wireless Communications \& Signal Processing WCSP 2009},
+  Year                     = {2009},
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/WCSP.2009.5371418},
+  File                     = {yanjia_09.pdf:yanjia_09.pdf:PDF},
+  Keywords                 = {ABP, Reed-Solomon},
+  Owner                    = {Scholl},
+  Review                   = {ABP mit anschließendem Chase Algorithmus},
+  Timestamp                = {2011.06.21}
+}
+
+@InProceedings{yanmou_00,
+  Title                    = {{C}rosstalk in {D}eep {S}ubmicron {DRAM}s},
+  Author                   = {Yang, Zemo and Mourad, Samiha},
+  Year                     = {2000},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-21}
+}
+
+@InProceedings{yaodem_94,
+  Title                    = {{A Scheduling Model for Reduced CPU Energy}},
+  Author                   = {F. Yao and A. Demers and S. Shenker},
+  Booktitle                = {IEEE Annual foundations of computer science},
+  Year                     = {1994},
+  Pages                    = {374--382},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{yasohb_17,
+  Title                    = {{A} cross point {C}u-{R}e{RAM} with a novel {OTS} selector for storage class memory applications},
+  Author                   = {S. Yasuda and K. Ohba and T. Mizuguchi and H. Sei and M. Shimuta and K. Aratani and T. Shiimoto and T. Yamamoto and T. Sone and S. Nonoguchi and J. Okuno and A. Kouchiyama and W. Otsuka and K. Tsutsui},
+  Booktitle                = {2017 Symposium on VLSI Technology},
+  Year                     = {2017},
+  Month                    = {June},
+  Pages                    = {T30-T31},
+
+  Doi                      = {10.23919/VLSIT.2017.7998189},
+  ISSN                     = {2158-9682},
+  Keywords                 = {copper;leakage currents;resistive RAM;cross point copper-ReRAM;OTS selector;storage class memory applications;resistive random access memory;SCM applications;program endurance;tight resistance distributions;barrier layer;ovonic threshold switch;cross point arrays;leakage current;threshold voltage variability;boron;carbon;time 100 ns;Cu;Electrodes;Switches;Leakage currents;Very large scale integration;Threshold voltage;Transistors;Resistance},
+  Timestamp                = {2018-08-29}
+}
+
+@Article{yazthw_16,
+  Title                    = {{M}itigating the {M}emory {B}ottleneck {W}ith {A}pproximate {L}oad {V}alue {P}rediction},
+  Author                   = {Yazdanbakhsh, A. and Thwaites,B. and Esmaeilzadeh, H. and Pekhimenko, G. and Mutlu, O. and Mowry, T. C.},
+  Journal                  = {IEEE Design \& Test},
+  Year                     = {2016},
+
+  Month                    = {February},
+  Number                   = {1},
+  Pages                    = {32-42},
+  Volume                   = {33},
+
+  Owner                    = {MJ},
+  Timestamp                = {2016-04-05}
+}
+
+@Article{yazhua_12,
+  Title                    = {{O}ptimal {D}esign of a {G}allager {B} {N}oisy {D}ecoder for {I}rregular {LDPC} {C}odes},
+  Author                   = {Yazdi, S.M.S.T. and Chu-Hsiang Huang and Dolecek, L.},
+  Journal                  = {Communications Letters, IEEE},
+  Year                     = {2012},
+  Number                   = {12},
+  Pages                    = {2052-2055},
+  Volume                   = {16},
+
+  Doi                      = {10.1109/LCOMM.2012.101712.121953},
+  ISSN                     = {1089-7798},
+  Keywords                 = {error statistics;optimisation;parity check codes;resource allocation;BER;Gallager B noisy decoder;bit error rate;irregular LDPC codes;low-density parity-check codes;optimal design;optimal resource allocation;optimization problem;processing errors;transmission noise;uninformed resource assignment;Bit error rate;Decoding;Hardware;Noise measurement;Parity check codes;Program processors;Gallager B algorithm;LDPC decoder;density evolution;irregular codes;noisy hardware},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.06.11}
+}
+
+@InProceedings{yeben_02,
+  Title                    = {{Analysis of Power Consumption on Switch Fabrics in Network Routers}},
+  Author                   = {T. T. Ye and L. Benini and De Micheli, G.},
+  Booktitle                = {Proc. 2002 Design Automation Conference (DAC '02)},
+  Year                     = {2002},
+
+  Address                  = {New Orleans, USA},
+  Month                    = jun,
+  Pages                    = {524--529},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{yemic_03,
+  Title                    = {{Packetized On-Chip Interconnect Communication Anaysis in MPSoC}},
+  Author                   = {T. T. Ye and De Micheli, G. and L. Benini},
+  Booktitle                = {Proc. 2003 Design, Automation and Test in Europe (DATE '03)},
+  Year                     = {2003},
+
+  Address                  = {Munich, Germany},
+  Month                    = mar,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{yedche_02,
+  Title                    = {{G}enerating code representations suitable for belief propagation decoding},
+  Author                   = {Yedidia, Jonathan S and Chen, Jinghu and Fossorier, Marc PC},
+  Booktitle                = {PROCEEDINGS OF THE ANNUAL ALLERTON CONFERENCE ON COMMUNICATION CONTROL AND COMPUTING},
+  Year                     = {2002},
+  Number                   = {1},
+  Pages                    = {447--456},
+  Volume                   = {40},
+
+  Owner                    = {kraft},
+  Timestamp                = {2018.05.31}
+}
+
+@InProceedings{yee_05,
+  Title                    = {{M}ax-log-{MAP} sphere decoder},
+  Author                   = {Mong Suan Yee},
+  Booktitle                = {Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on},
+  Year                     = {2005},
+  Pages                    = {iii/1013-iii/1016 Vol. 3},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/ICASSP.2005.1415884},
+  File                     = {yee_05.pdf:yee_05.pdf:PDF},
+  ISSN                     = {1520-6149},
+  Keywords                 = {channel coding;computational complexity;error statistics;maximum likelihood decoding;maximum likelihood detection;radio receivers;BER;channel coding;complexity reduction;max-log-MAP detector;multiple antenna systems;sphere decoder;wireless communication receiver design;AWGN;Algorithm design and analysis;Constellation diagram;Detectors;Europe;MIMO;Maximum likelihood decoding;Maximum likelihood detection;Maximum likelihood estimation;Quadrature amplitude modulation},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.02}
+}
+
+@Article{yehree_84,
+  Title                    = {{S}ystolic {M}ultipliers for {F}inite {F}ields {GF}(2m)},
+  Author                   = {C.-S. Yeh and Irvine S. Reed and Truong, T. K.},
+  Journal                  = {Computers, IEEE Transactions on},
+  Year                     = {1984},
+
+  Month                    = apr,
+  Number                   = {4},
+  Pages                    = {357-360},
+  Volume                   = {C-33},
+
+  Abstract                 = {Two systolic architectures are developed for performing the product�sum computation AB + C in the finite field GF(2m) of 2melements, where A, B, and C are arbitrary elements of GF(2m). The first multiplier is a serial-in, serial-out one-dimensional systolic array, while the second multiplier is a parallel-in, parallel-out two-dimensional systolic array. The first multiplier requires a smaller number of basic cells than the second multiplier. The second multiplier heeds less average time per computation than the first multiplier if a number of computations are performed consecutively. To perform single computations both multipliers require the same computational time. In both cases the architectures are simple and regular and possess the properties of concurrency and modularity. As a consequence they are well suited for use in VLSI systems.},
+  Cds_grade                = {0},
+  Cds_keywords             = {VLSI, galois field multiplier, FFM, lFinite field, logic design, primitive element, systolic array},
+  Cds_review               = {VLSI implementation for AB + C operation of GF(2^m)},
+  Doi                      = {10.1109/TC.1984.1676441},
+  File                     = {yehree_84.pdf:yehree_84.pdf:PDF},
+  ISSN                     = {0018-9340},
+  Owner                    = {CdS},
+  Timestamp                = {2009.03.17}
+}
+
+@Article{yeoana_03,
+  Title                    = {{Iterative decoder architectures}},
+  Author                   = {E. Yeo and V. Anantharam},
+  Journal                  = {IEEE Communications Magazine},
+  Year                     = {2003},
+
+  Month                    = aug,
+  Pages                    = {132--140},
+  Volume                   = {41},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{yeoaug_03,
+  Title                    = {{A 500-Mb/s Soft-Output Viterbi Decoder}},
+  Author                   = {E. Yeo and S. A. Augsburger and Davis, W. R. and B. Nikolic},
+  Journal                  = {IEEE Journal of Solid-State Circuits},
+  Year                     = {2003},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = {1234-1241},
+  Volume                   = {38},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{yeoaug_02,
+  Title                    = {{Implementation of High Throughput Soft Output Viterbi Decoders}},
+  Author                   = {E. Yeo and S. Augsburger and W. R. Davis and B. Nikoli\'c},
+  Booktitle                = {Proc. 2002 Workshop on Signal Processing Systems (SiPS '02)},
+  Year                     = {2002},
+
+  Address                  = {San Diego, California, USA},
+  Month                    = oct,
+  Pages                    = {146--151},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{yeonik_02,
+  Title                    = {{Architectures and Implementations of Low-Density Parity-Check Decoding Algorithms}},
+  Author                   = {E. Yeo and B. Nikolic and V. Anantharam},
+  Booktitle                = {Proc. IEEE International Midwest Symposium on Circuits and System},
+  Year                     = {2002},
+  Month                    = aug,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{yeopak_01,
+  Title                    = {{VLSI Architectures for Iterative Decoders in Magnetic Recording Channels}},
+  Author                   = {E. Yeo and P. Pakzad and B. Nikolic and V. Anantharam},
+  Journal                  = {IEEE Transactions on Magnetics},
+  Year                     = {2001},
+
+  Month                    = mar,
+  Number                   = {2},
+  Pages                    = {748--755},
+  Volume                   = {37},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{yeopak_01a,
+  Title                    = {{High Throughput Low-Density Parity-Check Decoder Architectures}},
+  Author                   = {E. Yeo and P. Pakzad and B. Nikolic and V. Anantharam},
+  Booktitle                = {Proc. 2001 Global Telecommunications Conference (GLOBECOM '01)},
+  Year                     = {2001},
+  Pages                    = {3019-3024},
+
+  File                     = {yeopak_01a.pdf:yeopak_01a.pdf:PDF},
+  Keywords                 = {staggered decoding},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{yeurab_95,
+  Title                    = {{A 210Mb/s Radix-4 Bit-level Pipelined Viterbi-Decoder}},
+  Author                   = {A. K. Yeung and J. M. Rabaey},
+  Booktitle                = {Proc. 1995 International Solid-State Circuits Conference (ISSCC '95)},
+  Year                     = {1995},
+
+  Address                  = {San Francisco, California, USA},
+  Month                    = feb,
+  Pages                    = {88--89},
+
+  File                     = {yeurab_95.pdf:yeurab_95.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{yinxue_12,
+  Title                    = {{B}ased on the top-hat algorithm of oral medical image information recognition and data processing},
+  Author                   = {Wang Yingli and Zhao Xueli and Wang Ming},
+  Booktitle                = {Measurement, Information and Control (MIC), 2012 International Conference on},
+  Year                     = {2012},
+  Month                    = {May},
+  Pages                    = {158-162},
+  Volume                   = {1},
+
+  Abstract                 = {This article mainly is the top-hat algorithm which is applied to medical image to gray image processing, according to different image, take different gray value, in order to achieve the different disease case image processing. Top-hat algorithm by changing in the gray scale value, enhances the different medical image of the contrast of gray scale images, which can be more accurately prominent oral required on site. Using top-hat algorithm for image processing more accurately, obviously and more conducive to the medicine to the diagnosis of oral disease.},
+  Cds_grade                = {3},
+  Cds_keywords             = {morphological filter, top-hat, medical image processing},
+  Cds_read                 = {2014-07-15},
+  Cds_review               = {algorithmic investigation + example images
+no hardware architecture
+no performance data},
+  Doi                      = {10.1109/MIC.2012.6273246},
+  File                     = {yinxue_12.pdf:yinxue_12.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.07.15}
+}
+
+@InProceedings{yookyu_03,
+  Title                    = {{A} 1.8 {V} 700 {M}b/s/pin 512 {M}b {DDR}-{II} {SDRAM} with on-die termination and off-chip driver calibration},
+  Author                   = {C. {Yoo} and K. {Kyung} and G. -. {Han} and K. {Lim} and H. {Lee} and J. {Chai} and N. -. {Heo} and G. {Byun} and D. -. {Lee} and H. -. {Choi} and H. -. {Choi} and C. -. {Kim} and S. {Cho}},
+  Booktitle                = {2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.},
+  Year                     = {2003},
+  Month                    = {Feb},
+  Pages                    = {312-496 vol.1},
+
+  Doi                      = {10.1109/ISSCC.2003.1234313},
+  ISSN                     = {0193-6530},
+  Keywords                 = {SRAM chips;CMOS memory circuits;calibration;high-speed integrated circuits;DDR-II SDRAM;on-die termination;off-chip driver calibration;JEDEC standard compliant;hierarchical I/O line sensing;local sensing;1.8 V;512 Mbit;700 Mbit/s;533 Mbit/s;SDRAM;Calibration;Driver circuits;Delay;Multiplexing;Switches;Prefetching;Random access memory;Low voltage;Bonding}
+}
+
+@Article{yoopar_15,
+  Title                    = {{P}artially {P}arallel {E}ncoder {A}rchitecture for {L}ong {P}olar {C}odes},
+  Author                   = {H. Yoo and I. C. Park},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2015},
+
+  Month                    = {March},
+  Number                   = {3},
+  Pages                    = {306-310},
+  Volume                   = {62},
+
+  Doi                      = {10.1109/TCSII.2014.2369131},
+  ISSN                     = {1549-7747},
+  Keywords                 = {error correction codes;parallel architectures;encoding process;error correcting codes;hardware complexity;long polar codes;partially parallel encoder architecture;very-large-scale integration implementation;Complexity theory;Computer architecture;Decoding;Delays;Encoding;Hardware;Registers;Polar codes;VLSI optimization;polar encoder;very-large-scale integration (VLSI) optimization},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{yoosan_13,
+  Title                    = {{T}owards simultaneous clustering and motif-modeling for a large number of protein family},
+  Author                   = {Young Joon Yoo and Sandhan, T. and Jinyoung Choi and Sun Kim},
+  Booktitle                = {Proceedings of the 2013 IEEE International Conference on Bioinformatics and Biomedicine (BIBM)},
+  Year                     = {2013},
+  Month                    = {Dec},
+  Pages                    = {22-28},
+
+  Abstract                 = {In this paper, we propose a novel clustering and motif modeling framework for analyzing large number of protein family using k-mer. Our approach of using k-mers utilizes both occurring frequency and position information of k-mers that essential for classification yet not fully used in previous methods. We found that the structure has close relationship between motif of protein family and hence well describe important biological features or motifs of each protein family. The classification/clustering procedure are executed in incremental manner which was difficult for previous algorithms and is modeled by using bipartite model. Furthermore, the method can be efficiently implemented using parallel computing and hash. Experimental results using the entire COG family database shows that our model can model a large number of protein families without sacrificing accuracy. In addition, the classification structure, path of the graph for protein sequences, explains characteristic subsequences or motif of each family quite well. Thus the proposed method has the potential to model both protein families and motifs, even for a large number of families.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/BIBM.2013.6732605},
+  File                     = {yoosan_13.pdf:yoosan_13.pdf:PDF},
+  Keywords                 = {graphs},
+  Owner                    = {CdS},
+  Timestamp                = {2014.11.28}
+}
+
+@InProceedings{youbla_12,
+  Title                    = {{A} 1.6\mbox{-}{mm}\textsuperscript{2} 38\mbox{-}{mW} 1.5\mbox{-}{Gb}/s {LDPC} decoder enabled by refresh-free embedded {DRAM}},
+  Author                   = {Youn Sung Park, MI and Blaauw, D. and Sylvester, D. and Zhengya Zhang},
+  Booktitle                = {VLSI Circuits (VLSIC), 2012 Symposium on},
+  Year                     = {2012},
+  Pages                    = {114--115},
+
+  Doi                      = {10.1109/VLSIC.2012.6243816},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.07.22},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6243816}
+}
+
+@Article{you_15,
+  Title                    = {{T}elecom {E}xperts {P}lot a {P}ath to 5{G}},
+  Author                   = {Young, L.},
+  Journal                  = {IEEE Spectrum Magazine},
+  Year                     = {2015},
+
+  Month                    = {October},
+
+  Owner                    = {scholl},
+  Timestamp                = {2016.04.26}
+}
+
+@InProceedings{yuche_18,
+  Title                    = {{A} {B}atteryless and {S}ingle-{I}nductor {DC}-{DC} {B}oost {C}onverter for {T}hermoelectric {E}nergy {H}arvesting {A}pplication with 190m{V} {C}old-{S}tart {V}oltage},
+  Author                   = {H. {Yu} and M. {Chen} and C. {Wu} and K. {Tang} and G. {Wang}},
+  Booktitle                = {2018 IEEE International Symposium on Circuits and Systems (ISCAS)},
+  Year                     = {2018},
+  Month                    = {May},
+  Pages                    = {1-4},
+
+  Ccr_flags                = {unread},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {8351428},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {todo},
+  Doi                      = {10.1109/ISCAS.2018.8351428},
+  Keywords                 = {TCS},
+  Keywords_original        = {CMOS integrated circuits;energy harvesting;maximum power point trackers;power inductors;switching convertors;thermoelectric conversion;zero current switching;thermoelectric energy harvesting;cold-start voltage;CMOS process;maximum power point tracking;single-inductor DC-DC boost converter;stepping-up architecture;zero-current switching;off-chip inductor;inductor sharing;batteryless DC-DC boost converter;voltage 190.0 mV;size 0.18 mum;voltage 50.0 mV;voltage 1 V to 1.6 V;efficiency 60 percent;Energy harvesting;Zero current switching;Inductors;Maximum power point trackers;Semiconductor device measurement;Switches;Clocks;DC-DC converter;boost converter;single inductor;thermoelectric energy harvesting;stepping-up;cold-start;zero-current switching (ZCS);maximum power point tracking (MPPT)},
+  Owner                    = {CCR}
+}
+
+@InProceedings{yugol_17,
+  Title                    = {{E}fficient {C}onvex {O}ptimization on {GPU}s for {E}mbedded {M}odel {P}redictive {C}ontrol},
+  Author                   = {Yu, Leiming and Goldsmith, Abraham and Di Cairano, Stefano},
+  Booktitle                = {Proceedings of the General Purpose {GPU}s},
+  Year                     = {2017},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {12--21},
+  Publisher                = {ACM},
+  Series                   = {GP{GPU}-10},
+
+  Acmid                    = {3038234},
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{GPU} PLATFORM; cite number in presentation [24]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1145/3038228.3038234},
+  ISBN                     = {978-1-4503-4915-4},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {Convex Optimization, {GPU}, Model Predictive Control, Tegra X1},
+  Location                 = {Austin, TX, USA},
+  Numpages                 = {10},
+  Owner                    = {CCR},
+  Url                      = {http://doi.acm.org/10.1145/3038228.3038234}
+}
+
+@InProceedings{yuber_12,
+  Title                    = {{A} complexity adaptive channel estimator for low power},
+  Author                   = {Zhibin Yu and van Berkel, C.H. and Hong Li},
+  Booktitle                = {Design, Automation Test in Europe Conference Exhibition (DATE), 2012},
+  Year                     = {2012},
+  Month                    = {march},
+  Pages                    = {1531 -1536},
+
+  ISSN                     = {1530-1591},
+  Keywords                 = {CMMB standard;China mobile multimedia broadcasting;DVFS;OFDM demodulator;SDR;SDR demodulator;SNR;channel estimation;complexity adaptive channel estimator;complexity scalable algorithm;dynamical voltage and frequency scaling;fast- fading channels;low-power design methodology;mean square error;processor architectures;signal noise ratio;software-defined radio;OFDM modulation;channel estimation;demodulators;digital multimedia broadcasting;fading channels;mean square error methods;mobile radio;software radio;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2012.11.21}
+}
+
+@Article{yuapar_14,
+  Title                    = {{L}ow-{L}atency {S}uccessive-{C}ancellation {P}olar {D}ecoder {A}rchitectures {U}sing 2-{B}it {D}ecoding},
+  Author                   = {Bo Yuan and K. Parhi},
+  Journal                  = {IEEE Transactions on Circuits and Systems I: Regular Papers},
+  Year                     = {2014},
+
+  Month                    = {April},
+  Number                   = {4},
+  Pages                    = {1241-1254},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCSI.2013.2283779},
+  ISSN                     = {1549-8328},
+  Keywords                 = {decoding;2 bit decoding;SC algorithm;hardware complexity;hardware design;hardware efficiency;least-latency SC decoder;low latency successive cancellation polar decoder architectures;successive cancellation;Algorithm design and analysis;Complexity theory;Computer architecture;Decoding;Encoding;Equations;Hardware;2-bit decoder;Look-ahead;overlapped scheduling;polar codes;precomputation;successive cancellation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Article{yuapar_15,
+  Title                    = {{L}ow-{L}atency {S}uccessive-{C}ancellation {L}ist {D}ecoders for {P}olar {C}odes {W}ith {M}ultibit {D}ecision},
+  Author                   = {Bo Yuan and K. K. Parhi},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2015},
+
+  Month                    = {Oct},
+  Number                   = {10},
+  Pages                    = {2268-2280},
+  Volume                   = {23},
+
+  Doi                      = {10.1109/TVLSI.2014.2359793},
+  ISSN                     = {1063-8210},
+  Keywords                 = {VLSI;decoding;error correction codes;parity check codes;turbo codes;2-bit reformulated SCL algorithm;2b-rSCL algorithm;2b-rSCL decoders;2n-2 clock cycles;3n-2 clock cycles;4b-rSCL decoders;SC list decoding algorithm;SCL decoder design;capacity-achieving error-correcting codes;error-correcting performance improvement;intermediate decoding;latency reduction;long-latency bottleneck;low-density parity-check codes;low-latency successive-cancellation list decoders;multibit decision;polar codes;successive-cancellation algorithm;turbo codes;very large-scale integration architectures;Algorithm design and analysis;Clocks;Computer architecture;Decoding;Sorting;Very large scale integration;Algorithm reformulation;list decoding;multibit decision;polar codes;successive cancellation (SC);successive cancellation (SC).},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{yuapar_14a,
+  Title                    = {{A}lgorithm and architecture for hybrid decoding of polar codes},
+  Author                   = {B. Yuan and K. K. Parhi},
+  Booktitle                = {Signals, Systems and Computers, 2014 48th Asilomar Conference on},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {2050-2053},
+
+  Doi                      = {10.1109/ACSSC.2014.7094833},
+  Keywords                 = {computational complexity;error correction codes;forward error correction;iterative decoding;BP decoding algorithm;SC decoding algorithm;SNR region;belief propagation decoding algorithm;capacity-achieving FEC codes;capacity-achieving forward error correction codes;decoding gain;decoding latency;early-stopping criteria;error-correcting performance problem;gain 0.2 dB;hybrid BP-SC decoding scheme;iteration number;low-complexity unified hardware architecture;polar codes;successive cancellation decoding algorithm;Decision support systems;belief propagation;hybrid;polar codes;successive cancellation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{yuapar_13,
+  Title                    = {{A}rchitecture optimizations for {BP} polar decoders},
+  Author                   = {B. Yuan and K. K. Parhi},
+  Booktitle                = {Acoustics, Speech and Signal Processing (ICASSP), 2013 IEEE International Conference on},
+  Year                     = {2013},
+  Month                    = {May},
+  Pages                    = {2654-2658},
+
+  Doi                      = {10.1109/ICASSP.2013.6638137},
+  ISSN                     = {1520-6149},
+  Keywords                 = {codecs;decoding;optimisation;BP polar decoders;MS decoder;SMS algorithm;SMS design;architecture optimizations;belief propagation-based architectures;capacity-achieving property;channel codes;decoding performance;efficient critical path reduction approach;hardware architectures;hardware efficiency;hardware performance;low-complexity polar decoding;min-sum approximated BP algorithm;scaled MS algorithm;successive cancellation algorithm;Adders;Algorithm design and analysis;Approximation algorithms;Computer architecture;Decoding;Hardware;Iterative decoding;Polar codes;VLSI;belief propagation;critical path reduction;scaled min-sum},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@Misc{yuaaam_09,
+  Title                    = {{A} {H}ybrid {A}nalytical {DRAM} {P}erformance {M}odel},
+
+  Author                   = {Yuan, George L. and Aamodt, Tor M.},
+  Year                     = {2009},
+
+  Owner                    = {MJ},
+  Timestamp                = {2019-09-11}
+}
+
+@InProceedings{yuamah_06,
+  Title                    = {{Design and Implementation of Turbo Decoders for Software Defined Radio}},
+  Author                   = {Yuan, Lin and Scott Mahlke and Trevor, Mudge and Chaitali, Chakrabarti and Alastair, Reid and Krisztian, Flautner},
+  Booktitle                = {Proc. IEEE 2006 Workshop on Signal Processing Systems (SiPS)},
+  Year                     = {2006},
+
+  File                     = {yuamah_06.pdf:yuamah_06.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.13}
+}
+
+@Misc{yua_16,
+  Title                    = {{S}hort {P}olar {C}odes},
+
+  Author                   = {Peihong Yuan},
+  HowPublished             = {LNT \& DLR Summer Workshop on Coding},
+  Month                    = {July},
+  Year                     = {2016},
+
+  File                     = {:yua_16.pdf:PDF},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-31},
+  Url                      = {https://www.lnt.ei.tum.de/fileadmin/staff/boecherer/ldc2015/ldc2016_yuan.pdf}
+}
+
+@InProceedings{yunyao_13,
+  Title                    = {{M}em{G}uard: {M}emory bandwidth reservation system for efficient performance isolation in multi-core platforms},
+  Author                   = {H. Yun and G. Yao and R. Pellizzoni and M. Caccamo and L. Sha},
+  Booktitle                = {2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)},
+  Year                     = {2013},
+  Month                    = {April},
+  Pages                    = {55-64},
+
+  Doi                      = {10.1109/RTAS.2013.6531079},
+  ISSN                     = {1080-1812},
+  Keywords                 = {multiprocessing systems;storage management;MemGuard;SPEC2006 benchmark;best effort memory bandwidth;guaranteed memory bandwidth;memory bandwidth reservation system;memory performance isolation;multicore platform;temporal isolation;Bandwidth;Benchmark testing;Multicore processing;Random access memory;Real-time systems;Regulators;Throughput},
+  Owner                    = {MJ},
+  Timestamp                = {2018-04-29}
+}
+
+@InProceedings{Yun2008,
+  Title                    = {{D}ata-aided {A}lgorithm {B}ased {F}requency {S}ynchronizer for {DVB}-{S}2},
+  Author                   = {Yun, Hyoung Jin and Park, Jang Woong and Park, Jang Woong and Sunwoo, Myung Hoon},
+  Booktitle                = {Proceedings of the 2nd International Conference on Ubiquitous Information Management and Communication},
+  Year                     = {2008},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {354--358},
+  Publisher                = {ACM},
+  Series                   = {ICUIMC '08},
+
+  Acmid                    = {1352867},
+  Doi                      = {10.1145/1352793.1352867},
+  ISBN                     = {978-1-59593-993-7},
+  Keywords                 = {coarse frequency synchronizer, data-aided (DA) algorithm, digital video broadcasting-satellite second generation (DVBS2), initial frequency synchronizer},
+  Location                 = {Suwon, Korea},
+  Numpages                 = {5},
+  Owner                    = {ali},
+  Timestamp                = {2015.03.26},
+  Url                      = {http://doi.acm.org/10.1145/1352793.1352867}
+}
+
+@InProceedings{zahhol_95,
+  Title                    = {{Advanced Method for Industry Related Education with and FPGA Design Self-Learning Kit}},
+  Author                   = {U. Zahm and T. Hollstein and H.-J. Herpel and N. Wehn and M. Glesner},
+  Booktitle                = {Field Programmable Logic and Applications},
+  Year                     = {1995},
+  Month                    = aug,
+  Number                   = {975},
+  Pages                    = {241--250},
+  Publisher                = {Springer Verlag},
+  Series                   = {Lecture Notes in Computer Science},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{Zakharov2001,
+  Title                    = {{DFT}-based frequency estimators with narrow acquisition range},
+  Author                   = {Zakharov, Y.V. and Baronkin, V.M. and Tozer, T.C.},
+  Journal                  = {IEE Proceedings Communications},
+  Year                     = {2001},
+
+  Month                    = {Feb},
+  Number                   = {1},
+  Pages                    = {1-7},
+  Volume                   = {148},
+
+  Doi                      = {10.1049/ip-com:20010060},
+  ISSN                     = {1350-2425},
+  Keywords                 = {AWGN;discrete Fourier transforms;frequency estimation;interpolation;signal processing;spectral analysis;AWGN channel;DFT-based frequency estimators;MLE;accuracy performance;coarse search;communication signal;computational load reduction;dichotomous search;discrete Fourier transform;fine search;frequency offset;input signal;maximum likelihood estimator;narrow acquisition range;narrow frequency acquisition range;parabolic interpolation;periodogram peak;signal processing;two-rate spectral estimation},
+  Owner                    = {ali},
+  Timestamp                = {2015.02.27}
+}
+
+@Article{zanjos_14,
+  Title                    = {{D}esign and {O}ptimization of {N}onvolatile {M}ultibit {1T1R} {R}esistive {RAM}},
+  Author                   = {M. {Zangeneh} and A. {Joshi}},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2014},
+
+  Month                    = {Aug},
+  Number                   = {8},
+  Pages                    = {1815-1828},
+  Volume                   = {22},
+
+  Ccr_flags                = {read, referenced},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {6595151},
+  Ccr_keywords             = {FRAM comparison},
+  Ccr_topic                = {ATC, todo},
+  Doi                      = {10.1109/TVLSI.2013.2277715},
+  ISSN                     = {1063-8210},
+  Keywords                 = {TCS},
+  Keywords_original        = {cellular arrays;circuit optimisation;energy consumption;hafnium compounds;integrated circuit design;logic design;memristors;random-access storage;titanium compounds;transistor circuits;optimization;memristor-based random access memory;nonvolatile multibit resistive RAM;flash memory;energy consumption;multibit one-transistor one-memristor cell;memory arrays;circuit-level performance;energy models;titanium dioxide;hafnium oxide;HSPICE simulations;performance-driven design approach;energy-optimized resistive RAM array;RRAM array;write energy;read energy;write access times;read access times;temperature variations;multibit RRAM cell;time 100 ns;time 1 ns;time 200 ns;TiO2;HfOx;Memristors;Computer architecture;Microprocessors;Hafnium compounds;Random access memory;Resistance;Nonvolatile memory;Memristor;modeling;reliability;resistive random access memory (RRAM).;Memristor;modeling;reliability;resistive random access memory (RRAM)},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-26}
+}
+
+@InProceedings{zarban_02,
+  Title                    = {{On implementation of min-sum algorithm for decoding low-density parity-check codes}},
+  Author                   = {F. Zarkeshvari and A. Banihashemi},
+  Booktitle                = {Proc. 2002 IEEE GLOBECOM},
+  Year                     = {2002},
+  Month                    = nov,
+  Pages                    = {1349-1353},
+  Volume                   = {2},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zemsam_06,
+  Title                    = {{C}rosstalk {I}nduced {F}ault {A}nalysis and {T}est in {DRAM}s},
+  Author                   = {Yang Zemo and Mourad Samisha},
+  Year                     = {2006},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-21}
+}
+
+@InProceedings{zerpop_05,
+  Title                    = {{IP}-block-based design environment for high-throughput {VLSI} dedicated digital signal processing systems},
+  Author                   = {Zergainoh, N. -E. and Popovici, K. and Jerraya, A. and Urard, P. },
+  Booktitle                = {Proc. Asia and South Pacific Design Automation Conference the ASP-DAC 2005},
+  Year                     = {2005},
+  Month                    = jan,
+  Pages                    = {612--618},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ASPDAC.2005.1466236},
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.01.27}
+}
+
+@Article{zhafai_03,
+  Title                    = {{T}echniques for early stopping and error detection in turbo decoding},
+  Author                   = {Fengqin Zhai and Fair, I. J.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2003},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {1617--1623},
+  Volume                   = {51},
+
+  Doi                      = {10.1109/TCOMM.2003.818099},
+  File                     = {zhafai_03.pdf:zhafai_03.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InProceedings{zhafai_01,
+  Title                    = {{Improved Performance of Error Detection in Turbo Decoding by Incorporating a Short CRC with the Mean-Sign-Change Criterion}},
+  Author                   = {F. Zhai and I. J. Fair},
+  Booktitle                = {Proc. 2001 IEEE International Symposium on Information Theory (ISIT '01)},
+  Year                     = {2001},
+
+  Address                  = {Washington DC, USA},
+  Month                    = jun,
+  Pages                    = {143},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhafai_00,
+  Title                    = {{New Error Detection Techniques and Stopping Criteria for Turbo Decoding}},
+  Author                   = {F. Zhai and I. J. Fair},
+  Booktitle                = {Proc. 2000 IEEE Canadian Conference on Electrical and Computer Engineering},
+  Year                     = {2000},
+
+  Address                  = {Halifax, Canada},
+  Month                    = mar,
+  Pages                    = {58--62},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhaars_06,
+  Title                    = {{An Efficient Decoder Scheme for Double Binary Circular Turbo Codes}},
+  Author                   = {C. Zhan and T. Arslan and A. T. Erdogan and S. MacDougall},
+  Booktitle                = {IEEE International Conference on Acoustics,Speech and Signal Processing (ICASSP)},
+  Year                     = {2006},
+
+  Owner                    = {vogt},
+  Timestamp                = {2007.03.26}
+}
+
+@InProceedings{zhaliu_10,
+  Title                    = {{D}esign and {I}mplementation of {A}rea-{E}fficient {DVB}-{S}2 {BCH} {D}ecoder},
+  Author                   = {Botao Zhang and Dongpei Liu and Shixian Wang and Xucan Chen and Hengzhu Liu},
+  Booktitle                = {Computer Engineering and Technology (ICCET), 2010 2nd International Conference on},
+  Year                     = {2010},
+  Month                    = apr,
+  Pages                    = {V3-179 -V3-184},
+  Volume                   = {3},
+
+  Abstract                 = {BCH code is adopted as a part of the Forward Error Correction subsystem of DVB-S2 system, which is the next generation digital video broadcast system based on satellite wireless communication system. As DVB-S2 system uses very long code length and multiple code modes, full compatible BCH decoder is high area cost. In order to reduce the area cost of the full compatible DVB-S2 BCH decoder, we have modified the VLSI implementation of Berlekamp Massey Algorithm for key equation solver which is the main part of BCH decoder, rebuilt the Galois Filed Multiplications including the constant Galois Field Multiplications and the general Galois Field Multiplications. In order to support all the code modes and Adaptive Coded Modulation, a novel duo-pipeline reconfigurable architecture have been proposed, which can support code mode switching without stalling the symbol stream. We have implemented the decoder with verilog HDL, and have evaluated it by FPGA platform and ASIC library. The results show that the logic area of the decoder is at least 13% fewer than other existing decoders.},
+  Cds_grade                = {0},
+  Cds_keywords             = {BCH, FPGA},
+  Doi                      = {10.1109/ICCET.2010.5485823},
+  File                     = {zhaliu_10.pdf:zhaliu_10.pdf:PDF},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2011.11.22}
+}
+
+@InProceedings{zhaliu_09,
+  Title                    = {{L}ow {C}omplexity {DVB}-{S}2 {LDPC} {D}ecoder},
+  Author                   = {Botao Zhang and Hengzhu Liu and Xucan Chen and Dongpei Liu and Xiaofei Yi},
+  Booktitle                = {Proc. IEEE 69th Vehicular Technology Conference VTC Spring 2009},
+  Year                     = {2009},
+  Month                    = apr,
+  Note                     = {Dieses Paper ist Schrott. Offset-MinSum als Check-Node und dadurch geringer Speicherverbrauch. Reicht aber sicher nicht für gute Performanz.},
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/VETECS.2009.5073653},
+  File                     = {zhaliu_09.pdf:zhaliu_09.pdf:PDF},
+  Grade                    = {--},
+  Owner                    = {Alles},
+  Timestamp                = {2009.08.20}
+}
+
+@TechReport{zhaoos_10,
+  Title                    = {{A}cceleration of {O}ption {P}ricing {T}echnique on {G}raphics {P}rocessing {U}nits},
+  Author                   = {Bowen Zhang and Cornelis. W. Oosterlee},
+  Institution              = {Delft University of Technology},
+  Year                     = {2010},
+  Month                    = feb,
+  Number                   = {10-03},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {GPU, Heston, multiple strike European options, COS method, Bermuda options},
+  Cds_read                 = {2012-03-05},
+  Cds_review               = {speedups between 10 and 100 for multiple strike European options},
+  File                     = {zhaoos_10.pdf:zhaoos_10.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {Delft University of Technology},
+  Timestamp                = {2011.01.06}
+}
+
+@Article{zhapar_14,
+  Title                    = {{L}atency {A}nalysis and {A}rchitecture {D}esign of {S}implified {SC} {P}olar {D}ecoders},
+  Author                   = {Chuan Zhang and K. Parhi},
+  Journal                  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
+  Year                     = {2014},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {115-119},
+  Volume                   = {61},
+
+  Doi                      = {10.1109/TCSII.2013.2291065},
+  ISSN                     = {1549-7747},
+  Keywords                 = {binary codes;decoding;tree codes;SSC decoding latency;architecture design;latency analysis;low-latency decoding;polar codes;precomputation;simplified SC polar decoders;simplified successive cancellation;specific code;Algorithm design and analysis;Clocks;Hardware;Maximum likelihood decoding;Schedules;Systematics;Binary tree;data-flow graph (DFG);polar codes;precomputation;simplified successive cancellation (SSC)},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{zhawan_14,
+  Title                    = {{E}fficient adaptive list successive cancellation decoder for polar codes},
+  Author                   = {C. Zhang and Z. Wang and X. You and B. Yuan},
+  Booktitle                = {Signals, Systems and Computers, 2014 48th Asilomar Conference on},
+  Year                     = {2014},
+  Month                    = {Nov},
+  Pages                    = {126-130},
+
+  Doi                      = {10.1109/ACSSC.2014.7094411},
+  Keywords                 = {adaptive decoding;computational complexity;linear codes;SC polar decoder;SNR;adaptive list successive cancellation decoder;computational complexity reduction;hardware architecture;polar code;Algorithm design and analysis;Computational complexity;Computer architecture;Hardware;Maximum likelihood decoding;adaptive list size;list decoding;polar codes;successive cancellation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{zhayou_14,
+  Title                    = {{H}ardware architecture for list successive cancellation polar decoder},
+  Author                   = {Chuan Zhang and Xiaohu You and Jin Sha},
+  Booktitle                = {Circuits and Systems (ISCAS), 2014 IEEE International Symposium on},
+  Year                     = {2014},
+  Month                    = {June},
+  Pages                    = {209-212},
+
+  Doi                      = {10.1109/ISCAS.2014.6865102},
+  Keywords                 = {decoding;interference suppression;ML decoder;list SC decoder;list successive cancellation polar decoder;maximum likelihood decoder;polar code;precomputation technique;Algorithm design and analysis;Approximation algorithms;Approximation methods;Equations;Hardware;Maximum likelihood decoding;Polar codes;list SC decoder;pre-computation;sub-optimal},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{zhayua_12,
+  Title                    = {{R}educed-latency {SC} polar decoder architectures},
+  Author                   = {C. Zhang and B. Yuan and K. K. Parhi},
+  Booktitle                = {Communications (ICC), 2012 IEEE International Conference on},
+  Year                     = {2012},
+  Month                    = {June},
+  Pages                    = {3471-3475},
+
+  Doi                      = {10.1109/ICC.2012.6364209},
+  ISSN                     = {1550-3607},
+  Keywords                 = {decoding;error correction codes;fast Fourier transforms;parallel processing;pipeline processing;ECC;FFT architecture;ICG block;PE design;code length;decoding algorithm;encoding method;error correction codes;gate-level analysis;input generating circuit block;look-ahead techniques;merged processing element design;parallel SC polar decoder;parallel processing schemes;pipelining processing schemes;polar codes;reduced-latency SC polar decoder architectures;substructure sharing approach;successive cancellation polar decoder designs;Algorithm design and analysis;Clocks;Complexity theory;Computer architecture;Decoding;Hardware;Logic gates;Polar codes;look-ahead;on-the-fly;sub-structure sharing;successive cancellation},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{zhalai_11,
+  Title                    = {{T}ree {S}earch {S}pace {R}eduction for {S}oft-{I}nput {S}oft-{O}utput {S}phere {D}ecoding in {MIMO} {S}ystems},
+  Author                   = {Dan Zhang and I-Wei Lai and Ascheid, G.},
+  Booktitle                = {Vehicular Technology Conference (VTC Spring), 2011 IEEE 73rd},
+  Year                     = {2011},
+  Pages                    = {1-5},
+
+  Doi                      = {10.1109/VETECS.2011.5956186},
+  ISSN                     = {1550-2252},
+  Keywords                 = {MIMO communication;communication complexity;decoding;tree searching;MIMO systems;Schnorr-Euchner enumeration;computational complexity;multiple-input multiple-output systems;negligible error rate performance loss;soft-input soft-output sphere decoding;tree pruning constraint;tree search space reduction;Complexity theory;Iterative decoding;Lattices;MIMO;Maximum likelihood decoding;Measurement},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.04.08}
+}
+
+@InProceedings{zhalai_10,
+  Title                    = {{I}nformed message update for iterative {MIMO} demapping and turbo decoding},
+  Author                   = {Dan Zhang and I-Wei Lai and Nikitopoulos, K. and Ascheid, G.},
+  Booktitle                = {Information Theory and its Applications (ISITA), 2010 International Symposium on},
+  Year                     = {2010},
+  Pages                    = {873-878},
+
+  Doi                      = {10.1109/ISITA.2010.5649576},
+  Keywords                 = {MIMO communication;iterative decoding;parity check codes;sequential decoding;turbo codes;LDPC decoding;LLR calculation;informed asynchronous scheduling;informed message update;iterative MIMO demapping;log-likelihood ratio calculation;low-density parity-check decoding;multiple-input multiple-output system;sequential scheduling;turbo code;turbo decoding;Complexity theory;Convergence;Decoding;Iterative decoding;MIMO;Measurement;Turbo codes},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.05.02}
+}
+
+@InProceedings{zhaleo_05a,
+  Title                    = {{R}econfigurable {A}cceleration for {M}onte {C}arlo based {F}inancial {S}imulation},
+  Author                   = {Zhang, G.L. and Leong, P.H.W. and Ho, C.H. and Tsoi, K.H. and Cheung, C.C.C. and Lee, D.-U. and Cheung, R.C.C. and Wayne Luk},
+  Booktitle                = {Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on},
+  Year                     = {2005},
+  Month                    = dec,
+  Pages                    = {215 -222},
+
+  Abstract                 = {This paper describes a novel hardware accelerator for Monte Carlo (MC) simulation, and illustrates its implementation in field programmable gate array (FPGA) technology for speeding up financial applications. Our accelerator is based on a generic architecture, which combines speed and flexibility by integrating a pipelined MC core with an on-chip instruction processor. We develop a generic number system representation for determining the choice of number representation that meets numerical precision requirements. Our approach is then used in a complex financial engineering application, involving the Brace, Gatarek and Musiela (BGM) interest rate model for pricing derivatives. We address, in our BGM model, several challenges including the generation of Gaussian distributed random numbers and pipelining of the MC simulation. Our BGM application, based on an off-the-shelf system with a Xilinx XC2VP30 device at 50 MHz, is over 25 times faster than software running on a 1.5 GHz, Intel Pentium machine},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPT.2005.1568549},
+  File                     = {zhaleo_05a.pdf:zhaleo_05a.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.11.23}
+}
+
+@InProceedings{zhaleo_05,
+  Title                    = {{Z}iggurat-based hardware {G}aussian random number generator},
+  Author                   = {Guanglie Zhang and Leong, P.H.W. and Dong-U Lee and Villasenor, J.D. and Cheung, R.C.C. and Wayne Luk},
+  Booktitle                = {Field Programmable Logic and Applications, 2005. International Conference on},
+  Year                     = {2005},
+  Month                    = {24-26},
+  Pages                    = { 275 - 280},
+
+  Abstract                 = {An architecture and implementation of a high performance Gaussian random number generator (GRNG) is described. The GRNG uses the Ziggurat algorithm which divides the area under the probability density function into three regions (rectangular, wedge and tail). The rejection method is then used and this amounts to determining whether a random point falls into one of the three regions. The vast majority of points lie in the rectangular region and are accepted to directly produce a random variate. For the nonrectangular regions, which occur 1.5% of the time, the exponential or logarithm functions must be computed and an iterative fixed point operation unit is used. Computation of the rectangular region is heavily pipelined and a buffering scheme is used to allow the processing of rectangular regions to continue to operate in parallel with evaluation of the wedge and tail computation. The resulting system can generate 169 million normally distributed random numbers per second on a Xilinx XC2VP3O-6 device.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/FPL.2005.1515734},
+  File                     = {zhaleo_05.pdf:zhaleo_05.pdf:PDF},
+  ISSN                     = { },
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2010.07.23}
+}
+
+@InProceedings{zhafos_02,
+  Title                    = {{S}huffled belief propagation decoding},
+  Author                   = {Juntan Zhang and Fossorier, M. },
+  Booktitle                = {Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers},
+  Year                     = {2002},
+  Month                    = nov,
+  Pages                    = {8--15},
+  Volume                   = {1},
+
+  Doi                      = {10.1109/ACSSC.2002.1197141},
+  File                     = {zhafos_02.pdf:zhafos_02.pdf:PDF},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@InProceedings{zhafos_05,
+  Title                    = {{Improved min-sum decoding of LDPC codes using 2-dimensional normalization}},
+  Author                   = {J. Zhang and M. Fossorier and D. Gu},
+  Booktitle                = {Proc. IEEE Global Telecommunications Conference 2005 (GLOBECOM '05)},
+  Year                     = {2005},
+
+  Address                  = {St. Louis, Missouri},
+  Month                    = nov,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{zhafos_05a,
+  Title                    = {{Shuffled Iterative Decoding}},
+  Author                   = {Juntan Zhang and Fossorier, Marc P. C.},
+  Journal                  = {IEEE Transactions on Communications},
+  Year                     = {2005},
+
+  Month                    = feb,
+  Number                   = {2},
+  Pages                    = {209--213},
+  Volume                   = {53},
+
+  File                     = {zhafos_05a.pdf:zhafos_05a.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhawan_05,
+  Title                    = {{Replica Shuffled Iterative Decoding}},
+  Author                   = {J. Zhang and Y. Wang and M. Fossorier and J.S. Yedidia},
+  Booktitle                = {Proc. 2005 IEEE International Symposium on Information Theory (ISIT)},
+  Year                     = {2005},
+
+  Address                  = {Adelaide, Australia},
+  Month                    = dec,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhashu_03,
+  Title                    = {{P}ricing {S}\&{P} 500 index options with {H}eston's model},
+  Author                   = {Jin E. Zhang and Jinghong Shu},
+  Booktitle                = {Proceedings of the IEEE International Conference on Computational Intelligence for Financial Engineering (CIFEr)},
+  Year                     = {2003},
+  Month                    = mar,
+  Pages                    = {85--92},
+
+  Abstract                 = {This paper studies the price of S&P 500 index options by using Heston's (1993) stochastic volatility option pricing model. The Heston model is calibrated by a two-step estimation procedure to incorporate both the information from time-series asset return and the information from cross-sectional option data. We find that both the Black-Scholes model and the Heston model overprice the out-of-the-money option and under price the in-the-money options, but the degree of the bias is different. The Heston model significantly outperforms the Black-Scholes model in almost all moneyness-maturity group. On average, the Heston model can reduce pricing errors by about 25%. However, pricing bias still exists in the Heston model, In particular, the Heston model always overprices short-term options, indicating that some other factors, such as the random jump, may also be needed to explain the option price.},
+  Cds_grade                = {4},
+  Cds_keywords             = {finance, Heston, calibration, numerical results},
+  Cds_read                 = {2014-08-11},
+  Cds_review               = {precise motivation + arguments why Heston is better than Black-Scholes
+numerical evaluation of S&P 500 calibration
+no performance data, no comment on platforms},
+  Doi                      = {10.1109/CIFER.2003.1196246},
+  File                     = {zhashu_03.pdf:zhashu_03.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2014.01.24}
+}
+
+@Article{Zhang2004,
+  Title                    = {{I}terative carrier phase recovery suited to turbo-coded systems},
+  Author                   = {Li Zhang and Burr, A.G.},
+  Journal                  = {IEEE Transactions on Wireless Communications},
+  Year                     = {2004},
+
+  Month                    = {Nov},
+  Number                   = {6},
+  Pages                    = {2267-2276},
+  Volume                   = {3},
+
+  Doi                      = {10.1109/TWC.2004.837407},
+  ISSN                     = {1536-1276},
+  Keywords                 = {AWGN channels;decoding;error statistics;iterative methods;maximum likelihood estimation;phase estimation;phase shift keying;probability;turbo codes;BER performance;a priori probability aided phase estimation;additive white Gaussian noise channel;bit-error-rate;iterative carrier phase recovery;iterative decoding;log-likelihood function;maximum-likelihood estimation;maximum-likelihood strategy;quaternary phase-shift keying system;synchronised system;turbo-coded binary phase-shift keying;Additive white noise;Estimation error;Iterative decoding;Maximum likelihood decoding;Maximum likelihood estimation;Noise robustness;Phase estimation;Phase shift keying;Signal to noise ratio;Turbo codes},
+  Owner                    = {ali},
+  Timestamp                = {2015.04.23}
+}
+
+@Article{Zhang2000,
+  Title                    = {{A} novel carrier phase recovery method for turbo coded {QPSK} systems},
+  Author                   = {Zhang, Li and Burr, Alister},
+  Journal                  = {Proc. of European Wireless Conf., Florence, Italy},
+  Year                     = {2000},
+
+  Owner                    = {ali},
+  Timestamp                = {2015.04.07}
+}
+
+@Article{zhamit_06,
+  Title                    = {{S}equential {E}lement {D}esign {W}ith {B}uilt-{I}n {S}oft {E}rror {R}esilience},
+  Author                   = {Zhang, M. and Mitra, S. and Mak, T. M. and Seifert, N. and Wang, N. J. and Shi, Q. and Kim, K. S. and Shanbhag, N. R. and Patel, S. J.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2006},
+
+  Month                    = dec,
+  Number                   = {12},
+  Pages                    = {1368--1378},
+  Volume                   = {14},
+
+  Doi                      = {10.1109/TVLSI.2006.887832},
+  File                     = {zhamit_06.pdf:zhamit_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.14}
+}
+
+@Article{zhasha_06,
+  Title                    = {{S}oft-{E}rror-{R}ate-{A}nalysis ({SERA}) {M}ethodology},
+  Author                   = {Ming Zhang and Shanbhag, N. R.},
+  Journal                  = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+  Year                     = {2006},
+
+  Month                    = oct,
+  Number                   = {10},
+  Pages                    = {2140--2155},
+  Volume                   = {25},
+
+  Doi                      = {10.1109/TCAD.2005.862738},
+  File                     = {zhasha_06.pdf:zhasha_06.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.04}
+}
+
+@PhdThesis{Phdzhang01,
+  Title                    = {{Algorithm/Architecture Co-Design for Wireless Communications Systems}},
+  Author                   = {N. Zhang},
+  School                   = {University of California, Berkeley},
+  Year                     = {2001},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InCollection{zhaman_15,
+  Title                    = {{C}omputing {V}alue at {R}isk in {O}pen{CL} on the {G}raphics {P}rocessing {U}nit},
+  Author                   = {Nan Zhang and Ka Lok Man and Dejun Xie},
+  Booktitle                = {Future Information Technology - II},
+  Publisher                = {Springer},
+  Year                     = {2015},
+  Chapter                  = {9},
+  Month                    = {Jan},
+  Pages                    = {71-78},
+  Series                   = {Lecture Notes in Electrical Engineering},
+  Volume                   = {329},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.07.31}
+}
+
+@InProceedings{zhar.w_00,
+  Title                    = {{Architectural Evaluation of Flexible Digital Signal Processing for Wireless Receivers}},
+  Author                   = {N. Zhang and R.W.Brodersen},
+  Booktitle                = {Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on},
+  Year                     = {2000},
+
+  Address                  = {Pacific Grove, CA, USA},
+  Month                    = nov,
+  Pages                    = {78--83},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{zhaliu_17,
+  Title                    = {{CRC} {C}ode {D}esign for {L}ist {D}ecoding of {P}olar {C}odes},
+  Author                   = {Q. Zhang and A. Liu and X. Pan and K. Pan},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2017},
+  Number                   = {99},
+  Pages                    = {1-1},
+  Volume                   = {PP},
+
+  Abstract                 = {Cyclic redundancy check (CRC) assisted list successive cancellation decoding (SCLD) makes polar codes competitive with the state-of-art codes. In this paper, we try to find the optimal CRC for polar codes to further improve its performance. We first analyze the undetected error probability of CRCaided SCLD as well as the characteristics of Hamming weight distribution of polar codes. Based on these characteristics, a multilevel SCLD-based searching strategy with moderate list size is proposed to compute the minimum Hamming weight distribution (MHWD) of different CRC-concatenated polar codes. Using the searched MHWD, the optimal CRC for polar codes are presented in this paper. Simulation results show that the performance of optimal CRC-aided SCLD significantly outperforms the standard one, especially at high code rate.},
+  Doi                      = {10.1109/LCOMM.2017.2672539},
+  File                     = {zhaliu_17.pdf:zhaliu_17.pdf:PDF},
+  ISSN                     = {1089-7798},
+  Keywords                 = {Cyclic redundancy check codes;Decoding;Error probability;Generators;Hamming weight;Standards;System performance;Cyclic redundancy check;List successive cancellation decoder;Polar codes},
+  Owner                    = {CK},
+  Timestamp                = {2017-03-29}
+}
+
+@PhdThesis{Phdzhang02,
+  Title                    = {{Efficient VLSI Architectures for Error-Correcting Coding}},
+  Author                   = {T. Zhang},
+  School                   = {University of Minnesota},
+  Year                     = {2002},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhapar_02,
+  Title                    = {{A 54 MBPS (3,6)-Regular FPGA LDPC Decoder}},
+  Author                   = {T. Zhang and K. Parhi},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems (SiPS '02)},
+  Year                     = {2002},
+
+  Address                  = {San Diego,USA},
+  Month                    = sep,
+  Pages                    = {127--132},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhapar_01,
+  Title                    = {{VLSI Implementation-Oriented (3,k)-Regular Low-Density Parity-Check Codes}},
+  Author                   = {T. Zhang and K. Parhi},
+  Booktitle                = {Proc. IEEE Workshop on Signal Processing Systems (SiPS '01)},
+  Year                     = {2001},
+
+  Address                  = {Antwerp,Belgium},
+  Month                    = sep,
+  Pages                    = {25--36},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhapor_14,
+  Title                    = {{CREAM}: a {C}oncurrent-{R}efresh-{A}ware {DRAM} {M}emory {A}rchitecture},
+  Author                   = {Zhang, Tao and Poremba, Matthew and Xu, Cong and Sun, Guangyu and Xie, Yuan},
+  Booktitle                = {High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on},
+  Year                     = {2014},
+  Organization             = {IEEE},
+  Pages                    = {368--379},
+
+  Owner                    = {MJ},
+  Timestamp                = {2015.07.10}
+}
+
+@InProceedings{zhawan_01,
+  Title                    = {{On finite precision implementation of low-density parity-check codes decoder}},
+  Author                   = {T. Zhang and Z. Wang and K. Parhi},
+  Booktitle                = {Proc. International Symposium on Circuits and Systems (ISCAS '01)},
+  Year                     = {2001},
+
+  Address                  = {Antwerp, Belgium},
+  Month                    = may,
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhaxu_14,
+  Title                    = {3{D}-{SWIFT}: {A} {H}igh-performance 3{D}-stacked {W}ide {IO} {DRAM}},
+  Author                   = {Zhang, Tao and Xu, Cong and Chen, Ke and Sun, Guangyu and Xie, Yuan},
+  Booktitle                = {Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI},
+  Year                     = {2014},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {51--56},
+  Publisher                = {ACM},
+  Series                   = {GLSVLSI '14},
+
+  Acmid                    = {2591529},
+  Doi                      = {10.1145/2591513.2591529},
+  File                     = {zhaxu_14.pdf:zhaxu_14.pdf:PDF},
+  ISBN                     = {978-1-4503-2816-6},
+  Keywords                 = {3D ICS, DRAM, memory parallelism, sub-bank, wide IO},
+  Location                 = {Houston, Texas, USA},
+  Numpages                 = {6},
+  Owner                    = {MJ},
+  Timestamp                = {2015.02.11}
+}
+
+@InProceedings{zhali_08,
+  Title                    = {{M}icroarchitecture soft error vulnerability characterization and mitigation under 3{D} integration technology},
+  Author                   = {Wangyuan Zhang and Tao Li},
+  Booktitle                = {Proc. MICRO-41 Microarchitecture 2008 41st IEEE/ACM Int. Symp},
+  Year                     = {2008},
+  Pages                    = {435--446},
+
+  Doi                      = {10.1109/MICRO.2008.4771811},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{zhawan_12,
+  Title                    = {{L}ow-power high-efficiency architecture for low-complexity chase soft-decision {R}eed-{S}olomon decoding},
+  Author                   = {W. Zhang and J. Wang and H. Wang and Y. Y. Liu and Z. Jiang and S. Q. Wu},
+  Journal                  = {IET Communications},
+  Year                     = {2012},
+
+  Month                    = {November},
+  Number                   = {17},
+  Pages                    = {3046-3052},
+  Volume                   = {6},
+
+  Doi                      = {10.1049/iet-com.2012.0170},
+  ISSN                     = {1751-8628},
+  Keywords                 = {Reed-Solomon codes;algebraic codes;amplification;application specific integrated circuits;computational complexity;decoding;interpolation;multiplying circuits;ASD;ASIC implementation;Galois Field;LCC decoding testing;RS code;Reed-Solomon codes;algebraic soft-decision decoding;application specific integrated circuit implementation;coding gain;computation complexity;erasure decoder block;hard-decision decoding;hardware requirement;low-complexity chase decoding testing;low-complexity chase soft-decision Reed-Solomon decoding;low-power high-efficiency architecture;multiple interpolators;multiplexer;multiplier;pipelined architecture;pipelined decoder;polynomial complexity;power consumption;re-encoder;test vectors}
+}
+
+@Article{zhapar_05,
+  Title                    = {{H}igh-{S}peed {A}rchitectures for {P}arallel {L}ong {BCH} {E}ncoders},
+  Author                   = {Xinmiao Zhang and Keshab K. Parhi},
+  Journal                  = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
+  Year                     = {2005},
+
+  Month                    = jul,
+  Number                   = {7},
+  Pages                    = { 872-877},
+  Volume                   = {13},
+
+  Abstract                 = {Long Bose�Chaudhuri�Hocquenghen (BCH) codes are used as the outer error correcting codes in the second-generation Digital Video Broadcasting Standard from the European Telecommunications Standard Institute. These codes can achieve around 0.6-dB additional coding gain over Reed�Solomon codes with similar code rate and codeword length in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. High-speed applications of BCH codes require parallel implementation of the encoders. In addition, long BCH encoders suffer from the effect of large fanout. In this paper, three novel architectures are proposed to reduce the achievable minimum clock period for long BCH encoders after the fanout bottleneck has been eliminated. For an (8191, 7684) BCH code, compared to the original 32-parallel BCH encoder architecture without fanout bottleneck, the proposed architectures can achieve a speedup of over 100%.},
+  Cds_grade                = {0},
+  Doi                      = {10.1109/TVLSI.2005.850125},
+  File                     = {zhapar_05.pdf:zhapar_05.pdf:PDF},
+  ISSN                     = {1063-8210},
+  Keywords                 = {BCH},
+  Owner                    = {CdS},
+  Timestamp                = {2009.03.05}
+}
+
+@Article{zhasie_12,
+  Title                    = {{A}daptive {C}ut {G}eneration {A}lgorithm for {I}mproved {L}inear {P}rogramming {D}ecoding of {B}inary {L}inear {C}odes},
+  Author                   = {Xiaojie Zhang and Siegel, P. H.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2012},
+  Number                   = {10},
+  Pages                    = {6581--6594},
+  Volume                   = {58},
+
+  Doi                      = {10.1109/TIT.2012.2204955},
+  File                     = {zhasie_12.pdf:zhasie_12.pdf:PDF},
+  Owner                    = {Scholl},
+  Timestamp                = {2013.02.18}
+}
+
+@Article{zhawu_12,
+  Title                    = {{N}ovel {I}nterpolation and {P}olynomial {S}election for {L}ow-{C}omplexity {C}hase {S}oft-{D}ecision {R}eed-{S}olomon {D}ecoding},
+  Author                   = {X. Zhang and Y. Wu and J. Zhu and Y. Zheng},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2012},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {1318-1322},
+  Volume                   = {20},
+
+  Doi                      = {10.1109/TVLSI.2011.2150254},
+  ISSN                     = {1063-8210},
+  Keywords                 = {Reed-Solomon codes;algebraic codes;decoding;interpolation;polynomials;LCC decoder area;LCC decoding;Reed-Solomon codes;algebraic soft-decision decoding;interpolation;low-complexity Chase ASD decoding;low-complexity Chase soft-decision Reed-Solomon decoding;low-complexity polynomial selection scheme;performance-complexity tradeoff;polynomial complexity;simplified polynomial selection;substantial coding gain;throughput-over-area ratio;Complexity theory;Computer architecture;Decoding;Hardware;Interpolation;Polynomials;Reed-Solomon codes;Algebraic soft-decision decoding (ASD);Reed-Solomon (RS) codes;VLSI design;interpolation;polynomial selection}
+}
+
+@Article{zhawu_11,
+  Title                    = {{N}ovel {I}nterpolation and {P}olynomial {S}election for {L}ow-{C}omplexity {C}hase {S}oft-{D}ecision {R}eed-{S}olomon {D}ecoding},
+  Author                   = {Zhang, X. and Wu, Y. and Zhu, J. and Zheng, Y.},
+  Journal                  = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+  Year                     = {2011},
+  Note                     = {Early Access},
+  Number                   = {99},
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/TVLSI.2011.2150254},
+  File                     = {zhawu_11.pdf:zhawu_11.pdf:PDF},
+  Keywords                 = {ASD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.27}
+}
+
+@InProceedings{zhazha_16a,
+  Title                    = {{AWARD}: {A}pproximation-a{WA}re {R}estore in {F}urther {S}caling {DRAM}},
+  Author                   = {Zhang, Xianwei and Zhang, Youtao and Childers, Bruce and Yang, Jun},
+  Booktitle                = {Proceedings of the Second International Symposium on Memory Systems},
+  Year                     = {2016},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {322--324},
+  Publisher                = {ACM},
+  Series                   = {MEMSYS '16},
+
+  Acmid                    = {2989127},
+  Doi                      = {10.1145/2989081.2989127},
+  ISBN                     = {978-1-4503-4305-3},
+  Keywords                 = {Approximate Computing, DRAM Scaling, Slow Restore},
+  Location                 = {Alexandria, VA, USA},
+  Numpages                 = {3},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-17},
+  Url                      = {http://doi.acm.org/10.1145/2989081.2989127}
+}
+
+@InProceedings{zhazha_16b,
+  Title                    = {{R}estore truncation for performance improvement in future {DRAM} systems},
+  Author                   = {X. Zhang and Y. Zhang and B. R. Childers and J. Yang},
+  Booktitle                = {2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)},
+  Year                     = {2016},
+  Month                    = {March},
+  Pages                    = {543-554},
+
+  Doi                      = {10.1109/HPCA.2016.7446093},
+  Keywords                 = {DRAM chips;performance evaluation;power aware computing;DRAM chips;DRAM module performance;DRAM scaling;DRAM systems;RT schemes;bit cell structure;cell data restoration;energy consumption;performance improvement;process variations;read write access;restore strategy;restore timing;restore truncation;Capacitors;DRAM chips;Hardware;Sensors;Timing;Transistors},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-17}
+}
+
+@InProceedings{zhazha_15,
+  Title                    = {{E}xploiting {DRAM} restore time variations in deep sub-micron scaling},
+  Author                   = {X. Zhang and Y. Zhang and B. R. Childers and J. Yang},
+  Booktitle                = {2015 Design, Automation Test in Europe Conference Exhibition (DATE)},
+  Year                     = {2015},
+  Month                    = {March},
+  Pages                    = {477-482},
+
+  ISSN                     = {1530-1591},
+  Keywords                 = {DRAM chips;microprocessor chips;multiprocessing systems;performance evaluation;4-core multiprocessor system;DRAM restore time variations;ECC;cell restore time;deep submicron scaling;memory chunks;performance degradation;relaxed timing constraints;row sparing;tWR;timing constraints;variation-aware memory controller;write recovery time;Capacitors;Degradation;Error correction codes;Integrated circuit modeling;Random access memory;Standards;Timing},
+  Owner                    = {MJ},
+  Timestamp                = {2016-11-17}
+}
+
+@InProceedings{zhazhe_11,
+  Title                    = {{E}fficient codeword recovery architecture for low-complexity {C}hase {R}eed-{S}olomon decoding},
+  Author                   = {Xinmiao Zhang and Yu Zheng},
+  Booktitle                = {Proc. Information Theory and Applications Workshop (ITA)},
+  Year                     = {2011},
+  Pages                    = {1--4},
+
+  Doi                      = {10.1109/ITA.2011.5743627},
+  File                     = {zhazhe_11.pdf:zhazhe_11.pdf:PDF},
+  Keywords                 = {ASD, Reed-Solomon},
+  Owner                    = {Scholl},
+  Timestamp                = {2011.07.27}
+}
+
+@InProceedings{zhazhu_10,
+  Title                    = {{H}ardware complexities of algebraic soft-decision {R}eed-{S}olomon decoders and comparisons},
+  Author                   = {X. Zhang and J. Zhu},
+  Booktitle                = {Information Theory and Applications Workshop (ITA), 2010},
+  Year                     = {2010},
+  Month                    = {Jan},
+  Pages                    = {1-10},
+
+  Doi                      = {10.1109/ITA.2010.5454070},
+  Keywords                 = {Reed-Solomon codes;algebraic codes;decoding;ASD algorithm;RS code;Reed-Solomon decoder;algebraic soft-decision decoding;code rate;codeword length;coding gain;decoder complexity;hard-decision decoding;hardware complexity;Decoding;Hardware;Reed-Solomon codes}
+}
+
+@Article{zhacha_06,
+  Title                    = {{A} unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems},
+  Author                   = {Ying Zhang and Chakrabarty, K.},
+  Journal                  = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
+  Year                     = {2006},
+
+  Month                    = {jan.},
+  Number                   = {1},
+  Pages                    = { 111 - 125},
+  Volume                   = {25},
+
+  Doi                      = {10.1109/TCAD.2005.852657},
+  ISSN                     = {0278-0070},
+  Keywords                 = {Checkpointing;Dynamic voltage scaling;Embedded system;Energy consumption;Energy management;Fault tolerance;Fault tolerant systems;Power system management;Real time systems;Voltage control; checkpointing; embedded systems; fault tolerant computing; microprocessor chips; checkpointing schemes; constant processor speed; dynamic power management; dynamic voltage scaling; fault tolerance; fault-oblivious methods; power consumption; processor data sheet; real-life checkpointing data sheet; real-time embedded systems; variable processor speed; Checkpointing; dynamic voltage scaling (DVS); fault tolerance; real-time scheduling;},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.02.06}
+}
+
+@Article{zhafen_18,
+  Title                    = {{CACF}: {A} {N}ovel {C}ircuit {A}rchitecture {C}o-optimization {F}ramework for {I}mproving {P}erformance, {R}eliability and {E}nergy of {R}e{RAM}-based {M}ain {M}emory {S}ystem},
+  Author                   = {Zhang, Yang and Feng, Dan and Tong, Wei and Hua, Yu and Liu, Jingning and Tan, Zhipeng and Wang, Chengning and Wu, Bing and Li, Zheng and Xu, Gaoxiang},
+  Journal                  = {ACM Trans. Archit. Code Optim.},
+  Year                     = {2018},
+
+  Month                    = may,
+  Number                   = {2},
+  Pages                    = {22:1--22:26},
+  Volume                   = {15},
+
+  Acmid                    = {3195799},
+  Address                  = {New York, NY, USA},
+  Articleno                = {22},
+  Doi                      = {10.1145/3195799},
+  ISSN                     = {1544-3566},
+  Issue_date               = {June 2018},
+  Keywords                 = {IR drop, ReRAM, crossbar, data patterns, nonuniform access latency, write disturbance},
+  Numpages                 = {26},
+  Publisher                = {ACM},
+  Timestamp                = {2018-08-29},
+  Url                      = {http://doi.acm.org/10.1145/3195799}
+}
+
+@InProceedings{zhalac_02,
+  Title                    = {{Odd/even bus invert with two-phase transfer for buses with coupling}},
+  Author                   = {Yan Zhang and John Lach and Kevin Skadron and Mircea R. Stan},
+  Booktitle                = {ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design},
+  Year                     = {2002},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {80--83},
+  Publisher                = {ACM Press},
+
+  Doi                      = {http://doi.acm.org/10.1145/566408.566431},
+  ISBN                     = {1-58113-475-4},
+  Location                 = {Monterey, California, USA},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Article{zhaliu_14,
+  Title                    = {{A} {M}odified {B}elief {P}ropagation {P}olar {D}ecoder},
+  Author                   = {Yingxian Zhang and Aijun Liu and Xiaofei Pan and Zhan Ye and Chao Gong},
+  Journal                  = {IEEE Communications Letters},
+  Year                     = {2014},
+
+  Month                    = {July},
+  Number                   = {7},
+  Pages                    = {1091-1094},
+  Volume                   = {18},
+
+  Doi                      = {10.1109/LCOMM.2014.2316365},
+  ISSN                     = {1089-7798},
+  Keywords                 = {block codes;decoding;error correction codes;linear codes;BP decoding;belief propagation polar decoder;check node message reliability;polar codes;Belief propagation;Bit error rate;Integrated circuits;Iterative decoding;Maximum likelihood decoding;Reliability;Belief propagation (BP) decoding;check node;polar codes},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.17}
+}
+
+@InProceedings{zhapar_04,
+  Title                    = {{P}arallel {T}urbo {D}ecoding},
+  Author                   = {Yuping Zhang and Parhi, K.K.},
+  Booktitle                = {Proc. 2004 International Symposium on Circuits and Systems (ISCAS '04)},
+  Year                     = {2004},
+
+  Address                  = {Vancouver, Canada},
+  Month                    = may,
+  Pages                    = {II-509--II-512},
+
+  Cds_grade                = {0},
+  File                     = {zhapar_04.pdf:zhapar_04.pdf:PDF},
+  Keywords                 = {Turbo},
+  Optvolume                = {2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zhapar_06,
+  Title                    = {{H}igh-{T}hroughput {R}adix-4 log{MAP} {T}urbo {D}ecoder {A}rchitecture},
+  Author                   = {Yuping Zhang and Parhi, K. K.},
+  Booktitle                = {Proc. Fortieth Asilomar Conference on Signals, Systems and Computers ACSSC '06},
+  Year                     = {2006},
+  Month                    = oct,
+  Pages                    = {1711--1715},
+
+  Doi                      = {10.1109/ACSSC.2006.355053},
+  File                     = {zhapar_06.pdf:zhapar_06.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.08.14}
+}
+
+@InProceedings{zhasha_09,
+  Title                    = {{FPGA} vs. {GPU} for sparse matrix vector multiply},
+  Author                   = {Y. Zhang and Y. H. Shalabi and R. Jain and K. K. Nagar and J. D. Bakos},
+  Booktitle                = {2009 International Conference on Field-Programmable Technology},
+  Year                     = {2009},
+  Month                    = {Dec},
+  Pages                    = {255-262},
+
+  Ccr_grade                = {n.a.},
+  Ccr_keywords             = {{FPGA} PLATFORMS; cite number in presentation [35]},
+  Ccr_topic                = {NetControl Paper},
+  Doi                      = {10.1109/FPT.2009.5377620},
+  Keywords                 = {MPC_FPGA},
+  Keywords_original        = {coprocessors;field programmable gate arrays;sparse matrices;sparse matrix vector multiplication;numerical linear algebra;computational kernel;{FPGA} acceleration;programmability;precision floating-point arithmetic;linear algebra computation;{FPGA} implementation;SpMV implementation;{GPU} implementation;field programmable gate arrays;graphics processing unit;Field programmable gate arrays;Sparse matrices;Computer architecture;Kernel;Acceleration;Biology computing;Vectors;Linear algebra;Scientific computing;Biological system modeling},
+  Owner                    = {CCR}
+}
+
+@InProceedings{zhazha_14,
+  Title                    = {{A} simplified belief propagation decoder for polar codes},
+  Author                   = {Yingxian Zhang and Qingshuang Zhang and Xiaofei Pan and Zhan Ye and Chao Gong},
+  Booktitle                = {Wireless Symposium (IWS), 2014 IEEE International},
+  Year                     = {2014},
+  Month                    = {March},
+  Pages                    = {1-4},
+
+  Doi                      = {10.1109/IEEE-IWS.2014.6864206},
+  Keywords                 = {belief networks;codecs;computational complexity;error correction codes;BP decoders;BP procedure;SBP decoder;computational complexity;frozen nodes;node messages;polar codes;simplified belief propagation decoder;Belief propagation;Computational complexity;Decoding;Equations;Mathematical model;Probability;polar codes;simplified belief propagation(SBP)},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@Article{zhaana_10,
+  Title                    = {{A}n {E}fficient 10{GBASE}-{T} {E}thernet {LDPC} {D}ecoder {D}esign {W}ith {L}ow {E}rror {F}loors},
+  Author                   = {Zhengya Zhang and Anantharam, V. and Wainwright, M.J. and Nikolic, B.},
+  Journal                  = {Solid-State Circuits, IEEE Journal of},
+  Year                     = {2010},
+  Number                   = {4},
+  Pages                    = {843-855},
+  Volume                   = {45},
+
+  Doi                      = {10.1109/JSSC.2010.2042255},
+  File                     = {zhaana_10.pdf:zhaana_10.pdf:PDF},
+  ISSN                     = {0018-9200},
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.04.24}
+}
+
+@InProceedings{zhaana_09,
+  Title                    = {{A} 47 {Gb}/s {LDPC} decoder with improved low error rate performance},
+  Author                   = {Zhengya Zhang and Venkat Anantharam and Martin J. Wainwright and Borivoje Nikolic},
+  Booktitle                = {VLSI Circuits, 2009 Symposium on},
+  Year                     = {2009},
+  Pages                    = {286--287},
+
+  Owner                    = {Schlaefer},
+  Timestamp                = {2013.03.25},
+  Url                      = {http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5205323}
+}
+
+@Article{zhazha_16,
+  Title                    = {{A} {S}plit-{R}educed {S}uccessive {C}ancellation {L}ist {D}ecoder for {P}olar {C}odes},
+  Author                   = {Zhaoyang Zhang and Liang Zhang and Xianbin Wang and Caijun Zhong and H. V. Poor},
+  Journal                  = {IEEE Journal on Selected Areas in Communications},
+  Year                     = {2016},
+
+  Month                    = {Feb},
+  Number                   = {2},
+  Pages                    = {292-302},
+  Volume                   = {34},
+
+  Doi                      = {10.1109/JSAC.2015.2504321},
+  ISSN                     = {0733-8716},
+  Keywords                 = {computational complexity;maximum likelihood decoding;probability;telecommunication network reliability;SCL decoding;decoding complexity reduction;decoding reliability;maximum likelihood decoder;polar code;probability;split-reduced successive cancellation list decoder;Complexity theory;Electronic mail;Gaussian approximation;Maximum likelihood decoding;Radiation detectors;Reliability;Gaussian approximation;Polar codes;split-reduced successive cancellation list decoder},
+  Owner                    = {StW},
+  Timestamp                = {2016.03.18}
+}
+
+@InProceedings{zhazhu_00,
+  Title                    = {{A} {P}ermutation-based {P}age {I}nterleaving {S}cheme to {R}educe {R}ow-buffer {C}onflicts and {E}xploit {D}ata {L}ocality},
+  Author                   = {Zhang, Zhao and Zhu, Zhichun and Zhang, Xiaodong},
+  Booktitle                = {Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture},
+  Year                     = {2000},
+
+  Address                  = {New York, NY, USA},
+  Pages                    = {32--41},
+  Publisher                = {ACM},
+  Series                   = {MICRO 33},
+
+  Acmid                    = {360134},
+  Doi                      = {10.1145/360128.360134},
+  ISBN                     = {1-58113-196-8},
+  Location                 = {Monterey, California, USA},
+  Numpages                 = {10},
+  Owner                    = {MJ},
+  Timestamp                = {2015.01.21},
+  Url                      = {http://doi.acm.org/10.1145/360128.360134}
+}
+
+@Article{zha_10,
+  Title                    = {{Full-Featured Pedometer Design Realized with 3-Axis Digital Accelerometer}},
+  Author                   = {Neil Zhao},
+  Journal                  = {Analog Dialogue 44-06},
+  Year                     = {2010},
+
+  Month                    = {jun},
+
+  Ccr_flags                = {read},
+  Ccr_grade                = {n.a.},
+  Ccr_key_original         = {pedometer},
+  Ccr_keywords             = {todo},
+  Ccr_topic                = {ATC, todo},
+  Keywords                 = {TCS},
+  Owner                    = {CCR},
+  Timestamp                = {2020-03-26},
+  Url                      = {http://www.analog.com/en/analog-dialogue/articles/pedometer-design-3-axis-digital-acceler.html}
+}
+
+@Article{zhetse_03,
+  Title                    = {{D}iversity and multiplexing: a fundamental tradeoff in multiple-antenna channels},
+  Author                   = {Zheng, Lizhong and Tse, D. N. C.},
+  Journal                  = {IEEE Transactions on Information Theory},
+  Year                     = {2003},
+  Number                   = {5},
+  Pages                    = {1073--1096},
+  Volume                   = {49},
+
+  Abstract                 = {Multiple antennas can be used for increasing the amount of diversity or the number of degrees of freedom in wireless communication systems. We propose the point of view that both types of gains can be simultaneously obtained for a given multiple-antenna channel, but there is a fundamental tradeoff between how much of each any coding scheme can get. For the richly scattered Rayleigh-fading channel, we give a simple characterization of the optimal tradeoff curve and use it to evaluate the performance of existing multiple antenna schemes.},
+  Doi                      = {10.1109/TIT.2003.810646},
+  File                     = {zhetse_03.pdf:zhetse_03.pdf:PDF},
+  Grade                    = {5},
+  ISSN                     = {0018-9448},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Review                   = {CG:
+Gelesen: 19.11.2008},
+  Timestamp                = {2008.10.10}
+}
+
+@InProceedings{zhetse_02,
+  Title                    = {{D}iversity and freedom: a fundamental tradeoff in multiple antenna channels},
+  Author                   = {Zheng, Lizhong and Tse, D. N. C.},
+  Booktitle                = {Proc. IEEE International Symposium on Information Theory},
+  Year                     = {2002},
+  Pages                    = {476--},
+
+  Abstract                 = {Multiple antennas can be used for increasing the amount of diversity or the number of degrees of freedom in wireless communication systems. We propose the point of view to study the tradeoff between the two types of gains. In this paper, we present the complete results on the optimal tradeoff, and give a brief discussion on the techniques used to get the results.},
+  Doi                      = {10.1109/ISIT.2002.1023748},
+  File                     = {zhetse_02.pdf:zhetse_02.pdf:PDF},
+  Grade                    = {0},
+  Keywords                 = {MIMO},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.10.10}
+}
+
+@InProceedings{zhesu_03,
+  Title                    = {{O}n {I}nter-block {P}ermutation and {T}urbo {C}odes},
+  Author                   = {Yan-Xiu Zheng and Yu-Ted Su},
+  Booktitle                = {Proc. 3rd International Symposium on Turbo Codes and Related Topics},
+  Year                     = {2003},
+
+  Address                  = {Brest, France},
+
+  File                     = {zhesu_03.pdf:zhesu_03.pdf:PDF},
+  Keywords                 = {Turbo},
+  Owner                    = {May},
+  Timestamp                = {2009.06.09}
+}
+
+@InProceedings{zhocru_09,
+  Title                    = {{S}ymbol-{B}ased {B}elief {P}ropagation {D}ecoding of {R}eed-{S}olomon {C}odes},
+  Author                   = {Zhong, C. and Cruz, J. R.},
+  Booktitle                = {Proc. IEEE 69th Vehicular Technology Conf. VTC Spring 2009},
+  Year                     = {2009},
+  Pages                    = {1--5},
+
+  Doi                      = {10.1109/VETECS.2009.5073872},
+  File                     = {zhocru_09.pdf:zhocru_09.pdf:PDF},
+  Keywords                 = {Reed-Solomon, ABP},
+  Owner                    = {Scholl},
+  Review                   = {erstes Paper mit nicht binaerem ABP (noch vor Fettweis Paper)},
+  Timestamp                = {2011.07.20}
+}
+
+@Conference{zholi_08,
+  Title                    = {{A}rea {O}ptimization of {B}it {P}arallel {F}inite {F}ield {M}ultipliers with {F}ast {C}arry {L}ogic on {FPGA}s},
+  Author                   = {Gang Zhou and Li Li and Harald Michalik},
+  Booktitle                = {International Conference on Field Programmable Logic and Applications (FPL)},
+  Year                     = {2008},
+  Month                    = sep,
+  Pages                    = {671-674},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {Galois Field Multiplier, Carry, FPGA},
+  Cds_read                 = {2008-10},
+  Cds_review               = {FFM FPGA Complexity
+Interesting for high powers of 2^m},
+  Date-added               = {2008-10-02 08:50:08 +0200},
+  Date-modified            = {2008-10-06 14:26:34 +0200},
+  File                     = {zholi_08.pdf:zholi_08.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Article{zhowan_08,
+  Title                    = {{A}ccurate closed-form approximation for pricing {A}sian and basket options},
+  Author                   = {Zhou, Jinke and Wang, Xiaolu},
+  Journal                  = {Applied Stochastic Models in Business and Industry},
+  Year                     = {2008},
+  Number                   = {4},
+  Pages                    = {343--358},
+  Volume                   = {24},
+
+  Abstract                 = {By approximating the distribution of the sum of correlated lognormals with some log-extended-skew-normal distribution, we present closed-form approximation formulae for pricing both Asian and basket options. Numerical comparison shows that our formulae provide both computational simplicity and accuracy. Copyright © 2008 John Wiley & Sons, Ltd.},
+  Cds_grade                = {0},
+  Doi                      = {10.1002/asmb.714},
+  File                     = {zhowan_08.pdf:zhowan_08.pdf:PDF},
+  ISSN                     = {1526-4025},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Publisher                = {John Wiley \& Sons, Ltd.},
+  Timestamp                = {2013.10.30},
+  Url                      = {http://dx.doi.org/10.1002/asmb.714}
+}
+
+@Book{zhoven_99,
+  Title                    = {{M}odeling, simulation, and control of flexible manufacturing systems: a {P}etri net approach},
+  Author                   = {Zhou, MengChu and Venkatesh, Kurapati},
+  Publisher                = {World Scientific},
+  Year                     = {1999},
+  Volume                   = {6},
+
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-27}
+}
+
+@InProceedings{zhozha_08,
+  Title                    = {{R}econfigurable baseband processing platform for communication systems},
+  Author                   = {Xiaofang Zhou and Shuang Zhao and Wenqing Lu and Chao Lu and Sobelman, G. E.},
+  Booktitle                = {Proc. IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008},
+  Year                     = {2008},
+  Month                    = nov,
+  Pages                    = {29--32},
+
+  Doi                      = {10.1109/APCCAS.2008.4745952},
+  Owner                    = {Alles},
+  Timestamp                = {2009.07.13}
+}
+
+@Article{zhuwan_15,
+  Title                    = {{R}educing {DRAM} refreshing in an error correction manner},
+  Author                   = {Zhu, DanFeng and Wang, Rui and Wei, YanJiang and Qian, DePei},
+  Journal                  = {Science China Information Sciences},
+  Year                     = {2015},
+  Pages                    = {1-14},
+
+  Doi                      = {10.1007/s11432-015-5352-4},
+  ISSN                     = {1674-733X},
+  Keywords                 = {DRAM refreshing; error correction; DRAM-ECP; counting bloom filter; retention time},
+  Language                 = {English},
+  Owner                    = {MJ},
+  Publisher                = {Science China Press},
+  Timestamp                = {2015.07.10},
+  Url                      = {http://dx.doi.org/10.1007/s11432-015-5352-4}
+}
+
+@Article{zhu_08,
+  Title                    = {{A} {S}imple and {E}xact {S}imulation {A}pproach to {H}eston {M}odel},
+  Author                   = {Jianwei Zhu},
+  Journal                  = {SSRN eLibrary},
+  Year                     = {2008},
+
+  Month                    = jul,
+
+  Abstract                 = {In this paper we will propose a simple approach to simulating Heston model efficiently and accurately. All existing simulation schemes so far directly work with the mean-reverting square root process of the variance in Heston model, instead we transform the variance to an equivalent volatility which follows a mean-reverting Ornstein-Uhlenbeck process. We will show it is more convenient to simulate the transformed volatility process than the original variance process since the new Ornstein-Uhlenbeck process does not have any term of square root, and is not restricted to any parameter restriction. Based on the transformed volatility process, we suggest a simple and exact scheme for the simulation of Heston model. Numerical examples show that the new scheme and Andersen's QE scheme perform very closely, and outperform other schemes such as log-normal scheme. While QE scheme suffers from the problem of "leaking correlation", transformed volatility scheme does not, and therefore, provides a high-quality alternative to the existing simulation schemes for Heston model.},
+  Cds_grade                = {0},
+  File                     = {zhu_08.pdf:zhu_08.pdf:PDF},
+  Keywords                 = {finance},
+  Language                 = {English},
+  Location                 = {http://ssrn.com/paper=1153950},
+  Owner                    = {CdS},
+  Publisher                = {SSRN},
+  Timestamp                = {2010.11.25},
+  Type                     = {Working Paper Series}
+}
+
+@InProceedings{zhuwan_02,
+  Title                    = {{F}actor graphs based iterative decoding of turbo codes},
+  Author                   = {Zhu, Lianxiang and Wang, Jifeng and Yang, Shizhong},
+  Booktitle                = {Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on},
+  Year                     = {2002},
+  Organization             = {IEEE},
+  Pages                    = {46--50},
+  Volume                   = {1},
+
+  Owner                    = {kraft},
+  Timestamp                = {2018.05.31}
+}
+
+@Article{zietei_09,
+  Title                    = {{C}oncepts for run-time and error-resilient control flow checking of embedded {RISC} {CPU}s},
+  Author                   = {Daniel Ziener and J. Teich},
+  Journal                  = {Int. Journal of Autonomous and Adaptive Communications Systems},
+  Year                     = {2009},
+
+  Month                    = jul,
+  Number                   = {3},
+  Pages                    = {256--275},
+  Volume                   = {2},
+
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.14}
+}
+
+@InProceedings{zietei_08,
+  Title                    = {{C}oncepts for {A}utonomous {C}ontrol {F}low {C}hecking for {E}mbedded {CPU}s},
+  Author                   = {Ziener, Daniel and Teich, Jürgen},
+  Booktitle                = {Proc. 5th International Conference on Autonomic and Trusted Computing (ATC-08)},
+  Year                     = {2008},
+  Month                    = jun,
+  Pages                    = {234--248},
+
+  File                     = {zietei_08.pdf:zietei_08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.04}
+}
+
+@Article{zie_60,
+  Title                    = {{A} class of cyclic linear error-correcting codes in pm symbols},
+  Author                   = {Zierler, N},
+  Journal                  = {Group Report},
+  Year                     = {1960},
+  Pages                    = {55--19},
+
+  Owner                    = {StW},
+  Timestamp                = {2017.03.06}
+}
+
+@InProceedings{zimjan_03,
+  Title                    = {{A} fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip},
+  Author                   = {Zimmer, H. and Jantsch, A.},
+  Booktitle                = {Proc. First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis},
+  Year                     = {2003},
+  Month                    = oct,
+  Pages                    = {188--193},
+
+  File                     = {zimjan_03.pdf:zimjan_03.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.12.04}
+}
+
+@Article{zimbit_06,
+  Title                    = {{C}omplexity {R}eduction in {I}terative {MIMO} {R}eceivers {B}ased on {EXIT} {C}hart {A}nalysis},
+  Author                   = {Ernesto Zimmermann and Steffen Bittner and Gerhard Fettweis},
+  Journal                  = {Proceedings of the International Symposium on Turbo Codes \& Related Topics (ISTC'06)},
+  Year                     = {2006},
+  Note                     = {nicht auffindbar},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2009.08.04}
+}
+
+@InProceedings{zimfet_06,
+  Title                    = {{U}nbiased {MMSE} {T}ree {S}earch {D}etection for {M}ultiple {A}ntenna {S}ystems},
+  Author                   = {E. Zimmermann and G. Fettweis},
+  Booktitle                = {Proceedings of the International Symposium on Wireless Personal Multimedia Communications (WPMC'06)},
+  Year                     = {2006},
+  Month                    = {September},
+
+  File                     = {zimfet_06.pdf:zimfet_06.pdf:PDF},
+  Owner                    = {Gimmler},
+  Timestamp                = {2010.03.03}
+}
+
+@InProceedings{zivpee_96,
+  Title                    = {{LISA-machine description language and generic machine model for HW/SW co-design}},
+  Author                   = {Zivojnovic, V. and Pees, S. and Meyr, H.},
+  Booktitle                = {VLSI Signal Processing, IX, 1996., [Workshop on]},
+  Year                     = {1996},
+  Month                    = oct # {--} # nov,
+  Pages                    = {127--136},
+
+  Doi                      = {10.1109/VLSISP.1996.558311},
+  Owner                    = {vogt},
+  Timestamp                = {2007.05.29}
+}
+
+@InProceedings{zogcho_93,
+  Title                    = {{I}mpulse noise mitigation strategies for multicarrier modulation},
+  Author                   = {Zogakis, T. N. and Chow, P. S. and Aslanis, J. T. and Cioffi, J. M. },
+  Booktitle                = {Proc. IEEE Int Communications ICC 93. Geneva. Technical Program, Conf. Record Conf},
+  Year                     = {1993},
+  Pages                    = {784--788},
+  Volume                   = {2},
+
+  Doi                      = {10.1109/ICC.1993.397380},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.02.16}
+}
+
+@Article{zorgiz_04,
+  Title                    = {{G}uest {E}ditors' {I}ntroduction: {D}esign for {Y}ield and {R}eliability},
+  Author                   = {Yervant Zorian and Dimitris Gizopoulos and Cary Vandenberg and Philippe Magarshack},
+  Journal                  = {IEEE Design and Test of Computers},
+  Year                     = {2004},
+  Number                   = {3},
+  Pages                    = {177--182},
+  Volume                   = {21},
+
+  Address                  = {Los Alamitos, CA, USA},
+  Doi                      = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.12},
+  File                     = {zorgiz_04.pdf:zorgiz_04.pdf:PDF},
+  ISSN                     = {0740-7475},
+  Keywords                 = {Reliability},
+  Owner                    = {Gimmler},
+  Publisher                = {IEEE Computer Society},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{zulhau_20,
+  Title                    = {{S}ystem {S}imulation with {PULP} {V}irtual {P}latform and {S}ystem{C}},
+  Author                   = {Zulian, Éder F. and Haugou, Germain and Weis, Christian and Jung, Matthias and Wehn, Norbert},
+  Booktitle                = {International Conference on High-Performance and Embedded Architectures and Compilers 2020 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)},
+  Year                     = {2020},
+  Month                    = {January},
+
+  Owner                    = {MJ},
+  Timestamp                = {2020-09-19}
+}
+
+@Article{zwe_11,
+  Title                    = {{G}ood versus optimal: {W}hy network analytic methods need more systematic evaluation},
+  Author                   = {Zweig, Katharina},
+  Journal                  = {Open Computer Science},
+  Year                     = {2011},
+  Number                   = {1},
+  Pages                    = {137--153},
+  Volume                   = {1},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.08.09}
+}
+
+@InProceedings{zwe_10,
+  Title                    = {{H}ow to {F}orget the {S}econd {S}ide of the {S}tory: {A} {N}ew {M}ethod for the {O}ne-{M}ode {P}rojection of {B}ipartite {G}raphs},
+  Author                   = {Zweig, K.A.},
+  Booktitle                = {Advances in Social Networks Analysis and Mining (ASONAM), 2010 International Conference on},
+  Year                     = {2010},
+  Month                    = {Aug},
+  Pages                    = {200-207},
+
+  Doi                      = {10.1109/ASONAM.2010.24},
+  Keywords                 = {graph theory;pattern clustering;Netflix prize data;bipartite graphs;bipartite setting;clustering behavior;market basket data;one mode projection;recommendation systems;Approximation methods;Bipartite graph;Correlation;Data models;Quality assessment;Runtime;Stability analysis;bipartite graphs;network analysis;recommendation systems},
+  Owner                    = {Brugger},
+  Timestamp                = {2014.11.26}
+}
+
+@Misc{zwebest15,
+  Title                    = {{B}est {P}aper {A}ward, 2500 {EUR}},
+
+  Author                   = {Katharina A. Zweig},
+  HowPublished             = {SPP 1736 - Algorithms for Big Data},
+  Month                    = sep,
+  Note                     = {For her outstanding work on "A Custom Computing System for Finding Similarties in Complex Networks"},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.31}
+}
+
+@Misc{zwebest15a,
+  Title                    = {{B}est {P}atent {A}ward, 2500 {EUR}},
+
+  Author                   = {Katharina A. Zweig},
+  HowPublished             = {SPP 1736 - Algorithms for Big Data},
+  Month                    = sep,
+  Note                     = {For her outstanding development of new hardware in the field of big data.},
+  Year                     = {2015},
+
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.31}
+}
+
+@Misc{zweautomated15,
+  Title                    = {{A}utomated {D}etermination {O}f {N}etwork {M}otifs},
+
+  Author                   = {Zweig, Katharina Anna and Brugger, Christian and Grigorovici, Valentin and De Schryver, Christian and Wehn, Norbert},
+  HowPublished             = {European Patent},
+  Month                    = jun,
+  Note                     = {File Number 15001681.4},
+  Year                     = {2015},
+
+  Nationality              = {European Patent},
+  Owner                    = {Brugger},
+  Timestamp                = {2015.07.31},
+  Yearfiled                = {2015}
+}
+
+@Article{zwekau_11,
+  Title                    = {{A} systematic approach to the one-mode projection of bipartite graphs},
+  Author                   = {Zweig, Katharina Anna and Kaufmann, Michael},
+  Journal                  = {Social Network Analysis and Mining},
+  Year                     = {2011},
+  Number                   = {3},
+  Pages                    = {187--218},
+  Volume                   = {1},
+
+  File                     = {zwekau_11.pdf:zwekau_11.pdf:PDF},
+  Owner                    = {Brugger},
+  Publisher                = {Springer},
+  Timestamp                = {2014.11.26}
+}
+
+@Book{ata_99,
+  Title                    = {{A}lgorithms and {T}heory of {C}omputation {H}andbook},
+  Editor                   = {Mikhail Atallah},
+  Publisher                = {CrC Press},
+  Year                     = {1998},
+
+  Address                  = {Boca Raton, FL},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.02.01}
+}
+
+@Book{balsch_13,
+  Title                    = {{P}roceedings of the 2nd {Y}oung {R}esearcher {S}ymposium ({YRS}) 2013},
+  Editor                   = {Frank Balle and Christian de Schryver and Sylvia Gerwalin and Thorsten Kowalke and Thomas Kuhn and André Liebscher and Claudia Redenbach and Konrad Steiner},
+  Publisher                = {Fraunhofer Verlag, Stuttgart},
+  Year                     = {2013},
+  Month                    = nov,
+  Note                     = {ISBN: 978-3-8396-0628-5, urn:nbn:de:0011-n-2667834},
+
+  File                     = {balsch_13.pdf:balsch_13.pdf:PDF},
+  Keywords                 = {AG Wehn},
+  Owner                    = {CdS},
+  Timestamp                = {2014.12.09},
+  Url                      = {http://publica.fraunhofer.de/dokumente/N-266783.html}
+}
+
+@Book{balsch_16,
+  Title                    = {{P}roceedings of the 3rd {Y}oung {R}esearcher {S}ymposium ({YRS}) 2016},
+  Editor                   = {Frank Balle and Christian De Schryver and Sylvia Gerwalin and Isabel Sattler and Berenike Schröder},
+  Publisher                = {Fraunhofer Verlag, Stuttgart},
+  Year                     = {2016},
+  Month                    = apr,
+  Note                     = {ISBN: 978-3-8396-1010-7, urn:nbn:de:0011-n-3893830},
+
+  File                     = {balsch_16.pdf:balsch_16.pdf:PDF},
+  Keywords                 = {AG Wehn},
+  Owner                    = {CDS},
+  Timestamp                = {2016-05-27},
+  Url                      = {http://publica.fraunhofer.de/dokumente/N-389383.html}
+}
+
+@Book{sch_15,
+  Title                    = {{FPGA} {B}ased {A}ccelerators for {F}inancial {A}pplications},
+  Editor                   = {De Schryver, Christian},
+  Publisher                = {Springer International Publishing},
+  Year                     = {2015},
+  Edition                  = {1st},
+  Month                    = jul,
+  Note                     = {eBook ISBN 978-3-319-15407-7, Hardcover ISBN 978-3-319-15406-0},
+
+  Abstract                 = {This book covers the latest approaches and results from reconfigurable computing architectures employed in the finance domain. So-called field-programmable gate arrays (FPGAs) have already shown to outperform standard CPU- and GPU-based computing architectures by far, saving up to 99% of energy depending on the compute tasks. Renowned authors from financial mathematics, computer architecture and finance business introduce the readers into today’s challenges in finance IT, illustrate the most advanced approaches and use cases and present currently known methodologies for integrating FPGAs in finance systems together with latest results. The complete algorithm-to-hardware flow is covered holistically, so this book serves as a hands-on guide for IT managers, researchers and quants/programmers who think about integrating FPGAs into their current IT systems.},
+  Doi                      = {10.1007/978-3-319-15407-7},
+  Keywords                 = {AGWehn, finance},
+  Owner                    = {CDS},
+  Timestamp                = {2015-08-21}
+}
+
+@Book{petri03,
+  Title                    = {{P}etri {N}et {T}echnology for {C}ommunication-{B}ased {S}ystems - {A}dvances in {P}etri {N}ets},
+  Editor                   = {Hartmut Ehrig and
+ Wolfgang Reisig and
+ Grzegorz Rozenberg and
+ Herbert Weber},
+  Publisher                = {Springer},
+  Year                     = {2003},
+  Series                   = {Lecture Notes in Computer Science},
+  Volume                   = {2472},
+
+  Bibsource                = {dblp computer science bibliography, http://dblp.org},
+  Biburl                   = {http://dblp2.uni-trier.de/rec/bib/conf/dfg/2003},
+  ISBN                     = {3-540-20538-1},
+  Owner                    = {MJ},
+  Timestamp                = {2017-02-27}
+}
+
+@Proceedings{system-level09,
+  Title                    = {{S}ystem-{L}evel {M}odeling, {A}nalysis and {S}ynthesis of {E}mbedded {M}ulti-{C}ore {D}esigns},
+  Year                     = {2009},
+  Editor                   = {Daniel D. Gajski},
+  Month                    = {April},
+  Organization             = {DATE Conference 2009},
+
+  Booktitle                = {System-Level Modeling, Analysis and Synthesis of Embedded Multi-Core Designs},
+  Cds_grade                = {4},
+  Cds_keywords             = {SystemC, TLM, Multicore, System Design},
+  Cds_read                 = {2009-04-20},
+  File                     = {system-level09.pdf:system-level09.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2010.04.14}
+}
+
+@InBook{gib_96,
+  Title                    = {{The Mobile Communications Handbook}},
+  Chapter                  = {Digital Communication System Performance},
+  Editor                   = {J. D. Gibson},
+  Pages                    = {177--195},
+  Publisher                = {CRC Press/IEEE Press},
+  Year                     = {1996},
+
+  Address                  = {Boca Raton, Florida, USA},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{jeryoo_03,
+  Title                    = {{E}mbedded {S}oftware for {S}o{C}},
+  Editor                   = {A.A. Jerraya and S. Yoo and D. Verkest and N. Wehn},
+  Publisher                = {Kluwer Academic Publishers, ISBN 1-4020-7528-6},
+  Year                     = {2003},
+
+  Owner                    = {kienle},
+  Timestamp                = {2007.04.24}
+}
+
+@Book{miclau_92,
+  Title                    = {{The Synthesis Approach to Digital System Design}},
+  Editor                   = {P. Michel and U. Lauther and P. Duzy},
+  Publisher                = {Kluwer Academic Publishers},
+  Year                     = {1992},
+
+  Address                  = {Boston/Dordrecht/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Proceedings{DBLP:conf/fdl/2010,
+  Title                    = {{P}roceedings of the 2010 {F}orum on specification {\&} {D}esign {L}anguages, {FDL} 2010, {S}eptember 14-16, 2010, {S}outhampton, {UK}},
+  Year                     = {2010},
+  Editor                   = {Adam Morawiec and Jinnie Hinderscheit},
+  Publisher                = {ECSI, Electronic Chips {\&} Systems design Initiative},
+
+  Bibsource                = {DBLP, http://dblp.uni-trier.de},
+  Booktitle                = {FDL},
+  Ee                       = {http://www.ecsi.org/fdl2010/}
+}
+
+@InBook{ojapra_98,
+  Title                    = {{Wideband CDMA for Third Generation Mobile Communications}},
+  Editor                   = {T. Ojanperä and R. Prasad},
+  Publisher                = {Artech House Publishers},
+  Year                     = {1998},
+
+  Address                  = {Boston/London},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Book{san_13,
+  Title                    = {{N}anoscale {S}emiconductor {M}emoriees: {T}echnology and applications},
+  Editor                   = {Santosh K. Kurinec, Krzysztof Iniewski},
+  Publisher                = {CRC Press},
+  Year                     = {2013},
+
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-27}
+}
+
+@Book{vanben_13,
+  Title                    = {{H}igh-{P}erformance {C}omputing {U}sing {FPGA}s},
+  Editor                   = {Wim Vanderbauwhede and Khaled Benkrid},
+  Publisher                = {Springer},
+  Year                     = {2013},
+
+  Owner                    = {CDS},
+  Timestamp                = {2015-02-13}
+}
+
+@Book{wicbha_94,
+  Title                    = {{R}eed-{S}olomon {C}odes and {T}heir {A}pplication},
+  Editor                   = {Stephen B. Wicker and Vijay K. Bhargava},
+  Publisher                = {IEEE Press},
+  Year                     = {1994},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {VLSI, RS, Soft-Decision},
+  Cds_read                 = {2009-06-22},
+  Cds_review               = {collection of different independent chapters
+no detailed VLSI implementation of RS decoder given},
+  Keywords                 = {BCH, Reed-Solomon},
+  Owner                    = {CdS},
+  Timestamp                = {2009.06.22}
+}
+
+@Article{_,
+  Owner                    = {DMM},
+  Timestamp                = {2018-04-26}
+}
+
+@Electronic{_a,
+  Owner                    = {DMM},
+  Timestamp                = {2018-08-29}
+}
+
+@Book{_b,
+  Owner                    = {MJ},
+  Timestamp                = {2019-01-02}
+}
+
+@InProceedings{_d,
+  Title                    = {{R}econfiguration {T}echniques for self-{X} {P}ower and {P}erformance {M}anagement on {X}ilinx {V}irtex-{II}/{V}irtex-{II}-{P}ro {FPGA}s},
+
+  Owner                    = {Brehm},
+  Timestamp                = {2011.10.18}
+}
+
+@Unpublished{_isvlsi09_106,
+  Title                    = {{D}ynamic {R}econfiguration of {T}wo-{L}evel {C}aches in {S}oft {R}eal-{T}ime {E}mbedded {S}ystems},
+
+  Abstract                 = {Cache reconfiguration is a promising optimization technique for reducing memory hierarchy energy consumption with little or no impact on overall system performance. While cache reconfiguration is successful in desktop-based systems, it is not directly applicable in real-time systems due to time constraints. Existing scheduling aware cache reconfiguration techniques consider only one-level cache. It is a major challenge to dynamically tune multi-level caches since the exploration space is prohibitively large. This paper efficiently integrate cache reconfiguration in soft real-time systems with a unified two-level cache hierarchy. We utilize a set of heuristics searching strategies during our static analysis which effectively decreases the exploration time while keeps the generated profile results beneficial to be leveraged during runtime to both reduce energy consumption and improve performance. Our experimental results composed of widely used benchmarks have demonstrated 32 - 49% energy savings with minor impact on performance.},
+  Cds_grade                = {4},
+  Cds_keywords             = {Real-Time Systems, Cache, Reconfiguration},
+  Cds_read                 = {2009-02-12},
+  Cds_review               = {blind review
+shows energy savings are 60 to 40% compared to base scenarios
+
+shows state-of-the-art cache reconfiguration strategies, currently only for 1 level
+new: heuristic approches for two-level caches:
+- Independent Level One Cache Tuning - IL1T <- states that data and instruction cache are independent
+- Two-Step Tuning - TST <- only consider pareto-optimal configurations
+- Interlaced Tuning - ILT <- based on importance of parameters (power, line size, associativity)
+
+2009-02-12 submitted review:
+- new approach of handling two-level caches in real-time systems is presented with respect to power savings
+- very good motivation, state of the art is presented and novelty of the work is highlighted
+- introduction: the meaning of "soft" real-time systems is explained, but the term should be clearly defined due to different meanings in literature
+- section 3.2: Why is Monte Carlo the best approach? A detailed justification would confirm the chosen approaches.
+- exploration methods are well-explained and can be understood with no difficulties
+- section 4.2: algorithm is shown and well-commented
+- results: a comparison of the quantitative amount of deadline misses between base scheme and the new heuristics would be very interesting
+- some irregularities with the language exist: several missing "-s" for third person (e.g. abstract: "this paper efficiently integrateS ..", and 3.2: "Since A preemptive system..."
+- altogether, a very interesting and understandable new examination of real-time system caches showing a significant improvement in power consumption and therefore is especially interesting for embedded system applications},
+  File                     = {_isvlsi09_106.pdf:_isvlsi09_106.pdf:PDF},
+  Keywords                 = {Review},
+  Owner                    = {CdS},
+  Timestamp                = {2009.02.12}
+}
+
+@Misc{4more,
+  Title                    = {{4MORE - 4G MC-CDMA Multiple Antenna System on Chip for Radio Enhancements}},
+  HowPublished             = {{{http://www.ist-4more.org}}},
+
+  Key                      = {4more},
+  Organization             = {IST},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Manual{a,
+  Owner                    = {varela},
+  Timestamp                = {2016.11.27}
+}
+
+@Misc{aeroflex,
+  Title                    = {{Aeroflex Gaisler}},
+  HowPublished             = {{http://{www.gaisler.com/}}},
+
+  Key                      = {xilinx_ip},
+  Owner                    = {May},
+  Timestamp                = {2009.07.07}
+}
+
+@Misc{ais,
+  Title                    = {{AIS Project}},
+  HowPublished             = {{{http://www.edacentrum.de/ais/}}},
+
+  Key                      = {xilinx_ip},
+  Keywords                 = {Reliability},
+  Owner                    = {may},
+  Timestamp                = {2008.08.15}
+}
+
+@Misc{analog,
+  Title                    = {{Analog Devices, Inc.}},
+  HowPublished             = {{{http://www.analog.com}}},
+
+  Key                      = {analogdevices},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{arc,
+  Title                    = {{ARC International Ltd.}},
+  HowPublished             = {{{http://www.arccores.com}}},
+
+  Key                      = {arc},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{arm,
+  Title                    = {{ARM Ltd.}},
+  HowPublished             = {{{http://www.arm.com}}},
+
+  Key                      = {arm},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{arm2,
+  Title                    = {{ARM Ltd. Cortex-A5}},
+  HowPublished             = {{http://www.arm.com/products/processors/cortex-a/cortex-a5.php, last access Feb.2012}},
+
+  Key                      = {arm},
+  Owner                    = {Kienle},
+  Timestamp                = {2008.11.26}
+}
+
+@Proceedings{b,
+  Owner                    = {MJ},
+  Timestamp                = {2020-09-19}
+}
+
+@Misc{coware,
+  Title                    = {{C}o{W}are},
+  HowPublished             = {http://www.coware.com},
+
+  Key                      = {coware},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Manual{cplex_man,
+  Title                    = {{ILOG},{CPLEX} 11 {U}ser’s {M}anual, 2007},
+
+  Owner                    = {punekar},
+  Timestamp                = {2009.09.04}
+}
+
+@Other{digital,
+  Title                    = {{Digital Video Broadcasting (DVB) Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications}},
+  Number                   = {EN 302 307},
+  Organization             = {ETSI},
+  Owner                    = {Gimmler},
+  Revision                 = {v1.1.2},
+  Timestamp                = {2008.11.26},
+  Url                      = {www.dvb.org}
+}
+
+@Misc{eu_davinci,
+  Title                    = {{EU}-{P}roject {INFSCO}-{ICT}-216203 {DA} {VINCI}: {D}esign {A}nd {V}ersatile {I}mplementation of {N}onbinary
+wireless {C}ommunications based on {I}nnovative {LDPC} {C}odes.},
+  HowPublished             = {http://www.ict-davincicodes.eu/},
+
+  Owner                    = {lehnigk},
+  Timestamp                = {2009.10.08}
+}
+
+@Misc{fmc,
+  Title                    = {{F}undamental {M}odeling {C}oncepts ({FMC})},
+  HowPublished             = {{{http://fmc.hpi.uni-potsdam.de}}},
+
+  Key                      = {fmc},
+  Opttitle                 = {{""}},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{ft2232,
+  Title                    = {{FT2232H Module Datasheet}},
+  HowPublished             = {\\ \url{http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf}},
+
+  Key                      = {FT2232},
+  Owner                    = {Brehm},
+  Timestamp                = {2013.5.20}
+}
+
+@Misc{ftdi,
+  Title                    = {{FTDI Inc.}},
+  HowPublished             = { \url{http://www.ftdi.com}},
+
+  Key                      = {ftdi},
+  Owner                    = {Brehm},
+  Timestamp                = {2013.5.20}
+}
+
+@Misc{genode,
+  Title                    = {{Genode FPGA Graphics (FX)}},
+  HowPublished             = {{{http://www.genode-labs.com/products/fpga-graphics}}},
+
+  Key                      = {GenodeFX},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{gnuoctave,
+  Title                    = {{GNU} {O}ctave},
+  HowPublished             = {http://www.gnu.org/software/octave/},
+
+  Owner                    = {CdS},
+  Timestamp                = {2011.02.10}
+}
+
+@Misc{gy,
+  Title                    = {{GY / T 220.1-2006 Mobile Multimedia Broadcasting Part 1: broadcast channel frame structure, channel coding and modulation}},
+
+  Abstract                 = {CMMB},
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.08}
+}
+
+@Misc{icoding,
+  Title                    = {{iCoding Technology Inc.}},
+  HowPublished             = {{{http://www.icoding.com}}},
+
+  Key                      = {iCoding},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Other{local,
+  Title                    = {{Local and Metropolitan Area Network, Part 16: Air Interface for Fixed Broadband Wireless Access Networks}},
+  Number                   = {802.16},
+  Organization             = {IEEE},
+  Owner                    = {Gimmler},
+  Revision                 = {2004},
+  Timestamp                = {2008.11.26}
+}
+
+@Other{matrice,
+  Title                    = {{MATRICE - MC-CDMA Transmission Techniques for Integrated Broadband Cellular Systems project}},
+  Key                      = {MATRICEGEN},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Url                      = {http://www.ist-matrice.org}
+}
+
+@Misc{ml507,
+  Title                    = {{ML507 Evaluation Platform}},
+  HowPublished             = {{\\ \url{http://www.xilinx.com/products/devkits/HW-V5-ML507-UNI-G.htm}}},
+
+  Key                      = {ML507},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{ml605,
+  Title                    = {{Xilinx ML-605 Development Board}},
+  HowPublished             = {\\ \url{http://www.xilinx.com/products/boards-and-kits/EK-V6-ML605-G.htm}},
+
+  Key                      = {ml605},
+  Owner                    = {Brehm},
+  Timestamp                = {2013.5.20}
+}
+
+@Misc{omitted,
+  Title                    = {-omitted for blind review-},
+
+  Owner                    = {CdS},
+  Timestamp                = {2012.09.12}
+}
+
+@Misc{private,
+  Title                    = {private communications with {THOMSON}, patent pending},
+
+  Annote                   = {for citation in diploma thesis},
+  Cds_grade                = {0},
+  Cds_read                 = {2008-09},
+  Date-added               = {2008-08-06 14:18:20 +0200},
+  Date-modified            = {2008-08-08 10:37:45 +0200},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10}
+}
+
+@Misc{rysavy,
+  Title                    = {{Transition to 4G: 3GPP Broadband Evolution to IMT-Advanced}},
+  HowPublished             = {{{http://www.rysavy.com}}},
+
+  Key                      = {rysavy},
+  Owner                    = {Kienle},
+  Timestamp                = {2012.02.23}
+}
+
+@Misc{spp1500,
+  Title                    = {{DFG SPP 1500}},
+  HowPublished             = {{{http://spp1500.itec.kit.edu}}},
+
+  Key                      = {SPP 1500},
+  Keywords                 = {Reliability},
+  Owner                    = {brehm},
+  Timestamp                = {2011.08.08}
+}
+
+@Misc{st,
+  Title                    = {{ST Microelectronics 802.11b/g/a WLAN Radio}},
+  HowPublished             = {\\{{http://www.st.com/stonline/products/literature/bd/12062.htm}}},
+
+  File                     = {stebri_07_slides_draft_v2.ppt:stebri_07_slides_draft_v2.ppt:PowerPoint},
+  Key                      = {st microelectronics},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{sta,
+  Title                    = {{ST Microelectronics Greenside Platform}},
+  HowPublished             = {\\{{http://www.st.com/stonline/products/literature/ta/11145.htm}}},
+
+  Key                      = {st microelectronics},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{starcore,
+  Title                    = {{StarCore Technology Centre, Atlanta, Georgia, USA}},
+  HowPublished             = {{{http://www.starcore-dsp.com}}},
+
+  Key                      = {starcore},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{stb,
+  Title                    = {{ST Microelectronics}},
+  HowPublished             = {{{http://www.st.com}}},
+
+  Key                      = {st microelectronics},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{stretch,
+  Title                    = {{Stretch}},
+  HowPublished             = {{{http://www.stretchinc.com}}},
+
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.01}
+}
+
+@Misc{synopsys,
+  Title                    = {{Synopsys Inc.}},
+  HowPublished             = {{{http://www.synopsys.com}}},
+
+  Key                      = {synopsys},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{target,
+  Title                    = {{Target Compiler Technologies}},
+  HowPublished             = {{{http://www.retarget.com}}},
+
+  Key                      = {Target Compiler},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.04.20}
+}
+
+@Misc{tensilica,
+  Title                    = {{Tensilica Inc.}},
+  HowPublished             = {{{http://www.tensilica.com}}},
+
+  Key                      = {tensilica},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Electronic{theEccPage,
+  Title                    = {{T}he {E}rror {C}orrecting {C}odes ({ECC}) {P}age},
+  Language                 = {en},
+  Note                     = {last access 2014-01-30},
+  Url                      = {\url{http://fly.isti.cnr.it/software/codes.html}},
+
+  Cds_grade                = {4},
+  Cds_read                 = {2008-02-19},
+  Date-added               = {2008-02-19 13:23:06 +0100},
+  Date-modified            = {2008-02-19 16:57:48 +0100},
+  LastChecked              = {2008-02-19},
+  Owner                    = {CdS},
+  Timestamp                = {2008.12.10},
+  Urldate                  = {1996}
+}
+
+@Misc{trellisware2,
+  Title                    = {{TrellisWare}},
+  HowPublished             = {{{http://www.trellisware.com/}}},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{turboconcept,
+  Title                    = {{TurboConcept}},
+  HowPublished             = {{{http://www.turboconcept.com}}},
+
+  Key                      = {TurboConcept},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{uranus,
+  Title                    = {{URANUS - Universal Radio-link platform for efficient User-centric access}},
+  HowPublished             = {{{https://project.ist-uranus.org}}},
+
+  Key                      = {uranus},
+  Organization             = {IST},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{wimedia,
+  Title                    = {{W}i{M}edia {A}lliance},
+  HowPublished             = {{{www.wimedia.org}}},
+
+  Owner                    = {Alles},
+  Timestamp                = {2009.12.17}
+}
+
+@Misc{xilinxa,
+  Title                    = {{Xilinx Inc. Virtex II Pro Data Sheet}},
+  HowPublished             = {{{http://www.xilinx.com/ipcenter}}},
+
+  Key                      = {xilinx_lut},
+  Optauthor                = {Xilinx Inc.},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{xilinxb,
+  Title                    = {{Xilinx Inc.}},
+  HowPublished             = {{http://{www.xilinx.com/ipcenter}}},
+
+  Key                      = {xilinx_ip},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{xilinxc,
+  Title                    = {{Xilinx Inc.}},
+  HowPublished             = {{http://{www.xilinx.com/}}},
+
+  Key                      = {xilinx_ip},
+  Owner                    = {May},
+  Timestamp                = {2009.07.07}
+}
+
+@Misc{xilinxd,
+  Title                    = {{Xilinx ML-507 Development Board}},
+  HowPublished             = {\\ \url{http://www.xilinx.com/products/boards/ml507/docs.htm}},
+
+  Key                      = {ml507},
+  Owner                    = {Brehm},
+  Timestamp                = {2013.5.20}
+}
+
+@Misc{xilinx-virtex4,
+  Title                    = {{Xilinx Inc. Virtex 4 Data Sheet}},
+  HowPublished             = {{{http://www.xilinx.com/ipcenter}}},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2015-07-21}
+}
+
+@Misc{git17,
+  Title                    = {{G}it},
+  HowPublished             = {Online},
+  Year                     = {2017},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.09.01},
+  Url                      = {https://git-scm.com/}
+}
+
+@Misc{github16,
+  Title                    = {{G}it{H}ub},
+  HowPublished             = {Online},
+  Year                     = {2016},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22},
+  Url                      = {https://github.com/}
+}
+
+@Electronic{cisco_15,
+  Title                    = {{C}isco {V}isual {N}etworking {I}ndex: {F}orecast and {M}ethodology, 2014 – 2019},
+  Language                 = {en},
+  Month                    = jun,
+  Note                     = {last access 2016-08-03},
+  Organization             = {Cisco},
+  Url                      = {http://www.cisco.com/en/US/solutions/collateral/ns341/ns525/ns537/ns705/ns827/white_paper_c11-520862.html},
+  Year                     = {2015},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {HPC, cloud, traffic, internet, prediction},
+  Cds_read                 = {2014-02-07},
+  Cds_review               = {80% traaffic increase in 2013 compared to 2012, another 10x increase until 2018},
+  File                     = {cisco_14.pdf:cisco_14.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Electronic{jpmorgan_15,
+  Title                    = {{A}dvances and {I}nnovations - {F}ield {P}rogrammable {G}ate {A}rrays ({FPGA}s)},
+  Language                 = {en},
+  Note                     = {last access: 2015-02-09},
+  Organization             = {J.P. Morgan},
+  Url                      = {http://careers.jpmorgan.com/experienced/jpmorgan/jobs/businesses/ib/technology/advances#Field_Programmable_Gate_Arrays__FPGAs_},
+  Year                     = {2015},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {FPGA, finance},
+  Cds_read                 = {2013-12-02},
+  Cds_review               = {two-page presentation about FPGAs in finance},
+  File                     = {jpmorgan_15_factsheet.pdf:jpmorgan_15_factsheet.pdf:PDF;jpmorgan_15.pdf:jpmorgan_15.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.02}
+}
+
+@Electronic{cisco_14,
+  Title                    = {{C}isco {V}isual {N}etworking {I}ndex: {G}lobal {M}obile {D}ata {T}raffic {F}orecast {U}pdate, 2013–2018},
+  HowPublished             = {\url{http://www.cisco.com/en/US/solutions/collateral/ns341/ns525/ns537/ns705/ns827/white_paper_c11-520862.html}},
+  Language                 = {en},
+  Month                    = feb,
+  Note                     = {last access 2014-07-02},
+  Organization             = {Cisco},
+  Url                      = {http://www.cisco.com/en/US/solutions/collateral/ns341/ns525/ns537/ns705/ns827/white_paper_c11-520862.html},
+  Year                     = {2014},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {HPC, cloud, traffic, internet, prediction},
+  Cds_read                 = {2014-02-07},
+  Cds_review               = {80% traaffic increase in 2013 compared to 2012, another 10x increase until 2018},
+  File                     = {cisco_14.pdf:cisco_14.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Manual{cuda14,
+  Title                    = {{CUDA} {C} {P}rogramming {G}uide},
+  Edition                  = {{PG-02829-001\_v6.5}},
+  Month                    = {aug},
+  Organization             = {NVIDIA},
+  Year                     = {2014},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.01.13},
+  Url                      = {http://docs.nvidia.com/cuda/pdf/CUDA_C_Programming_Guide.pdf}
+}
+
+@Standard{DVBRCS2_14,
+  Title                    = {{D}igital {V}ideo {B}roadcasting ({DVB}); {S}ecocond {G}eneration {DVB}; {I}nteractive {S}atellite {S}ystem ({DVB}-{RCS}2); {P}art 2: {L}ower {L}ayers for {S}atellite standard; {ETSI} {EN} 301 545-2 {V}1.2.1},
+  Organization             = {ETSI},
+  Month                    = {Apr.},
+  Year                     = {2014},
+
+  Owner                    = {Imran},
+  Timestamp                = {2015.01.18}
+}
+
+@Standard{DVBRCS2_14a,
+  Title                    = {{D}igital {V}ideo {B}roadcasting ({DVB}); {S}ecocond {G}eneration {DVB}; {I}nteractive {S}atellite {S}ystem ({DVB}-{RCS}2); {P}art 4: {G}uidelines for {I}mplementation and {U}se of {EN} 301 545-2; {ETSI} {TR} 101 545-4 {V}1.1.1},
+  Month                    = {Apr.},
+  Year                     = {2014},
+
+  Owner                    = {Imran},
+  Timestamp                = {2015.01.18}
+}
+
+@Misc{etsi_14,
+  Title                    = {{Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications} {Part II: S2-Extensions (DVB-S2X) - (Optional)} {DVB Document A83-2}},
+  Month                    = {mar},
+  Year                     = {2014},
+
+  Institution              = {ETSI},
+  Organization             = {European Telecommunications Standards Institute},
+  Owner                    = {schlaefer},
+  Timestamp                = {2015.11.19}
+}
+
+@Electronic{heise_14,
+  Title                    = {{W}eltweiter mobiler {D}atenverkehr wuchs 2013 um 80 {P}rozent},
+  HowPublished             = {\url{http://www.heise.de/newsticker/meldung/Weltweiter-mobiler-Datenverkehr-wuchs-2013-um-80-Prozent-2106758.html}},
+  Language                 = {de},
+  Month                    = feb,
+  Note                     = {last access 2014-07-02},
+  Organization             = {heise online},
+  Url                      = {http://www.heise.de/newsticker/meldung/Weltweiter-mobiler-Datenverkehr-wuchs-2013-um-80-Prozent-2106758.html},
+  Year                     = {2014},
+
+  Abstract                 = {Ende 2013 flossen 1,5 Exabyte Daten über mobile Datenverbindungen, ergab der jüngste Cisco Visual Networking Index. 2018 sollen es zehnmal so viel sein.},
+  Cds_grade                = {4},
+  Cds_keywords             = {HPC, cloud, traffic, internet},
+  Cds_read                 = {2014-02-07},
+  File                     = {heise_14.pdf:heise_14.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Manual{jetson14,
+  Title                    = {{J}etson {TK}1 {D}evelopment {K}it - {U}ser {G}uide},
+
+  Address                  = {Santa Clara, CA, USA},
+  Edition                  = {01},
+  Month                    = {Nov},
+  Note                     = {DA-07498-001},
+  Organization             = {NVIDIA Corporation},
+  Year                     = {2014},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.10.22},
+  Url                      = {https://developer.download.nvidia.com/embedded/jetson/TK1/docs/2_GetStart/Jeston_TK1_User_Guide.pdf}
+}
+
+@Misc{project14,
+  Title                    = {{P}roject {J}upyter},
+  HowPublished             = {Online},
+  Year                     = {2014},
+
+  Owner                    = {varela},
+  Timestamp                = {2017.08.22},
+  Url                      = {http://jupyter.org/}
+}
+
+@Manual{tegra14,
+  Title                    = {{T}egra {K}1 {M}obile {P}rocessor, {T}echnical {R}eference {M}anual},
+  Edition                  = {{DP-06905-001\_v03p}},
+  Month                    = {oct},
+  Organization             = {NVIDIA},
+  Year                     = {2014},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.01.13}
+}
+
+@Misc{2013,
+  Title                    = {{Universal Verification Methodology}},
+  HowPublished             = {\\ \url{http://www.accellera.org/community/uvm}},
+  Month                    = {{ May }},
+  Year                     = {2013},
+
+  Owner                    = {Brehm},
+  Timestamp                = {2013.05.26},
+  Url                      = {{http://www.accellera.org/community/uvm}}
+}
+
+@Misc{2013a,
+  Title                    = {{X}ilinx {L}ogi{CORE} {IP} {R}eed-{S}olomon {D}ecoder},
+  HowPublished             = {{{http://www.xilinx.com/products/intellectual-property/DO-DI-RSD.htm}}},
+  Month                    = {March},
+  Year                     = {2013},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2013.03.05}
+}
+
+@Misc{accelera_uvm,
+  Title                    = {{Universal Verification Methodology}},
+  HowPublished             = {\\ \url{http://www.accellera.org/community/uvm}},
+  Month                    = {{ May }},
+  Year                     = {2013},
+
+  Owner                    = {Brehm},
+  Timestamp                = {2013.05.26},
+  Url                      = {{http://www.accellera.org/community/uvm}}
+}
+
+@Misc{cisco13,
+  Title                    = {{C}isco {V}isual {N}etworking {I}ndex: {G}lobal {M}obile {D}ata {T}raffic {F}orecast {U}pdate, 2012–2017},
+  Month                    = {February},
+  Year                     = {2013},
+
+  Institution              = {Cisco Systems},
+  Owner                    = {Gimmler},
+  Timestamp                = {2013.08.22}
+}
+
+@Electronic{jpmorgan_13,
+  Title                    = {{I}nnovation in {I}nvestment {B}anking {T}echnology - {F}ield {P}rogrammable {G}ate {A}rrays ({FPGA}s)},
+  Language                 = {en},
+  Note                     = {last access: 2014-09-16},
+  Organization             = {J.P. Morgan},
+  Url                      = {http://techcareers.jpmorgan.com/cm/BlobServer/fpga_emea.pdf?blobkey=id&blobwhere=1320595530514&blobcol=urldata&blobtable=MungoBlobs},
+  Year                     = {2013},
+
+  Cds_grade                = {3},
+  Cds_keywords             = {FPGA, finance},
+  Cds_read                 = {2013-12-02},
+  Cds_review               = {two-page presentation about FPGAs in finance},
+  File                     = {jpmorgan_13.pdf:jpmorgan_13.pdf:PDF},
+  Keywords                 = {finance},
+  Owner                    = {CdS},
+  Timestamp                = {2013.12.02}
+}
+
+@Manual{tesla13,
+  Title                    = {{T}esla {K}20{X} {GPU} {A}ccelerator, {B}oard {S}pecification},
+  Edition                  = {{BD-06397-001\_v07}},
+  Month                    = {jul},
+  Organization             = {NVIDIA},
+  Year                     = {2013},
+
+  Owner                    = {varela},
+  Timestamp                = {2015.01.13}
+}
+
+@Misc{xilinx_13,
+  Title                    = {{X}ilinx {L}ogi{CORE} {IP} {R}eed-{S}olomon {D}ecoder},
+  HowPublished             = {{{http://www.xilinx.com/products/intellectual-property/DO-DI-RSD.htm}}},
+  Month                    = {March},
+  Year                     = {2013},
+
+  Owner                    = {Scholl},
+  Timestamp                = {2013.03.05}
+}
+
+@Misc{2012a,
+  Title                    = {{Q}uant{L}ib - {A} free/open-source library for quantitative finance},
+  HowPublished             = {\url{http://quantlib.org}},
+  Month                    = mar,
+  Year                     = {2012},
+
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.05}
+}
+
+@Misc{2012b,
+  Title                    = {{S}ynopsys {P}rocessor {D}esigner},
+  HowPublished             = {\\ \url{http://www.synopsys.com/Systems/BlockDesign/ProcessorDev/}},
+  Month                    = {{ June }},
+  Year                     = {2012},
+
+  Owner                    = {Brehm},
+  Timestamp                = {2012.06.26},
+  Url                      = {http://www.synopsys.com/Systems/BlockDesign/ProcessorDev/}
+}
+
+@Misc{2012c,
+  Title                    = {{S}ynopsys {V}irtualizer},
+  HowPublished             = {\\ \url{http://www.synopsys.com/Systems/VirtualPrototyping/Pages/Virtualizer.aspx}},
+  Month                    = {{ June }},
+  Year                     = {2012},
+
+  Owner                    = {Brehm},
+  Timestamp                = {2012.06.26},
+  Url                      = {http://www.synopsys.com/Systems/VirtualPrototyping/Pages/Virtualizer.aspx}
+}
+
+@Article{ieee11,
+  Title                    = {{IEEE} {S}tandard for {S}tandard {S}ystem{C} {L}anguage {R}eference {M}anual},
+  Journal                  = {IEEE Std 1666-2011 (Revision of IEEE Std 1666-2005)},
+  Year                     = {2012},
+
+  Month                    = {Jan},
+  Pages                    = {1-638},
+
+  Doi                      = {10.1109/IEEESTD.2012.6134619},
+  Keywords                 = {ANSI standards;C++ language;IEEE standards;ANSI standard C++ class library;IEEE standard;SystemC class library;Computer languages;Discrete event simulation;Electronic design automation and methodology;Embedded software;Hardware design languages;IEEE standards;Programming;System-on-a-chip;C++;IEEE 1666;SystemC;computer languages;digital systems;discrete event simulation;electronic design automation;electronic system level;electronic systems;embedded software;fixed-point;hardware description language;hardware design;hardware verification;system modeling;system-on-chip;transaction level}
+}
+
+@Misc{quantlib,
+  Title                    = {{Q}uant{L}ib - {A} free/open-source library for quantitative finance},
+  HowPublished             = {\url{http://quantlib.org}},
+  Month                    = mar,
+  Note                     = {last access 2014-07-02},
+  Year                     = {2012},
+
+  Owner                    = {CdS},
+  Timestamp                = {2012.03.05}
+}
+
+@Misc{synopsys_pd,
+  Title                    = {{S}ynopsys {P}rocessor {D}esigner},
+  HowPublished             = {\\ \url{http://www.synopsys.com/Systems/BlockDesign/ProcessorDev/}},
+  Month                    = {{ June }},
+  Year                     = {2012},
+
+  Owner                    = {Brehm},
+  Timestamp                = {2012.06.26},
+  Url                      = {http://www.synopsys.com/Systems/BlockDesign/ProcessorDev/}
+}
+
+@Misc{synopsys_vpa,
+  Title                    = {{S}ynopsys {V}irtualizer},
+  HowPublished             = {\\ \url{http://www.synopsys.com/Systems/VirtualPrototyping/Pages/Virtualizer.aspx}},
+  Month                    = {{ June }},
+  Year                     = {2012},
+
+  Owner                    = {Brehm},
+  Timestamp                = {2012.06.26},
+  Url                      = {http://www.synopsys.com/Systems/VirtualPrototyping/Pages/Virtualizer.aspx}
+}
+
+@TechReport{altera_11,
+  Title                    = {{I}mplementing {FPGA} {D}esign with the {O}pen{CL} {S}tandard},
+  Institution              = {Altera Corporation},
+  Year                     = {2011},
+
+  Address                  = {\url{http://www.altera.com/literature/wp/wp-01173-opencl.pdf}},
+  Month                    = nov,
+  Note                     = {last access 2015-02-05},
+
+  Cds_grade                = {4},
+  Cds_keywords             = {FPGA, OpenCL, Methodology},
+  Cds_read                 = {2011-11-29},
+  Cds_review               = {white paper, overview of design methodology with OpenCL
+case study: Monte Carlo Black-Scholes
+
+signed into Altera OpenCL program 2011-11-30},
+  File                     = {altera_11.pdf:altera_11.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2015-02-05},
+  Url                      = {\url{http://www.altera.com/literature/wp/wp-01173-opencl.pdf}}
+}
+
+@Electronic{cdp_11,
+  Title                    = {{C}loud {C}omputing – {T}he {IT} {S}olution for the 21st {C}entury},
+  Language                 = {en},
+  Note                     = {last access 2014-02-07},
+  Organization             = {Carbon Disclosure Project},
+  Url                      = {\url{https://www.cdp.net/Documents/Cloud-Computing-The-IT-Solution-for-the-21st-Century.pdf}},
+  Year                     = {2011},
+
+  Cds_grade                = {0},
+  Cds_keywords             = {cloud computing, carbon, power, energy efficiency},
+  File                     = {cdp_11.pdf:cdp_11.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2014.02.07}
+}
+
+@Article{misc_10,
+  Title                    = {{D}esigning {C}hips without {G}uarantees},
+  Journal                  = {Design \& Test of Computers, IEEE},
+  Year                     = {2010},
+  Number                   = {5},
+  Pages                    = {60--67},
+  Volume                   = {27},
+
+  Cb_grade                 = {SPP 1500},
+  Doi                      = {10.1109/MDT.2010.105},
+  File                     = {misc_10.pdf:misc_10.pdf:PDF},
+  Owner                    = {Brehm},
+  Timestamp                = {2011.01.21}
+}
+
+@Unpublished{_SASP09a,
+  Title                    = {{H}ardware {A}cceleration of {S}ignificance {M}ap {D}ecoding for the {H}.264/{AVC} {C}ontext {A}daptative {B}inary {D}ecoder},
+
+  Month                    = may,
+  Year                     = {2009},
+
+  Cds_grade                = {5},
+  Cds_keywords             = {AVC, H.264, MPEG-4, VLSI, CABAC},
+  Cds_read                 = {2009-05-15},
+  Cds_review               = {Strongest points:
+Very good overview of CABAC / CABAD and of related work
+Paper is well-structured and language is very good
+Decoding process and presented decoder structure can be understood very well
+
+Weakest points:
+the topic: a hardware acceleration unit is presented, but no connection to application specific processors is made
+
+The presentation of your work and the essential context is very good. The paper is fun to read and it is absolutely clear what you have done and what the results are. You should have included at least one paragraph of how your unit can act in an ASIP environment, with respect to interface and communication needs - at the moment, the paper is out of topic of the symposium.},
+  File                     = {_SASP09a.pdf:_SASP09a.pdf:PDF},
+  Owner                    = {CdS},
+  Timestamp                = {2009.05.15}
+}
+
+@Manual{cell09,
+  Title                    = {{C}ell {B}roadband {E}ngine {P}rogramming {H}andbook {V}1.12},
+  Month                    = apr,
+  Organization             = {Business Machines Corporation (IBM)},
+  Year                     = {2009},
+
+  Keywords                 = {IBM Cell processor},
+  Owner                    = {lehnigk},
+  Timestamp                = {2010.05.20}
+}
+
+@Article{ieee08,
+  Title                    = {{D}esign in the late- and post-silicon eras},
+  Journal                  = {IEEE Design \& Test of Computers},
+  Year                     = {2008},
+
+  Month                    = jul # {--} # aug,
+  Volume                   = {Vol. 25, Issue 4},
+
+  File                     = {ieee08.pdf:ieee08.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2009.09.04}
+}
+
+@Misc{2006,
+  Title                    = {{LDPC@work: International Workshop on VLSI-Architectures for LDPC Decoders}},
+  HowPublished             = {{{https://dbkn.ismb.it/DBKN\%20Content/4/ldpc-codes-work/view}}},
+  Month                    = oct,
+  Year                     = {2006},
+
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.13}
+}
+
+@Misc{ldpcwork:06,
+  Title                    = {{LDPC@work: International Workshop on VLSI-Architectures for LDPC Decoders}},
+  HowPublished             = {{{https://dbkn.ismb.it/DBKN\%20Content/4/ldpc-codes-work/view}}},
+  Month                    = oct,
+  Year                     = {2006},
+
+  Owner                    = {vogt},
+  Timestamp                = {2006.12.13}
+}
+
+@Manual{synthesis06,
+  Title                    = {{Synthesis and Simulation Design Guide 8.2i}},
+  Organization             = {XILINX},
+  Year                     = {2006},
+
+  HowPublished             = {{{www.xilinx.com}}},
+  Optauthor                = {Xilinx Inc.},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Other{2005a,
+  Title                    = {{Digital Video Broadcasting (DVB); Interaction Channel for Satellite Distribution System, EN 301 790 v1.4.1}},
+  Abstract                 = {DVB RCS standard},
+  Month                    = dec,
+  Number                   = {EN 301 790},
+  Organization             = {ETSI},
+  Owner                    = {Gimmler},
+  Revision                 = {v1.4.1},
+  Timestamp                = {2008.11.26},
+  Url                      = {www.dvb.org},
+  Year                     = {2005}
+}
+
+@Manual{c65lp_st_dpreg05,
+  Title                    = {{C65LP\_ST\_DPREG 1.0 User Manual}},
+  Month                    = sep,
+  Organization             = {STM},
+  Year                     = {2005},
+
+  File                     = {c65lp_st_dpreg05.pdf:c65lp_st_dpreg05.pdf:PDF},
+  HowPublished             = {{Company Confidential}},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Other{dvbrcs_05,
+  Title                    = {{Digital Video Broadcasting (DVB); Interaction Channel for Satellite Distribution System, EN 301 790 v1.4.1}},
+  Abstract                 = {DVB RCS standard},
+  Month                    = dec,
+  Number                   = {EN 301 790},
+  Organization             = {ETSI},
+  Owner                    = {Gimmler},
+  Revision                 = {v1.4.1},
+  Timestamp                = {2008.11.26},
+  Url                      = {www.dvb.org},
+  Year                     = {2005}
+}
+
+@Proceedings{ieee05,
+  Title                    = {{IEEE} {M}icro},
+  Year                     = {2005},
+  Month                    = nov # {--} # dec,
+  Note                     = {Reliability-Aware Microarchitecture},
+  Number                   = {6},
+  Volume                   = {25},
+
+  File                     = {ieee05.pdf:ieee05.pdf:PDF},
+  Keywords                 = {Reliability},
+  Owner                    = {May},
+  Timestamp                = {2010.09.24}
+}
+
+@Misc{2003b,
+  Title                    = {{Xilinx Inc. Fast Fourier Transform v2.0}},
+  HowPublished             = {{}},
+  Month                    = mar,
+  Year                     = {2003},
+
+  Key                      = {xilinx_fft},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{2003c,
+  Title                    = {{Xilinx Inc. CORDIC v2.0}},
+  HowPublished             = {{{www.xilinx.com/ipcenter}}},
+  Month                    = mar,
+  Year                     = {2003},
+
+  Key                      = {xilinx_cordic},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@InProceedings{iccadt2_03,
+  Title                    = {{T}utorial 2: {L}eakage {I}ssues in {IC} {D}esign: {T}rends, {E}stimation, and {A}voidance},
+  Booktitle                = {ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design},
+  Year                     = {2003},
+
+  Address                  = {Washington, DC, USA},
+  Pages                    = {.11},
+  Publisher                = {IEEE Computer Society},
+
+  Doi                      = {http://dx.doi.org/10.1109/ICCAD.2003.145},
+  File                     = {iccadt2_03.ppt:iccadt2_03.ppt:PowerPoint},
+  ISBN                     = {1-58113-762-1},
+  Owner                    = {May},
+  Timestamp                = {2009.12.03}
+}
+
+@Manual{pcd03v03,
+  Title                    = {{PCD03V 3GPP Turbo and Viterbi Decoder}},
+
+  Address                  = {Payneham South, South Australia, Australia},
+  Month                    = jun,
+  Note                     = {Version 1.12},
+  Organization             = {Small World Communications},
+  Year                     = {2003},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{xilinx03,
+  Title                    = {{Xilinx Inc. Fast Fourier Transform v2.0}},
+  HowPublished             = {{}},
+  Month                    = mar,
+  Year                     = {2003},
+
+  Key                      = {xilinx_fft},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{xilinx03a,
+  Title                    = {{Xilinx Inc. CORDIC v2.0}},
+  HowPublished             = {{{www.xilinx.com/ipcenter}}},
+  Month                    = mar,
+  Year                     = {2003},
+
+  Key                      = {xilinx_cordic},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{2002,
+  Title                    = {{Xilinx Inc. Sine/Cosine Look-Up Table v4.2}},
+  HowPublished             = {{{www.xilinx.com/ipcenter}}},
+  Month                    = nov,
+  Year                     = {2002},
+
+  Key                      = {xilinx_lut},
+  Optauthor                = {Xilinx Inc.},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{xilinx02,
+  Title                    = {{Xilinx Inc. Sine/Cosine Look-Up Table v4.2}},
+  HowPublished             = {{{www.xilinx.com/ipcenter}}},
+  Month                    = nov,
+  Year                     = {2002},
+
+  Key                      = {xilinx_lut},
+  Optauthor                = {Xilinx Inc.},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Other{2001a,
+  Title                    = {{Interaction Channel for Digital Terrestrial Television}},
+  Month                    = aug,
+  Number                   = {EN 301 958},
+  Organization             = {ETSI},
+  Owner                    = {Gimmler},
+  Revision                 = {v1.1.1,pp. 28-30},
+  Timestamp                = {2008.11.26},
+  Year                     = {2001}
+}
+
+@Proceedings{ieee01,
+  Title                    = {{IEEE Transactions on Information Theory}},
+  Year                     = {2001},
+  Month                    = feb,
+  Note                     = {Special Issue on Codes on Graphs and Iterative Algorithms},
+  Volume                   = {47},
+
+  Key                      = {TrIT},
+  Optnumber                = {2},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Other{interaction01,
+  Title                    = {{Interaction Channel for Digital Terrestrial Television}},
+  Month                    = aug,
+  Number                   = {EN 301 958},
+  Organization             = {ETSI},
+  Owner                    = {Gimmler},
+  Revision                 = {v1.1.1,pp. 28-30},
+  Timestamp                = {2008.11.26},
+  Year                     = {2001}
+}
+
+@Manual{pcd0301,
+  Title                    = {{PCD03 3GPP Turbo Decoder}},
+
+  Address                  = {Payneham South, South Australia, Australia},
+  Month                    = mar,
+  Note                     = {Version 0.4},
+  Organization             = {Small World Communications},
+  Year                     = {2001},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Manual{tms320c641601,
+  Title                    = {{TMS320C6416 Fixed-Point Digital Signal Processor}},
+
+  Address                  = {Houston, Texas, USA},
+  Month                    = feb,
+  Note                     = {Product Preview SPRS164},
+  Organization             = {Texas Instruments Incorporated},
+  Year                     = {2001},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Manual{map03t/map04t00,
+  Title                    = {{MAP03T/MAP04T Very High Speed MAP Decoder}},
+
+  Address                  = {Payneham South, South Australia, Australia},
+  Month                    = dec,
+  Note                     = {Version 3.1},
+  Organization             = {Small World Communications},
+  Year                     = {2000},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{1999a,
+  Title                    = {{Project Broadband Radio Access Networks (BRAN); Hyplerlan Type 2}},
+  Month                    = oct,
+  Year                     = {1999},
+
+  Organization             = {ETSI},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Type                     = {Technical Spezification; Physical Layer}
+}
+
+@Manual{map04b99,
+  Title                    = {{MAP04B 16 State MAP Decoder}},
+
+  Address                  = {Payneham South, South Australia, Australia},
+  Month                    = aug,
+  Note                     = {Version 1.3},
+  Organization             = {Small World Communications},
+  Year                     = {1999},
+
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26}
+}
+
+@Misc{project99,
+  Title                    = {{Project Broadband Radio Access Networks (BRAN); Hyplerlan Type 2}},
+  Month                    = oct,
+  Year                     = {1999},
+
+  Organization             = {ETSI},
+  Owner                    = {Gimmler},
+  Timestamp                = {2008.11.26},
+  Type                     = {Technical Spezification; Physical Layer}
+}
+
+@inproceedings{gholi_19,
+author = {Ghose, Saugata and Li, Tianshi and Hajinazar, Nastaran and Senol Cali, Damla and Mutlu, Onur},
+year = {2019},
+month = {06},
+pages = {93-93},
+title = {{Demystifying Complex Workload-DRAM Interactions: An Experimental Study}}
+}
+
+@comment{jabref-meta: databaseType:biblatex;}
+
+@comment{jabref-meta: selector_keywords:ABP;AGWehn;ASD;ASIP;BCH;Convol
+utional;InfTheory;LDPC;LPDecoding;MBBP;MIMO;MPSoC;OSD;Power;random num
+bers;Reed-Solomon;Reliability;Review;Sensor;Standard;Turbo;finance;non
+ binary LDPC;}
+
+@comment{jabref-meta: selector_author:Alexander Worm;Christian Brehm;C
+hristian de Schryver;Christian Neeb;Frank Gilbert;Frank Kienle;Friedbe
+rt Berens;Heiko Michel;Matthias Alles;Michael J. Thul;Norbert Wehn;Tim
+o Vogt;}
+
diff --git a/test.csv b/test.csv
new file mode 100644
index 0000000..f46f806
--- /dev/null
+++ b/test.csv
@@ -0,0 +1,7 @@
+a,b
+1,1
+2,2
+3,3
+4,4
+5,5
+6,6
\ No newline at end of file
diff --git a/tool_demo.tex b/tool_demo.tex
new file mode 100644
index 0000000..e5f31ce
--- /dev/null
+++ b/tool_demo.tex
@@ -0,0 +1,181 @@
+\makeatletter
+\p@=1bp
+\makeatother\documentclass[10pt,ngerman,oneside,twocolumn,a4paper]{article}
+\usepackage{graphicx}
+%% Font: Times
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage{tabularx}
+\usepackage{ragged2e}
+\usepackage[singlelinecheck=false]{caption}
+\usepackage[T1]{fontenc}
+\usepackage[numbers]{natbib}
+\usepackage{amsmath}
+\def\figurename{Bild}%
+\def\tablename{Tabelle}%
+\RequirePackage[blocks]{authblk}
+\usepackage{babel}
+\pagestyle{empty}
+\hoffset-1in
+\voffset-1in
+\oddsidemargin20truemm
+
+\makeatletter
+\let\ps@plain\ps@empty
+\def\@xivpt{14bp}
+
+\setcounter{secnumdepth}{4}
+\columnsep5mm
+\def\@sect#1#2#3#4#5#6[#7]#8{%
+  \ifnum #2>\c@secnumdepth
+    \let\@svsec\@empty
+  \else
+    \refstepcounter{#1}%
+    \protected@edef\@svsec{%
+      \ifnum #2<4
+        \hb@xt@10mm{\csname the#1\endcsname}\relax
+      \else
+        \hb@xt@12mm{\csname the#1\endcsname}\relax
+      \fi}%
+  \fi
+  \@tempskipa #5\relax
+  \ifdim \@tempskipa>\z@
+    \begingroup
+      #6{%
+        \@hangfrom{\hskip #3\relax\@svsec}%
+          \interlinepenalty \@M #8\@@par}%
+    \endgroup
+    \csname #1mark\endcsname{#7}%
+    \addcontentsline{toc}{#1}{%
+      \ifnum #2>\c@secnumdepth \else
+        \protect\numberline{\csname the#1\endcsname}%
+      \fi
+      #7}%
+  \else
+    \def\@svsechd{%
+      #6{\hskip #3\relax
+      \@svsec #8}%
+      \csname #1mark\endcsname{#7}%
+      \addcontentsline{toc}{#1}{%
+        \ifnum #2>\c@secnumdepth \else
+          \protect\numberline{\csname the#1\endcsname}%
+        \fi
+        #7}}%
+  \fi
+  \@xsect{#5}}
+    %
+\renewcommand\LARGE{\@setfontsize\LARGE{16}{20}}
+\def\abstract#1{\def\@abstract{#1}}
+\def\abstractEn#1{\def\@abstractEn{#1}}
+\def\titleEn#1{\def\@titleEn{#1}}
+%% Def. Titelei
+\headheight0bp
+\headsep0mm
+\topskip10bp
+\topmargin18mm
+\textwidth170mm
+\textheight60\baselineskip
+\def\@maketitle{%
+  \newpage
+  \null
+  \let \footnote \thanks
+    {\LARGE\bfseries\RaggedRight \@title \par}%
+    %{\LARGE\bfseries\RaggedRight \@titleEn \par}%
+    \vskip 1\baselineskip%
+    {\normalsize
+      % \lineskip 1ex%
+      \@author\par}%
+    \vskip 2\baselineskip%
+    {\section*{Kurzfassung}
+      \@abstract}%
+    %\vskip \baselineskip%
+    %{\section*{Abstract}
+    %  \@abstractEn}%
+  \par
+  \vskip 3\baselineskip}
+
+\renewcommand\section{\@startsection {section}{1}{\z@}%
+                                   {-3.5ex \@plus -1ex \@minus -.2ex}%
+                                   {\baselineskip}%
+                                   {\normalfont\Large\bfseries\RaggedRight}}
+\renewcommand\subsection{\@startsection{subsection}{2}{\z@}%
+                                     {\baselineskip}%
+                                     {1ex}%
+                                     {\normalfont\large\bfseries\RaggedRight}}
+\renewcommand\subsubsection{\@startsection{subsubsection}{3}{\z@}%
+                                     {1\baselineskip}%
+                                     {3bp}%
+                                     {\normalfont\normalsize\bfseries\RaggedRight}}
+\renewcommand\paragraph{\@startsection{paragraph}{4}{\z@}%
+                                    {1\baselineskip\@plus1ex \@minus.2ex}%
+                                    {3bp}%
+                                    {\normalfont\normalsize\RaggedRight}}
+\renewcommand\subparagraph{\@startsection{subparagraph}{5}{\parindent}%
+                                       {3.25ex \@plus1ex \@minus .2ex}%
+                                       {-1em}%
+                                      {\normalfont\normalsize\bfseries\RaggedRight}}
+\affilsep0pt
+\parindent\p@
+\makeatother
+\bibsep3bp
+\raggedbottom
+\DeclareCaptionLabelSeparator{enskip}{\enskip}
+\captionsetup{labelsep=enskip,justification=RaggedRight,labelfont=bf,skip=10pt}
+\renewcommand\bibsection{\section*{Literatur}}
+\title{Der Open-Source-DRAM-Simulator DRAMSys4.0}
+%\titleEn{Title of contribution (16 pt bold)}
+\author{M.Sc. Lukas Steiner$\,^1$,
+Dr.-Ing. Matthias Jung$\,^2$,
+Prof. Dr.-Ing. Norbert Wehn$\,^1$
+}
+\affil{%
+1: Technische Universität Kaiserslautern, Germany \{lsteiner, wehn\}@eit.uni-kl.de\\
+2: Fraunhofer IESE, Kaiserslautern, Germany, matthias.jung@iese.fraunhofer.de
+}
+
+\abstract{%
+DRAMSys4.0 ist ein schnelles und flexibles Open-Source-Simulations-Framework für \textit{Dynamic Random Access Memory} (DRAM), das auf dem SystemC-TLM-2.0-Standard basiert. Das Framework wurde an der Technischen Universität Kaiserslautern und am Fraunhofer IESE entwickelt. Ziel ist es, die Herausforderungen heutiger Speichersysteme in Bezug auf Anwendungen, Leistungsaufnahme, Temperaturverteilung, Retention-Fehler und verschiedene DRAM-Architekturen zu bewältigen.
+}%
+
+\begin{document}
+
+\maketitle
+
+\section*{DRAMSys4.0}
+%
+DRAMSys~\cite{stejun_20} besteht aus Modellen, welche die DRAM-Funktionalität, -Leistung und -Temperatur widerspiegeln. Mit diesen Modellen können Systementwickler die begrenzenden Parameter und Probleme im Hinblick auf die aktuellen DRAM-Standards in ihrem Systemkontext analysieren. Das Framework bietet ein benutzerfreundliches Trace-Analyzer-Tool für tiefgreifende Analysen und Erkenntnisgewinne. Mit diesen Erkenntnissen ist der Entwickler in der Lage, das DRAM-Subsystem in Bezug auf die Controller-Architektur, das Leistungs- und Temperaturmanagement sowie die Bausteinauswahl und die Kanalkonfiguration für eine bestimmte Anwendung zu optimieren.
+\begin{figure}[h]
+    \includegraphics[width=1.0\columnwidth]{dramsys-traceanalyzer-fraunhofer-iese.png}
+    \caption{DRAMSys Trace Analyzer}
+    \centering
+\end{figure}
+
+DRAMSys hilft Ihnen, den Entwurfsraum des DRAM-Subsystems zu untersuchen, um instinktives Handeln durch simulationsgestützte Fakten zu ersetzen. Die Anwendungsfälle für den Simulator sind vielfältig:
+\begin{itemize}
+\item Welche DRAM-Konfiguration oder welcher DRAM-Standard passt am besten zu meinem System?
+\item Wie werden neue Standards wie DDR5 oder LPDDR5 das Verhalten meines Systems verändern? Bringen sie einen neuen Nutzen für mein System?
+\item  Wie sollte ich den Speicher-Controller konfigurieren, um maximale Leistung oder minimalen Energieverbrauch zu errreichen?
+\item Wie kann ich meine Systemanwendung im Hinblick auf das verwendete DRAM-Subsystem optimieren?
+\end{itemize}
+Die Open-Source-Version von DRAMSys wird auf GitHub gehostet\footnote{https://github.com/tukl-msd/DRAMSys}. Das Repository wird regelmäßig mit neuen Funktionen aktualisiert.
+%
+%
+%
+Die Funktionen von DRAMSys4.0 auf einen Blick:
+\begin{itemize}
+    \setlength\itemsep{0em}
+    \item TLM2.0-AT-konform
+    \item Unterstützung für DDR3, DDR4, DDR5, LPDDR4, LPDDR5\footnote{Derzeit in Entwicklung} Wide I/O 1/2, GDDR5, GDDR5X, GDDR6 und HBM1/2
+    \item Scheduling Policies (FIFO, FR-FCFS und FR-FCFS mit read/write grouping)
+    \item Page Policies (open, closed, open adaptive und closed adaptive)
+    \item Refresh-Strategien (all-bank refresh, per-bank refresh, same-bank refresh, pulled-in refresh, postponed refresh)
+    \item Power-Down-Strategien (PDNA, PDNP, SREF, …)
+    \item Schätzung der Leistungsaufnahme
+    \item Thermische Simulation
+    \item Trace Analyzer für die visuelle Ergebnisanalyse
+\end{itemize}
+%
+\bibliographystyle{IEEEtran}
+\bibliography{IEEEabrv,references_JR}
+\end{document}
+