39 lines
3.6 KiB
TeX
39 lines
3.6 KiB
TeX
\section{Introduction}
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\label{sec:introduction}
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%vlt noch warum DRAMs immer mehr eingesetzt werden
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Today's computing systems accompany us in almost all areas of life in the form of smart devices, computers, or game consoles.
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With the increasing performance requirements on these devices, not only faster processors are needed, but also high-performance memory systems, namely dynamic random access memories, which are supposed to deliver a lot of bandwidth at low latency.
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While these storage systems are very complex and offer a lot of room for configuration, e.g., the \revabbr{dynamic random-access memory}{DRAM} standard, the memory controller configuration or the address mapping, there are different requirements for the very different applications\cite{Gomony2012}.
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Consequently, system designers are entrusted with the complex task of finding the most effective configurations that match the performance and power contraints with good optimizations applied for the specific use case.
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\input{img/thesis.tikzstyles}
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\begin{figure}[!ht]
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\begin{center}
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\tikzfig{img/cloud}
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\caption{Exemplary DRAM configuration parameters to consider when designing a system.}
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\label{fig:cloud}
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\end{center}
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\end{figure}
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For the exploration of the design space of these configurations it is impractical to use real systems as they are too cost-intensive and not modifyable and therefore not suitable for rapid prototyping.
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To overcome this limitation, it is important to simulate the memory system using a simulation framework with sufficient accuracy.
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Such a simulation framework is DRAMSys \cite{Steiner2020, Jung2017}, which is based on SystemC \revabbr{transaction level modeling}{TLM} and enables the fast simulation of numerous DRAM standards and controller configurations with cycle-accuracy.
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Stimuli for the memory system can either be generated using a prerecorded trace file with timestamps, a traffic generator that acts as a state machine and initiates different request patterns, or a detailed processor model of the gem5 \cite{Binkert2011} simulation framework.
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However, the two former methods lack in accurary whereas the latter may provide the sufficient precision but is a very time-consuming effort.
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To fill this gap of fast but accurate traffic generation, a new simulation frontend for DRAMSys is developed and presented in this thesis.
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The methology this new framework is based on is dynamic binary instrumentation.
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It allows the extraction of memory accesses of multi-threaded applications while they are executed on real hardware.
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These memory access traces are then played back using a simplified core model and are filtered by a cache model before the memory requests are passed to the DRAM.
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This allows an accurate modeling of the system and the variation of numerous configuration parameters in a short time.
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The remainder of the thesis is structured as follows:
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In Section \ref{sec:dynamorio} the used dynamic binary instrumentation framework, DynamoRIO, is introduced.
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Section \ref{sec:systemc} presents the modeling language SystemC, on which the developed core and cache models are based on.
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After that, Section \ref{sec:caches} gives a short overview of modern cache architectures and their high-level implementations.
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Section \ref{sec:dramsys} introduces the DRAMSys simulation framework and its basic functionalities.
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Section \ref{sec:implementation} explains the implementation of the cache model, the processor model and the instrumentation tool in detail.
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In Section \ref{sec:simulation_results} the accuracy of the new framework is compared against the gem5 and Ramulator \cite{Kim2016} simulators, whereas Section \ref{sec:future_work} denotes future improvements that can be achieved.
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