40 lines
963 B
TeX
40 lines
963 B
TeX
\section{Appendix}
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\label{sec:appendix}
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\subsection{Simulation Address Mappings}
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\label{sec:address_mappings}
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\begin{table}[!hbt]
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\caption{Memory configuration used in comparison simulations against gem5.}
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\begin{center}
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\begin{tabular}{|c|c|c|c|c|c|c|c|}
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\hline
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DRAM & \parbox{2.2cm}{\centering Ranks\\per Channel} & \parbox{2cm}{\centering Banks\\per Rank} & Rows & Columns & \parbox{2cm}{\centering Devices\\per Rank} & Width\\
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\hline
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\hline
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DDR3 & 2 & 8 & 65536 & 1024 & 8 & 8\\
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\hline
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DDR4 & 2 & 16 & 65536 & 1024 & 8 & 8\\
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\hline
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\end{tabular}
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\end{center}
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\end{table}
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\begin{table}[!hbt]
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\caption{Address mappings used in comparison simulations against gem5.}
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\begin{center}
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\begin{tabular}{|c|c|c|c|c|c|c|c|}
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\hline
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DRAM & Byte & Column & Bankgroup & Bank & Rank & Row\\
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\hline
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\hline
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DDR3 & 0-2 & 3-12 & - & 13-15 & 16 & 17-32 \\
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\hline
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DDR4 & 0-2 & 3-12 & 13-14 & 15-16 & 17 & 18-33 \\
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\hline
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\end{tabular}
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\end{center}
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\end{table}
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