\section{SystemC}
\label{sec:systemc}

This section covers the basics of virtual prototyping, SystemC and transaction level modeling.

\revabbr{Virtual prototypes}{VPs} are software models of physical hardware systems, that can be used for software development before the actual hardware is available.
They make it easier to test the product as VPs provide visiblity and controllability across the entire system and therefore reduce the time-to-market and development cost\cite{Antonino2018}.

SystemC is a C++ class library with an event-driven simulation kernel, used for developing complex system models (i.e. VPs) in a high-level language.
It is defined under the IEEE 1666-2011 standard \cite{IEEE2012} and provided as an open-source library by Accellera.

SystemC supports numerous abstraction levels for modeling systems, namely \textit{cycle-accurate}, which is the most accurate abstraction but also the slowest, \textit{approximateley-timed} and \textit{loosley-timed}.
The latter two abstraction levels belog to \revabbr{transaction level modeling}{TLM}, which will be discussed in the next section \ref{sec:tlm}.
One further abstraction level, \textit{untimed}, will not be topic of this thesis.

\subsection{Transaction Level Modeling}
\label{sec:tlm}

TLM abstracts the modeling of the communication between modules using so-called transactions, which are transferred through function calls \cite{Menard2017}.
In contrast to pin and cycle accurate models, this greatly reduces the simulation overhead at the cost of reduced accuracy.

Modules communicate with each other through \textit{initiator} sockets and \textit{target} sockets.
A processor for example sends requests to a memory using its initiator socket, whereas the memory responds trough its target socket.
Interconnect modules, which can be used to model a bus, use both sockets to communicate with both the initiator and the target modules.
This concept is illustrated in figure \ref{fig:tlm}.

The transaction object itself is a \revabbr{generic payload}{GP}, which consists of address, command, status and other information as well as the actual data to transfer.
GPs are transferred as references, avoiding the need to copy them between the modules.

\input{img/thesis.tikzstyles}
\begin{figure}[!ht]
\begin{center}
\tikzfig{img/tlm}
\caption{Forward and backward path between TLM sockets\cite{Menard2017}. $\blacksquare$ denotes an initiator socket, $\square$ denotes a target socket.}
\label{fig:tlm}
\end{center}
\end{figure}

In the \revabbr{loosley-timed}{LT} coding style, a transaction is blocking, meaning it will be modeled by only one function call.
This comes at the cost of limited timing accuracy as only the beginning and the end of the transaction are modeled as timing points and no other module can initiate transcations during this time.

The \revabbr{approximateley-timed}{AT} coding style is non-blocking and consists of a four-phase handshake:
\texttt{BEGIN\_REQ},
\texttt{END\_REQ},
\texttt{BEGIN\_RESP} and
\texttt{END\_RESP}.

When an initiator requests certain data from a target, it starts the transaction with the \texttt{BEGIN\_REQ} phase using its \texttt{nb\_transport\_fw()} method.
The target now enqueues the payload into its \revabbr{payload event queue}{PEQ} and pretends it has received the payload after the delay, the initiator has specified.
When the target is not ready yet to accept the requests, it defers its \texttt{END\_REQ} until it is.
During this time, the initiator is blocked from sending further requests to other modules as the target applies \textit{back pressure} on the initiator.
This concept is called the \textit{exclusion rule}.

The target now prepares the response and sends the \texttt{BEGIN\_RESP} phase through its \texttt{nb\_transport\_bw()} method when the data is available.
The initiator can now also apply back pressure to the target by deferring its \texttt{END\_RESP} phase.
When the \texttt{END\_RESP} phase is received by the target, the transaction is completed.
Figure \ref{fig:tlm_at} shows an exemplary handshake sequence diagram with all four phases.

\begin{figure}[!ht]
\begin{center}
\tikzfig{img/tlm_at}
\caption{Sequence diagram of an exemplary transaction.}
\label{fig:tlm_at}
\end{center}
\end{figure}

SystemC also supports additional user-defined phases through its \texttt{DECLARE\_EXTENDED\_PHASE()} macro.
In contrast to the TLM-LT protocol, TLM-AT makes it possible model pipelining of transactions; multiple transactions can be processed by a target at one time.
The responses also do not need to be in the same order as the initiator has sent them: they can be \textit{out out order}.

The TLM-AT protol is the used protocol to implement the processor model and the cache model in section \ref{sec:implementation} of this thesis.
