Simulation additions

doc.bib

@@ -16,7 +16,7 @@
 @InProceedings{Abel19a,
   author    = {Abel, Andreas and Reineke, Jan},
   booktitle = {ASPLOS},
-  title     = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures},
+  title     = {uops.info: {C}haracterizing {L}atency, {T}hroughput, and {P}ort {U}sage of {I}nstructions on {I}ntel {M}icroarchitectures},
   year      = {2019},
   address   = {New York, NY, USA},
   pages     = {673--686},
@@ -33,20 +33,20 @@
 @Book{Jacob2008,
   author    = {Bruce Jacob and Spencer W. Ng and David T. Wang},
   publisher = {Morgan Kaufmann},
-  title     = {Memory Systems: Cache, DRAM, Disk},
+  title     = {{Memory Systems: Cache, DRAM, Disk}},
   year      = {2008},
 }
 
 @Article{Jahre2007,
   author = {Jahre, Magnus and Natvig, Lasse},
-  title  = {Performance Effects of a Cache Miss Handling Architecture in a Multi-core Processor},
+  title  = {{Performance Effects of a Cache Miss Handling Architecture in a Multi-core Processor}},
   year   = {2007},
 }
 
 @InProceedings{Antonino2018,
   author    = {Antonino, Pablo Oliveira and Jung, Matthias and Morgenstern, Andreas and Fa{\ss}nacht, Florian and Bauer, Thomas and Bachorek, Adam and Kuhn, Thomas and Nakagawa, Elisa Yumi},
   booktitle = {Software Architecture},
-  title     = {Enabling Continuous Software Engineering for Embedded Systems Architectures with Virtual Prototypes},
+  title     = {{Enabling Continuous Software Engineering for Embedded Systems Architectures with Virtual Prototypes}},
   year      = {2018},
   address   = {Cham},
   editor    = {Cuesta, Carlos E. and Garlan, David and P{\'e}rez, Jennifer},
@@ -58,7 +58,7 @@
 
 @Article{IEEE2012,
   journal = {IEEE Std 1666-2011 (Revision of IEEE Std 1666-2005)},
-  title   = {IEEE Standard for Standard SystemC Language Reference Manual},
+  title   = {{IEEE} {S}tandard for {S}tandard {S}ystem{C} {L}anguage {R}eference {M}anual},
   year    = {2012},
   doi     = {10.1109/IEEESTD.2012.6134619},
 }
@@ -66,7 +66,7 @@
 @InProceedings{Menard2017,
   author    = {Menard, Christian and Castrillon, Jeronimo and Jung, Matthias and Wehn, Norbert},
   booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
-  title     = {System simulation with gem5 and SystemC: The keystone for full interoperability},
+  title     = {{System simulation with gem5 and SystemC: The keystone for full interoperability}},
   year      = {2017},
   pages     = {62-69},
   doi       = {10.1109/SAMOS.2017.8344612},
@@ -75,7 +75,7 @@
 @InProceedings{Steiner2020,
   author    = {Steiner, Lukas and Jung, Matthias and Prado, Felipe S. and Bykov, Kirill and Wehn, Norbert},
   booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
-  title     = {DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator},
+  title     = {{DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator}},
   year      = {2020},
   address   = {Cham},
   editor    = {Orailoglu, Alex and Jung, Matthias and Reichenbach, Marc},
@@ -88,7 +88,7 @@
 @Book{Jung2017,
   author    = {Jung, Matthias},
   publisher = {Technische Universit{\"a}t Kaiserslautern},
-  title     = {System-level Modeling, Analysis and Optimization of DRAM Memories and Controller Architectures},
+  title     = {{System-level Modeling, Analysis and Optimization of DRAM Memories and Controller Architectures}},
   year      = {2017},
   isbn      = {9783959740517},
   series    = {Forschungsberichte Mikroelektronik},
@@ -97,7 +97,7 @@
 @Article{Binkert2011,
   author     = {Binkert, Nathan and Beckmann, Bradford and Black, Gabriel and Reinhardt, Steven K. and Saidi, Ali and Basu, Arkaprava and Hestness, Joel and Hower, Derek R. and Krishna, Tushar and Sardashti, Somayeh and Sen, Rathijit and Sewell, Korey and Shoaib, Muhammad and Vaish, Nilay and Hill, Mark D. and Wood, David A.},
   journal    = {SIGARCH Comput. Archit. News},
-  title      = {The Gem5 Simulator},
+  title      = {{The Gem5 Simulator}},
   year       = {2011},
   issn       = {0163-5964},
   month      = aug,
@@ -115,7 +115,7 @@
 @InProceedings{Jung2017a,
   author    = {Jung, Matthias and Kraft, Kira and Wehn, Norbert},
   booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
-  title     = {A new state model for DRAMs using Petri Nets},
+  title     = {{A new state model for DRAMs using Petri Nets}},
   year      = {2017},
   doi       = {10.1109/SAMOS.2017.8344631},
 }
@@ -123,7 +123,7 @@
 @Book{Hennessy2011,
   author    = {Hennessy, John L. and Patterson, David A.},
   publisher = {Morgan Kaufmann Publishers Inc.},
-  title     = {Computer Architecture, Fifth Edition: A Quantitative Approach},
+  title     = {{Computer Architecture, Fifth Edition: A Quantitative Approach}},
   year      = {2011},
   address   = {San Francisco, CA, USA},
   edition   = {5th},
@@ -134,7 +134,7 @@
 @Article{Ghose2019,
   author     = {Ghose, Saugata and Li, Tianshi and Hajinazar, Nastaran and Cali, Damla Senol and Mutlu, Onur},
   journal    = {Proc. ACM Meas. Anal. Comput. Syst.},
-  title      = {Demystifying Complex Workload-DRAM Interactions: An Experimental Study},
+  title      = {{Demystifying Complex Workload-DRAM Interactions: An Experimental Study}},
   year       = {2019},
   month      = {dec},
   number     = {3},
@@ -153,7 +153,7 @@
 @InProceedings{Gomony2012,
   author    = {Gomony, Manil Dev and Weis, Christian and Akesson, Benny and Wehn, Norbert and Goossens, Kees},
   booktitle = {2012 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
-  title     = {DRAM selection and configuration for real-time mobile systems},
+  title     = {{DRAM selection and configuration for real-time mobile systems}},
   year      = {2012},
   pages     = {51-56},
   doi       = {10.1109/DATE.2012.6176432},
@@ -162,7 +162,7 @@
 @Article{Kim2016,
   author  = {Kim, Yoongu and Yang, Weikun and Mutlu, Onur},
   journal = {IEEE Computer Architecture Letters},
-  title   = {Ramulator: A Fast and Extensible DRAM Simulator},
+  title   = {{Ramulator: A Fast and Extensible DRAM Simulator}},
   year    = {2016},
   number  = {1},
   pages   = {45-49},
@@ -200,7 +200,7 @@
   note   = {https://github.com/RRZE-HPC/TheBandwidthBenchmark. Accessed: 2022-06-28},
 }
 
-@Article{,
+@Article{Qemu,
   journal = {A generic and open source machine emulator and virtualizer},
   title   = {Q{E}{M}{U}},
   note    = {https://www.qemu.org/. Accessed: 2022-06-28},