Cache implementation

inc/4.caches.tex

@@ -84,6 +84,7 @@ In a fully associative cache, a memory reference can be placed anywhere, consequ
 Although this policy has the highest potential cache hit rate, the high space consumption due to comparators and high power consumption due to the lookup process, makes it non-feasable for many systems.
 
 The hybrid approach of set-associative caches offers a trade-off between both policies.
+The term \textit{associtativity} denotes the number of cache lines that are contained in a set.
 
 \subsection{Replacement Policies}
 \label{sec:replacement_policies}
@@ -118,6 +119,9 @@ To mitigate the problem, a write buffer can be used, which allows the processor
 
 An alternative is a so called \textit{write-back} cache.
 Instead of writing the updated value immediately to the underlying memory, it will be written back when the corresponding cache line is evicted.
+To identify if a cache line has to be written back, a so-called \textit{dirty-bit} is used:
+It denotes if the value has been updated while it has been in the cache.
+If it is the case, it has to be written back to ensure consistency, otherwise it is not needed.
 Also here, a write buffer can be used to place the actual write back requests into a queue.
 
 \subsection{Virtual Addressing}
@@ -183,13 +187,13 @@ As this is a major slowdown, non-blocking caches try to solve this problem, maki
 
 Similarly to the write buffer, previously discussed in \ref{sec:write_policies}, a new buffer will be introduced: the \revabbr{miss status hold register}{MSHR}.
 The number of MSHRs correspond to the number of misses the cache can handle concurrently; when all available MSHRs are occupied and a further miss occurs, the cache will block.
-A MSHR entry always corresponds to one cache line that is currently being fetched from the underlying memory subsystem.
+An MSHR entry always corresponds to one cache line that is currently being fetched from the underlying memory subsystem.
 
 There are two variants of cache misses:
-\textit{Primary misses} are misses that lead to another occupation of a MSHR, where as \textit{secondary misses} are added to an existing MSHR entry and therefore cannot cause the cache to block.
+\textit{Primary misses} are misses that lead to another occupation of an MSHR, where as \textit{secondary misses} are added to an existing MSHR entry and therefore cannot cause the cache to block.
 This is the case when the same cache line as accessed.
 
-An architecture of a MSHR file is illustrated in figure \ref{fig:mshr_file}.
+An architecture of an MSHR file is illustrated in figure \ref{fig:mshr_file}.
 
 \begin{figure}[!ht]
 \begin{center}