Cache implementation

inc/3.systemc.tex

@@ -9,6 +9,22 @@ They make it easier to test the product as VPs provide visiblity and controllabi
 SystemC is a C++ class library with an event-driven simulation kernel, used for developing complex system models (i.e. VPs) in a high-level language.
 It is defined under the IEEE 1666-2011 standard \cite{IEEE2012} and provided as an open-source library by Accellera.
 
+All SystemC modules inherit from the \texttt{sc\_module} base class.
+Those modules can hierarchically be composed of other modules or implement their functionality directly.
+Ports are then used to connect modules with each other, creating the structure of the simulation.
+There are two ways to implement a process in a module:
+% \begin{itemize}
+%  \item
+    An \texttt{SC\_METHOD} are sensitive to \texttt{sc\_event}s or other signals.
+    They can be executed multiple times.
+%  \item
+    An \texttt{SC\_THREAD} is started at the beginning of the simulation and should not terminate.
+    Instead, threads should contain infinite loops and should call explicitly \texttt{wait()} to wait a specific time or on events.
+% \end{itemize}
+Moreover, there is \texttt{sc\_event\_queue} which makes it possible to queue multiple pending events, where as an \texttt{sc\_event} ignores further notifications until it is waited on.
+
+Those concepts being introduced will become important in section \ref{sec:implementation} where the implementation of several SystemC modules will be discussed.
+
 SystemC supports numerous abstraction levels for modeling systems, namely \textit{cycle-accurate}, which is the most accurate abstraction but also the slowest, \textit{approximateley-timed} and \textit{loosley-timed}.
 The latter two abstraction levels belog to \revabbr{transaction level modeling}{TLM}, which will be discussed in the next section \ref{sec:tlm}.
 One further abstraction level, \textit{untimed}, will not be topic of this thesis.