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@@ -10,7 +10,7 @@ The general architecture of DRAMSys is illustrated in Figure \ref{fig:dramsys}.
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\begin{figure}[!ht]
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\begin{center}
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\includegraphics{img/dramsys.pdf}
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\caption{Structure of DRAMSys \cite{Jung2017}.}
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\caption[Structure of DRAMSys.]{Structure of DRAMSys \cite{Jung2017}.}
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\label{fig:dramsys}
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\end{center}
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\end{figure}
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@@ -22,7 +22,7 @@ To support a variety of DRAM standards in a robust and error-free manner, DRAMSy
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Using this language, all timing dependencies between DRAM commands of a standard can be defined.
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From this formal description, the source code of internal timing checkers is generated, which ensure compliance to the specific standard \cite{Jung2017a}.
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Since a single memory access can result in the issuance of multiple commands (e.g. a precharge (\texttt{PRE}), an activate (\texttt{ACT}), a read (\texttt{RD}) or a write (\texttt{WR})), the four-phase handshake of the TLM-AT protocol is not sufficient to model the communication between the DRAM controller and the DRAM device.
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Since a single memory access can result in the issuance of multiple commands (e.g., a precharge (\texttt{PRE}), an activate (\texttt{ACT}), a read (\texttt{RD}) or a write (\texttt{WR})), the four-phase handshake of the TLM-AT protocol is not sufficient to model the communication between the DRAM controller and the DRAM device.
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Therefore, a custom TLM protocol called DRAM-AT is used as the communication protocol between the channel controller and the DRAM device \cite{Steiner2020}.
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This custom protocol introduces a \texttt{BEGIN} and \texttt{END} phase for every available DRAM command.
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Which commands can be issued depends on the DRAM standard used.
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@@ -60,6 +60,8 @@ DRAMSys also provides the so-called \textit{Trace Analyzer}, a graphical tool th
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An exemplary trace database, visualized in the Trace Analyzer, is shown in Figure \ref{fig:traceanalyzer}.
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Furthermore, the Trace Analyzer is capable of calculating numerous metrics and creating plots of interesting characteristics.
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In Section \ref{sec:implementation} of this thesis, a new simulation frontend for DRAMSys will be developed.
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\begin{landscape}
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\begin{figure}
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\begin{center}
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@@ -69,5 +71,3 @@ Furthermore, the Trace Analyzer is capable of calculating numerous metrics and c
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\end{center}
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\end{figure}
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\end{landscape}
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In Section \ref{sec:implementation} of this thesis, a new simulation frontend for DRAMSys will be developed.
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