Last fixes
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@@ -21,7 +21,7 @@ Finally, the advantage of non-blocking caches is the topic of Section \ref{sec:c
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\label{sec:caches_locality_principles}
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Access patterns of a typical application are not random.
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They tend to repeat in time or are located in the near surrounding of previous accesses.
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They tend to repeat themselfes in time or are located in the near surrounding of previous accesses.
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Those two heuristics are called \textit{temporal locality} and \textit{spatial locality}.
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\subsubsection{Temporal Locality}
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@@ -65,7 +65,7 @@ There are three main policies:
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\begin{figure}
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\begin{center}
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\tikzfig{img/associativity}
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\caption{Four organizations for a cache of eight blocks \cite{Jacob2008}.}
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\caption[Four organizations for a cache of eight blocks.]{Four organizations for a cache of eight blocks \cite{Jacob2008}.}
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\label{fig:associativity}
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\end{center}
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\end{figure}
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@@ -154,11 +154,11 @@ Figure \ref{fig:virtual_address} shows an exemplary division of a virtual addres
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Before a process can access a specific region in memory, the kernel has to translate the virtual page number into a physical page number.
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For conversions, so-called \textit{page tables} are used to look up the physical page number.
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Page tables are usually multiple levels deep (e.g. 4-levels on x86), so a single conversion can cause a number of memory accesses, which is expensive.
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Page tables are usually multiple levels deep (e.g., 4-levels on x86), so a single conversion can cause a number of memory accesses, which is expensive.
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To improve performance, a \revabbr{translation lookaside buffer}{TLB} is used, which acts like a cache on its own for physical page numbers.
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However, as long as the physical address is not present, the data cache cannot look up its entries as the index is not known yet.
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So the cache has to wait for the TLB or even multiple memory accesses if the physical page number is not stored in it.
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So the cache has to wait for the TLB or even multiple memory accesses in case the physical page number is not stored in it.
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To circumvent this problem, the cache can be indexed by the virtual address, which makes it possible to parallelize both procedures.
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Such a cache is called \textit{virtually indexed} and \textit{physically tagged} and is illustrated in Figure \ref{fig:virtual_address_conversion}.
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@@ -207,7 +207,7 @@ A possible architecture of an MSHR file is illustrated in Figure \ref{fig:mshr_f
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\begin{figure}
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\begin{center}
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\tikzfig{img/mshr_file}
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\caption[Miss Status Holding Register File \cite{Jahre2007}.]{Miss Status Holding Register File \cite{Jahre2007}. \textit{V} refers to a valid bit.}
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\caption[Miss Status Holding Register File.]{Miss Status Holding Register File \cite{Jahre2007}. \textit{V} refers to a valid bit.}
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\label{fig:mshr_file}
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\end{center}
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\end{figure}
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