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Simulations Kapitel

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Derek Christ
2022-07-16 18:05:29 +02:00
parent f542b2c034
commit 6324ae1d3d
4 changed files with 82 additions and 40 deletions
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7
inc/appendix.tex
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@@ -72,6 +72,7 @@
\end{center}
\end{table}
\newpage
\subsection{Simulation Results}
\label{sec:appendix_sim_results}
@@ -109,7 +110,7 @@
\end{table}
\begin{table}[!ht]
\caption{Results for memory access latency and data bus utilization with DDR3-1600.}
\caption{Results for the total simulation time and the average response latency with DDR3-1600.}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|c|}
\hline
@@ -138,11 +139,11 @@
\end{tabular}
\end{center}
\label{tab:benchmark_access_ddr3}
\label{tab:benchmark_gem5_access_ddr3}
\end{table}
\begin{table}[!ht]
\caption{Results for memory access latency and data bus utilization with DDR4-2400.}
\caption{Results for the total simulation time and the average response latency with DDR4-2400.}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|c|}
\hline