Future work
This commit is contained in:
@@ -4,7 +4,7 @@
|
||||
In this section the accuracy of the new simulation frontend will be evaluated.
|
||||
After a short discussion about the general expections regarding the accuracy and considerations to make, the simulation results will be presented.
|
||||
The presentation is structured into two parts:
|
||||
At first simulation statistics of numerous benchmarks are compared against the gem5\cite{Binkert2011} simulator that uses detailed processor models and can be considered as a reference. .
|
||||
At first simulation statistics of numerous benchmarks are compared against the gem5\cite{Binkert2011} simulator that uses detailed processor models and can be considered as a reference.
|
||||
Secondly, the new simulation frontend is compared against the memory access trace generator tool of the Ramulator DRAM simulator\cite{Ghose2019}.
|
||||
|
||||
\subsection{Accuracy}
|
||||
@@ -19,4 +19,4 @@ Since the DBI cannot observe the fetching of those instructions, the new simulat
|
||||
|
||||
\subsection{Comparison to the gem5 Simulator}
|
||||
|
||||
|
||||
At first, the micro-benchmark suite TheBandwithBenchmark\cite{} will be used to compare the gem5 full-system simulation as well as the gem5 syscall-emulation simulation modes with the newly developed frontend.
|
||||
|
||||
Reference in New Issue
Block a user