derek/bachelor-thesis
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Future work

Browse Source
This commit is contained in:
Derek Christ
2022-06-25 16:50:50 +02:00
parent 8f554d8eaa
commit 443ac6bf30
5 changed files with 74 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
inc/6.implementation.tex
View File

@@ -20,7 +20,9 @@ It is a purely observational client and does not modify the behavior of the appl
Optionally, DrCacheSim converts the addresses of the memory accesses from virtual addresses into physical addresses, which is an important step for simulating a real memory system.
The physical address conversion only works on Linux and requires root privileges (or alternatively the CAP\_SYS\_ADMIN capability) in modern kernel versions.
The analyzer tool can either be running alongside with DrCacheSim (online) or operate on an internal trace format (offline).
As of writing this thesis, the offline tracing mode does not yet support the physical address conversation, so the online mode has to be used.
Offline tracing has the additional advantage of being able to disassemble the executed instructions afterwards.
For this, the mapping of the executable binaries and shared libraries is stored alongside with the trace, enabling the decoding of the instructions from the traced program counter values.
As of writing this thesis, the offline tracing mode has recently gained support for the physical address conversation, but the online mode will be used throughout this thesis as its support is still limited.
In case of the online tracing, DrCacheSim consists of two separate processes:
\begin{itemize}
@@ -64,15 +66,17 @@ This instruction count is used to approximate the delay between the memory acces
\begin{textcode}
# instruction count,read/write,data size,data address
# <timestamp>
<13295366593324052>
4,r,8,1774ef30
0,r,8,1774ef38
1,w,8,1774ef28
2,w,8,1774ee88
0,r,8,17744728
1,r,8,238c3fb0
<13300116157764414>
3,r,8,1190cf3f0
9,w,16,1190cf270
2,r,8,10200be48
0,w,16,1190cf280
1,w,16,1190cf290
2,w,16,1190cf2a0
1,w,16,1190cf2b0
0,w,16,1190cf2c0
\end{textcode}
\caption{Example of a memory access trace with a timestamp.}
\caption{Example of a memory access trace with a timestamp. For each thread, a seperate trace file is generated.}
\label{list:memtrace}
\end{listing}