From 2406771a6f2be25fc1769eb079bb08852cadb8c1 Mon Sep 17 00:00:00 2001
From: Derek Christ <dchrist@rhrk.uni-kl.de>
Date: Wed, 13 Jul 2022 15:25:21 +0200
Subject: [PATCH] Fix align issue

---
 inc/6.implementation.tex | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/inc/6.implementation.tex b/inc/6.implementation.tex
index 31f0a6b..9864ff9 100644
--- a/inc/6.implementation.tex
+++ b/inc/6.implementation.tex
@@ -113,6 +113,14 @@ Also, comments which, are ignored by the trace player, can be added by starting
 \label{list:memtrace}
 \end{listing}
 
+\begin{figure}
+\begin{center}
+\tikzfig{img/without_caching}
+\caption{Architecture of the \textit{DbiPlayer} without caches.}
+\label{fig:dbiplayer_without_caches}
+\end{center}
+\end{figure}
+
 As of writing this thesis, there is no application binary interface for analysis tools defined for the DrMemtrace framework.
 Therefore it is not possible to load the DRAMTracer tool as a shared library but rather it is required to modify the DynamoRIO source code to integrate the tool.
 
@@ -131,14 +139,6 @@ This new interface will be further discussed in Section \ref{sec:traceplayer_int
 For the \textit{DbiPlayer}, an additional interconnect module will bundle up all \\ \texttt{simple\_initiator\_sockets} into a single \texttt{multi\_passthrough\_initiator\_socket}.
 So the \textit{DbiPlayer} is a hierarchical module that consists of a more complex architecture with multiple traffic initiators, illustrated in Figure \ref{fig:dbiplayer_without_caches}.
 
-\begin{figure}
-\begin{center}
-\tikzfig{img/without_caching}
-\caption{Architecture of the \textit{DbiPlayer} without caches.}
-\label{fig:dbiplayer_without_caches}
-\end{center}
-\end{figure}
-
 As the memory accesses are directly extracted from the executed instructions, simply sending a transaction to the DRAM subsystem for every data reference would completely neglect the caches of today's processors.
 Therefore, also a cache model is required whose implementation will be explained in more detail in Section \ref{sec:cache_implementation}.
 Many modern cache hierarchies are composed of 3 cache levels: 2 caches for every processor core, the L1 and L2 cache, and one cache that is shared across all cores, the L3 cache.