Cache coherency

inc/5.dramsys.tex

@@ -2,7 +2,7 @@
 \label{sec:dramsys}
 
 DRAMSys is an open-source design space exploration framework, capable of simulating the latest \revabbr{Joint Electron Device Engineering Council}{JEDEC} DRAM standards.
-It is optimized to achieve high simulation speeds and utilizes the TLM-AT coding style while still achieving cycle accurate results\cite{Steiner2020}.
+It is optimized to achieve high simulation speeds and utilizes the TLM-AT coding style while still achieving cycle accurate results \cite{Steiner2020}.
 
 DRAMSys is composed of an arbitration \& mapping unit (also called arbiter) and independent channel controllers with a DRAM device each.
 The general architecture of DRAMSys is illustrated in figure \ref{fig:dramsys}.
@@ -16,7 +16,7 @@ The general architecture of DRAMSys is illustrated in figure \ref{fig:dramsys}.
 \end{figure}
 
 Several initiators can be connected to the arbiter, sending requests to the DRAM subsystem.
-An initiator can either be a sophisticated processor model like the gem5 out of order processor model\cite{Binkert2011} or a trace player that simply replays a trace file containing a sequence of memory requests and timestamps.
+An initiator can either be a sophisticated processor model like the gem5 out of order processor model \cite{Binkert2011} or a trace player that simply replays a trace file containing a sequence of memory requests and timestamps.
 
 To support a large variety of DRAM standards robustly and error-free, DRAMSys uses a formal domain specific language based on petri nets called DRAMml.
 This language includes a standards timing dependencies between all DRAM commands and compiles to source code of the internal timing checkers that ensure compliance to the specific standard \cite{Jung2017a}.