Introduction + accuracy discussion

doc.bib

@@ -120,4 +120,54 @@
   doi       = {10.1109/SAMOS.2017.8344631},
 }
 
+@Book{Hennessy2011,
+  author    = {Hennessy, John L. and Patterson, David A.},
+  publisher = {Morgan Kaufmann Publishers Inc.},
+  title     = {Computer Architecture, Fifth Edition: A Quantitative Approach},
+  year      = {2011},
+  address   = {San Francisco, CA, USA},
+  edition   = {5th},
+  isbn      = {012383872X},
+  abstract  = {The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change. Updated to cover the mobile computing revolutionEmphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")Includes three review appendices in the printed text. Additional reference appendices are available online.Includes updated Case Studies and completely new exercises.},
+}
+
+@Article{Ghose2019,
+  author     = {Ghose, Saugata and Li, Tianshi and Hajinazar, Nastaran and Cali, Damla Senol and Mutlu, Onur},
+  journal    = {Proc. ACM Meas. Anal. Comput. Syst.},
+  title      = {Demystifying Complex Workload-DRAM Interactions: An Experimental Study},
+  year       = {2019},
+  month      = {dec},
+  number     = {3},
+  volume     = {3},
+  abstract   = {It has become increasingly difficult to understand the complex interactions between modern applications and main memory, composed of Dynamic Random Access Memory (DRAM) chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, memory access patterns of prevalent and emerging applications are rapidly diverging, as these applications manipulate larger data sets in very different ways. As a result, the combined DRAM-workload behavior is often difficult to intuitively determine today, which can hinder memory optimizations in both hardware and software. In this work, we identify important families of workloads, as well as prevalent types of DRAM chips, and rigorously analyze the combined DRAM-workload behavior. To this end, we perform a comprehensive experimental study of the interaction between nine different DRAM types and 115 modern applications and multiprogrammed workloads. We draw 12 key observations from our characterization, enabled in part by our development of new metrics that take into account contention between memory requests due to hardware design. Notably, we find that (1) newer DRAM technologies such as DDR4 and HMC often do not outperform older technologies such as DDR3, due to higher access latencies and, also in the case of HMC, poor exploitation of locality; (2) there is no single memory type that can effectively cater to all of the components of a heterogeneous system (e.g., GDDR5 significantly outperforms other memories for multimedia acceleration, while HMC significantly outperforms other memories for network acceleration); and (3) there is still a strong need to lower DRAM latency, but unfortunately the current design trend of commodity DRAM is toward higher latencies to obtain other benefits. We hope that the trends we identify can drive optimizations in both hardware and software design. To aid further study, we open-source our extensively-modified simulator, as well as a benchmark suite containing our applications.},
+  address    = {New York, NY, USA},
+  articleno  = {60},
+  doi        = {10.1145/3366708},
+  issue_date = {December 2019},
+  keywords   = {power consumption, memory systems, performance modeling, experimental characterization, dram, low-power memory, energy, 3d-stacked memory},
+  numpages   = {50},
+  publisher  = {Association for Computing Machinery},
+  url        = {https://doi.org/10.1145/3366708},
+}
+
+@InProceedings{Gomony2012,
+  author    = {Gomony, Manil Dev and Weis, Christian and Akesson, Benny and Wehn, Norbert and Goossens, Kees},
+  booktitle = {2012 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
+  title     = {DRAM selection and configuration for real-time mobile systems},
+  year      = {2012},
+  pages     = {51-56},
+  doi       = {10.1109/DATE.2012.6176432},
+}
+
+@Article{Kim2016,
+  author  = {Kim, Yoongu and Yang, Weikun and Mutlu, Onur},
+  journal = {IEEE Computer Architecture Letters},
+  title   = {Ramulator: A Fast and Extensible DRAM Simulator},
+  year    = {2016},
+  number  = {1},
+  pages   = {45-49},
+  volume  = {15},
+  doi     = {10.1109/LCA.2015.2414456},
+}
+
 @Comment{jabref-meta: databaseType:bibtex;}