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Derek Christ
2022-07-03 21:56:01 +02:00
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inc/8.future_work.tex
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@@ -15,6 +15,9 @@ Also, the Pin-Tool based memory access tracing of the Ramulator DRAM simulator w
A noteworthy advantage of the newly developed tool is its support for all hardware architectures that DynamoRIO provides (currently IA-32, x86-64, ARM, and AArch64) in contrast to the supported architectures of Pin (IA-32 and x86-64).
Still, there is room for improvement.
To improve the simulation runtime, a binary trace format could be used instead of the text-based format.
Both the performance during tracing and parsing should increase by using such a binary format.
As mentioned in \ref{sec:cache_implementation}, the cache models do not yet guarantee cache coherency due to the lack of a snooping protocol.
Although this can be a complex task, it is possible to implement this in future work.