Lukas' second improvements

inc/8.future_work.tex

@@ -2,7 +2,7 @@
 \label{sec:future_work}
 
 Due to the complexity of possible memory subsystem configurations, simulation is an indispensable part of the development process of today's systems.
-It not only has an high impact on the development cost but also significantly reduces the time-to-market and enables the rapid release of new products.
+It not only has a high impact on the development cost but also significantly reduces the time-to-market and enables the rapid release of new products.
 However, the accurate simulation of a specific application takes a large period of time because of the detailed processor core models.
 On the other hand, fixed or relative time memory traces allow faster simulation at the expense of accuracy, which makes them often unsuitable.
 To fill this gap, this thesis introduced a new simulation frontend for DRAMSys, which fastens the process while only making few compromises on accuracy.
@@ -29,7 +29,7 @@ This deviation could be prevented by recording used processor cores on the initi
 
 Another inaccuracy can be caused by the hyperthreading of some of today's processors:
 While hyperthreading enables the parallel processing of two pipelines in a processor core, those threads do share the same first level cache.
-Currently, this is not taken into account and every application thread gets its own first level cache assigned.
+Currently, this is not taken into account, and each application thread is assigned its own first level cache.
 
 Further room for improvement offers the consideration of the special prefetch and instructions the architectures provide.
 DynamoRIO already offers an interface to catch those instructions without much effort.