Lukas' second improvements

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2022-08-10 20:08:20 +02:00
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7 changed files with 27 additions and 18 deletions

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@@ -71,10 +71,14 @@ There are three main policies:
\end{figure}
Figure \ref{fig:associativity} illustrates four different organizations for a cache of eight cache lines.
In all three cases, the least significant portion of the physical address of the referenced data, the \textit{index}, determines the set in which the data is to store.
As an example, a data block with the address \texttt{0x40} may be placed in the second set for the direct-mapped, two-way associative and four-way associative cache configurations.
However, in the latter two configurations, the cache can choose the horizontal placement of the block within the set.
For the fully associative cache, every cache line is a valid placement as it consists of only one set.
In each cache configuration, the least significant portion of the physical address of the referenced data, the \textit{index}, determines the set in which the data is to store.
However, several entries in the DRAM map to the same set, so the remaining most significant portion of the address is used as a \textit{tag} and is stored next to the actual data in the cache line.
After an entry is fetched from the cache, the tag is used to determine if the entry actually corresponds to the referenced data.
An example subdivision of the address in the index, tag and byte offset is shown in Figure \ref{fig:address_mapping}.
An exemplary subdivision of the address in the index, tag and byte offset is shown in Figure \ref{fig:address_mapping}.
\begin{figure}[!ht]
\begin{center}