Lukas' second improvements
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@@ -71,10 +71,14 @@ There are three main policies:
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\end{figure}
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Figure \ref{fig:associativity} illustrates four different organizations for a cache of eight cache lines.
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In all three cases, the least significant portion of the physical address of the referenced data, the \textit{index}, determines the set in which the data is to store.
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As an example, a data block with the address \texttt{0x40} may be placed in the second set for the direct-mapped, two-way associative and four-way associative cache configurations.
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However, in the latter two configurations, the cache can choose the horizontal placement of the block within the set.
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For the fully associative cache, every cache line is a valid placement as it consists of only one set.
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In each cache configuration, the least significant portion of the physical address of the referenced data, the \textit{index}, determines the set in which the data is to store.
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However, several entries in the DRAM map to the same set, so the remaining most significant portion of the address is used as a \textit{tag} and is stored next to the actual data in the cache line.
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After an entry is fetched from the cache, the tag is used to determine if the entry actually corresponds to the referenced data.
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An example subdivision of the address in the index, tag and byte offset is shown in Figure \ref{fig:address_mapping}.
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An exemplary subdivision of the address in the index, tag and byte offset is shown in Figure \ref{fig:address_mapping}.
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\begin{figure}[!ht]
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\begin{center}
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