406 lines
23 KiB
C++
406 lines
23 KiB
C++
/*
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* Copyright (c) 2022, Technische Universität Kaiserslautern
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Iron Prando da Silva
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*/
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#include "TimeDependenciesInfoLPDDR5.h"
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using namespace std;
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TimeDependenciesInfoLPDDR5::TimeDependenciesInfoLPDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
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mInitializeValues();
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}
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void TimeDependenciesInfoLPDDR5::mInitializeValues() {
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burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
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dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
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per2BankOffset = mMemspecJson["memarchitecturespec"].toObject()["per2BankOffset"].toInt();
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tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
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tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt();
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tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt();
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tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
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tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt();
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tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt();
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tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt();
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tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt();
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tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt();
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tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
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tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt();
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tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
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tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
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tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt();
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tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt();
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tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
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tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
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tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt();
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tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt();
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tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
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tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
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tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt();
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tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt();
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tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
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tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt();
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tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
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tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
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tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt();
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tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt();
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tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
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tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
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tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
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tRBTP = tCK * mMemspecJson["memtimingspec"].toObject()["RBTP"].toInt();
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BL_n_min_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_16"].toInt();
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BL_n_min_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_32"].toInt();
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BL_n_max_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_16"].toInt();
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BL_n_max_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_32"].toInt();
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BL_n_S_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_16"].toInt();
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BL_n_S_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_32"].toInt();
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BL_n_L_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_16"].toInt();
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BL_n_L_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_32"].toInt();
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tWCK2DQO = tCK * mMemspecJson["memtimingspec"].toObject()["WCK2DQO"].toInt();
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tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt();
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tpbR2act = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2act"].toInt();
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tpbR2pbR = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2pbR"].toInt();
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tBURST16 = (uint) (16 / (float) dataRate) * tCK;
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tBURST32 = (uint) (32 / (float) dataRate) * tCK;
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mPools.insert({
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"CMD_BUS", {
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1, {
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{"ACT", 2 * tCK},
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{"RD", tCK},
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{"WR", tCK},
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{"RDA", tCK},
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{"WRA", tCK},
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{"PREPB", tCK},
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{"PREAB", tCK},
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{"REFAB", tCK},
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{"REFPB", tCK},
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{"REFP2B", tCK},
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}
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}
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});
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mPools.insert({
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"NAW", {
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4, {
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{"ACT", tFAW},
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{"REFPB", tFAW},
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{"REFP2B", tFAW},
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}
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}
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});
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}
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const std::vector<QString> TimeDependenciesInfoLPDDR5::getPossiblePhases() {
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return {
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"ACT",
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"RD",
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"WR",
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"PREPB",
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"RDA",
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"WRA",
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"REFPB",
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"REFP2B",
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"REFAB",
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"PREAB",
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};
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}
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DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
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DependencyMap dmap;
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auto passBurstLength16 = std::make_shared<PassFunction>(
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[] PASSFUNCTIONDECL {
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auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
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if (!other) return false;
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return other->tBurstLength == 16;
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}
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);
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auto passBurstLength32 = std::make_shared<PassFunction>(
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[] PASSFUNCTIONDECL {
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auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
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if (!other) return false;
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return other->tBurstLength == 32;
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}
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);
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dmap.emplace(
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piecewise_construct,
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forward_as_tuple("ACT"),
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forward_as_tuple(
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initializer_list<TimeDependency>{
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{tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"},
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{tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
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{BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK", passBurstLength16},
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{BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK", passBurstLength32},
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{tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK", passBurstLength16},
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{tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK", passBurstLength32},
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{tRPpb - tCK, "PREPB", DependencyType::IntraBank, "tRPpb - tCK"},
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{tRPab - tCK, "PREAB", DependencyType::IntraRank, "tRPab - tCK"},
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{tRFCab - tCK, "REFAB", DependencyType::IntraRank, "tRFCab - tCK"},
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{tpbR2act - tCK, "REFPB", DependencyType::IntraRank, "tpbR2act - tCK"},
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{tpbR2act - tCK, "REFP2B", DependencyType::IntraRank, "tpbR2act - tCK"},
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{tRFCpb - tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - tCK"},
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{tRFCpb - tCK, "REFP2B", DependencyType::IntraBank, "tRFCpb - tCK"},
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{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
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{0, "NAW", DependencyType::IntraRank, "tFAW"},
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}
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)
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);
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dmap.emplace(
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piecewise_construct,
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forward_as_tuple("RD"),
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forward_as_tuple(
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initializer_list<TimeDependency>{
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{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
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{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
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{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
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{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
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{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
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{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
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{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
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{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
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{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
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{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
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{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
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{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
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{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
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{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
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{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
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{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
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{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
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{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
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{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
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{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
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{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
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{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
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}
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)
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);
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dmap.emplace(
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piecewise_construct,
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forward_as_tuple("WR"),
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forward_as_tuple(
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initializer_list<TimeDependency>{
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{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
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{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
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{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
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{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
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{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
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{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
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{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
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{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
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{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
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{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
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{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
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{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
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{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
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{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
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{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
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{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
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{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
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{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
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{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
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{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
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{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
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{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
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}
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)
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);
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dmap.emplace(
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piecewise_construct,
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forward_as_tuple("PREPB"),
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forward_as_tuple(
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initializer_list<TimeDependency>{
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{tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
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{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP", passBurstLength16},
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{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP", passBurstLength32},
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{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
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{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
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{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
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{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
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}
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)
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);
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dmap.emplace(
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piecewise_construct,
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forward_as_tuple("RDA"),
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forward_as_tuple(
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initializer_list<TimeDependency>{
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{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
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{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
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{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
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{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
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{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
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{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
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{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
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{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
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{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
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{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
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{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
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{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
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{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
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{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
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{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
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{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
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{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
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{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
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{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
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{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
|
|
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
|
|
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("WRA"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
|
|
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
|
|
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
|
|
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
|
|
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
|
|
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
|
|
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
|
|
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
|
|
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
|
|
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
|
|
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
|
|
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
|
|
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
|
|
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
|
|
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
|
|
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
|
|
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
|
|
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
|
|
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
|
|
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
|
|
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
|
|
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("REFAB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRCpb + tCK, "ACT", DependencyType::IntraRank, "tRCpb + tCK"},
|
|
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
|
|
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
|
|
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
|
|
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
|
|
{tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
|
|
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
|
|
{tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
|
|
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("PREAB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"},
|
|
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16},
|
|
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32},
|
|
{BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16},
|
|
{BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32},
|
|
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
|
|
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
|
|
{tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
|
|
{tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
|
|
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
|
|
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("REFPB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
|
|
{tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
|
|
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
|
|
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
|
|
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
|
|
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
|
|
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
|
|
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
|
|
{tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"},
|
|
{tpbR2pbR, "REFPB", DependencyType::IntraRank, "tpbR2pbR"},
|
|
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
|
|
{0, "NAW", DependencyType::IntraRank, "tFAW"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("REFP2B"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
|
|
{tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
|
|
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
|
|
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
|
|
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
|
|
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
|
|
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
|
|
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
|
|
{tRFCpb, "REFP2B", DependencyType::IntraBank, "tRFCpb"},
|
|
{tpbR2pbR, "REFP2B", DependencyType::IntraRank, "tpbR2pbR"},
|
|
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
|
|
{0, "NAW", DependencyType::IntraRank, "tFAW"},
|
|
}
|
|
)
|
|
);
|
|
|
|
return dmap;
|
|
}
|