f11adf51dc
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
51 lines
1.2 KiB
C++
51 lines
1.2 KiB
C++
#include "Fr_Fcfs.h"
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#include "../../common/dramExtension.h"
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#include "../core/configuration/Configuration.h"
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#include <algorithm>
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using namespace std;
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void FR_FCFS::schedule(gp *payload)
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{
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buffer[DramExtension::getExtension(payload).getBank()].emplace_back(payload);
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}
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std::pair<Command, gp*> FR_FCFS::getNextRequest(Bank bank)
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{
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if(buffer[bank].empty())
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{
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return pair<Command, tlm::tlm_generic_payload*>(Command::NOP, NULL);
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}
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deque<gp*>::iterator it = FindRowHit(bank);
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if(it != buffer[bank].end())
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{
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gp* payload = *it;
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buffer[bank].erase(it);
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return pair<Command, gp*>(getReadWriteCommand(*payload), payload);
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}
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return pair<Command, gp*>(getNextCommand(buffer[bank].front()), buffer[bank].front());
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}
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deque<gp*>::iterator FR_FCFS::FindRowHit(Bank bank)
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{
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deque<gp*> &queue = buffer[bank];
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if(!controllerCore.getRowBufferStates().rowBufferIsOpen(bank))
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return queue.end();
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for(auto it = queue.begin(); it!=queue.end(); it++)
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{
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gp* payload = *it;
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//Found row-hit
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if(DramExtension::getRow(payload) == controllerCore.getRowBufferStates().getRowInRowBuffer(bank))
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{
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return it;
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}
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}
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return queue.end();
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}
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