f11adf51dc
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
35 lines
798 B
C++
35 lines
798 B
C++
/*
|
|
* Fifo.cpp
|
|
*
|
|
* Created on: Mar 19, 2014
|
|
* Author: robert
|
|
*/
|
|
|
|
#include "Fifo.h"
|
|
|
|
using namespace std;
|
|
|
|
void Fifo::schedule(gp* payload)
|
|
{
|
|
buffer[DramExtension::getExtension(payload).getBank()].emplace_back(payload);
|
|
}
|
|
|
|
pair<Command, tlm::tlm_generic_payload*> Fifo::getNextRequest(Bank bank)
|
|
{
|
|
if(!buffer[bank].empty())
|
|
{
|
|
gp* payload = buffer[bank].front();
|
|
Command command = IScheduler::getNextCommand(*payload);
|
|
if(command == Command::Read || command == Command::ReadA || command == Command::Write || command == Command::WriteA)
|
|
{
|
|
buffer[bank].pop_front();
|
|
}
|
|
|
|
return pair<Command, tlm::tlm_generic_payload*>(command, payload);
|
|
}
|
|
|
|
return pair<Command, tlm::tlm_generic_payload*>(Command::NOP, NULL);
|
|
}
|
|
|
|
|