f11adf51dc
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
43 lines
982 B
C++
43 lines
982 B
C++
/*
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* BankwiseRefreshManager.h
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*
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* Created on: Mar 9, 2014
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* Author: jonny
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*/
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#ifndef BANKWISEREFRESHMANAGER_H_
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#define BANKWISEREFRESHMANAGER_H_
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#include "../../../common/dramExtension.h"
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#include "../configuration/MemSpec.h"
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#include "IRefreshManager.h"
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class ControllerCore;
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class RefreshManagerBankwise : public IRefreshManager
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{
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public:
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RefreshManagerBankwise(ControllerCore& controllerCore);
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virtual ~RefreshManagerBankwise();
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virtual bool hasCollision(const ScheduledCommand& command) override;
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virtual void scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time) override;
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void reInitialize(Bank bank, sc_time time) override;
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bool isInvalidated(tlm::tlm_generic_payload& payload,sc_time time) override;
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private:
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ControllerCore& controllerCore;
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std::map<Bank, tlm::tlm_generic_payload> refreshPayloads;
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std::map<Bank, sc_time> nextPlannedRefreshs;
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void planNextRefresh(Bank bank);
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};
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#endif /* BANKWISEREFRESHMANAGER_H_ */
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