f11adf51dc
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
62 lines
901 B
C++
62 lines
901 B
C++
/*
|
|
* Slots.cpp
|
|
*
|
|
* Created on: Mar 29, 2014
|
|
* Author: robert
|
|
*/
|
|
|
|
#include "Slots.h"
|
|
#include "TimingCalculation.h"
|
|
|
|
|
|
Slots::Slots(sc_time clk) :
|
|
clk(clk)
|
|
{
|
|
|
|
}
|
|
|
|
Slots::~Slots()
|
|
{
|
|
}
|
|
|
|
void Slots::moveCommandToNextFreeSlot(ScheduledCommand& command)
|
|
{
|
|
while(!isFree(command.getStart()))
|
|
command.delayStart(clk);
|
|
}
|
|
|
|
void Slots::cleanUpSlots(sc_time time)
|
|
{
|
|
slotSet.erase(slotSet.begin(), slotSet.lower_bound(time));
|
|
}
|
|
|
|
void Slots::blockSlot(sc_time time)
|
|
{
|
|
sc_assert(isClkAligned(time, clk));
|
|
slotSet.insert(time);
|
|
}
|
|
|
|
bool Slots::isFree(sc_time time)
|
|
{
|
|
return (slotSet.count(time) == 0);
|
|
}
|
|
|
|
void Slots::blockSlots(sc_time begin, sc_time end, bool excludeBorders)
|
|
{
|
|
sc_assert(isClkAligned(begin, clk));
|
|
sc_assert(isClkAligned(end, clk));
|
|
|
|
if (excludeBorders)
|
|
{
|
|
begin += clk;
|
|
end -= clk;
|
|
}
|
|
|
|
for (sc_time time = begin; time <= end; time += clk)
|
|
{
|
|
slotSet.insert(time);
|
|
}
|
|
|
|
}
|
|
|