f11adf51dc
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
56 lines
1.3 KiB
C++
56 lines
1.3 KiB
C++
/*
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* controller_state.h
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*
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* Created on: Mar 5, 2014
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* Author: jonny
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*/
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#ifndef CONTROLLER_STATE_H_
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#define CONTROLLER_STATE_H_
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#include <systemc.h>
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#include "RowBufferStates.h"
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#include "core/Slots.h"
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#include "core/configuration/Configuration.h"
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#include <map>
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#include <set>
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#include <list>
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class ControllerState
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{
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public:
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ControllerState(Configuration* config) :
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rowBufferStates(), bus(config->memSpec.clk), config(config)
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{
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}
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virtual ~ControllerState()
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{
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}
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const ScheduledCommand getLastCommand(Command command, Bank bank);
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const ScheduledCommand getLastCommand(Command command);
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const ScheduledCommand getLastScheduledCommand(Bank bank);
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const ScheduledCommand getLastScheduledCommand();
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void change(const ScheduledCommand& scheduledCommand);
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void cleanUp(sc_time time);
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RowBufferState rowBufferStates;
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//used by the various checkers
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std::map<Command, std::map<Bank, ScheduledCommand> > lastScheduledByCommandAndBank;
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std::map<Command, ScheduledCommand> lastScheduledByCommand;
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std::map<Bank, ScheduledCommand> lastScheduledByBank;
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ScheduledCommand lastScheduled;
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Slots bus;
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std::vector<ScheduledCommand> lastDataStrobeCommands;
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std::map<sc_time, ScheduledCommand> lastActivates;
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private:
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Configuration* config;
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};
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#endif /* CONTROLLER_STATE_H_ */
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