131 lines
4.9 KiB
C++
131 lines
4.9 KiB
C++
/*
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* Copyright (c) 2019, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lukas Steiner
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*/
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#ifndef CONTROLLER_H
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#define CONTROLLER_H
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#include "DRAMSys/controller/ControllerIF.h"
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#include "DRAMSys/controller/Command.h"
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#include "DRAMSys/controller/BankMachine.h"
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#include "DRAMSys/controller/cmdmux/CmdMuxIF.h"
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#include "DRAMSys/controller/checker/CheckerIF.h"
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#include "DRAMSys/controller/refresh/RefreshManagerIF.h"
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#include "DRAMSys/controller/powerdown/PowerDownManagerIF.h"
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#include "DRAMSys/controller/respqueue/RespQueueIF.h"
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#include "DRAMSys/simulation/AddressDecoder.h"
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#include <vector>
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#include <stack>
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#include <systemc>
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#include <tlm>
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namespace DRAMSys
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{
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class Controller : public ControllerIF
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{
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public:
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Controller(const sc_core::sc_module_name& name, const Configuration& config, const AddressDecoder& addressDecoder);
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SC_HAS_PROCESS(Controller);
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protected:
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tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
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sc_core::sc_time& delay) override;
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tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
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sc_core::sc_time& delay) override;
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void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) override;
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unsigned int transport_dbg(tlm::tlm_generic_payload& trans) override;
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virtual void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay);
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virtual void controllerMethod();
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std::unique_ptr<SchedulerIF> scheduler;
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const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
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const sc_core::sc_time thinkDelayFw;
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const sc_core::sc_time thinkDelayBw;
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const sc_core::sc_time phyDelayFw;
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const sc_core::sc_time phyDelayBw;
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const sc_core::sc_time blockingReadDelay;
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const sc_core::sc_time blockingWriteDelay;
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private:
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unsigned totalNumberOfPayloads = 0;
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ControllerVector<Rank, unsigned> ranksNumberOfPayloads;
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ReadyCommands readyCommands;
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ControllerVector<Bank, std::unique_ptr<BankMachine>> bankMachines;
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ControllerVector<Rank, ControllerVector<Bank, BankMachine*>> bankMachinesOnRank;
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std::unique_ptr<CmdMuxIF> cmdMux;
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std::unique_ptr<CheckerIF> checker;
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std::unique_ptr<RespQueueIF> respQueue;
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ControllerVector<Rank, std::unique_ptr<RefreshManagerIF>> refreshManagers;
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ControllerVector<Rank, std::unique_ptr<PowerDownManagerIF>> powerDownManagers;
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const AddressDecoder& addressDecoder;
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uint64_t nextChannelPayloadIDToAppend = 1;
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struct PayloadAndArrival
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{
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tlm::tlm_generic_payload* payload = nullptr;
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sc_core::sc_time arrival = sc_core::sc_max_time();
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} transToAcquire, transToRelease;
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void manageResponses();
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void manageRequests(const sc_core::sc_time& delay);
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sc_core::sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent;
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const unsigned minBytesPerBurst;
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const unsigned maxBytesPerBurst;
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void createChildTranses(tlm::tlm_generic_payload& parentTrans);
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class MemoryManager : public tlm::tlm_mm_interface
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{
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public:
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~MemoryManager() override;
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tlm::tlm_generic_payload& allocate();
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void free(tlm::tlm_generic_payload* trans) override;
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private:
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std::stack<tlm::tlm_generic_payload*> freePayloads;
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} memoryManager;
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};
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} // namespace DRAMSys
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#endif // CONTROLLER_H
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