4dbc9b8a78
scheduled in the future to trigger a schedule of a refresh command. This allows for more sophisticated refresh logics in the futurer (postponing).
68 lines
2.3 KiB
C++
68 lines
2.3 KiB
C++
#include <gtest/gtest.h>
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#include "core/scheduling/CommandSequenceGenerator.h"
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#include "testUtils.h"
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#include <vector>
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using namespace controller;
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using namespace common;
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using namespace std;
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constexpr unsigned int numberOfBanks = 8;
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constexpr tlm::tlm_command READ = tlm::tlm_command::TLM_READ_COMMAND;
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constexpr tlm::tlm_command WRITE = tlm::tlm_command::TLM_WRITE_COMMAND;
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TEST(CommandSequenceGenerator, ReadAndWriteWithRowHit)
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{
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ControllerState state(numberOfBanks);
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CommandSequenceGenerator generator(state);
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state.bankStates.openRowInRowBuffer(Bank(0), Row(3));
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auto hit_read = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), READ);
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auto hit_write = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), WRITE);
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vector<Command> expected_read ({Command::Read});
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vector<Command> expected_write ({Command::Write});
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EXPECT_EQ(expected_read, generator.generateCommandSequence(hit_read.get()));
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EXPECT_EQ(expected_write, generator.generateCommandSequence(hit_write.get()));
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}
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TEST(CommandSequenceGenerator, ReadAndWriteWithRowMiss)
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{
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ControllerState state(numberOfBanks);
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CommandSequenceGenerator generator(state);
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state.bankStates.openRowInRowBuffer(Bank(0), Row(3));
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auto miss_read = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), READ);
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auto miss_write = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), WRITE);
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vector<Command> expected_read ({Command::Precharge, Command::Activate, Command::Read});
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vector<Command> expected_write ({Command::Precharge, Command::Activate, Command::Write});
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EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get()));
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EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get()));
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}
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TEST(CommandSequenceGenerator, ReadAndWriteWithBankMiss)
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{
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ControllerState state(numberOfBanks);
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CommandSequenceGenerator generator(state);
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state.bankStates.openRowInRowBuffer(Bank(0), Row(3));
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auto miss_read = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), READ);
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auto miss_write = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), WRITE);
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vector<Command> expected_read ({Command::Activate, Command::Read});
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vector<Command> expected_write ({Command::Activate, Command::Write});
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EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get()));
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EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get()));
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}
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