Derek Christ
1ef2b3bd9c
Update the DRAMUtils version and fix all configs that now require DBI parameters for the memimpedance spec.
1044 lines
26 KiB
C++
1044 lines
26 KiB
C++
/*
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* Copyright (c) 2022, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Derek Christ
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*/
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#pragma once
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#include <string_view>
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inline constexpr std::string_view addressMappingJsonString = R"(
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{
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"addressmapping": {
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"BYTE_BIT": [
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0
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],
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"COLUMN_BIT": [
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1,
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2,
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3,
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4,
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9,
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10,
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11,
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12,
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13,
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14
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],
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"BANKGROUP_BIT": [
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5,
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6
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],
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"BANK_BIT": [
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7,
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8
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],
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"ROW_BIT": [
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27,
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28,
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29,
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30
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]
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}
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}
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)";
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inline constexpr std::string_view validAddressMappingJsonString = R"(
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{
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"addressmapping": {
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"BYTE_BIT": [
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0,
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1,
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2
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],
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"COLUMN_BIT": [
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3,
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4,
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5,
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10,
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11,
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12,
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13,
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14,
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15,
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16
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],
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"BANKGROUP_BIT": [
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6,
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9
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],
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"BANK_BIT": [
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7,
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8
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],
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"ROW_BIT": [
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27,
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28,
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29,
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30
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]
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}
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}
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)";
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inline constexpr std::string_view validMemSpecJsonString = R"(
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{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 8,
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"dataRate": 2,
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"nbrOfBankGroups": 4,
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"nbrOfBanks": 16,
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"nbrOfColumns": 1024,
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"nbrOfRanks": 1,
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"nbrOfRows": 16384,
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"width": 8,
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"nbrOfDevices": 8,
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"nbrOfChannels": 1,
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"RefMode": 1
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},
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"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
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"memoryType": "DDR4",
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"mempowerspec": {
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"vdd": 1.2,
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"idd0": 60.75e-3,
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"idd2n": 38.25e-3,
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"idd3n": 44.0e-3,
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"idd4r": 184.5e-3,
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"idd4w": 168.75e-3,
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"idd6n": 20.25e-3,
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"idd2p": 17.0e-3,
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"idd3p": 22.5e-3,
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"vpp": 2.5,
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"ipp0": 4.05e-3,
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"ipp2n": 0,
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"ipp3n": 0,
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"ipp4r": 0,
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"ipp4w": 0,
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"ipp6n": 2.6e-3,
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"ipp2p": 17.0e-3,
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"ipp3p": 22.5e-3,
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"idd5B": 118.0e-3,
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"ipp5B": 0.0,
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"idd5F2": 0.0,
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"ipp5F2": 0.0,
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"idd5F4": 0.0,
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"ipp5F4": 0.0,
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"vddq": 0.0,
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"iBeta_vdd": 60.75e-3,
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"iBeta_vpp": 4.05e-3
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},
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"memtimingspec": {
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"AL": 0,
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"CCD_L": 6,
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"CCD_S": 4,
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"CKE": 6,
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"CKESR": 7,
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"CL": 16,
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"DQSCK": 2,
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"FAW": 26,
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"RAS": 39,
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"RC": 55,
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"RCD": 16,
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"REFM": 1,
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"REFI": 4680,
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"RFC1": 313,
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"RFC2": 0,
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"RFC4": 0,
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"RL": 16,
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"RPRE": 1,
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"RP": 16,
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"RRD_L": 6,
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"RRD_S": 4,
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"RTP": 12,
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"WL": 16,
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"WPRE": 1,
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"WR": 18,
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"WTR_L": 9,
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"WTR_S": 3,
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"XP": 8,
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"XPDLL": 325,
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"XS": 324,
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"XSDLL": 512,
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"ACTPDEN": 2,
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"PRPDEN": 2,
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"REFPDEN": 2,
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"RTRS": 1,
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"tCK": 833e-12
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},
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"bankwisespec": {
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"factRho": 1.0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wdqs_termination": true,
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"wdqs_R_eq": 1e6,
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"wdqs_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12,
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"wdbi_termination": true,
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"wdbi_R_eq": 1e6,
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"wdbi_dyn_E": 1e-12,
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"rdbi_termination": true,
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"rdbi_R_eq": 1e6,
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"rdbi_dyn_E": 1e-12
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},
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"prepostamble": {
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"read_zeroes": 0.0,
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"write_zeroes": 0.0,
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"read_ones": 0.0,
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"write_ones": 0.0,
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"read_zeroes_to_ones": 0,
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"write_zeroes_to_ones": 0,
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"write_ones_to_zeroes": 0,
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"read_ones_to_zeroes": 0,
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"readMinTccd": 0,
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"writeMinTccd": 0
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}
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}
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}
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)";
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inline constexpr std::string_view validNP2MemSpecJsonString = R"(
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{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 7,
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"dataRate": 2,
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"nbrOfBankGroups": 4,
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"nbrOfBanks": 16,
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"nbrOfColumns": 1024,
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"nbrOfRanks": 1,
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"nbrOfRows": 16384,
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"width": 8,
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"nbrOfDevices": 7,
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"nbrOfChannels": 1,
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"RefMode": 1
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},
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"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
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"memoryType": "DDR4",
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"mempowerspec": {
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"vdd": 1.2,
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"idd0": 60.75e-3,
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"idd2n": 38.25e-3,
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"idd3n": 44.0e-3,
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"idd4r": 184.5e-3,
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"idd4w": 168.75e-3,
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"idd6n": 20.25e-3,
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"idd2p": 17.0e-3,
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"idd3p": 22.5e-3,
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"vpp": 2.5,
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"ipp0": 4.05e-3,
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"ipp2n": 0,
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"ipp3n": 0,
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"ipp4r": 0,
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"ipp4w": 0,
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"ipp6n": 2.6e-3,
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"ipp2p": 17.0e-3,
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"ipp3p": 22.5e-3,
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"idd5B": 118.0e-3,
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"ipp5B": 0.0,
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"idd5F2": 0.0,
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"ipp5F2": 0.0,
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"idd5F4": 0.0,
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"ipp5F4": 0.0,
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"vddq": 0.0,
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"iBeta_vdd": 60.75e-3,
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"iBeta_vpp": 4.05e-3
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},
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"memtimingspec": {
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"AL": 0,
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"CCD_L": 6,
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"CCD_S": 4,
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"CKE": 6,
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"CKESR": 7,
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"CL": 16,
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"DQSCK": 2,
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"FAW": 26,
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"RAS": 39,
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"RC": 55,
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"RCD": 16,
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"REFM": 1,
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"REFI": 4680,
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"RFC1": 313,
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"RFC2": 0,
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"RFC4": 0,
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"RL": 16,
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"RPRE": 1,
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"RP": 16,
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"RRD_L": 6,
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"RRD_S": 4,
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"RTP": 12,
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"WL": 16,
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"WPRE": 1,
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"WR": 18,
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"WTR_L": 9,
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"WTR_S": 3,
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"XP": 8,
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"XPDLL": 325,
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"XS": 324,
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"XSDLL": 512,
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"ACTPDEN": 2,
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"PRPDEN": 2,
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"REFPDEN": 2,
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"RTRS": 1,
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"tCK": 833e-12
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},
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"bankwisespec": {
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"factRho": 1.0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wdqs_termination": true,
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"wdqs_R_eq": 1e6,
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"wdqs_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12,
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"wdbi_termination": true,
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"wdbi_R_eq": 1e6,
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"wdbi_dyn_E": 1e-12,
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"rdbi_termination": true,
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"rdbi_R_eq": 1e6,
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"rdbi_dyn_E": 1e-12
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},
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"prepostamble": {
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"read_zeroes": 0.0,
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"write_zeroes": 0.0,
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"read_ones": 0.0,
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"write_ones": 0.0,
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"read_zeroes_to_ones": 0,
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"write_zeroes_to_ones": 0,
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"write_ones_to_zeroes": 0,
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"read_ones_to_zeroes": 0,
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"readMinTccd": 0,
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"writeMinTccd": 0
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}
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}
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}
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)";
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inline constexpr std::string_view invalidMaxAddressMemSpecJsonString = R"(
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{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 8,
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"dataRate": 2,
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"nbrOfBankGroups": 4,
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"nbrOfBanks": 16,
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"nbrOfColumns": 1024,
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"nbrOfRanks": 1,
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"nbrOfRows": 16385,
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"width": 8,
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"nbrOfDevices": 8,
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"nbrOfChannels": 1,
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"RefMode": 1
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},
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"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
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"memoryType": "DDR4",
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"mempowerspec": {
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"vdd": 1.2,
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"idd0": 60.75e-3,
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"idd2n": 38.25e-3,
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"idd3n": 44.0e-3,
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"idd4r": 184.5e-3,
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"idd4w": 168.75e-3,
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"idd6n": 20.25e-3,
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"idd2p": 17.0e-3,
|
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"idd3p": 22.5e-3,
|
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"vpp": 2.5,
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"ipp0": 4.05e-3,
|
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"ipp2n": 0,
|
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"ipp3n": 0,
|
|
"ipp4r": 0,
|
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"ipp4w": 0,
|
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"ipp6n": 2.6e-3,
|
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"ipp2p": 17.0e-3,
|
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"ipp3p": 22.5e-3,
|
|
|
|
"idd5B": 118.0e-3,
|
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"ipp5B": 0.0,
|
|
"idd5F2": 0.0,
|
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"ipp5F2": 0.0,
|
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"idd5F4": 0.0,
|
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"ipp5F4": 0.0,
|
|
"vddq": 0.0,
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|
|
|
"iBeta_vdd": 60.75e-3,
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"iBeta_vpp": 4.05e-3
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},
|
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"memtimingspec": {
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"AL": 0,
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|
"CCD_L": 6,
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"CCD_S": 4,
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"CKE": 6,
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|
"CKESR": 7,
|
|
"CL": 16,
|
|
"DQSCK": 2,
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|
"FAW": 26,
|
|
"RAS": 39,
|
|
"RC": 55,
|
|
"RCD": 16,
|
|
"REFM": 1,
|
|
"REFI": 4680,
|
|
"RFC1": 313,
|
|
"RFC2": 0,
|
|
"RFC4": 0,
|
|
"RL": 16,
|
|
"RPRE": 1,
|
|
"RP": 16,
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|
"RRD_L": 6,
|
|
"RRD_S": 4,
|
|
"RTP": 12,
|
|
"WL": 16,
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|
"WPRE": 1,
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|
"WR": 18,
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|
"WTR_L": 9,
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|
"WTR_S": 3,
|
|
"XP": 8,
|
|
"XPDLL": 325,
|
|
"XS": 324,
|
|
"XSDLL": 512,
|
|
"ACTPDEN": 2,
|
|
"PRPDEN": 2,
|
|
"REFPDEN": 2,
|
|
"RTRS": 1,
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|
"tCK": 833e-12
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|
},
|
|
"bankwisespec": {
|
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"factRho": 1.0
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|
},
|
|
"memimpedancespec": {
|
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"ck_termination": true,
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|
"ck_R_eq": 1e6,
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|
"ck_dyn_E": 1e-12,
|
|
|
|
"ca_termination": true,
|
|
"ca_R_eq": 1e6,
|
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"ca_dyn_E": 1e-12,
|
|
|
|
"rdq_termination": true,
|
|
"rdq_R_eq": 1e6,
|
|
"rdq_dyn_E": 1e-12,
|
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"wdq_termination": true,
|
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"wdq_R_eq": 1e6,
|
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"wdq_dyn_E": 1e-12,
|
|
|
|
"wdqs_termination": true,
|
|
"wdqs_R_eq": 1e6,
|
|
"wdqs_dyn_E": 1e-12,
|
|
"rdqs_termination": true,
|
|
"rdqs_R_eq": 1e6,
|
|
"rdqs_dyn_E": 1e-12,
|
|
|
|
"wdbi_termination": true,
|
|
"wdbi_R_eq": 1e6,
|
|
"wdbi_dyn_E": 1e-12,
|
|
"rdbi_termination": true,
|
|
"rdbi_R_eq": 1e6,
|
|
"rdbi_dyn_E": 1e-12
|
|
},
|
|
"prepostamble": {
|
|
"read_zeroes": 0.0,
|
|
"write_zeroes": 0.0,
|
|
"read_ones": 0.0,
|
|
"write_ones": 0.0,
|
|
"read_zeroes_to_ones": 0,
|
|
"write_zeroes_to_ones": 0,
|
|
"write_ones_to_zeroes": 0,
|
|
"read_ones_to_zeroes": 0,
|
|
"readMinTccd": 0,
|
|
"writeMinTccd": 0
|
|
}
|
|
}
|
|
}
|
|
)";
|
|
|
|
inline constexpr std::string_view addressMappingWithDuplicatesJsonString = R"(
|
|
{
|
|
"addressmapping": {
|
|
"BYTE_BIT": [
|
|
0,
|
|
1,
|
|
2
|
|
],
|
|
"COLUMN_BIT": [
|
|
3,
|
|
4,
|
|
5,
|
|
3,
|
|
10,
|
|
11
|
|
],
|
|
"BANKGROUP_BIT": [
|
|
6,
|
|
9
|
|
],
|
|
"BANK_BIT": [
|
|
7,
|
|
8
|
|
],
|
|
"ROW_BIT": [
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30
|
|
]
|
|
}
|
|
}
|
|
)";
|
|
|
|
inline constexpr std::string_view nonContinuousByteBitsAddressMappingJsonString = R"(
|
|
{
|
|
"addressmapping": {
|
|
"BYTE_BIT": [
|
|
0,
|
|
1,
|
|
3
|
|
],
|
|
"COLUMN_BIT": [
|
|
2,
|
|
4,
|
|
5,
|
|
10,
|
|
11,
|
|
12
|
|
],
|
|
"BANKGROUP_BIT": [
|
|
6,
|
|
9
|
|
],
|
|
"BANK_BIT": [
|
|
7,
|
|
8
|
|
],
|
|
"ROW_BIT": [
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30
|
|
]
|
|
}
|
|
}
|
|
)";
|
|
|
|
inline constexpr std::string_view invalidChannelMemSpecJsonString = R"(
|
|
{
|
|
"memspec": {
|
|
"memarchitecturespec": {
|
|
"burstLength": 8,
|
|
"dataRate": 2,
|
|
"nbrOfBankGroups": 4,
|
|
"nbrOfBanks": 8,
|
|
"nbrOfColumns": 1024,
|
|
"nbrOfRanks": 1,
|
|
"nbrOfRows": 16384,
|
|
"width": 8,
|
|
"nbrOfDevices": 8,
|
|
"nbrOfChannels": 2,
|
|
"RefMode": 1
|
|
},
|
|
"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
|
|
"memoryType": "DDR4",
|
|
"mempowerspec": {
|
|
"vdd": 1.2,
|
|
"idd0": 60.75e-3,
|
|
"idd2n": 38.25e-3,
|
|
"idd3n": 44.0e-3,
|
|
"idd4r": 184.5e-3,
|
|
"idd4w": 168.75e-3,
|
|
"idd6n": 20.25e-3,
|
|
"idd2p": 17.0e-3,
|
|
"idd3p": 22.5e-3,
|
|
|
|
"vpp": 2.5,
|
|
"ipp0": 4.05e-3,
|
|
"ipp2n": 0,
|
|
"ipp3n": 0,
|
|
"ipp4r": 0,
|
|
"ipp4w": 0,
|
|
"ipp6n": 2.6e-3,
|
|
"ipp2p": 17.0e-3,
|
|
"ipp3p": 22.5e-3,
|
|
|
|
"idd5B": 118.0e-3,
|
|
"ipp5B": 0.0,
|
|
"idd5F2": 0.0,
|
|
"ipp5F2": 0.0,
|
|
"idd5F4": 0.0,
|
|
"ipp5F4": 0.0,
|
|
"vddq": 0.0,
|
|
|
|
"iBeta_vdd": 60.75e-3,
|
|
"iBeta_vpp": 4.05e-3
|
|
},
|
|
"memtimingspec": {
|
|
"AL": 0,
|
|
"CCD_L": 6,
|
|
"CCD_S": 4,
|
|
"CKE": 6,
|
|
"CKESR": 7,
|
|
"CL": 16,
|
|
"DQSCK": 2,
|
|
"FAW": 26,
|
|
"RAS": 39,
|
|
"RC": 55,
|
|
"RCD": 16,
|
|
"REFM": 1,
|
|
"REFI": 4680,
|
|
"RFC1": 313,
|
|
"RFC2": 0,
|
|
"RFC4": 0,
|
|
"RL": 16,
|
|
"RPRE": 1,
|
|
"RP": 16,
|
|
"RRD_L": 6,
|
|
"RRD_S": 4,
|
|
"RTP": 12,
|
|
"WL": 16,
|
|
"WPRE": 1,
|
|
"WR": 18,
|
|
"WTR_L": 9,
|
|
"WTR_S": 3,
|
|
"XP": 8,
|
|
"XPDLL": 325,
|
|
"XS": 324,
|
|
"XSDLL": 512,
|
|
"ACTPDEN": 2,
|
|
"PRPDEN": 2,
|
|
"REFPDEN": 2,
|
|
"RTRS": 1,
|
|
"tCK": 833e-12
|
|
},
|
|
"bankwisespec": {
|
|
"factRho": 1.0
|
|
},
|
|
"memimpedancespec": {
|
|
"ck_termination": true,
|
|
"ck_R_eq": 1e6,
|
|
"ck_dyn_E": 1e-12,
|
|
|
|
"ca_termination": true,
|
|
"ca_R_eq": 1e6,
|
|
"ca_dyn_E": 1e-12,
|
|
|
|
"rdq_termination": true,
|
|
"rdq_R_eq": 1e6,
|
|
"rdq_dyn_E": 1e-12,
|
|
"wdq_termination": true,
|
|
"wdq_R_eq": 1e6,
|
|
"wdq_dyn_E": 1e-12,
|
|
|
|
"wdqs_termination": true,
|
|
"wdqs_R_eq": 1e6,
|
|
"wdqs_dyn_E": 1e-12,
|
|
"rdqs_termination": true,
|
|
"rdqs_R_eq": 1e6,
|
|
"rdqs_dyn_E": 1e-12,
|
|
|
|
"wdbi_termination": true,
|
|
"wdbi_R_eq": 1e6,
|
|
"wdbi_dyn_E": 1e-12,
|
|
"rdbi_termination": true,
|
|
"rdbi_R_eq": 1e6,
|
|
"rdbi_dyn_E": 1e-12
|
|
},
|
|
"prepostamble": {
|
|
"read_zeroes": 0.0,
|
|
"write_zeroes": 0.0,
|
|
"read_ones": 0.0,
|
|
"write_ones": 0.0,
|
|
"read_zeroes_to_ones": 0,
|
|
"write_zeroes_to_ones": 0,
|
|
"write_ones_to_zeroes": 0,
|
|
"read_ones_to_zeroes": 0,
|
|
"readMinTccd": 0,
|
|
"writeMinTccd": 0
|
|
}
|
|
}
|
|
}
|
|
)";
|
|
|
|
inline constexpr std::string_view invalidBankGroupMemSpecJsonString = R"(
|
|
{
|
|
"memspec": {
|
|
"memarchitecturespec": {
|
|
"burstLength": 8,
|
|
"dataRate": 2,
|
|
"nbrOfBankGroups": 8,
|
|
"nbrOfBanks": 8,
|
|
"nbrOfColumns": 1024,
|
|
"nbrOfRanks": 1,
|
|
"nbrOfRows": 16384,
|
|
"width": 8,
|
|
"nbrOfDevices": 8,
|
|
"nbrOfChannels": 1,
|
|
"RefMode": 1
|
|
},
|
|
"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
|
|
"memoryType": "DDR4",
|
|
"mempowerspec": {
|
|
"vdd": 1.2,
|
|
"idd0": 60.75e-3,
|
|
"idd2n": 38.25e-3,
|
|
"idd3n": 44.0e-3,
|
|
"idd4r": 184.5e-3,
|
|
"idd4w": 168.75e-3,
|
|
"idd6n": 20.25e-3,
|
|
"idd2p": 17.0e-3,
|
|
"idd3p": 22.5e-3,
|
|
|
|
"vpp": 2.5,
|
|
"ipp0": 4.05e-3,
|
|
"ipp2n": 0,
|
|
"ipp3n": 0,
|
|
"ipp4r": 0,
|
|
"ipp4w": 0,
|
|
"ipp6n": 2.6e-3,
|
|
"ipp2p": 17.0e-3,
|
|
"ipp3p": 22.5e-3,
|
|
|
|
"idd5B": 118.0e-3,
|
|
"ipp5B": 0.0,
|
|
"idd5F2": 0.0,
|
|
"ipp5F2": 0.0,
|
|
"idd5F4": 0.0,
|
|
"ipp5F4": 0.0,
|
|
"vddq": 0.0,
|
|
|
|
"iBeta_vdd": 60.75e-3,
|
|
"iBeta_vpp": 4.05e-3
|
|
},
|
|
"memtimingspec": {
|
|
"AL": 0,
|
|
"CCD_L": 6,
|
|
"CCD_S": 4,
|
|
"CKE": 6,
|
|
"CKESR": 7,
|
|
"CL": 16,
|
|
"DQSCK": 2,
|
|
"FAW": 26,
|
|
"RAS": 39,
|
|
"RC": 55,
|
|
"RCD": 16,
|
|
"REFM": 1,
|
|
"REFI": 4680,
|
|
"RFC1": 313,
|
|
"RFC2": 0,
|
|
"RFC4": 0,
|
|
"RL": 16,
|
|
"RPRE": 1,
|
|
"RP": 16,
|
|
"RRD_L": 6,
|
|
"RRD_S": 4,
|
|
"RTP": 12,
|
|
"WL": 16,
|
|
"WPRE": 1,
|
|
"WR": 18,
|
|
"WTR_L": 9,
|
|
"WTR_S": 3,
|
|
"XP": 8,
|
|
"XPDLL": 325,
|
|
"XS": 324,
|
|
"XSDLL": 512,
|
|
"ACTPDEN": 2,
|
|
"PRPDEN": 2,
|
|
"REFPDEN": 2,
|
|
"RTRS": 1,
|
|
"tCK": 833e-12
|
|
},
|
|
"bankwisespec": {
|
|
"factRho": 1.0
|
|
},
|
|
"memimpedancespec": {
|
|
"ck_termination": true,
|
|
"ck_R_eq": 1e6,
|
|
"ck_dyn_E": 1e-12,
|
|
|
|
"ca_termination": true,
|
|
"ca_R_eq": 1e6,
|
|
"ca_dyn_E": 1e-12,
|
|
|
|
"rdq_termination": true,
|
|
"rdq_R_eq": 1e6,
|
|
"rdq_dyn_E": 1e-12,
|
|
"wdq_termination": true,
|
|
"wdq_R_eq": 1e6,
|
|
"wdq_dyn_E": 1e-12,
|
|
|
|
"wdqs_termination": true,
|
|
"wdqs_R_eq": 1e6,
|
|
"wdqs_dyn_E": 1e-12,
|
|
"rdqs_termination": true,
|
|
"rdqs_R_eq": 1e6,
|
|
"rdqs_dyn_E": 1e-12,
|
|
|
|
"wdbi_termination": true,
|
|
"wdbi_R_eq": 1e6,
|
|
"wdbi_dyn_E": 1e-12,
|
|
"rdbi_termination": true,
|
|
"rdbi_R_eq": 1e6,
|
|
"rdbi_dyn_E": 1e-12
|
|
},
|
|
"prepostamble": {
|
|
"read_zeroes": 0.0,
|
|
"write_zeroes": 0.0,
|
|
"read_ones": 0.0,
|
|
"write_ones": 0.0,
|
|
"read_zeroes_to_ones": 0,
|
|
"write_zeroes_to_ones": 0,
|
|
"write_ones_to_zeroes": 0,
|
|
"read_ones_to_zeroes": 0,
|
|
"readMinTccd": 0,
|
|
"writeMinTccd": 0
|
|
}
|
|
}
|
|
}
|
|
)";
|
|
|
|
inline constexpr std::string_view invalidRanksMemSpecJsonString = R"(
|
|
{
|
|
"memspec": {
|
|
"memarchitecturespec": {
|
|
"burstLength": 8,
|
|
"dataRate": 2,
|
|
"nbrOfBankGroups": 2,
|
|
"nbrOfBanks": 8,
|
|
"nbrOfColumns": 1024,
|
|
"nbrOfRanks": 2,
|
|
"nbrOfRows": 16384,
|
|
"width": 8,
|
|
"nbrOfDevices": 8,
|
|
"nbrOfChannels": 1,
|
|
"RefMode": 1
|
|
},
|
|
"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
|
|
"memoryType": "DDR4",
|
|
"mempowerspec": {
|
|
"vdd": 1.2,
|
|
"idd0": 60.75e-3,
|
|
"idd2n": 38.25e-3,
|
|
"idd3n": 44.0e-3,
|
|
"idd4r": 184.5e-3,
|
|
"idd4w": 168.75e-3,
|
|
"idd6n": 20.25e-3,
|
|
"idd2p": 17.0e-3,
|
|
"idd3p": 22.5e-3,
|
|
|
|
"vpp": 2.5,
|
|
"ipp0": 4.05e-3,
|
|
"ipp2n": 0,
|
|
"ipp3n": 0,
|
|
"ipp4r": 0,
|
|
"ipp4w": 0,
|
|
"ipp6n": 2.6e-3,
|
|
"ipp2p": 17.0e-3,
|
|
"ipp3p": 22.5e-3,
|
|
|
|
"idd5B": 118.0e-3,
|
|
"ipp5B": 0.0,
|
|
"idd5F2": 0.0,
|
|
"ipp5F2": 0.0,
|
|
"idd5F4": 0.0,
|
|
"ipp5F4": 0.0,
|
|
"vddq": 0.0,
|
|
|
|
"iBeta_vdd": 60.75e-3,
|
|
"iBeta_vpp": 4.05e-3
|
|
},
|
|
"memtimingspec": {
|
|
"AL": 0,
|
|
"CCD_L": 6,
|
|
"CCD_S": 4,
|
|
"CKE": 6,
|
|
"CKESR": 7,
|
|
"CL": 16,
|
|
"DQSCK": 2,
|
|
"FAW": 26,
|
|
"RAS": 39,
|
|
"RC": 55,
|
|
"RCD": 16,
|
|
"REFM": 1,
|
|
"REFI": 4680,
|
|
"RFC1": 313,
|
|
"RFC2": 0,
|
|
"RFC4": 0,
|
|
"RL": 16,
|
|
"RPRE": 1,
|
|
"RP": 16,
|
|
"RRD_L": 6,
|
|
"RRD_S": 4,
|
|
"RTP": 12,
|
|
"WL": 16,
|
|
"WPRE": 1,
|
|
"WR": 18,
|
|
"WTR_L": 9,
|
|
"WTR_S": 3,
|
|
"XP": 8,
|
|
"XPDLL": 325,
|
|
"XS": 324,
|
|
"XSDLL": 512,
|
|
"ACTPDEN": 2,
|
|
"PRPDEN": 2,
|
|
"REFPDEN": 2,
|
|
"RTRS": 1,
|
|
"tCK": 833e-12
|
|
},
|
|
"bankwisespec": {
|
|
"factRho": 1.0
|
|
},
|
|
"memimpedancespec": {
|
|
"ck_termination": true,
|
|
"ck_R_eq": 1e6,
|
|
"ck_dyn_E": 1e-12,
|
|
|
|
"ca_termination": true,
|
|
"ca_R_eq": 1e6,
|
|
"ca_dyn_E": 1e-12,
|
|
|
|
"rdq_termination": true,
|
|
"rdq_R_eq": 1e6,
|
|
"rdq_dyn_E": 1e-12,
|
|
"wdq_termination": true,
|
|
"wdq_R_eq": 1e6,
|
|
"wdq_dyn_E": 1e-12,
|
|
|
|
"wdqs_termination": true,
|
|
"wdqs_R_eq": 1e6,
|
|
"wdqs_dyn_E": 1e-12,
|
|
"rdqs_termination": true,
|
|
"rdqs_R_eq": 1e6,
|
|
"rdqs_dyn_E": 1e-12,
|
|
|
|
"wdbi_termination": true,
|
|
"wdbi_R_eq": 1e6,
|
|
"wdbi_dyn_E": 1e-12,
|
|
"rdbi_termination": true,
|
|
"rdbi_R_eq": 1e6,
|
|
"rdbi_dyn_E": 1e-12
|
|
},
|
|
"prepostamble": {
|
|
"read_zeroes": 0.0,
|
|
"write_zeroes": 0.0,
|
|
"read_ones": 0.0,
|
|
"write_ones": 0.0,
|
|
"read_zeroes_to_ones": 0,
|
|
"write_zeroes_to_ones": 0,
|
|
"write_ones_to_zeroes": 0,
|
|
"read_ones_to_zeroes": 0,
|
|
"readMinTccd": 0,
|
|
"writeMinTccd": 0
|
|
}
|
|
}
|
|
}
|
|
)"; |