667 lines
40 KiB
C++
667 lines
40 KiB
C++
/*
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* Copyright (c) 2022, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Iron Prando da Silva
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*/
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#include "TimeDependenciesInfoDDR5.h"
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#include <cmath>
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using namespace std;
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TimeDependenciesInfoDDR5::TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
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mInitializeValues();
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}
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void TimeDependenciesInfoDDR5::rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const {
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logRID = rankID;
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physRID = logRID / mNumLogicalRanksPerPhysicalRank;
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dimmRID = physRID / mNumPhysicalRanksPerDIMMRank;
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}
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void TimeDependenciesInfoDDR5::bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const {
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bankInGroup = logicalRankID * mNumBanksPerGroup + bankID % mNumBanksPerGroup;
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}
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void TimeDependenciesInfoDDR5::mInitializeValues() {
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mNumOfRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfRanks"].toInt();
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mNumOfDIMMRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfDIMMRanks"].toInt();
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mNumPhysicalRanksPerDIMMRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt();
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mNumLogicalRanksPerPhysicalRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt();
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mNumBanksPerGroup = mMemspecJson["memarchitecturespec"].toObject()["nbrOfBanks"].toInt(1);
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mNumBanksPerGroup /= mMemspecJson["memarchitecturespec"].toObject()["nbrOfBankGroups"].toInt(1);
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burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
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dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
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refMode = mMemspecJson["memarchitecturespec"].toObject()["refMode"].toInt();
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cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
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bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt();
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tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
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tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt();
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tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
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tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
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tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
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RBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt();
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tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
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tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt();
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tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt();
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tRDDQS = tCK * mMemspecJson["memtimingspec"].toObject()["RDDQS"].toInt();
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tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
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WBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt();
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tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
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tWPST = tCK * mMemspecJson["memtimingspec"].toObject()["WPST"].toInt();
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tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
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tCCD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_slr"].toInt();
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tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR_slr"].toInt();
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tCCD_L_WR2_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt();
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tCCD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_slr"].toInt();
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tCCD_S_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_WR_slr"].toInt();
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tCCD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_dlr"].toInt();
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tCCD_WR_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dlr"].toInt();
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tCCD_WR_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dpr"].toInt();
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tRRD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S_slr"].toInt();
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tRRD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L_slr"].toInt();
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tRRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_dlr"].toInt();
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tFAW_slr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_slr"].toInt();
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tFAW_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_dlr"].toInt();
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tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt();
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tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt();
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tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_slr"].toInt();
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tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dlr"].toInt();
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tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dpr"].toInt();
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tRFCsb_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_slr"].toInt();
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tRFCsb_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_dlr"].toInt();
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tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI"].toInt();
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tREFSBRD_slr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_slr"].toInt();
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tREFSBRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_dlr"].toInt();
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tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
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UNKNOWN = tCK * mMemspecJson["memtimingspec"].toObject()["NKNOWN"].toInt();
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tCPDED = tCK * mMemspecJson["memtimingspec"].toObject()["CPDED"].toInt();
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tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt();
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tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
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tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt();
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tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
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tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
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tRC = tRAS + tRP;
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if (refMode == 1) {
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tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_slr"].toInt();
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tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dlr"].toInt();
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tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dpr"].toInt();
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tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI1"].toInt();
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} else {
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tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_slr"].toInt();
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tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dlr"].toInt();
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tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dpr"].toInt();
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tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI2"].toInt();
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}
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if (cmdMode == 2) {
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shortCmdOffset = 1 * tCK;
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longCmdOffset = 3 * tCK;
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} else {
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shortCmdOffset = 0 * tCK;
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longCmdOffset = 1 * tCK;
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}
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cmdLengthDiff = tCK * mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
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tBURST16 = 8 * tCK;
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tBURST32 = 16 * tCK;
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tRD_BURST = (uint) (RBL / (float) dataRate) * tCK;
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tWR_BURST = (uint) (WBL / (float) dataRate) * tCK;
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tWTRA = tWR - tRTP;
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tWRRDA = tWL + tBURST16 + tWTRA;
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tWRPRE = tWL + tBURST16 + tWR;
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tRDAACT = tRTP + tRP;
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tWRAACT = tWRPRE + tRP;
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tCCD_L_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
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tCCD_S_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
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tCCD_RTW_dlr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
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tRDRD_dpr = tRD_BURST + tRTRS;
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tRDRD_ddr = tRD_BURST + tRTRS;
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tRDWR_dpr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE;
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tRDWR_ddr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE;
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tCCD_L_WTR_slr = tWL + tBURST16 + tWTR_L;
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tCCD_S_WTR_slr = tWL + tBURST16 + tWTR_S;
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tCCD_WTR_dlr = tWL + tBURST16 + tWTR_S;
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tWRWR_dpr = max(tCCD_WR_dpr, tBURST16 + tRTRS);
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tWRWR_ddr = tBURST16 + tRTRS;
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tWRRD_dpr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE;
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tWRRD_ddr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE;
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tRDPDEN = tRL + tBURST16 + cmdLengthDiff;
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tWRPDEN = tWL + tBURST16 + tWR + cmdLengthDiff;
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tWRAPDEN = tWL + tBURST16 + tWR + cmdLengthDiff;
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mPools.insert({
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"CMD_BUS", {
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1, {
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{"ACT", 2 * tCK},
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{"RD", 2 * tCK},
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{"WR", 2 * tCK},
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{"RDA", 2 * tCK},
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{"WRA", 2 * tCK},
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{"PREPB", tCK},
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{"PREAB", tCK},
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{"REFAB", tCK},
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{"PRESB", tCK},
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{"RFMAB", tCK},
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{"REFSB", tCK},
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{"RFMSB", tCK},
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}
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}
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});
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mPools.insert({
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"FAW_LOGICAL", {
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4, {
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{"ACT", tFAW_slr - longCmdOffset},
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{"REFSB", tFAW_slr - shortCmdOffset},
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{"RFMSB", tFAW_slr - shortCmdOffset},
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}
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}
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});
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mPools.insert({
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"FAW_PHYSICAL", {
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4, {
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{"ACT", tFAW_dlr - longCmdOffset},
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{"REFSB", tFAW_dlr - shortCmdOffset},
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{"RFMSB", tFAW_dlr - shortCmdOffset},
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}
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}
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});
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}
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const std::vector<QString> TimeDependenciesInfoDDR5::getPossiblePhases() {
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return {
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"ACT",
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"RD",
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"WR",
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"PRESB",
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"PREPB",
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"RDA",
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"WRA",
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"RFMAB",
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"REFSB",
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"RFMSB",
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"REFAB",
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"PREAB",
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"PDEP",
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"PDXP",
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"SREFEN",
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"SREFEX",
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"PDEA",
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"PDXA",
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};
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}
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DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
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DependencyMap dmap;
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auto passBurstLength16 = std::make_shared<PassFunction>(
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[] PASSFUNCTIONDECL {
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auto other = std::dynamic_pointer_cast<DDR5DBPhaseEntry>(otherPhase);
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if (!other) return false;
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return other->tBurstLength == 16;
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}
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);
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auto passBurstLength32 = std::make_shared<PassFunction>(
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[] PASSFUNCTIONDECL {
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auto other = std::dynamic_pointer_cast<DDR5DBPhaseEntry>(otherPhase);
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if (!other) return false;
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return other->tBurstLength == 32;
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}
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);
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const auto localBitWidth = bitWidth;
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auto passThisBL16AndBW4 = std::make_shared<PassFunction>(
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[localBitWidth] PASSFUNCTIONDECL {
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auto thisP = std::dynamic_pointer_cast<DDR5DBPhaseEntry>(thisPhase);
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if (!thisP) return false;
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return thisP->tBurstLength == 16 && localBitWidth == 4;
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}
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);
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auto passOtherBL32ThisBL16BW4 = std::make_shared<PassFunction>(
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[passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL {
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return passBurstLength32->execute(thisPhase, otherPhase) && passThisBL16AndBW4->execute(thisPhase, otherPhase);
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}
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);
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auto passOtherBL32ThisNotBL16BW4 = std::make_shared<PassFunction>(
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[passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL {
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return passBurstLength32->execute(thisPhase, otherPhase) && !passThisBL16AndBW4->execute(thisPhase, otherPhase);
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}
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);
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auto passOtherBL16ThisBL16BW4 = std::make_shared<PassFunction>(
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[passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL {
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return passBurstLength16->execute(thisPhase, otherPhase) && passThisBL16AndBW4->execute(thisPhase, otherPhase);
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}
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);
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auto passOtherBL16ThisNotBL16BW4 = std::make_shared<PassFunction>(
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[passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL {
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return passBurstLength16->execute(thisPhase, otherPhase) && !passThisBL16AndBW4->execute(thisPhase, otherPhase);
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}
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);
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dmap.emplace(
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piecewise_construct,
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forward_as_tuple("ACT"),
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forward_as_tuple(
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initializer_list<TimeDependency>{
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{tRC, "ACT", DependencyType::IntraBank, "tRC"},
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{tRRD_L_slr, "ACT", DependencyType::IntraBankGroup, "tRRD_L_slr"},
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{tRRD_S_slr, "ACT", DependencyType::IntraLogicalRank, "tRRD_S_slr"},
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{tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"},
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{tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"},
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{tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT", passBurstLength16},
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{tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16", passBurstLength32},
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{tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"},
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{tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"},
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{tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"},
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{tRFC_slr - cmdLengthDiff, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
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{tRFC_slr - cmdLengthDiff, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
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{tRFCsb_slr - cmdLengthDiff, "REFSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"},
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{tREFSBRD_slr - cmdLengthDiff, "REFSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"},
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{tREFSBRD_dlr - cmdLengthDiff, "REFSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"},
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{tRFCsb_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"},
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{tREFSBRD_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"},
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{tREFSBRD_dlr - cmdLengthDiff, "RFMSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"},
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{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
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{tFAW_slr - longCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
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{tFAW_dlr - longCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
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}
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)
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);
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dmap.emplace(
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piecewise_construct,
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forward_as_tuple("RD"),
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forward_as_tuple(
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initializer_list<TimeDependency>{
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{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
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{tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"},
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{tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
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{tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16},
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{tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
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{tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16},
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{tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32},
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{tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16},
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{tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32},
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{tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"},
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{tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
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{tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16},
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{tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
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{tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16},
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{tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32},
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{tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16},
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{tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16},
|
|
{tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16},
|
|
{tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16},
|
|
{tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32},
|
|
{tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16},
|
|
{tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32},
|
|
{tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16},
|
|
{tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16},
|
|
{tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16},
|
|
{tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16},
|
|
{tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32},
|
|
{tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16},
|
|
{tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32},
|
|
{tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16},
|
|
{tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32},
|
|
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("WR"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
|
|
{tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16},
|
|
{tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16},
|
|
{tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32},
|
|
{tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16},
|
|
{tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32},
|
|
{tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16},
|
|
{tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32},
|
|
{tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16},
|
|
{tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16},
|
|
{tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16},
|
|
{tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32},
|
|
{tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16},
|
|
{tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32},
|
|
{tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16},
|
|
{tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32},
|
|
{tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16},
|
|
{tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passOtherBL16ThisBL16BW4},
|
|
{tCCD_L_WR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passOtherBL32ThisBL16BW4},
|
|
{tCCD_L_WR2_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr", passOtherBL16ThisNotBL16BW4},
|
|
{tCCD_L_WR2_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr + tBURST16", passOtherBL32ThisNotBL16BW4},
|
|
{tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
|
|
{tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16},
|
|
{tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
|
|
{tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16},
|
|
{tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32},
|
|
{tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16},
|
|
{tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passOtherBL16ThisBL16BW4},
|
|
{tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passOtherBL32ThisBL16BW4},
|
|
{tCCD_L_WR2_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr", passOtherBL16ThisNotBL16BW4},
|
|
{tCCD_L_WR2_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr + tBURST16", passOtherBL32ThisNotBL16BW4},
|
|
{tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
|
|
{tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16},
|
|
{tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
|
|
{tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16},
|
|
{tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32},
|
|
{tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16},
|
|
{tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32},
|
|
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("PREPB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
|
|
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraBank, "tRTP + tCK"},
|
|
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK", passBurstLength16},
|
|
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16", passBurstLength32},
|
|
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
|
|
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
|
|
{tPPD, "PRESB", DependencyType::IntraPhysicalRank, "tPPD"},
|
|
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("RDA"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
|
|
{tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"},
|
|
{tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
|
|
{tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16},
|
|
{tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
|
|
{tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16},
|
|
{tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32},
|
|
{tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16},
|
|
{tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"},
|
|
{tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
|
|
{tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16},
|
|
{tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
|
|
{tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16},
|
|
{tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32},
|
|
{tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16},
|
|
{tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32},
|
|
{tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA", passBurstLength16},
|
|
{tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16", passBurstLength32},
|
|
{tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16},
|
|
{tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16},
|
|
{tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16},
|
|
{tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32},
|
|
{tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16},
|
|
{tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32},
|
|
{tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16},
|
|
{tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16},
|
|
{tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16},
|
|
{tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16},
|
|
{tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32},
|
|
{tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16},
|
|
{tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32},
|
|
{tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16},
|
|
{tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32},
|
|
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("WRA"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
|
|
{tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16},
|
|
{tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16},
|
|
{tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32},
|
|
{tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16},
|
|
{tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32},
|
|
{tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16},
|
|
{tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32},
|
|
{tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16},
|
|
{tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16},
|
|
{tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16},
|
|
{tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32},
|
|
{tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16},
|
|
{tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32},
|
|
{tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16},
|
|
{tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32},
|
|
{tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16},
|
|
{tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
|
|
{tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
|
|
{tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16},
|
|
{tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
|
|
{tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16},
|
|
{tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32},
|
|
{tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16},
|
|
{tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32},
|
|
{tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passBurstLength16},
|
|
{tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passBurstLength32},
|
|
{tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
|
|
{tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16},
|
|
{tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
|
|
{tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16},
|
|
{tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32},
|
|
{tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16},
|
|
{tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32},
|
|
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("REFAB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
|
|
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
|
|
{tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16},
|
|
{tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32},
|
|
{tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"},
|
|
{tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"},
|
|
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
|
|
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
|
|
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
|
|
{tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
|
|
{tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
|
|
{tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
|
|
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("RFMAB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
|
|
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
|
|
{tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16},
|
|
{tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32},
|
|
{tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"},
|
|
{tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"},
|
|
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
|
|
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
|
|
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
|
|
{tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
|
|
{tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
|
|
{tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
|
|
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("REFSB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"},
|
|
{tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
|
|
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"},
|
|
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK", passBurstLength16},
|
|
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32},
|
|
{tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"},
|
|
{tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"},
|
|
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
|
|
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
|
|
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
|
|
{tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
|
|
{tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
|
|
{tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
|
|
{tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
|
|
{tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
|
|
{tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
|
|
{tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
|
|
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
{tFAW_slr - shortCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
|
|
{tFAW_dlr - shortCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("RFMSB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"},
|
|
{tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
|
|
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"},
|
|
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK", passBurstLength16},
|
|
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32},
|
|
{tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"},
|
|
{tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"},
|
|
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
|
|
{tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
|
|
{tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
|
|
{tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
|
|
{tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
|
|
{tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
|
|
{tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
|
|
{tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
|
|
{tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
|
|
{tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
|
|
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
{tFAW_slr - shortCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
|
|
{tFAW_dlr - shortCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("PREAB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"},
|
|
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"},
|
|
{tRTP + cmdLengthDiff, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"},
|
|
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16},
|
|
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32},
|
|
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16},
|
|
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32},
|
|
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
|
|
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
|
|
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
dmap.emplace(
|
|
piecewise_construct,
|
|
forward_as_tuple("PRESB"),
|
|
forward_as_tuple(
|
|
initializer_list<TimeDependency>{
|
|
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"},
|
|
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"},
|
|
{tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"},
|
|
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16},
|
|
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32},
|
|
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16},
|
|
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32},
|
|
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
|
|
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
|
|
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
|
|
}
|
|
)
|
|
);
|
|
|
|
return dmap;
|
|
}
|