117 lines
3.9 KiB
C++
117 lines
3.9 KiB
C++
/*
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* Copyright (c) 2019, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lukas Steiner
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*/
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#ifndef BANKMACHINE_H
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#define BANKMACHINE_H
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#include "DRAMSys/controller/ManagerIF.h"
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#include "DRAMSys/controller/scheduler/SchedulerIF.h"
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#include "DRAMSys/controller/checker/CheckerIF.h"
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#include "DRAMSys/controller/Command.h"
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#include "DRAMSys/common/dramExtensions.h"
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#include "DRAMSys/configuration/memspec/MemSpec.h"
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#include "DRAMSys/configuration/Configuration.h"
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#include <systemc>
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#include <tlm>
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namespace DRAMSys
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{
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class BankMachine : public ManagerIF
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{
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public:
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CommandTuple::Type getNextCommand() override;
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void update(Command command) override;
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void block();
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[[nodiscard]] Rank getRank() const;
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[[nodiscard]] BankGroup getBankGroup() const;
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[[nodiscard]] Bank getBank() const;
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[[nodiscard]] Row getOpenRow() const;
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[[nodiscard]] bool isIdle() const;
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[[nodiscard]] bool isActivated() const;
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[[nodiscard]] bool isPrecharged() const;
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[[nodiscard]] uint64_t getRefreshManagementCounter() const;
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protected:
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enum class State {Precharged, Activated} state = State::Precharged;
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BankMachine(const Configuration& config, const SchedulerIF& scheduler, Bank bank);
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const MemSpec& memSpec;
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tlm::tlm_generic_payload* currentPayload = nullptr;
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const SchedulerIF& scheduler;
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Command nextCommand = Command::NOP;
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Row openRow;
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const Bank bank;
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const BankGroup bankgroup;
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const Rank rank;
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bool blocked = false;
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bool sleeping = false;
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unsigned refreshManagementCounter = 0;
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const bool refreshManagement = false;
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bool keepTrans = false;
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};
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class BankMachineOpen final : public BankMachine
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{
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public:
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BankMachineOpen(const Configuration& config, const SchedulerIF& scheduler, Bank bank);
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void evaluate() override;
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};
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class BankMachineClosed final : public BankMachine
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{
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public:
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BankMachineClosed(const Configuration& config, const SchedulerIF& scheduler, Bank bank);
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void evaluate() override;
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};
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class BankMachineOpenAdaptive final : public BankMachine
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{
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public:
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BankMachineOpenAdaptive(const Configuration& config, const SchedulerIF& scheduler, Bank bank);
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void evaluate() override;
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};
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class BankMachineClosedAdaptive final : public BankMachine
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{
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public:
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BankMachineClosedAdaptive(const Configuration& config, const SchedulerIF& scheduler, Bank bank);
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void evaluate() override;
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};
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} // namespace DRAMSys
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#endif // BANKMACHINE_H
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