Files
DRAMSys/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json
2025-05-09 16:45:54 +02:00

142 lines
3.7 KiB
JSON

{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 8,
"nbrOfDevices": 4,
"nbrOfChannels": 2,
"cmdMode": 1,
"RefMode": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAADEC" : 16,
"maxBurstLength": 16
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4000A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 28,
"PPD": 2,
"RP": 28,
"RAS": 64,
"RL": 28,
"RTP": 15,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 26,
"WPRE": 2,
"WPST": 0,
"WR": 60,
"CCD_L_slr": 10,
"CCD_L_WR_slr": 40,
"CCD_L_WR2_slr": 20,
"CCD_M_slr": 10,
"CCD_M_WR_slr": 40,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 10,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 20,
"WTR_M": 20,
"WTR_S": 5,
"RFC1_slr": 390,
"RFC2_slr": 260,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 230,
"RFCsb_dlr": 0,
"REFI1": 7800,
"REFI2": 3900,
"REFISB": 1950,
"REFSBRD_slr": 60,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 10,
"PD": 15,
"XP": 15,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"tCK": 500e-12
},
"mempowerspec": {
"vdd": 0.0,
"idd0": 0.0,
"idd2n": 0.0,
"idd3n": 0.0,
"idd4r": 0.0,
"idd4w": 0.0,
"idd5c": 0.0,
"idd6n": 0.0,
"idd2p": 0.0,
"idd3p": 0.0,
"vpp": 0.0,
"ipp0": 0.0,
"ipp2n": 0.0,
"ipp3n": 0.0,
"ipp4r": 0.0,
"ipp4w": 0.0,
"ipp5c": 0.0,
"ipp6n": 0.0,
"ipp2p": 0.0,
"ipp3p": 0.0,
"idd5b": 0.0,
"idd5f": 0.0,
"ipp5b": 0.0,
"ipp5f": 0.0,
"vddq": 0.0,
"iBeta_vdd": 0.0,
"iBeta_vpp": 0.0
},
"memimpedancespec": {
"ck_termination": true,
"ck_R_eq": 1e6,
"ck_dyn_E": 1e-12,
"ca_termination": true,
"ca_R_eq": 1e6,
"ca_dyn_E": 1e-12,
"rdq_termination": true,
"rdq_R_eq": 1e6,
"rdq_dyn_E": 1e-12,
"wdq_termination": true,
"wdq_R_eq": 1e6,
"wdq_dyn_E": 1e-12,
"wdqs_termination": true,
"wdqs_R_eq": 1e6,
"wdqs_dyn_E": 1e-12,
"rdqs_termination": true,
"rdqs_R_eq": 1e6,
"rdqs_dyn_E": 1e-12
},
"dataratespec": {
"ca_bus_rate": 2,
"dq_bus_rate": 2,
"dqs_bus_rate": 2
},
"bankwisespec": {
"factRho": 1
}
}
}