142 lines
3.7 KiB
JSON
142 lines
3.7 KiB
JSON
{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 16,
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"dataRate": 2,
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"nbrOfBankGroups": 8,
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"nbrOfBanks": 16,
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"nbrOfColumns": 1024,
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"nbrOfRanks": 1,
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"nbrOfDIMMRanks": 1,
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"nbrOfPhysicalRanks": 1,
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"nbrOfLogicalRanks": 1,
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"nbrOfRows": 65536,
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"width": 8,
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"nbrOfDevices": 4,
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"nbrOfChannels": 2,
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"cmdMode": 1,
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"RefMode": 1,
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"RAAIMT" : 16,
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"RAAMMT" : 96,
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"RAADEC" : 16,
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"maxBurstLength": 16
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},
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"memoryId": "JEDEC_2x4x1Gbx8_DDR5-3600A",
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"memoryType": "DDR5",
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"memtimingspec": {
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"RCD": 26,
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"PPD": 2,
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"RP": 26,
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"RAS": 58,
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"RL": 26,
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"RTP": 14,
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"RPRE": 1,
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"RPST": 0,
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"RDDQS": 0,
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"WL": 24,
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"WPRE": 2,
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"WPST": 0,
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"WR": 54,
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"CCD_L_slr": 9,
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"CCD_L_WR_slr": 36,
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"CCD_L_WR2_slr": 18,
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"CCD_M_slr": 9,
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"CCD_M_WR_slr": 36,
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"CCD_S_slr": 8,
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"CCD_S_WR_slr": 8,
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"CCD_dlr": 0,
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"CCD_WR_dlr": 0,
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"CCD_WR_dpr": 0,
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"RRD_L_slr": 9,
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"RRD_S_slr": 8,
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"RRD_dlr": 0,
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"FAW_slr": 32,
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"FAW_dlr": 0,
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"WTR_L": 18,
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"WTR_M": 18,
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"WTR_S": 5,
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"RFC1_slr": 351,
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"RFC2_slr": 234,
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"RFC1_dlr": 0,
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"RFC2_dlr": 0,
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"RFC1_dpr": 0,
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"RFC2_dpr": 0,
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"RFCsb_slr": 207,
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"RFCsb_dlr": 0,
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"REFI1": 7020,
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"REFI2": 3510,
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"REFISB": 1755,
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"REFSBRD_slr": 54,
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"REFSBRD_dlr": 0,
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"RTRS": 2,
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"CPDED": 9,
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"PD": 14,
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"XP": 14,
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"ACTPDEN": 2,
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"PRPDEN": 2,
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"REFPDEN": 2,
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"tCK": 556e-12
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},
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"mempowerspec": {
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"vdd": 0.0,
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"idd0": 0.0,
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"idd2n": 0.0,
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"idd3n": 0.0,
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"idd4r": 0.0,
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"idd4w": 0.0,
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"idd5c": 0.0,
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"idd6n": 0.0,
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"idd2p": 0.0,
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"idd3p": 0.0,
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"vpp": 0.0,
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"ipp0": 0.0,
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"ipp2n": 0.0,
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"ipp3n": 0.0,
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"ipp4r": 0.0,
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"ipp4w": 0.0,
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"ipp5c": 0.0,
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"ipp6n": 0.0,
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"ipp2p": 0.0,
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"ipp3p": 0.0,
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"idd5b": 0.0,
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"idd5f": 0.0,
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"ipp5b": 0.0,
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"ipp5f": 0.0,
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"vddq": 0.0,
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"iBeta_vdd": 0.0,
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"iBeta_vpp": 0.0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wdqs_termination": true,
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"wdqs_R_eq": 1e6,
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"wdqs_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12
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},
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"dataratespec": {
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"ca_bus_rate": 2,
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"dq_bus_rate": 2,
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"dqs_bus_rate": 2
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},
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"bankwisespec": {
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"factRho": 1
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}
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}
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}
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