Files
DRAMSys/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json
2025-05-09 16:45:54 +02:00

111 lines
2.7 KiB
JSON

{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"nbrOfBankGroups": 1,
"maxBurstLength": 16
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-2133",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CCDMW": 32,
"CKE": 9,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 2,
"DQSS": 0,
"ESCKE": 3,
"FAW": 43,
"PPD": 4,
"RCD": 20,
"REFI": 4166,
"REFIpb": 520,
"RFCab": 406,
"RFCpb": 203,
"RL": 20,
"RAS": 45,
"RPab": 23,
"RPpb": 20,
"RCab": 68,
"RCpb": 65,
"RPST": 0,
"RRD": 11,
"RTP": 9,
"SR": 17,
"WL": 10,
"WPRE": 2,
"WR": 20,
"WTR": 11,
"XP": 9,
"XSR": 414,
"RTRS": 1,
"tCK": 938e-12
},
"mempowerspec": {
"vdd1": 0.0,
"idd01": 0.0,
"idd2n1": 0.0,
"idd3n1": 0.0,
"idd4r1": 0.0,
"idd4w1": 0.0,
"idd51": 0.0,
"idd5pb1": 0.0,
"idd61": 0.0,
"idd2p1": 0.0,
"idd3p1": 0.0,
"vdd2": 0.0,
"idd02": 0.0,
"idd2n2": 0.0,
"idd3n2": 0.0,
"idd4r2": 0.0,
"idd4w2": 0.0,
"idd52": 0.0,
"idd5pb2": 0.0,
"idd62": 0.0,
"idd2p2": 0.0,
"idd3p2": 0.0,
"vddq": 0.0,
"iBeta_vdd1": 0.0,
"iBeta_vdd2": 0.0
},
"memimpedancespec": {
"ck_termination": true,
"ck_R_eq": 1e6,
"ck_dyn_E": 1e-12,
"ca_termination": true,
"ca_R_eq": 1e6,
"ca_dyn_E": 1e-12,
"rdq_termination": true,
"rdq_R_eq": 1e6,
"rdq_dyn_E": 1e-12,
"wdq_termination": true,
"wdq_R_eq": 1e6,
"wdq_dyn_E": 1e-12,
"wdqs_termination": true,
"wdqs_R_eq": 1e6,
"wdqs_dyn_E": 1e-12,
"rdqs_termination": true,
"rdqs_R_eq": 1e6,
"rdqs_dyn_E": 1e-12
},
"bankwisespec": {
"factRho": 1,
"factSigma": 1,
"pasrMode": 0,
"hasPASR": false
}
}
}