f11adf51dc
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
134 lines
5.6 KiB
Prolog
134 lines
5.6 KiB
Prolog
TEMPLATE = app
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CONFIG += console
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CONFIG -= app_bundle
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CONFIG -= qt
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LIBS += -L/opt/systemc/lib-linux64 -lsystemc
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LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system
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LIBS += -L/opt/sqlite3/lib -lsqlite3
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LIBS += -lpthread
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LIBS += -L/opt/xerces/lib -lxerces-c
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LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml
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LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower
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INCLUDEPATH += /opt/systemc/include
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INCLUDEPATH += /opt/boost/include
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INCLUDEPATH += /opt/sqlite3/include
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INCLUDEPATH += /opt/xerces/include
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INCLUDEPATH += ../src/common/third_party/DRAMPower/src
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INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower
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DEFINES += TIXML_USE_STL
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DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
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DEFINES += USE_XERCES=1
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release {
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DEFINES += NDEBUG
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}
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QMAKE_CXXFLAGS += -std=c++11
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QMAKE_CXXFLAGS += -isystem /opt/systemc/include
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QMAKE_CXXFLAGS += -isystem /opt/boost/include
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QMAKE_CXXFLAGS += -iquote ../src/common/third_party/DRAMPower/src/
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SOURCES += \
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../src/common/third_party/tinyxml2.cpp \
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../src/common/xmlAddressdecoder.cpp \
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../src/common/Utils.cpp \
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../src/common/TlmRecorder.cpp \
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../src/common/dramExtension.cpp \
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../src/common/DebugManager.cpp \
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../src/controller/core/configuration/Configuration.cpp \
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../src/controller/core/powerdown/PowerDownManagerTimeout.cpp \
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../src/controller/core/powerdown/PowerDownManagerBankwise.cpp \
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../src/controller/core/powerdown/PowerDownManager.cpp \
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../src/controller/scheduler/ThreadLoad.cpp \
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../src/controller/scheduler/PARBS.cpp \
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../src/controller/scheduler/Fr_Fcfs.cpp \
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../src/controller/scheduler/Fifo.cpp \
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../src/controller/core/refresh/RefreshManagerBankwise.cpp \
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../src/controller/core/refresh/RefreshManager.cpp \
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../src/controller/core/scheduling/checker/WriteChecker.cpp \
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../src/controller/core/scheduling/checker/RefreshChecker.cpp \
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../src/controller/core/scheduling/checker/ReadChecker.cpp \
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../src/controller/core/scheduling/checker/PrechargeChecker.cpp \
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../src/controller/core/scheduling/checker/PrechargeAllChecker.cpp \
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../src/controller/core/scheduling/checker/PowerDownChecker.cpp \
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../src/controller/core/scheduling/checker/ActivateChecker.cpp \
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../src/controller/core/scheduling/ScheduledCommand.cpp \
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../src/controller/core/TimingCalculation.cpp \
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../src/controller/core/Slots.cpp \
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../src/controller/core/ControllerCore.cpp \
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../src/simulation/SimulationManager.cpp \
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../src/simulation/Simulation.cpp \
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../src/simulation/MemoryManager.cpp \
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../src/simulation/main.cpp \
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../src/controller/scheduler/readwritegrouper.cpp \
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../src/controller/core/configuration/ConfigurationLoader.cpp \
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../src/controller/core/powerdown/NoPowerDown.cpp \
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../src/controller/Command.cpp \
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../src/controller/Controller.cpp \
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../src/controller/ControllerState.cpp \
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../src/controller/RowBufferStates.cpp \
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../src/controller/scheduler/IScheduler.cpp \
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../src/controller/scheduler/FifoStrict.cpp
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HEADERS += \
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../src/common/third_party/tinyxml2.h \
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../src/common/xmlAddressdecoder.h \
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../src/common/Utils.h \
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../src/common/TlmRecorder.h \
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../src/common/tlm2_base_protocol_checker.h \
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../src/common/protocol.h \
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../src/common/dramExtension.h \
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../src/common/DebugManager.h \
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../src/controller/core/configuration/Configuration.h \
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../src/controller/core/powerdown/PowerDownManagerTimeout.h \
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../src/controller/core/powerdown/PowerDownManagerBankwise.h \
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../src/controller/core/powerdown/PowerDownManager.h \
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../src/controller/scheduler/ThreadLoad.h \
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../src/controller/scheduler/PARBS.h \
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../src/controller/scheduler/Fr_Fcfs.h \
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../src/controller/scheduler/Fifo.h \
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../src/controller/Controller.h \
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../src/controller/core/refresh/RefreshManagerBankwise.h \
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../src/controller/core/refresh/RefreshManager.h \
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../src/controller/core/refresh/IRefreshManager.h \
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../src/controller/core/scheduling/checker/WriteChecker.h \
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../src/controller/core/scheduling/checker/RefreshChecker.h \
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../src/controller/core/scheduling/checker/ReadChecker.h \
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../src/controller/core/scheduling/checker/PrechargeChecker.h \
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../src/controller/core/scheduling/checker/PrechargeAllChecker.h \
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../src/controller/core/scheduling/checker/PowerDownChecker.h \
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../src/controller/core/scheduling/checker/ICommandChecker.h \
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../src/controller/core/scheduling/checker/ActivateChecker.h \
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../src/controller/core/scheduling/Trigger.h \
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../src/controller/core/scheduling/ScheduledCommand.h \
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../src/controller/core/TimingCalculation.h \
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../src/controller/core/Slots.h \
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../src/controller/core/ControllerCore.h \
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../src/simulation/TracePlayer.h \
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../src/simulation/SimulationManager.h \
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../src/simulation/Simulation.h \
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../src/simulation/MemoryManager.h \
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../src/simulation/Dram.h \
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../src/simulation/Arbiter.h \
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../src/common/libDRAMPower.h \
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../src/controller/scheduler/readwritegrouper.h \
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../src/simulation/ReorderBuffer.h \
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../src/controller/core/configuration/MemSpec.h \
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../src/simulation/StlPlayer.h \
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../src/simulation/TracePlayerListener.h \
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../src/simulation/TraceGenerator.h \
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../src/controller/core/powerdown/NoPowerDown.h \
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../src/controller/Command.h \
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../src/controller/RowBufferStates.h \
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../src/controller/ControllerState.h \
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../src/controller/core/powerdown/IPowerDownManager.h \
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../src/controller/scheduler/IScheduler.h \
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../src/controller/scheduler/FifoStrict.h \
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../src/controller/IController.h
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../src/controller/core/configuration/ConfigurationLoader.h
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