121 lines
4.7 KiB
C++
121 lines
4.7 KiB
C++
/*
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* Copyright (c) 2020, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lukas Steiner
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*/
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#ifndef CHECKERDDR5_H
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#define CHECKERDDR5_H
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#include <queue>
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#include <vector>
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#include <DRAMSys/controller/checker/CheckerIF.h>
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#include <DRAMSys/common/utils.h>
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#include <DRAMSys/configuration/Configuration.h>
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#include <DRAMSys/configuration/memspec/MemSpecDDR5.h>
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namespace DRAMSys
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{
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class CheckerDDR5 final : public CheckerIF
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{
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public:
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explicit CheckerDDR5(const Configuration& config);
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sc_core::sc_time
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timeToSatisfyConstraints(Command command,
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const tlm::tlm_generic_payload& payload) const override;
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void insert(Command command, const tlm::tlm_generic_payload& payload) override;
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private:
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const MemSpecDDR5* memSpec;
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std::vector<ControllerVector<DimmRank, sc_core::sc_time>> lastScheduledByCommandAndDimmRank;
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std::vector<ControllerVector<PhysicalRank, sc_core::sc_time>>
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lastScheduledByCommandAndPhysicalRank;
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std::vector<ControllerVector<LogicalRank, sc_core::sc_time>>
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lastScheduledByCommandAndLogicalRank;
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std::vector<ControllerVector<BankGroup, sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
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std::vector<ControllerVector<Bank, sc_core::sc_time>> lastScheduledByCommandAndBank;
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std::vector<sc_core::sc_time> lastScheduledByCommand;
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sc_core::sc_time lastCommandOnBus;
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TimeInterval dummyCommandOnBus;
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std::vector<ControllerVector<Bank, sc_core::sc_time>> lastScheduledByCommandAndBankInGroup;
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ControllerVector<PhysicalRank, std::queue<sc_core::sc_time>> last4ActivatesPhysical;
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ControllerVector<LogicalRank, std::queue<sc_core::sc_time>> last4ActivatesLogical;
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std::vector<ControllerVector<DimmRank, uint8_t>> lastBurstLengthByCommandAndDimmRank;
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std::vector<ControllerVector<PhysicalRank, uint8_t>> lastBurstLengthByCommandAndPhysicalRank;
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std::vector<ControllerVector<LogicalRank, uint8_t>> lastBurstLengthByCommandAndLogicalRank;
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std::vector<ControllerVector<BankGroup, uint8_t>> lastBurstLengthByCommandAndBankGroup;
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std::vector<ControllerVector<Bank, uint8_t>> lastBurstLengthByCommandAndBank;
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std::vector<uint8_t> lastBurstLengthByCommand;
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std::vector<ControllerVector<Bank, uint8_t>> lastBurstLengthByCommandAndBankInGroup;
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// TODO: store BL of last RD and WR globally or for each hierarchy?
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const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
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sc_core::sc_time cmdLengthDiff;
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sc_core::sc_time tBURST16;
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sc_core::sc_time tBURST32;
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sc_core::sc_time tWTRA;
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sc_core::sc_time tWRRDA;
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sc_core::sc_time tWRPRE;
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sc_core::sc_time tRDAACT;
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sc_core::sc_time tWRAACT;
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sc_core::sc_time tCCD_L_RTW_slr;
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sc_core::sc_time tCCD_S_RTW_slr;
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sc_core::sc_time tCCD_RTW_dlr;
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sc_core::sc_time tRDRD_dpr;
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sc_core::sc_time tRDRD_ddr;
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sc_core::sc_time tRDWR_dpr;
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sc_core::sc_time tRDWR_ddr;
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sc_core::sc_time tCCD_L_WTR_slr;
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sc_core::sc_time tCCD_M_WTR_slr;
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sc_core::sc_time tCCD_S_WTR_slr;
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sc_core::sc_time tCCD_WTR_dlr;
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sc_core::sc_time tWRWR_dpr;
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sc_core::sc_time tWRWR_ddr;
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sc_core::sc_time tWRRD_dpr;
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sc_core::sc_time tWRRD_ddr;
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sc_core::sc_time tRDPDEN;
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sc_core::sc_time tWRPDEN;
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sc_core::sc_time tWRAPDEN;
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};
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} // namespace DRAMSys
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#endif // CHECKERDDR5_H
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