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DRAMSys/DRAM/src/core/TimingConfiguration.h
robert 7fc688a02d ..
2014-03-16 19:37:22 +01:00

65 lines
1.3 KiB
C++

/*
* TimingConfiguration.h
*
* Created on: Mar 6, 2014
* Author: jonny
*/
#ifndef TIMINGS_H_
#define TIMINGS_H_
#include <systemc.h>
#include "core/utils/Utils.h"
namespace core{
struct RefreshTiming
{
RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}
sc_time tRFC;
sc_time tREFI;
};
struct TimingConfiguration
{
TimingConfiguration(unsigned int numberOfBanks)
{
for (unsigned int i = 0; i < numberOfBanks; ++i)
{
sc_time tRFC = 18*clk;
sc_time tREFI = sc_time(15.6, SC_US); //TODO align
refreshTimings.push_back(RefreshTiming(tRFC, tREFI));
}
clk = sc_time(6.0, SC_NS); // 166MHz
tRP = 3*clk; //precharge-time (pre -> act same bank)
tRAS = 6*clk; //active-time (act -> pre same bank)
tRC = tRP + tRAS; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
tRRD = 2*clk; //(min time bw 2 succesive ACT to different banks)
tRCD = 3*clk; //act -> read/write
tRL = 3*clk; //read latency (read command start to data strobe)
tTAW = clkAlign(sc_time(50, SC_NS), clk); //two activate window
}
sc_time clk;
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRRD;
sc_time tRCD;
sc_time tTAW;
sc_time tRL;
std::vector<RefreshTiming> refreshTimings;
};
} /* namespace controller */
#endif /* TimingConfiguration_H_ */