132 lines
3.4 KiB
JSON
132 lines
3.4 KiB
JSON
{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 32,
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"dataRate": 4,
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"nbrOfBankGroups": 1,
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"nbrOfBanks": 8,
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"nbrOfColumns": 2048,
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"nbrOfRows": 32768,
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"nbrOfRanks": 1,
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"nbrOfDevices": 1,
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"nbrOfChannels": 1,
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"width": 16,
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"per2BankOffset": 8,
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"WCKalwaysOn": false,
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"maxBurstLength": 32
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},
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"mempowerspec": {
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"vdd1": 0.0,
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"idd01": 0.0,
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"idd2n1": 0.0,
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"idd3n1": 0.0,
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"idd4r1": 0.0,
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"idd4w1": 0.0,
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"idd51": 0.0,
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"idd5pb1": 0.0,
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"idd61": 0.0,
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"idd6ds1": 0.0,
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"idd2p1": 0.0,
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"idd3p1": 0.0,
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"vdd2h": 0.0,
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"idd02h": 0.0,
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"idd2n2h": 0.0,
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"idd3n2h": 0.0,
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"idd4r2h": 0.0,
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"idd4w2h": 0.0,
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"idd52h": 0.0,
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"idd5pb2h": 0.0,
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"idd62h": 0.0,
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"idd6ds2h": 0.0,
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"idd2p2h": 0.0,
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"idd3p2h": 0.0,
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"vdd2l": 0.0,
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"idd02l": 0.0,
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"idd2n2l": 0.0,
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"idd3n2l": 0.0,
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"idd4r2l": 0.0,
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"idd4w2l": 0.0,
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"idd52l": 0.0,
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"idd5pb2l": 0.0,
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"idd62l": 0.0,
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"idd6ds2l": 0.0,
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"idd2p2l": 0.0,
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"idd3p2l": 0.0,
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"vddq": 0.0,
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"iBeta_vdd1": 0.0,
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"iBeta_vdd2h": 0.0,
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"iBeta_vdd2l": 0.0
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},
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"bankwisespec": {
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"factRho": 1.0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wck_termination": true,
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"wck_R_eq": 1e6,
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"wck_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12
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},
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"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-1067",
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"memoryType": "LPDDR5",
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"memtimingspec": {
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"RCD_L": 5,
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"RCD_S": 5,
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"PPD": 2,
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"RPab": 6,
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"RPpb": 5,
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"RAS": 12,
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"RCab": 17,
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"RCpb": 16,
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"FAW": 11,
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"RRD": 3,
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"RL": 8,
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"WCK2CK": 0,
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"WCK2DQO": 1,
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"RBTP": 0,
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"RPRE": 0,
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"RPST": 0,
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"WL": 4,
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"WCK2DQI": 0,
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"WPRE": 0,
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"WPST": 0,
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"WR": 10,
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"WTR_L": 4,
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"WTR_S": 4,
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"CCDMW": 16,
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"REFI": 1041,
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"REFIpb": 130,
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"RFCab": 56,
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"RFCpb": 32,
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"RTRS": 1,
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"BL_n_min_16": 8,
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"BL_n_max_16": 8,
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"BL_n_L_16": 8,
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"BL_n_S_16": 8,
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"BL_n_min_32": 8,
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"BL_n_max_32": 8,
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"BL_n_L_32": 8,
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"BL_n_S_32": 8,
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"pbR2act": 3,
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"pbR2pbR": 24,
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"tCK": 3745e-12
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}
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}
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}
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